ASoC: SOF: amd: Fix for incorrect acp error register offsets

Addition of 'dsp_intr_base' to ACP error register offsets points to
wrong register offsets in irq handler. Correct the acp error register
offsets. ACP error status register offset and acp error reason register
offset got changed from ACP6.0 onwards. Add 'acp_error_stat' and
'acp_sw0_i2s_err_reason' as descriptor fields in sof_amd_acp_desc
structure and update the values based on the ACP variant.
>From Rembrandt platform onwards, errors related to SW1 Soundwire manager
instance/I2S controller connected on P1 power tile is reported with
ACP_SW1_I2S_ERROR_REASON register. Add conditional check for the same.

Fixes: 96eb81851012 ("ASoC: SOF: amd: add interrupt handling for SoundWire manager devices")
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://patch.msgid.link/20240813105944.3126903-2-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Vijendar Mukunda and committed by

Mark Brown 2 years ago 897e91e9 c56ba3e4

+19 -6

6 changed files

expand all

sound

soc

sof

amd

acp-dsp-offset.h

acp.c

acp.h

pci-acp63.c

pci-rmb.c

pci-rn.c

+4 -2

sound/soc/sof/amd/acp-dsp-offset.h

··· 76 76 #define DSP_SW_INTR_CNTL_OFFSET 0x0 77 77 #define DSP_SW_INTR_STAT_OFFSET 0x4 78 78 #define DSP_SW_INTR_TRIG_OFFSET 0x8 79 - #define ACP_ERROR_STATUS 0x18C4 79 + #define ACP3X_ERROR_STATUS 0x18C4 80 + #define ACP6X_ERROR_STATUS 0x1A4C 80 81 #define ACP3X_AXI2DAGB_SEM_0 0x1880 81 82 #define ACP5X_AXI2DAGB_SEM_0 0x1884 82 83 #define ACP6X_AXI2DAGB_SEM_0 0x1874 83 84 84 85 /* ACP common registers to report errors related to I2S & SoundWire interfaces */ 85 - #define ACP_SW0_I2S_ERROR_REASON 0x18B4 86 + #define ACP3X_SW_I2S_ERROR_REASON 0x18C8 87 + #define ACP6X_SW0_I2S_ERROR_REASON 0x18B4 86 88 #define ACP_SW1_I2S_ERROR_REASON 0x1A50 87 89 88 90 /* Registers from ACP_SHA block */

+7 -4

sound/soc/sof/amd/acp.c

··· 92 92 unsigned int idx, unsigned int dscr_count) 93 93 { 94 94 struct snd_sof_dev *sdev = adata->dev; 95 + const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 95 96 unsigned int val, status; 96 97 int ret; 97 98 ··· 103 102 val & (1 << ch), ACP_REG_POLL_INTERVAL, 104 103 ACP_REG_POLL_TIMEOUT_US); 105 104 if (ret < 0) { 106 - status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS); 105 + status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat); 107 106 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32)); 108 107 109 108 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status); ··· 403 402 404 403 if (val & ACP_ERROR_IRQ_MASK) { 405 404 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 406 - snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW0_I2S_ERROR_REASON, 0); 407 - snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW1_I2S_ERROR_REASON, 0); 408 - snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_ERROR_STATUS, 0); 405 + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0); 406 + /* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */ 407 + if (desc->rev >= 6) 408 + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0); 409 + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); 409 410 irq_flag = 1; 410 411 } 411 412

sound/soc/sof/amd/acp.h

··· 203 203 u32 probe_reg_offset; 204 204 u32 reg_start_addr; 205 205 u32 reg_end_addr; 206 + u32 acp_error_stat; 207 + u32 acp_sw0_i2s_err_reason; 206 208 u32 sdw_max_link_count; 207 209 u64 sdw_acpi_dev_addr; 208 210 };

sound/soc/sof/amd/pci-acp63.c

··· 35 35 .ext_intr_cntl = ACP6X_EXTERNAL_INTR_CNTL, 36 36 .ext_intr_stat = ACP6X_EXT_INTR_STAT, 37 37 .ext_intr_stat1 = ACP6X_EXT_INTR_STAT1, 38 + .acp_error_stat = ACP6X_ERROR_STATUS, 39 + .acp_sw0_i2s_err_reason = ACP6X_SW0_I2S_ERROR_REASON, 38 40 .dsp_intr_base = ACP6X_DSP_SW_INTR_BASE, 39 41 .sram_pte_offset = ACP6X_SRAM_PTE_OFFSET, 40 42 .hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0,

sound/soc/sof/amd/pci-rmb.c

··· 33 33 .pgfsm_base = ACP6X_PGFSM_BASE, 34 34 .ext_intr_stat = ACP6X_EXT_INTR_STAT, 35 35 .dsp_intr_base = ACP6X_DSP_SW_INTR_BASE, 36 + .acp_error_stat = ACP6X_ERROR_STATUS, 37 + .acp_sw0_i2s_err_reason = ACP6X_SW0_I2S_ERROR_REASON, 36 38 .sram_pte_offset = ACP6X_SRAM_PTE_OFFSET, 37 39 .hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0, 38 40 .fusion_dsp_offset = ACP6X_DSP_FUSION_RUNSTALL,

sound/soc/sof/amd/pci-rn.c

··· 33 33 .pgfsm_base = ACP3X_PGFSM_BASE, 34 34 .ext_intr_stat = ACP3X_EXT_INTR_STAT, 35 35 .dsp_intr_base = ACP3X_DSP_SW_INTR_BASE, 36 + .acp_error_stat = ACP3X_ERROR_STATUS, 37 + .acp_sw0_i2s_err_reason = ACP3X_SW_I2S_ERROR_REASON, 36 38 .sram_pte_offset = ACP3X_SRAM_PTE_OFFSET, 37 39 .hw_semaphore_offset = ACP3X_AXI2DAGB_SEM_0, 38 40 .acp_clkmux_sel = ACP3X_CLKMUX_SEL,

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