Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: Implement 10-bit color alpha for v12.0 DPU
v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register
differences and new implementations of setup_alpha_out(),
setup_border_color() and setup_blend_config().
Notable changes in v6:
Correct fg_alpha shift on new DPU, pointed out by Abel Vesas.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/659629/
Link: https://lore.kernel.org/r/20250618-b4-sm8750-display-v7-10-a591c609743d@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
authored by
Krzysztof Kozlowski
and committed by
Dmitry Baryshkov
8984f97c
afff6425
+97
-10
+16
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+16
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
···
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}
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static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
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-
struct dpu_plane_state *pstate, const struct msm_format *format)
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+
struct dpu_plane_state *pstate,
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+
const struct msm_format *format,
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const struct dpu_mdss_version *mdss_ver)
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{
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struct dpu_hw_mixer *lm = mixer->hw_lm;
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u32 blend_op;
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-
u32 fg_alpha, bg_alpha;
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+
u32 fg_alpha, bg_alpha, max_alpha;
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-
fg_alpha = pstate->base.alpha >> 8;
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-
bg_alpha = 0xff - fg_alpha;
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+
if (mdss_ver->core_major_ver < 12) {
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+
max_alpha = 0xff;
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+
fg_alpha = pstate->base.alpha >> 8;
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+
} else {
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max_alpha = 0x3ff;
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fg_alpha = pstate->base.alpha >> 6;
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}
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bg_alpha = max_alpha - fg_alpha;
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/* default to opaque blending */
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if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
···
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} else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
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blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
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DPU_BLEND_BG_ALPHA_FG_PIXEL;
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-
if (fg_alpha != 0xff) {
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+
if (fg_alpha != max_alpha) {
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bg_alpha = fg_alpha;
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blend_op |= DPU_BLEND_BG_MOD_ALPHA |
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DPU_BLEND_BG_INV_MOD_ALPHA;
···
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/* coverage blending */
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blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
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DPU_BLEND_BG_ALPHA_FG_PIXEL;
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if (fg_alpha != 0xff) {
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+
if (fg_alpha != max_alpha) {
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bg_alpha = fg_alpha;
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blend_op |= DPU_BLEND_FG_MOD_ALPHA |
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DPU_BLEND_FG_INV_MOD_ALPHA |
···
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/* blend config update */
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for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
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_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
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+
_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format,
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+
ctl->mdss_ver);
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if (bg_alpha_enable && !format->alpha_enable)
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mixer[lm_idx].mixer_op_mode = 0;
+81
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+81
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
···
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/* These register are offset to mixer base + stage base */
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#define LM_BLEND0_OP 0x00
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+
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/* <v12 DPU with offset to mixer base + stage base */
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#define LM_BLEND0_CONST_ALPHA 0x04
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#define LM_FG_COLOR_FILL_COLOR_0 0x08
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#define LM_FG_COLOR_FILL_COLOR_1 0x0C
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#define LM_FG_COLOR_FILL_SIZE 0x10
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#define LM_FG_COLOR_FILL_XY 0x14
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+
/* >= v12 DPU */
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#define LM_BORDER_COLOR_0_V12 0x1c
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#define LM_BORDER_COLOR_1_V12 0x20
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+
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/* >= v12 DPU with offset to mixer base + stage base */
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#define LM_BLEND0_CONST_ALPHA_V12 0x08
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#define LM_BLEND0_FG_ALPHA 0x04
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#define LM_BLEND0_BG_ALPHA 0x08
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···
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}
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}
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+
static void dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer *ctx,
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struct dpu_mdss_color *color,
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u8 border_en)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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+
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+
if (border_en) {
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DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12,
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(color->color_0 & 0x3ff) |
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+
((color->color_1 & 0x3ff) << 16));
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DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12,
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+
(color->color_2 & 0x3ff) |
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((color->color_3 & 0x3ff) << 16));
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}
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}
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+
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static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
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{
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dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0);
···
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const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16);
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DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha);
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DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
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}
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static void
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dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx,
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u32 stage, u32 fg_alpha,
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u32 bg_alpha, u32 blend_op)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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int stage_off;
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u32 const_alpha;
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if (stage == DPU_STAGE_BASE)
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return;
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+
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stage_off = _stage_offset(ctx, stage);
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if (WARN_ON(stage_off < 0))
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return;
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const_alpha = (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16);
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DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha);
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DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
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}
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···
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DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
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}
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+
static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer *ctx,
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uint32_t mixer_op_mode)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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int op_mode, stages, stage_off, i;
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stages = ctx->cap->sblk->maxblendstages;
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if (stages <= 0)
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return;
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for (i = DPU_STAGE_0; i <= stages; i++) {
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stage_off = _stage_offset(ctx, i);
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if (WARN_ON(stage_off < 0))
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return;
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/* set color_out3 bit in blend0_op when enabled in mixer_op_mode */
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op_mode = DPU_REG_READ(c, LM_BLEND0_OP + stage_off);
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if (mixer_op_mode & BIT(i))
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op_mode |= BIT(30);
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else
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op_mode &= ~BIT(30);
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DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode);
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}
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}
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+
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/**
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* dpu_hw_lm_init() - Initializes the mixer hw driver object.
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* should be called once before accessing every mixer.
···
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c->idx = cfg->id;
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c->cap = cfg;
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c->ops.setup_mixer_out = dpu_hw_lm_setup_out;
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-
if (mdss_ver->core_major_ver >= 4)
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+
if (mdss_ver->core_major_ver >= 12)
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c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha_v12;
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else if (mdss_ver->core_major_ver >= 4)
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c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
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else
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c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config;
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-
c->ops.setup_alpha_out = dpu_hw_lm_setup_color3;
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c->ops.setup_border_color = dpu_hw_lm_setup_border_color;
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if (mdss_ver->core_major_ver < 12) {
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c->ops.setup_alpha_out = dpu_hw_lm_setup_color3;
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c->ops.setup_border_color = dpu_hw_lm_setup_border_color;
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} else {
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c->ops.setup_alpha_out = dpu_hw_lm_setup_color3_v12;
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c->ops.setup_border_color = dpu_hw_lm_setup_border_color_v12;
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}
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c->ops.setup_misr = dpu_hw_lm_setup_misr;
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c->ops.collect_misr = dpu_hw_lm_collect_misr;
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