Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
usb: dwc3: Add Google Tensor SoC DWC3 glue driver
Add support for the DWC3 USB controller found on Google Tensor G5
(codename: laguna). The controller features dual-role functionality
and hibernation.
The primary focus is implementing hibernation support in host mode,
enabling the controller to enter a low-power state (D3). This is
particularly relevant during system power state transition and
runtime power management for power efficiency.
Highlights:
- Align suspend callback with dwc3_suspend_common() for deciding
between a full teardown and hibernation in host mode.
- Integration with `psw` (power switchable) and `top` power domains,
managing their states and device links to support hibernation.
- A notifier callback dwc3_google_usb_psw_pd_notifier() for
`psw` power domain events to manage controller state
transitions to/from D3.
- Coordination of the `non_sticky` reset during power state
transitions, asserting it on D3 entry and deasserting on D0 entry
in hibernation scenario.
- Handling of high-speed and super-speed PME interrupts
that are generated by remote wakeup during hibernation.
Co-developed-by: Joy Chakraborty <joychakr@google.com>
Signed-off-by: Joy Chakraborty <joychakr@google.com>
Co-developed-by: Naveen Kumar <mnkumar@google.com>
Signed-off-by: Naveen Kumar <mnkumar@google.com>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Roy Luo <royluo@google.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://patch.msgid.link/20251218-controller-v10-2-4047c9077274@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Roy Luo
and committed by
Greg Kroah-Hartman
8995a373
32bc790a
+641
+1
MAINTAINERS
+1
MAINTAINERS
+11
drivers/usb/dwc3/Kconfig
+11
drivers/usb/dwc3/Kconfig
···
211
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mode on these machines.
212
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Say 'Y' or 'M' if you have such device.
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config USB_DWC3_GOOGLE
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tristate "Google Platform"
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help
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Support the DesignWare Core USB3 IP found on Google Tensor SoCs,
218
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starting with the G5 generation (Laguna). This driver includes
219
+
support for hibernation in host mode.
220
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Say 'Y' or 'M' if you have one such device.
221
+
222
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To compile this driver as a module, choose M here: the
223
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module will be called dwc3-google.ko.
224
+
214
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endif
+1
drivers/usb/dwc3/Makefile
+1
drivers/usb/dwc3/Makefile
+628
drivers/usb/dwc3/dwc3-google.c
+628
drivers/usb/dwc3/dwc3-google.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
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* dwc3-google.c - Google DWC3 Specific Glue Layer
4
+
*
5
+
* Copyright (c) 2025, Google LLC
6
+
* Author: Roy Luo <royluo@google.com>
7
+
*/
8
+
9
+
#include <linux/bitfield.h>
10
+
#include <linux/clk.h>
11
+
#include <linux/iopoll.h>
12
+
#include <linux/irq.h>
13
+
#include <linux/kernel.h>
14
+
#include <linux/mfd/syscon.h>
15
+
#include <linux/module.h>
16
+
#include <linux/of.h>
17
+
#include <linux/platform_device.h>
18
+
#include <linux/pm_domain.h>
19
+
#include <linux/regmap.h>
20
+
#include <linux/reset.h>
21
+
#include "core.h"
22
+
#include "glue.h"
23
+
24
+
/* HOST CFG registers */
25
+
#define HC_STATUS_OFFSET 0x0
26
+
#define HC_STATUS_CURRENT_POWER_STATE_U2PMU GENMASK(1, 0)
27
+
#define HC_STATUS_CURRENT_POWER_STATE_U3PMU GENMASK(4, 3)
28
+
29
+
#define HOST_CFG1_OFFSET 0x4
30
+
#define HOST_CFG1_PME_EN BIT(3)
31
+
#define HOST_CFG1_PM_POWER_STATE_REQUEST GENMASK(5, 4)
32
+
#define HOST_CFG1_PM_POWER_STATE_D0 0x0
33
+
#define HOST_CFG1_PM_POWER_STATE_D3 0x3
34
+
35
+
/* USBINT registers */
36
+
#define USBINT_CFG1_OFFSET 0x0
37
+
#define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK BIT(2)
38
+
#define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK BIT(3)
39
+
#define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN BIT(8)
40
+
#define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN BIT(9)
41
+
#define USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR BIT(14)
42
+
#define USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR BIT(15)
43
+
44
+
#define USBINT_STATUS_OFFSET 0x4
45
+
#define USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW BIT(2)
46
+
#define USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW BIT(3)
47
+
48
+
#define USBCS_TOP_CTRL_CFG1_OFFSET 0xc
49
+
#define USBCS_TOP_CTRL_CFG1_USB2ONLY_MODE BIT(5)
50
+
51
+
#define DWC3_GOOGLE_MAX_RESETS 4
52
+
53
+
struct dwc3_google {
54
+
struct device *dev;
55
+
struct dwc3 dwc;
56
+
struct clk_bulk_data *clks;
57
+
int num_clks;
58
+
struct reset_control_bulk_data rsts[DWC3_GOOGLE_MAX_RESETS];
59
+
int num_rsts;
60
+
struct reset_control *non_sticky_rst;
61
+
struct device *usb_psw_pd;
62
+
struct device_link *usb_psw_pd_dl;
63
+
struct notifier_block usb_psw_pd_nb;
64
+
struct device *usb_top_pd;
65
+
struct device_link *usb_top_pd_dl;
66
+
struct regmap *usb_cfg_regmap;
67
+
unsigned int host_cfg_offset;
68
+
unsigned int usbint_cfg_offset;
69
+
int hs_pme_irq;
70
+
int ss_pme_irq;
71
+
bool is_usb2only;
72
+
bool is_hibernation;
73
+
};
74
+
75
+
#define to_dwc3_google(d) container_of_const((d), struct dwc3_google, dwc)
76
+
77
+
static int dwc3_google_rst_init(struct dwc3_google *google)
78
+
{
79
+
int ret;
80
+
81
+
google->num_rsts = 4;
82
+
google->rsts[0].id = "non_sticky";
83
+
google->rsts[1].id = "sticky";
84
+
google->rsts[2].id = "drd_bus";
85
+
google->rsts[3].id = "top";
86
+
87
+
ret = devm_reset_control_bulk_get_exclusive(google->dev,
88
+
google->num_rsts,
89
+
google->rsts);
90
+
91
+
if (ret < 0)
92
+
return ret;
93
+
94
+
google->non_sticky_rst = google->rsts[0].rstc;
95
+
96
+
return 0;
97
+
}
98
+
99
+
static int dwc3_google_set_pmu_state(struct dwc3_google *google, int state)
100
+
{
101
+
u32 reg;
102
+
int ret;
103
+
104
+
regmap_read(google->usb_cfg_regmap,
105
+
google->host_cfg_offset + HOST_CFG1_OFFSET, ®);
106
+
107
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reg &= ~HOST_CFG1_PM_POWER_STATE_REQUEST;
108
+
reg |= (FIELD_PREP(HOST_CFG1_PM_POWER_STATE_REQUEST, state) |
109
+
HOST_CFG1_PME_EN);
110
+
regmap_write(google->usb_cfg_regmap,
111
+
google->host_cfg_offset + HOST_CFG1_OFFSET, reg);
112
+
113
+
ret = regmap_read_poll_timeout(google->usb_cfg_regmap,
114
+
google->host_cfg_offset + HC_STATUS_OFFSET, reg,
115
+
(FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U2PMU,
116
+
reg) == state &&
117
+
FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U3PMU,
118
+
reg) == state),
119
+
10, 10000);
120
+
121
+
if (ret)
122
+
dev_err(google->dev, "failed to set PMU state %d\n", state);
123
+
124
+
return ret;
125
+
}
126
+
127
+
/*
128
+
* Clear pme interrupts and report their status.
129
+
* The hardware requires write-1 then write-0 sequence to clear the interrupt bits.
130
+
*/
131
+
static u32 dwc3_google_clear_pme_irqs(struct dwc3_google *google)
132
+
{
133
+
u32 irq_status, reg_set, reg_clear;
134
+
135
+
regmap_read(google->usb_cfg_regmap,
136
+
google->usbint_cfg_offset + USBINT_STATUS_OFFSET, &irq_status);
137
+
138
+
irq_status &= (USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW |
139
+
USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW);
140
+
if (!irq_status)
141
+
return irq_status;
142
+
143
+
regmap_read(google->usb_cfg_regmap,
144
+
google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®_set);
145
+
146
+
reg_clear = reg_set;
147
+
if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW) {
148
+
reg_set |= USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR;
149
+
reg_clear &= ~USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR;
150
+
}
151
+
if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW) {
152
+
reg_set |= USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR;
153
+
reg_clear &= ~USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR;
154
+
}
155
+
156
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regmap_write(google->usb_cfg_regmap,
157
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google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg_set);
158
+
regmap_write(google->usb_cfg_regmap,
159
+
google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg_clear);
160
+
161
+
return irq_status;
162
+
}
163
+
164
+
static void dwc3_google_enable_pme_irq(struct dwc3_google *google)
165
+
{
166
+
u32 reg;
167
+
168
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regmap_read(google->usb_cfg_regmap,
169
+
google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®);
170
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reg &= ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK |
171
+
USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK);
172
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reg |= (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN |
173
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USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN);
174
+
regmap_write(google->usb_cfg_regmap,
175
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google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg);
176
+
177
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enable_irq(google->hs_pme_irq);
178
+
enable_irq(google->ss_pme_irq);
179
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enable_irq_wake(google->hs_pme_irq);
180
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enable_irq_wake(google->ss_pme_irq);
181
+
}
182
+
183
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static void dwc3_google_disable_pme_irq(struct dwc3_google *google)
184
+
{
185
+
u32 reg;
186
+
187
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regmap_read(google->usb_cfg_regmap,
188
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google->usbint_cfg_offset + USBINT_CFG1_OFFSET, ®);
189
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reg &= ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN |
190
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USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN);
191
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reg |= (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK |
192
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USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK);
193
+
regmap_write(google->usb_cfg_regmap,
194
+
google->usbint_cfg_offset + USBINT_CFG1_OFFSET, reg);
195
+
196
+
disable_irq_wake(google->hs_pme_irq);
197
+
disable_irq_wake(google->ss_pme_irq);
198
+
disable_irq_nosync(google->hs_pme_irq);
199
+
disable_irq_nosync(google->ss_pme_irq);
200
+
}
201
+
202
+
static irqreturn_t dwc3_google_resume_irq(int irq, void *data)
203
+
{
204
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struct dwc3_google *google = data;
205
+
struct dwc3 *dwc = &google->dwc;
206
+
u32 irq_status, dr_role;
207
+
208
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irq_status = dwc3_google_clear_pme_irqs(google);
209
+
dr_role = dwc->current_dr_role;
210
+
211
+
if (!irq_status || !google->is_hibernation ||
212
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dr_role != DWC3_GCTL_PRTCAP_HOST) {
213
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dev_dbg(google->dev, "spurious pme irq %d, hibernation %d, dr_role %u\n",
214
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irq, google->is_hibernation, dr_role);
215
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return IRQ_HANDLED;
216
+
}
217
+
218
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if (dwc->xhci)
219
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pm_runtime_resume(&dwc->xhci->dev);
220
+
221
+
return IRQ_HANDLED;
222
+
}
223
+
224
+
static int dwc3_google_request_irq(struct dwc3_google *google, struct platform_device *pdev,
225
+
const char *irq_name, const char *req_name)
226
+
{
227
+
int ret;
228
+
int irq;
229
+
230
+
irq = platform_get_irq_byname(pdev, irq_name);
231
+
if (irq < 0) {
232
+
dev_err(google->dev, "invalid irq name %s\n", irq_name);
233
+
return irq;
234
+
}
235
+
236
+
irq_set_status_flags(irq, IRQ_NOAUTOEN);
237
+
ret = devm_request_threaded_irq(google->dev, irq, NULL,
238
+
dwc3_google_resume_irq,
239
+
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
240
+
req_name, google);
241
+
if (ret < 0) {
242
+
dev_err(google->dev, "failed to request irq %s\n", req_name);
243
+
return ret;
244
+
}
245
+
246
+
return irq;
247
+
}
248
+
249
+
static int dwc3_google_usb_psw_pd_notifier(struct notifier_block *nb, unsigned long action, void *d)
250
+
{
251
+
struct dwc3_google *google = container_of(nb, struct dwc3_google, usb_psw_pd_nb);
252
+
int ret;
253
+
254
+
if (!google->is_hibernation)
255
+
return NOTIFY_OK;
256
+
257
+
if (action == GENPD_NOTIFY_OFF) {
258
+
dev_dbg(google->dev, "enter D3 power state\n");
259
+
dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D3);
260
+
ret = reset_control_assert(google->non_sticky_rst);
261
+
if (ret)
262
+
dev_err(google->dev, "non sticky reset assert failed: %d\n", ret);
263
+
} else if (action == GENPD_NOTIFY_ON) {
264
+
dev_dbg(google->dev, "enter D0 power state\n");
265
+
dwc3_google_clear_pme_irqs(google);
266
+
ret = reset_control_deassert(google->non_sticky_rst);
267
+
if (ret)
268
+
dev_err(google->dev, "non sticky reset deassert failed: %d\n", ret);
269
+
dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D0);
270
+
}
271
+
272
+
return NOTIFY_OK;
273
+
}
274
+
275
+
static void dwc3_google_pm_domain_deinit(struct dwc3_google *google)
276
+
{
277
+
if (google->usb_top_pd_dl)
278
+
device_link_del(google->usb_top_pd_dl);
279
+
280
+
if (!IS_ERR_OR_NULL(google->usb_top_pd)) {
281
+
device_set_wakeup_capable(google->usb_top_pd, false);
282
+
dev_pm_domain_detach(google->usb_top_pd, true);
283
+
}
284
+
285
+
if (google->usb_psw_pd_dl)
286
+
device_link_del(google->usb_psw_pd_dl);
287
+
288
+
if (!IS_ERR_OR_NULL(google->usb_psw_pd)) {
289
+
dev_pm_genpd_remove_notifier(google->usb_psw_pd);
290
+
dev_pm_domain_detach(google->usb_psw_pd, true);
291
+
}
292
+
}
293
+
294
+
static int dwc3_google_pm_domain_init(struct dwc3_google *google)
295
+
{
296
+
int ret;
297
+
298
+
/*
299
+
* Establish PM RUNTIME link between dwc dev and its power domain usb_psw_pd,
300
+
* register notifier block to handle hibernation.
301
+
*/
302
+
google->usb_psw_pd = dev_pm_domain_attach_by_name(google->dev, "psw");
303
+
if (IS_ERR_OR_NULL(google->usb_psw_pd)) {
304
+
dev_err(google->dev, "failed to get psw pd");
305
+
ret = google->usb_psw_pd ? PTR_ERR(google->usb_psw_pd) : -ENODATA;
306
+
return ret;
307
+
}
308
+
309
+
google->usb_psw_pd_nb.notifier_call = dwc3_google_usb_psw_pd_notifier;
310
+
ret = dev_pm_genpd_add_notifier(google->usb_psw_pd, &google->usb_psw_pd_nb);
311
+
if (ret) {
312
+
dev_err(google->dev, "failed to add psw pd notifier");
313
+
goto err;
314
+
}
315
+
316
+
google->usb_psw_pd_dl = device_link_add(google->dev, google->usb_psw_pd,
317
+
DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
318
+
DL_FLAG_RPM_ACTIVE);
319
+
if (!google->usb_psw_pd_dl) {
320
+
dev_err(google->usb_psw_pd, "failed to add device link");
321
+
ret = -ENODEV;
322
+
goto err;
323
+
}
324
+
325
+
/*
326
+
* usb_top_pd is the parent power domain of usb_psw_pd. Keeping usb_top_pd on
327
+
* while usb_psw_pd is off places the controller in a power-gated state,
328
+
* essential for hibernation. Acquire a handle to usb_top_pd and sets it as
329
+
* wakeup-capable to allow the domain to be left on during system suspend.
330
+
*/
331
+
google->usb_top_pd = dev_pm_domain_attach_by_name(google->dev, "top");
332
+
if (IS_ERR_OR_NULL(google->usb_top_pd)) {
333
+
dev_err(google->dev, "failed to get top pd");
334
+
ret = google->usb_top_pd ? PTR_ERR(google->usb_top_pd) : -ENODATA;
335
+
goto err;
336
+
}
337
+
device_set_wakeup_capable(google->usb_top_pd, true);
338
+
339
+
google->usb_top_pd_dl = device_link_add(google->dev, google->usb_top_pd,
340
+
DL_FLAG_STATELESS);
341
+
if (!google->usb_top_pd_dl) {
342
+
dev_err(google->usb_top_pd, "failed to add device link");
343
+
ret = -ENODEV;
344
+
goto err;
345
+
}
346
+
347
+
return 0;
348
+
349
+
err:
350
+
dwc3_google_pm_domain_deinit(google);
351
+
352
+
return ret;
353
+
}
354
+
355
+
static void dwc3_google_program_usb2only(struct dwc3_google *google)
356
+
{
357
+
u32 reg;
358
+
359
+
regmap_read(google->usb_cfg_regmap,
360
+
google->usbint_cfg_offset + USBCS_TOP_CTRL_CFG1_OFFSET, ®);
361
+
reg |= USBCS_TOP_CTRL_CFG1_USB2ONLY_MODE;
362
+
regmap_write(google->usb_cfg_regmap,
363
+
google->usbint_cfg_offset + USBCS_TOP_CTRL_CFG1_OFFSET, reg);
364
+
}
365
+
366
+
static int dwc3_google_probe(struct platform_device *pdev)
367
+
{
368
+
struct dwc3_probe_data probe_data = {};
369
+
struct device *dev = &pdev->dev;
370
+
struct dwc3_google *google;
371
+
struct resource *res;
372
+
int ret;
373
+
u32 args[2];
374
+
375
+
google = devm_kzalloc(&pdev->dev, sizeof(*google), GFP_KERNEL);
376
+
if (!google)
377
+
return -ENOMEM;
378
+
379
+
google->dev = &pdev->dev;
380
+
381
+
ret = dwc3_google_pm_domain_init(google);
382
+
if (ret < 0)
383
+
return dev_err_probe(dev, ret, "failed to init pdom\n");
384
+
385
+
google->usb_cfg_regmap =
386
+
syscon_regmap_lookup_by_phandle_args(dev->of_node,
387
+
"google,usb-cfg-csr",
388
+
ARRAY_SIZE(args), args);
389
+
if (IS_ERR(google->usb_cfg_regmap)) {
390
+
return dev_err_probe(dev, PTR_ERR(google->usb_cfg_regmap),
391
+
"invalid usb cfg csr\n");
392
+
}
393
+
394
+
google->host_cfg_offset = args[0];
395
+
google->usbint_cfg_offset = args[1];
396
+
397
+
if (device_property_match_string(dev, "phy-names", "usb3-phy") < 0) {
398
+
google->is_usb2only = true;
399
+
dwc3_google_program_usb2only(google);
400
+
}
401
+
402
+
ret = devm_clk_bulk_get_all_enabled(dev, &google->clks);
403
+
if (ret < 0) {
404
+
ret = dev_err_probe(dev, ret, "failed to get and enable clks\n");
405
+
goto err_deinit_pdom;
406
+
}
407
+
google->num_clks = ret;
408
+
409
+
ret = dwc3_google_rst_init(google);
410
+
if (ret) {
411
+
ret = dev_err_probe(dev, ret, "failed to get resets\n");
412
+
goto err_deinit_pdom;
413
+
}
414
+
415
+
ret = reset_control_bulk_deassert(google->num_rsts, google->rsts);
416
+
if (ret) {
417
+
ret = dev_err_probe(dev, ret, "failed to deassert rsts\n");
418
+
goto err_deinit_pdom;
419
+
}
420
+
421
+
ret = dwc3_google_request_irq(google, pdev, "hs_pme", "USB HS wakeup");
422
+
if (ret < 0) {
423
+
ret = dev_err_probe(dev, ret, "failed to request hs pme irq");
424
+
goto err_reset_assert;
425
+
}
426
+
google->hs_pme_irq = ret;
427
+
428
+
ret = dwc3_google_request_irq(google, pdev, "ss_pme", "USB SS wakeup");
429
+
if (ret < 0) {
430
+
ret = dev_err_probe(dev, ret, "failed to request ss pme irq");
431
+
goto err_reset_assert;
432
+
}
433
+
google->ss_pme_irq = ret;
434
+
435
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
436
+
if (!res) {
437
+
ret = dev_err_probe(dev, -ENODEV, "invalid memory\n");
438
+
goto err_reset_assert;
439
+
}
440
+
441
+
device_init_wakeup(dev, true);
442
+
443
+
google->dwc.dev = dev;
444
+
probe_data.dwc = &google->dwc;
445
+
probe_data.res = res;
446
+
probe_data.ignore_clocks_and_resets = true;
447
+
ret = dwc3_core_probe(&probe_data);
448
+
if (ret) {
449
+
ret = dev_err_probe(dev, ret, "failed to register DWC3 Core\n");
450
+
goto err_reset_assert;
451
+
}
452
+
453
+
return 0;
454
+
455
+
err_reset_assert:
456
+
reset_control_bulk_assert(google->num_rsts, google->rsts);
457
+
458
+
err_deinit_pdom:
459
+
dwc3_google_pm_domain_deinit(google);
460
+
461
+
return ret;
462
+
}
463
+
464
+
static void dwc3_google_remove(struct platform_device *pdev)
465
+
{
466
+
struct dwc3 *dwc = platform_get_drvdata(pdev);
467
+
struct dwc3_google *google = to_dwc3_google(dwc);
468
+
469
+
dwc3_core_remove(&google->dwc);
470
+
471
+
reset_control_bulk_assert(google->num_rsts, google->rsts);
472
+
473
+
dwc3_google_pm_domain_deinit(google);
474
+
}
475
+
476
+
static int dwc3_google_suspend(struct dwc3_google *google, pm_message_t msg)
477
+
{
478
+
if (pm_runtime_suspended(google->dev))
479
+
return 0;
480
+
481
+
if (google->dwc.current_dr_role == DWC3_GCTL_PRTCAP_HOST) {
482
+
/*
483
+
* Follow dwc3_suspend_common() guidelines for deciding between
484
+
* a full teardown and hibernation.
485
+
*/
486
+
if (PMSG_IS_AUTO(msg) || device_may_wakeup(google->dev)) {
487
+
dev_dbg(google->dev, "enter hibernation");
488
+
pm_runtime_get_sync(google->usb_top_pd);
489
+
device_wakeup_enable(google->usb_top_pd);
490
+
dwc3_google_enable_pme_irq(google);
491
+
google->is_hibernation = true;
492
+
return 0;
493
+
}
494
+
}
495
+
496
+
reset_control_bulk_assert(google->num_rsts, google->rsts);
497
+
clk_bulk_disable_unprepare(google->num_clks, google->clks);
498
+
499
+
return 0;
500
+
}
501
+
502
+
static int dwc3_google_resume(struct dwc3_google *google, pm_message_t msg)
503
+
{
504
+
int ret;
505
+
506
+
if (google->is_hibernation) {
507
+
dev_dbg(google->dev, "exit hibernation");
508
+
dwc3_google_disable_pme_irq(google);
509
+
device_wakeup_disable(google->usb_top_pd);
510
+
pm_runtime_put_sync(google->usb_top_pd);
511
+
google->is_hibernation = false;
512
+
return 0;
513
+
}
514
+
515
+
if (google->is_usb2only)
516
+
dwc3_google_program_usb2only(google);
517
+
518
+
ret = clk_bulk_prepare_enable(google->num_clks, google->clks);
519
+
if (ret)
520
+
return ret;
521
+
522
+
ret = reset_control_bulk_deassert(google->num_rsts, google->rsts);
523
+
if (ret) {
524
+
clk_bulk_disable_unprepare(google->num_clks, google->clks);
525
+
return ret;
526
+
}
527
+
528
+
return 0;
529
+
}
530
+
531
+
static int dwc3_google_pm_suspend(struct device *dev)
532
+
{
533
+
struct dwc3 *dwc = dev_get_drvdata(dev);
534
+
struct dwc3_google *google = to_dwc3_google(dwc);
535
+
int ret;
536
+
537
+
ret = dwc3_pm_suspend(&google->dwc);
538
+
if (ret)
539
+
return ret;
540
+
541
+
return dwc3_google_suspend(google, PMSG_SUSPEND);
542
+
}
543
+
544
+
static int dwc3_google_pm_resume(struct device *dev)
545
+
{
546
+
struct dwc3 *dwc = dev_get_drvdata(dev);
547
+
struct dwc3_google *google = to_dwc3_google(dwc);
548
+
int ret;
549
+
550
+
ret = dwc3_google_resume(google, PMSG_RESUME);
551
+
if (ret)
552
+
return ret;
553
+
554
+
return dwc3_pm_resume(&google->dwc);
555
+
}
556
+
557
+
static void dwc3_google_complete(struct device *dev)
558
+
{
559
+
struct dwc3 *dwc = dev_get_drvdata(dev);
560
+
561
+
dwc3_pm_complete(dwc);
562
+
}
563
+
564
+
static int dwc3_google_prepare(struct device *dev)
565
+
{
566
+
struct dwc3 *dwc = dev_get_drvdata(dev);
567
+
568
+
return dwc3_pm_prepare(dwc);
569
+
}
570
+
571
+
static int dwc3_google_runtime_suspend(struct device *dev)
572
+
{
573
+
struct dwc3 *dwc = dev_get_drvdata(dev);
574
+
struct dwc3_google *google = to_dwc3_google(dwc);
575
+
int ret;
576
+
577
+
ret = dwc3_runtime_suspend(&google->dwc);
578
+
if (ret)
579
+
return ret;
580
+
581
+
return dwc3_google_suspend(google, PMSG_AUTO_SUSPEND);
582
+
}
583
+
584
+
static int dwc3_google_runtime_resume(struct device *dev)
585
+
{
586
+
struct dwc3 *dwc = dev_get_drvdata(dev);
587
+
struct dwc3_google *google = to_dwc3_google(dwc);
588
+
int ret;
589
+
590
+
ret = dwc3_google_resume(google, PMSG_AUTO_RESUME);
591
+
if (ret)
592
+
return ret;
593
+
594
+
return dwc3_runtime_resume(&google->dwc);
595
+
}
596
+
597
+
static int dwc3_google_runtime_idle(struct device *dev)
598
+
{
599
+
return dwc3_runtime_idle(dev_get_drvdata(dev));
600
+
}
601
+
602
+
static const struct dev_pm_ops dwc3_google_dev_pm_ops = {
603
+
SYSTEM_SLEEP_PM_OPS(dwc3_google_pm_suspend, dwc3_google_pm_resume)
604
+
RUNTIME_PM_OPS(dwc3_google_runtime_suspend, dwc3_google_runtime_resume,
605
+
dwc3_google_runtime_idle)
606
+
.complete = pm_sleep_ptr(dwc3_google_complete),
607
+
.prepare = pm_sleep_ptr(dwc3_google_prepare),
608
+
};
609
+
610
+
static const struct of_device_id dwc3_google_of_match[] = {
611
+
{ .compatible = "google,lga-dwc3" },
612
+
{ }
613
+
};
614
+
MODULE_DEVICE_TABLE(of, dwc3_google_of_match);
615
+
616
+
static struct platform_driver dwc3_google_driver = {
617
+
.probe = dwc3_google_probe,
618
+
.remove = dwc3_google_remove,
619
+
.driver = {
620
+
.name = "dwc3-google",
621
+
.pm = pm_ptr(&dwc3_google_dev_pm_ops),
622
+
.of_match_table = dwc3_google_of_match,
623
+
},
624
+
};
625
+
626
+
module_platform_driver(dwc3_google_driver);
627
+
MODULE_LICENSE("GPL");
628
+
MODULE_DESCRIPTION("DesignWare DWC3 Google Glue Driver");