clk: renesas: rzv2h: Skip monitor checks for external clocks

For module clocks whose parent mux may select an external source, bypass
the normal monitor (CLK_MON) register check when the external clock is
active. Introduce a new `ext_clk_mux_index` in `struct rzv2h_mod_clk` and
`struct mod_clock`, and detect the current mux index in
`rzv2h_mod_clock_is_enabled()` to disable monitoring if it matches the
external source index.

Provide the `DEF_MOD_MUX_EXTERNAL()` macro for declaring external-source
module clocks, and populate the `ext_clk_mux_index` field in
`rzv2h_cpg_register_mod_clk()`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250509160121.331073-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Lad Prabhakar and committed by

Geert Uytterhoeven 1 year ago 899e7ede 19272b37

+41 -6

2 changed files

expand all

drivers

clk

renesas

rzv2h-cpg.c

rzv2h-cpg.h

+28 -2

drivers/clk/renesas/rzv2h-cpg.c

··· 119 119 * @on_bit: ON/MON bit 120 120 * @mon_index: monitor register offset 121 121 * @mon_bit: monitor bit 122 + * @ext_clk_mux_index: mux index for external clock source, or -1 if internal 122 123 */ 123 124 struct mod_clock { 124 125 struct rzv2h_cpg_priv *priv; ··· 130 129 u8 on_bit; 131 130 s8 mon_index; 132 131 u8 mon_bit; 132 + s8 ext_clk_mux_index; 133 133 }; 134 134 135 135 #define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw) ··· 565 563 spin_unlock_irqrestore(&priv->rmw_lock, flags); 566 564 } 567 565 566 + static int rzv2h_parent_clk_mux_to_index(struct clk_hw *hw) 567 + { 568 + struct clk_hw *parent_hw; 569 + struct clk *parent_clk; 570 + struct clk_mux *mux; 571 + u32 val; 572 + 573 + /* This will always succeed, so no need to check for IS_ERR() */ 574 + parent_clk = clk_get_parent(hw->clk); 575 + 576 + parent_hw = __clk_get_hw(parent_clk); 577 + mux = to_clk_mux(parent_hw); 578 + 579 + val = readl(mux->reg) >> mux->shift; 580 + val &= mux->mask; 581 + return clk_mux_val_to_index(parent_hw, mux->table, 0, val); 582 + } 583 + 568 584 static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw) 569 585 { 570 586 struct mod_clock *clock = to_mod_clock(hw); 571 587 struct rzv2h_cpg_priv *priv = clock->priv; 588 + int mon_index = clock->mon_index; 572 589 u32 bitmask; 573 590 u32 offset; 574 591 575 - if (clock->mon_index >= 0) { 576 - offset = GET_CLK_MON_OFFSET(clock->mon_index); 592 + if (clock->ext_clk_mux_index >= 0 && 593 + rzv2h_parent_clk_mux_to_index(hw) == clock->ext_clk_mux_index) 594 + mon_index = -1; 595 + 596 + if (mon_index >= 0) { 597 + offset = GET_CLK_MON_OFFSET(mon_index); 577 598 bitmask = BIT(clock->mon_bit); 578 599 579 600 if (!(readl(priv->base + offset) & bitmask)) ··· 712 687 clock->mon_index = mod->mon_index; 713 688 clock->mon_bit = mod->mon_bit; 714 689 clock->no_pm = mod->no_pm; 690 + clock->ext_clk_mux_index = mod->ext_clk_mux_index; 715 691 clock->priv = priv; 716 692 clock->hw.init = &init; 717 693 clock->mstop_data = mod->mstop_data;

+13 -4

drivers/clk/renesas/rzv2h-cpg.h

··· 199 199 * @on_bit: ON bit 200 200 * @mon_index: monitor register index 201 201 * @mon_bit: monitor bit 202 + * @ext_clk_mux_index: mux index for external clock source, or -1 if internal 202 203 */ 203 204 struct rzv2h_mod_clk { 204 205 const char *name; ··· 211 210 u8 on_bit; 212 211 s8 mon_index; 213 212 u8 mon_bit; 213 + s8 ext_clk_mux_index; 214 214 }; 215 215 216 - #define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \ 216 + #define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \ 217 + _onbit, _monindex, _monbit, _ext_clk_mux_index) \ 217 218 { \ 218 219 .name = (_name), \ 219 220 .mstop_data = (_mstop), \ ··· 226 223 .on_bit = (_onbit), \ 227 224 .mon_index = (_monindex), \ 228 225 .mon_bit = (_monbit), \ 226 + .ext_clk_mux_index = (_ext_clk_mux_index), \ 229 227 } 230 228 231 229 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 232 - DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) 230 + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, -1) 233 231 234 232 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 235 - DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit) 233 + DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, -1) 236 234 237 235 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 238 - DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit) 236 + DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, -1) 237 + 238 + #define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \ 239 + _ext_clk_mux_index) \ 240 + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \ 241 + _ext_clk_mux_index) 239 242 240 243 /** 241 244 * struct rzv2h_reset - Reset definitions

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