Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux
Tariq Toukan says:
====================
mlx5-next updates 2025-03-10
The following pull-request contains common mlx5 updates for your *net-next* tree.
Please pull and let me know of any problem.
* 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux:
net/mlx5: Add IFC bits for PPCNT recovery counters group
net/mlx5: fs, add RDMA TRANSPORT steering domain support
net/mlx5: Query ADV_RDMA capabilities
net/mlx5: Limit non-privileged commands
net/mlx5: Allow the throttle mechanism to be more dynamic
net/mlx5: Add RDMA_CTRL HW capabilities
====================
Link: https://patch.msgid.link/1741608293-41436-1-git-send-email-tariqt@nvidia.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+379
-40
+104
-16
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
+104
-16
drivers/net/ethernet/mellanox/mlx5/core/cmd.c
···
94
94
return MLX5_GET(mbox_in, in, opcode);
95
95
}
96
96
97
+
static u16 in_to_uid(void *in)
98
+
{
99
+
return MLX5_GET(mbox_in, in, uid);
100
+
}
101
+
97
102
/* Returns true for opcodes that might be triggered very frequently and throttle
98
103
* the command interface. Limit their command slots usage.
99
104
*/
···
828
823
829
824
opcode = in_to_opcode(in);
830
825
op_mod = MLX5_GET(mbox_in, in, op_mod);
831
-
uid = MLX5_GET(mbox_in, in, uid);
826
+
uid = in_to_uid(in);
832
827
status = MLX5_GET(mbox_out, out, status);
833
828
834
829
if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY &&
···
1876
1871
return in_to_opcode(in) == MLX5_CMD_OP_MANAGE_PAGES;
1877
1872
}
1878
1873
1874
+
static bool mlx5_has_privileged_uid(struct mlx5_core_dev *dev)
1875
+
{
1876
+
return !xa_empty(&dev->cmd.vars.privileged_uids);
1877
+
}
1878
+
1879
+
static bool mlx5_cmd_is_privileged_uid(struct mlx5_core_dev *dev,
1880
+
u16 uid)
1881
+
{
1882
+
return !!xa_load(&dev->cmd.vars.privileged_uids, uid);
1883
+
}
1884
+
1879
1885
/* Notes:
1880
1886
* 1. Callback functions may not sleep
1881
1887
* 2. Page queue commands do not support asynchrous completion
···
1897
1881
{
1898
1882
struct mlx5_cmd_msg *inb, *outb;
1899
1883
u16 opcode = in_to_opcode(in);
1900
-
bool throttle_op;
1884
+
bool throttle_locked = false;
1885
+
bool unpriv_locked = false;
1886
+
u16 uid = in_to_uid(in);
1901
1887
int pages_queue;
1902
1888
gfp_t gfp;
1903
1889
u8 token;
···
1908
1890
if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, opcode))
1909
1891
return -ENXIO;
1910
1892
1911
-
throttle_op = mlx5_cmd_is_throttle_opcode(opcode);
1912
-
if (throttle_op) {
1913
-
if (callback) {
1914
-
if (down_trylock(&dev->cmd.vars.throttle_sem))
1915
-
return -EBUSY;
1916
-
} else {
1893
+
if (!callback) {
1894
+
/* The semaphore is already held for callback commands. It was
1895
+
* acquired in mlx5_cmd_exec_cb()
1896
+
*/
1897
+
if (uid && mlx5_has_privileged_uid(dev)) {
1898
+
if (!mlx5_cmd_is_privileged_uid(dev, uid)) {
1899
+
unpriv_locked = true;
1900
+
down(&dev->cmd.vars.unprivileged_sem);
1901
+
}
1902
+
} else if (mlx5_cmd_is_throttle_opcode(opcode)) {
1903
+
throttle_locked = true;
1917
1904
down(&dev->cmd.vars.throttle_sem);
1918
1905
}
1919
1906
}
···
1964
1941
out_in:
1965
1942
free_msg(dev, inb);
1966
1943
out_up:
1967
-
if (throttle_op)
1944
+
if (throttle_locked)
1968
1945
up(&dev->cmd.vars.throttle_sem);
1946
+
if (unpriv_locked)
1947
+
up(&dev->cmd.vars.unprivileged_sem);
1948
+
1969
1949
return err;
1970
1950
}
1971
1951
···
2130
2104
struct mlx5_async_work *work = _work;
2131
2105
struct mlx5_async_ctx *ctx;
2132
2106
struct mlx5_core_dev *dev;
2133
-
u16 opcode;
2107
+
bool throttle_locked;
2108
+
bool unpriv_locked;
2134
2109
2135
2110
ctx = work->ctx;
2136
2111
dev = ctx->dev;
2137
-
opcode = work->opcode;
2112
+
throttle_locked = work->throttle_locked;
2113
+
unpriv_locked = work->unpriv_locked;
2138
2114
status = cmd_status_err(dev, status, work->opcode, work->op_mod, work->out);
2139
2115
work->user_callback(status, work);
2140
2116
/* Can't access "work" from this point on. It could have been freed in
2141
2117
* the callback.
2142
2118
*/
2143
-
if (mlx5_cmd_is_throttle_opcode(opcode))
2119
+
if (throttle_locked)
2144
2120
up(&dev->cmd.vars.throttle_sem);
2121
+
if (unpriv_locked)
2122
+
up(&dev->cmd.vars.unprivileged_sem);
2145
2123
if (atomic_dec_and_test(&ctx->num_inflight))
2146
2124
complete(&ctx->inflight_done);
2147
2125
}
···
2154
2124
void *out, int out_size, mlx5_async_cbk_t callback,
2155
2125
struct mlx5_async_work *work)
2156
2126
{
2127
+
struct mlx5_core_dev *dev = ctx->dev;
2128
+
u16 uid;
2157
2129
int ret;
2158
2130
2159
2131
work->ctx = ctx;
···
2163
2131
work->opcode = in_to_opcode(in);
2164
2132
work->op_mod = MLX5_GET(mbox_in, in, op_mod);
2165
2133
work->out = out;
2134
+
work->throttle_locked = false;
2135
+
work->unpriv_locked = false;
2136
+
uid = in_to_uid(in);
2137
+
2166
2138
if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight)))
2167
2139
return -EIO;
2168
-
ret = cmd_exec(ctx->dev, in, in_size, out, out_size,
2140
+
2141
+
if (uid && mlx5_has_privileged_uid(dev)) {
2142
+
if (!mlx5_cmd_is_privileged_uid(dev, uid)) {
2143
+
if (down_trylock(&dev->cmd.vars.unprivileged_sem)) {
2144
+
ret = -EBUSY;
2145
+
goto dec_num_inflight;
2146
+
}
2147
+
work->unpriv_locked = true;
2148
+
}
2149
+
} else if (mlx5_cmd_is_throttle_opcode(in_to_opcode(in))) {
2150
+
if (down_trylock(&dev->cmd.vars.throttle_sem)) {
2151
+
ret = -EBUSY;
2152
+
goto dec_num_inflight;
2153
+
}
2154
+
work->throttle_locked = true;
2155
+
}
2156
+
2157
+
ret = cmd_exec(dev, in, in_size, out, out_size,
2169
2158
mlx5_cmd_exec_cb_handler, work, false);
2170
-
if (ret && atomic_dec_and_test(&ctx->num_inflight))
2159
+
if (ret)
2160
+
goto sem_up;
2161
+
2162
+
return 0;
2163
+
2164
+
sem_up:
2165
+
if (work->throttle_locked)
2166
+
up(&dev->cmd.vars.throttle_sem);
2167
+
if (work->unpriv_locked)
2168
+
up(&dev->cmd.vars.unprivileged_sem);
2169
+
dec_num_inflight:
2170
+
if (atomic_dec_and_test(&ctx->num_inflight))
2171
2171
complete(&ctx->inflight_done);
2172
2172
2173
2173
return ret;
···
2435
2371
sema_init(&cmd->vars.sem, cmd->vars.max_reg_cmds);
2436
2372
sema_init(&cmd->vars.pages_sem, 1);
2437
2373
sema_init(&cmd->vars.throttle_sem, DIV_ROUND_UP(cmd->vars.max_reg_cmds, 2));
2374
+
sema_init(&cmd->vars.unprivileged_sem,
2375
+
DIV_ROUND_UP(cmd->vars.max_reg_cmds, 2));
2376
+
2377
+
xa_init(&cmd->vars.privileged_uids);
2438
2378
2439
2379
cmd->pool = dma_pool_create("mlx5_cmd", mlx5_core_dma_dev(dev), size, align, 0);
2440
-
if (!cmd->pool)
2441
-
return -ENOMEM;
2380
+
if (!cmd->pool) {
2381
+
err = -ENOMEM;
2382
+
goto err_destroy_xa;
2383
+
}
2442
2384
2443
2385
err = alloc_cmd_page(dev, cmd);
2444
2386
if (err)
···
2478
2408
free_cmd_page(dev, cmd);
2479
2409
err_free_pool:
2480
2410
dma_pool_destroy(cmd->pool);
2411
+
err_destroy_xa:
2412
+
xa_destroy(&dev->cmd.vars.privileged_uids);
2481
2413
return err;
2482
2414
}
2483
2415
···
2492
2420
destroy_msg_cache(dev);
2493
2421
free_cmd_page(dev, cmd);
2494
2422
dma_pool_destroy(cmd->pool);
2423
+
xa_destroy(&dev->cmd.vars.privileged_uids);
2495
2424
}
2496
2425
2497
2426
void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
···
2500
2427
{
2501
2428
dev->cmd.state = cmdif_state;
2502
2429
}
2430
+
2431
+
int mlx5_cmd_add_privileged_uid(struct mlx5_core_dev *dev, u16 uid)
2432
+
{
2433
+
return xa_insert(&dev->cmd.vars.privileged_uids, uid,
2434
+
xa_mk_value(uid), GFP_KERNEL);
2435
+
}
2436
+
EXPORT_SYMBOL(mlx5_cmd_add_privileged_uid);
2437
+
2438
+
void mlx5_cmd_remove_privileged_uid(struct mlx5_core_dev *dev, u16 uid)
2439
+
{
2440
+
void *data = xa_erase(&dev->cmd.vars.privileged_uids, uid);
2441
+
2442
+
WARN(!data, "Privileged UID %u does not exist\n", uid);
2443
+
}
2444
+
EXPORT_SYMBOL(mlx5_cmd_remove_privileged_uid);
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/esw/acl/helper.c
+1
-1
drivers/net/ethernet/mellanox/mlx5/core/esw/acl/helper.c
···
27
27
esw_debug(dev, "Create vport[%d] %s ACL table\n", vport_num,
28
28
ns == MLX5_FLOW_NAMESPACE_ESW_INGRESS ? "ingress" : "egress");
29
29
30
-
root_ns = mlx5_get_flow_vport_acl_namespace(dev, ns, vport->index);
30
+
root_ns = mlx5_get_flow_vport_namespace(dev, ns, vport->index);
31
31
if (!root_ns) {
32
32
esw_warn(dev, "Failed to get E-Switch root namespace for vport (%d)\n",
33
33
vport_num);
+3
-3
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c
+3
-3
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c
···
2828
2828
if (IS_ERR(vport))
2829
2829
return PTR_ERR(vport);
2830
2830
2831
-
egress_ns = mlx5_get_flow_vport_acl_namespace(master,
2832
-
MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2833
-
vport->index);
2831
+
egress_ns = mlx5_get_flow_vport_namespace(master,
2832
+
MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2833
+
vport->index);
2834
2834
if (!egress_ns)
2835
2835
return -EINVAL;
2836
2836
+2
drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c
+2
drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c
+166
-12
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
+166
-12
drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
···
1456
1456
struct mlx5_flow_table *ft;
1457
1457
int autogroups_max_fte;
1458
1458
1459
-
ft = mlx5_create_flow_table(ns, ft_attr);
1459
+
ft = mlx5_create_vport_flow_table(ns, ft_attr, ft_attr->vport);
1460
1460
if (IS_ERR(ft))
1461
1461
return ft;
1462
1462
···
2764
2764
}
2765
2765
EXPORT_SYMBOL(mlx5_get_flow_namespace);
2766
2766
2767
-
struct mlx5_flow_namespace *mlx5_get_flow_vport_acl_namespace(struct mlx5_core_dev *dev,
2768
-
enum mlx5_flow_namespace_type type,
2769
-
int vport)
2767
+
struct mlx5_flow_namespace *
2768
+
mlx5_get_flow_vport_namespace(struct mlx5_core_dev *dev,
2769
+
enum mlx5_flow_namespace_type type, int vport_idx)
2770
2770
{
2771
2771
struct mlx5_flow_steering *steering = dev->priv.steering;
2772
2772
···
2775
2775
2776
2776
switch (type) {
2777
2777
case MLX5_FLOW_NAMESPACE_ESW_EGRESS:
2778
-
if (vport >= steering->esw_egress_acl_vports)
2778
+
if (vport_idx >= steering->esw_egress_acl_vports)
2779
2779
return NULL;
2780
2780
if (steering->esw_egress_root_ns &&
2781
-
steering->esw_egress_root_ns[vport])
2782
-
return &steering->esw_egress_root_ns[vport]->ns;
2781
+
steering->esw_egress_root_ns[vport_idx])
2782
+
return &steering->esw_egress_root_ns[vport_idx]->ns;
2783
2783
else
2784
2784
return NULL;
2785
2785
case MLX5_FLOW_NAMESPACE_ESW_INGRESS:
2786
-
if (vport >= steering->esw_ingress_acl_vports)
2786
+
if (vport_idx >= steering->esw_ingress_acl_vports)
2787
2787
return NULL;
2788
2788
if (steering->esw_ingress_root_ns &&
2789
-
steering->esw_ingress_root_ns[vport])
2790
-
return &steering->esw_ingress_root_ns[vport]->ns;
2789
+
steering->esw_ingress_root_ns[vport_idx])
2790
+
return &steering->esw_ingress_root_ns[vport_idx]->ns;
2791
+
else
2792
+
return NULL;
2793
+
case MLX5_FLOW_NAMESPACE_RDMA_TRANSPORT_RX:
2794
+
if (vport_idx >= steering->rdma_transport_rx_vports)
2795
+
return NULL;
2796
+
if (steering->rdma_transport_rx_root_ns &&
2797
+
steering->rdma_transport_rx_root_ns[vport_idx])
2798
+
return &steering->rdma_transport_rx_root_ns[vport_idx]->ns;
2799
+
else
2800
+
return NULL;
2801
+
case MLX5_FLOW_NAMESPACE_RDMA_TRANSPORT_TX:
2802
+
if (vport_idx >= steering->rdma_transport_tx_vports)
2803
+
return NULL;
2804
+
2805
+
if (steering->rdma_transport_tx_root_ns &&
2806
+
steering->rdma_transport_tx_root_ns[vport_idx])
2807
+
return &steering->rdma_transport_tx_root_ns[vport_idx]->ns;
2791
2808
else
2792
2809
return NULL;
2793
2810
default:
2794
2811
return NULL;
2795
2812
}
2796
2813
}
2814
+
EXPORT_SYMBOL(mlx5_get_flow_vport_namespace);
2797
2815
2798
2816
static struct fs_prio *_fs_create_prio(struct mlx5_flow_namespace *ns,
2799
2817
unsigned int prio,
···
3215
3197
cleanup_root_ns(steering->rdma_tx_root_ns);
3216
3198
steering->rdma_tx_root_ns = NULL;
3217
3199
return err;
3200
+
}
3201
+
3202
+
static int
3203
+
init_rdma_transport_rx_root_ns_one(struct mlx5_flow_steering *steering,
3204
+
int vport_idx)
3205
+
{
3206
+
struct fs_prio *prio;
3207
+
3208
+
steering->rdma_transport_rx_root_ns[vport_idx] =
3209
+
create_root_ns(steering, FS_FT_RDMA_TRANSPORT_RX);
3210
+
if (!steering->rdma_transport_rx_root_ns[vport_idx])
3211
+
return -ENOMEM;
3212
+
3213
+
/* create 1 prio*/
3214
+
prio = fs_create_prio(&steering->rdma_transport_rx_root_ns[vport_idx]->ns,
3215
+
MLX5_RDMA_TRANSPORT_BYPASS_PRIO, 1);
3216
+
return PTR_ERR_OR_ZERO(prio);
3217
+
}
3218
+
3219
+
static int
3220
+
init_rdma_transport_tx_root_ns_one(struct mlx5_flow_steering *steering,
3221
+
int vport_idx)
3222
+
{
3223
+
struct fs_prio *prio;
3224
+
3225
+
steering->rdma_transport_tx_root_ns[vport_idx] =
3226
+
create_root_ns(steering, FS_FT_RDMA_TRANSPORT_TX);
3227
+
if (!steering->rdma_transport_tx_root_ns[vport_idx])
3228
+
return -ENOMEM;
3229
+
3230
+
/* create 1 prio*/
3231
+
prio = fs_create_prio(&steering->rdma_transport_tx_root_ns[vport_idx]->ns,
3232
+
MLX5_RDMA_TRANSPORT_BYPASS_PRIO, 1);
3233
+
return PTR_ERR_OR_ZERO(prio);
3234
+
}
3235
+
3236
+
static int init_rdma_transport_rx_root_ns(struct mlx5_flow_steering *steering)
3237
+
{
3238
+
struct mlx5_core_dev *dev = steering->dev;
3239
+
int total_vports;
3240
+
int err;
3241
+
int i;
3242
+
3243
+
/* In case eswitch not supported and working in legacy mode */
3244
+
total_vports = mlx5_eswitch_get_total_vports(dev) ?: 1;
3245
+
3246
+
steering->rdma_transport_rx_root_ns =
3247
+
kcalloc(total_vports,
3248
+
sizeof(*steering->rdma_transport_rx_root_ns),
3249
+
GFP_KERNEL);
3250
+
if (!steering->rdma_transport_rx_root_ns)
3251
+
return -ENOMEM;
3252
+
3253
+
for (i = 0; i < total_vports; i++) {
3254
+
err = init_rdma_transport_rx_root_ns_one(steering, i);
3255
+
if (err)
3256
+
goto cleanup_root_ns;
3257
+
}
3258
+
steering->rdma_transport_rx_vports = total_vports;
3259
+
return 0;
3260
+
3261
+
cleanup_root_ns:
3262
+
while (i--)
3263
+
cleanup_root_ns(steering->rdma_transport_rx_root_ns[i]);
3264
+
kfree(steering->rdma_transport_rx_root_ns);
3265
+
steering->rdma_transport_rx_root_ns = NULL;
3266
+
return err;
3267
+
}
3268
+
3269
+
static int init_rdma_transport_tx_root_ns(struct mlx5_flow_steering *steering)
3270
+
{
3271
+
struct mlx5_core_dev *dev = steering->dev;
3272
+
int total_vports;
3273
+
int err;
3274
+
int i;
3275
+
3276
+
/* In case eswitch not supported and working in legacy mode */
3277
+
total_vports = mlx5_eswitch_get_total_vports(dev) ?: 1;
3278
+
3279
+
steering->rdma_transport_tx_root_ns =
3280
+
kcalloc(total_vports,
3281
+
sizeof(*steering->rdma_transport_tx_root_ns),
3282
+
GFP_KERNEL);
3283
+
if (!steering->rdma_transport_tx_root_ns)
3284
+
return -ENOMEM;
3285
+
3286
+
for (i = 0; i < total_vports; i++) {
3287
+
err = init_rdma_transport_tx_root_ns_one(steering, i);
3288
+
if (err)
3289
+
goto cleanup_root_ns;
3290
+
}
3291
+
steering->rdma_transport_tx_vports = total_vports;
3292
+
return 0;
3293
+
3294
+
cleanup_root_ns:
3295
+
while (i--)
3296
+
cleanup_root_ns(steering->rdma_transport_tx_root_ns[i]);
3297
+
kfree(steering->rdma_transport_tx_root_ns);
3298
+
steering->rdma_transport_tx_root_ns = NULL;
3299
+
return err;
3300
+
}
3301
+
3302
+
static void cleanup_rdma_transport_roots_ns(struct mlx5_flow_steering *steering)
3303
+
{
3304
+
int i;
3305
+
3306
+
if (steering->rdma_transport_rx_root_ns) {
3307
+
for (i = 0; i < steering->rdma_transport_rx_vports; i++)
3308
+
cleanup_root_ns(steering->rdma_transport_rx_root_ns[i]);
3309
+
3310
+
kfree(steering->rdma_transport_rx_root_ns);
3311
+
steering->rdma_transport_rx_root_ns = NULL;
3312
+
}
3313
+
3314
+
if (steering->rdma_transport_tx_root_ns) {
3315
+
for (i = 0; i < steering->rdma_transport_tx_vports; i++)
3316
+
cleanup_root_ns(steering->rdma_transport_tx_root_ns[i]);
3317
+
3318
+
kfree(steering->rdma_transport_tx_root_ns);
3319
+
steering->rdma_transport_tx_root_ns = NULL;
3320
+
}
3218
3321
}
3219
3322
3220
3323
/* FT and tc chains are stored in the same array so we can re-use the
···
3770
3631
cleanup_root_ns(steering->rdma_rx_root_ns);
3771
3632
cleanup_root_ns(steering->rdma_tx_root_ns);
3772
3633
cleanup_root_ns(steering->egress_root_ns);
3634
+
cleanup_rdma_transport_roots_ns(steering);
3773
3635
3774
3636
devl_params_unregister(priv_to_devlink(dev), mlx5_fs_params,
3775
3637
ARRAY_SIZE(mlx5_fs_params));
···
3836
3696
3837
3697
if (MLX5_CAP_FLOWTABLE_NIC_TX(dev, ft_support)) {
3838
3698
err = init_egress_root_ns(steering);
3699
+
if (err)
3700
+
goto err;
3701
+
}
3702
+
3703
+
if (MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(dev, ft_support)) {
3704
+
err = init_rdma_transport_rx_root_ns(steering);
3705
+
if (err)
3706
+
goto err;
3707
+
}
3708
+
3709
+
if (MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(dev, ft_support)) {
3710
+
err = init_rdma_transport_tx_root_ns(steering);
3839
3711
if (err)
3840
3712
goto err;
3841
3713
}
···
4002
3850
struct mlx5_flow_namespace *ns;
4003
3851
4004
3852
if (ns_type == MLX5_FLOW_NAMESPACE_ESW_EGRESS ||
4005
-
ns_type == MLX5_FLOW_NAMESPACE_ESW_INGRESS)
4006
-
ns = mlx5_get_flow_vport_acl_namespace(dev, ns_type, 0);
3853
+
ns_type == MLX5_FLOW_NAMESPACE_ESW_INGRESS ||
3854
+
ns_type == MLX5_FLOW_NAMESPACE_RDMA_TRANSPORT_TX ||
3855
+
ns_type == MLX5_FLOW_NAMESPACE_RDMA_TRANSPORT_RX)
3856
+
ns = mlx5_get_flow_vport_namespace(dev, ns_type, 0);
4007
3857
else
4008
3858
ns = mlx5_get_flow_namespace(dev, ns_type);
4009
3859
if (!ns)
+10
-2
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h
+10
-2
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h
···
115
115
FS_FT_PORT_SEL = 0X9,
116
116
FS_FT_FDB_RX = 0xa,
117
117
FS_FT_FDB_TX = 0xb,
118
-
FS_FT_MAX_TYPE = FS_FT_FDB_TX,
118
+
FS_FT_RDMA_TRANSPORT_RX = 0xd,
119
+
FS_FT_RDMA_TRANSPORT_TX = 0xe,
120
+
FS_FT_MAX_TYPE = FS_FT_RDMA_TRANSPORT_TX,
119
121
};
120
122
121
123
enum fs_flow_table_op_mod {
···
160
158
struct mlx5_flow_root_namespace *port_sel_root_ns;
161
159
int esw_egress_acl_vports;
162
160
int esw_ingress_acl_vports;
161
+
struct mlx5_flow_root_namespace **rdma_transport_rx_root_ns;
162
+
struct mlx5_flow_root_namespace **rdma_transport_tx_root_ns;
163
+
int rdma_transport_rx_vports;
164
+
int rdma_transport_tx_vports;
163
165
};
164
166
165
167
struct fs_node {
···
440
434
(type == FS_FT_PORT_SEL) ? MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) : \
441
435
(type == FS_FT_FDB_RX) ? MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) : \
442
436
(type == FS_FT_FDB_TX) ? MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) : \
443
-
(BUILD_BUG_ON_ZERO(FS_FT_FDB_TX != FS_FT_MAX_TYPE))\
437
+
(type == FS_FT_RDMA_TRANSPORT_RX) ? MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(mdev, cap) : \
438
+
(type == FS_FT_RDMA_TRANSPORT_TX) ? MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(mdev, cap) : \
439
+
(BUILD_BUG_ON_ZERO(FS_FT_RDMA_TRANSPORT_TX != FS_FT_MAX_TYPE))\
444
440
)
445
441
446
442
#endif
+7
drivers/net/ethernet/mellanox/mlx5/core/fw.c
+7
drivers/net/ethernet/mellanox/mlx5/core/fw.c
+1
drivers/net/ethernet/mellanox/mlx5/core/main.c
+1
drivers/net/ethernet/mellanox/mlx5/core/main.c
+12
include/linux/mlx5/device.h
+12
include/linux/mlx5/device.h
···
1251
1251
MLX5_CAP_GENERAL_2 = 0x20,
1252
1252
MLX5_CAP_PORT_SELECTION = 0x25,
1253
1253
MLX5_CAP_ADV_VIRTUALIZATION = 0x26,
1254
+
MLX5_CAP_ADV_RDMA = 0x28,
1254
1255
/* NUM OF CAP Types */
1255
1256
MLX5_CAP_NUM
1256
1257
};
···
1346
1345
#define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \
1347
1346
MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1348
1347
1348
+
#define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(mdev, cap) \
1349
+
MLX5_CAP_ADV_RDMA(mdev, rdma_transport_rx_flow_table_properties.cap)
1350
+
1351
+
#define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(mdev, cap) \
1352
+
MLX5_CAP_ADV_RDMA(mdev, rdma_transport_tx_flow_table_properties.cap)
1353
+
1349
1354
#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1350
1355
MLX5_GET(flow_table_eswitch_cap, \
1351
1356
mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
···
1390
1383
#define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \
1391
1384
MLX5_GET(adv_virtualization_cap, \
1392
1385
mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1386
+
1387
+
#define MLX5_CAP_ADV_RDMA(mdev, cap) \
1388
+
MLX5_GET(adv_rdma_cap, \
1389
+
mdev->caps.hca[MLX5_CAP_ADV_RDMA]->cur, cap)
1393
1390
1394
1391
#define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \
1395
1392
MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
···
1517
1506
MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1518
1507
MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13,
1519
1508
MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1509
+
MLX5_PHYSICAL_LAYER_RECOVERY_GROUP = 0x1a,
1520
1510
MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1521
1511
MLX5_INFINIBAND_EXTENDED_PORT_COUNTERS_GROUP = 0x21,
1522
1512
};
+6
include/linux/mlx5/driver.h
+6
include/linux/mlx5/driver.h
···
304
304
struct semaphore sem;
305
305
struct semaphore pages_sem;
306
306
struct semaphore throttle_sem;
307
+
struct semaphore unprivileged_sem;
308
+
struct xarray privileged_uids;
307
309
} vars;
308
310
enum mlx5_cmdif_state state;
309
311
void *cmd_alloc_buf;
···
966
964
mlx5_async_cbk_t user_callback;
967
965
u16 opcode; /* cmd opcode */
968
966
u16 op_mod; /* cmd op_mod */
967
+
u8 throttle_locked:1;
968
+
u8 unpriv_locked:1;
969
969
void *out; /* pointer to the cmd output buffer */
970
970
};
971
971
···
998
994
int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
999
995
void *out, int out_size);
1000
996
bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
997
+
int mlx5_cmd_add_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
998
+
void mlx5_cmd_remove_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1001
999
1002
1000
void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1003
1001
void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
+7
-3
include/linux/mlx5/fs.h
+7
-3
include/linux/mlx5/fs.h
···
40
40
41
41
#define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
42
42
43
+
#define MLX5_RDMA_TRANSPORT_BYPASS_PRIO 0
43
44
#define MLX5_FS_MAX_POOL_SIZE BIT(30)
44
45
45
46
enum mlx5_flow_destination_type {
···
111
110
MLX5_FLOW_NAMESPACE_RDMA_TX_IPSEC,
112
111
MLX5_FLOW_NAMESPACE_RDMA_RX_MACSEC,
113
112
MLX5_FLOW_NAMESPACE_RDMA_TX_MACSEC,
113
+
MLX5_FLOW_NAMESPACE_RDMA_TRANSPORT_RX,
114
+
MLX5_FLOW_NAMESPACE_RDMA_TRANSPORT_TX,
114
115
};
115
116
116
117
enum {
···
197
194
mlx5_get_flow_namespace(struct mlx5_core_dev *dev,
198
195
enum mlx5_flow_namespace_type type);
199
196
struct mlx5_flow_namespace *
200
-
mlx5_get_flow_vport_acl_namespace(struct mlx5_core_dev *dev,
201
-
enum mlx5_flow_namespace_type type,
202
-
int vport);
197
+
mlx5_get_flow_vport_namespace(struct mlx5_core_dev *dev,
198
+
enum mlx5_flow_namespace_type type,
199
+
int vport_idx);
203
200
204
201
struct mlx5_flow_table_attr {
205
202
int prio;
···
207
204
u32 level;
208
205
u32 flags;
209
206
u16 uid;
207
+
u16 vport;
210
208
struct mlx5_flow_table *next_ft;
211
209
212
210
struct {
+60
-3
include/linux/mlx5/mlx5_ifc.h
+60
-3
include/linux/mlx5/mlx5_ifc.h
···
1570
1570
enum {
1571
1571
MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1572
1572
MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1573
+
MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3,
1574
+
MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4,
1573
1575
};
1574
1576
1575
1577
#define MLX5_FC_BULK_SIZE_FACTOR 128
···
1993
1991
u8 max_geneve_tlv_options[0x8];
1994
1992
u8 reserved_at_568[0x3];
1995
1993
u8 max_geneve_tlv_option_data_len[0x5];
1996
-
u8 reserved_at_570[0x9];
1994
+
u8 reserved_at_570[0x1];
1995
+
u8 adv_rdma[0x1];
1996
+
u8 reserved_at_572[0x7];
1997
1997
u8 adv_virtualization[0x1];
1998
1998
u8 reserved_at_57a[0x6];
1999
1999
···
2144
2140
u8 log_min_mkey_entity_size[0x5];
2145
2141
u8 reserved_at_1b0[0x10];
2146
2142
2147
-
u8 reserved_at_1c0[0x60];
2143
+
u8 general_obj_types_127_64[0x40];
2144
+
u8 reserved_at_200[0x20];
2148
2145
2149
2146
u8 reserved_at_220[0x1];
2150
2147
u8 sw_vhca_id_valid[0x1];
···
2643
2638
2644
2639
struct mlx5_ifc_field_select_802_1qau_rp_bits {
2645
2640
u8 field_select_8021qaurp[0x20];
2641
+
};
2642
+
2643
+
struct mlx5_ifc_phys_layer_recovery_cntrs_bits {
2644
+
u8 total_successful_recovery_events[0x20];
2645
+
2646
+
u8 reserved_at_20[0x7a0];
2646
2647
};
2647
2648
2648
2649
struct mlx5_ifc_phys_layer_cntrs_bits {
···
4852
4841
struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
4853
4842
struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4854
4843
struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4844
+
struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs;
4855
4845
u8 reserved_at_0[0x7c0];
4856
4846
};
4857
4847
···
10591
10579
};
10592
10580
10593
10581
struct mlx5_ifc_pcam_enhanced_features_bits {
10594
-
u8 reserved_at_0[0x1d];
10582
+
u8 reserved_at_0[0x10];
10583
+
u8 ppcnt_recovery_counters[0x1];
10584
+
u8 reserved_at_11[0xc];
10595
10585
u8 fec_200G_per_lane_in_pplm[0x1];
10596
10586
u8 reserved_at_1e[0x2a];
10597
10587
u8 fec_100G_per_lane_in_pplm[0x1];
···
12509
12495
};
12510
12496
12511
12497
enum {
12498
+
MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = BIT_ULL(0x13),
12499
+
};
12500
+
12501
+
enum {
12512
12502
MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12513
12503
MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12514
12504
MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12515
12505
MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12516
12506
MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12517
12507
MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12508
+
MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53,
12518
12509
MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12519
12510
};
12520
12511
···
13085
13066
u8 syndrome[0x20];
13086
13067
13087
13068
u8 reserved_at_40[0x40];
13069
+
};
13070
+
13071
+
struct mlx5_ifc_adv_rdma_cap_bits {
13072
+
u8 rdma_transport_manager[0x1];
13073
+
u8 rdma_transport_manager_other_eswitch[0x1];
13074
+
u8 reserved_at_2[0x1e];
13075
+
13076
+
u8 rcx_type[0x8];
13077
+
u8 reserved_at_28[0x2];
13078
+
u8 ps_entry_log_max_value[0x6];
13079
+
u8 reserved_at_30[0x6];
13080
+
u8 qp_max_ps_num_entry[0xa];
13081
+
13082
+
u8 mp_max_num_queues[0x8];
13083
+
u8 ps_user_context_max_log_size[0x8];
13084
+
u8 message_based_qp_and_striding_wq[0x8];
13085
+
u8 reserved_at_58[0x8];
13086
+
13087
+
u8 max_receive_send_message_size_stride[0x10];
13088
+
u8 reserved_at_70[0x10];
13089
+
13090
+
u8 max_receive_send_message_size_byte[0x20];
13091
+
13092
+
u8 reserved_at_a0[0x160];
13093
+
13094
+
struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties;
13095
+
13096
+
struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties;
13097
+
13098
+
struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2;
13099
+
13100
+
struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2;
13101
+
13102
+
struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2;
13103
+
13104
+
struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2;
13105
+
13106
+
u8 reserved_at_800[0x3800];
13088
13107
};
13089
13108
13090
13109
struct mlx5_ifc_adv_virtualization_cap_bits {