Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Define function to readout LT Phy PLL state
Define a function to readout hw state for LT Phy PLL which
can be used in get_config function call.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-23-suraj.kandpal@intel.com
+50
+14
drivers/gpu/drm/i915/display/intel_ddi.c
+14
drivers/gpu/drm/i915/display/intel_ddi.c
···
4246
4246
&crtc_state->dpll_hw_state);
4247
4247
}
4248
4248
4249
+
static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
4250
+
struct intel_crtc_state *crtc_state)
4251
+
{
4252
+
intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll);
4253
+
4254
+
if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
4255
+
crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
4256
+
else
4257
+
crtc_state->port_clock =
4258
+
intel_lt_phy_calc_port_clock(encoder, crtc_state);
4259
+
intel_ddi_get_config(encoder, crtc_state);
4260
+
}
4261
+
4249
4262
static void mtl_ddi_get_config(struct intel_encoder *encoder,
4250
4263
struct intel_crtc_state *crtc_state)
4251
4264
{
···
5254
5241
encoder->enable_clock = intel_xe3plpd_pll_enable;
5255
5242
encoder->disable_clock = intel_xe3plpd_pll_disable;
5256
5243
encoder->port_pll_type = intel_mtl_port_pll_type;
5244
+
encoder->get_config = xe3plpd_ddi_get_config;
5257
5245
} else if (DISPLAY_VER(display) >= 14) {
5258
5246
encoder->enable_clock = intel_mtl_pll_enable;
5259
5247
encoder->disable_clock = intel_mtl_pll_disable;
+33
drivers/gpu/drm/i915/display/intel_lt_phy.c
+33
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
1886
1886
return true;
1887
1887
}
1888
1888
1889
+
void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
1890
+
const struct intel_crtc_state *crtc_state,
1891
+
struct intel_lt_phy_pll_state *pll_state)
1892
+
{
1893
+
u8 owned_lane_mask;
1894
+
u8 lane;
1895
+
intel_wakeref_t wakeref;
1896
+
int i, j, k;
1897
+
1898
+
pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
1899
+
if (pll_state->tbt_mode)
1900
+
return;
1901
+
1902
+
owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
1903
+
lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1;
1904
+
wakeref = intel_lt_phy_transaction_begin(encoder);
1905
+
1906
+
pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG);
1907
+
pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG);
1908
+
pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG);
1909
+
1910
+
for (i = 0; i <= 12; i++) {
1911
+
for (j = 3, k = 0; j >= 0; j--, k++)
1912
+
pll_state->data[i][k] =
1913
+
intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
1914
+
LT_PHY_VDR_X_DATAY(i, j));
1915
+
}
1916
+
1917
+
pll_state->clock =
1918
+
intel_lt_phy_calc_port_clock(encoder, crtc_state);
1919
+
intel_lt_phy_transaction_end(encoder, wakeref);
1920
+
}
1921
+
1889
1922
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
1890
1923
const struct intel_crtc_state *crtc_state)
1891
1924
{
+3
drivers/gpu/drm/i915/display/intel_lt_phy.h
+3
drivers/gpu/drm/i915/display/intel_lt_phy.h
···
28
28
bool
29
29
intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
30
30
const struct intel_lt_phy_pll_state *b);
31
+
void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
32
+
const struct intel_crtc_state *crtc_state,
33
+
struct intel_lt_phy_pll_state *pll_state);
31
34
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
32
35
const struct intel_crtc_state *crtc_state);
33
36
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);