Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpu: host1x: Add context device management code
Add code to register context devices from device tree, allocate them
out and manage their refcounts.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
authored by
Mikko Perttunen
and committed by
Thierry Reding
8aa5bcb6
a72d4b18
+248
-1
+3
drivers/gpu/host1x/Makefile
+3
drivers/gpu/host1x/Makefile
+160
drivers/gpu/host1x/context.c
+160
drivers/gpu/host1x/context.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, NVIDIA Corporation.
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*/
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#include <linux/device.h>
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#include <linux/kref.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/pid.h>
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#include <linux/slab.h>
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#include "context.h"
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#include "dev.h"
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int host1x_memory_context_list_init(struct host1x *host1x)
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{
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struct host1x_memory_context_list *cdl = &host1x->context_list;
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struct device_node *node = host1x->dev->of_node;
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struct host1x_memory_context *ctx;
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unsigned int i;
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int err;
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cdl->devs = NULL;
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cdl->len = 0;
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mutex_init(&cdl->lock);
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err = of_property_count_u32_elems(node, "iommu-map");
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if (err < 0)
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return 0;
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cdl->devs = kcalloc(err, sizeof(*cdl->devs), GFP_KERNEL);
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if (!cdl->devs)
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return -ENOMEM;
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cdl->len = err / 4;
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for (i = 0; i < cdl->len; i++) {
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struct iommu_fwspec *fwspec;
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ctx = &cdl->devs[i];
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ctx->host = host1x;
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device_initialize(&ctx->dev);
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/*
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* Due to an issue with T194 NVENC, only 38 bits can be used.
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* Anyway, 256GiB of IOVA ought to be enough for anyone.
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*/
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ctx->dma_mask = DMA_BIT_MASK(38);
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ctx->dev.dma_mask = &ctx->dma_mask;
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ctx->dev.coherent_dma_mask = ctx->dma_mask;
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dev_set_name(&ctx->dev, "host1x-ctx.%d", i);
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ctx->dev.bus = &host1x_context_device_bus_type;
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ctx->dev.parent = host1x->dev;
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dma_set_max_seg_size(&ctx->dev, UINT_MAX);
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err = device_add(&ctx->dev);
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if (err) {
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dev_err(host1x->dev, "could not add context device %d: %d\n", i, err);
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goto del_devices;
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}
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err = of_dma_configure_id(&ctx->dev, node, true, &i);
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if (err) {
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dev_err(host1x->dev, "IOMMU configuration failed for context device %d: %d\n",
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i, err);
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device_del(&ctx->dev);
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goto del_devices;
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}
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fwspec = dev_iommu_fwspec_get(&ctx->dev);
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if (!fwspec || !device_iommu_mapped(&ctx->dev)) {
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dev_err(host1x->dev, "Context device %d has no IOMMU!\n", i);
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device_del(&ctx->dev);
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goto del_devices;
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}
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ctx->stream_id = fwspec->ids[0] & 0xffff;
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}
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return 0;
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del_devices:
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while (i--)
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device_del(&cdl->devs[i].dev);
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kfree(cdl->devs);
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cdl->len = 0;
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return err;
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}
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void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl)
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{
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unsigned int i;
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for (i = 0; i < cdl->len; i++)
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device_del(&cdl->devs[i].dev);
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kfree(cdl->devs);
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cdl->len = 0;
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}
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struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
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struct pid *pid)
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{
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struct host1x_memory_context_list *cdl = &host1x->context_list;
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struct host1x_memory_context *free = NULL;
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int i;
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if (!cdl->len)
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return ERR_PTR(-EOPNOTSUPP);
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mutex_lock(&cdl->lock);
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for (i = 0; i < cdl->len; i++) {
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struct host1x_memory_context *cd = &cdl->devs[i];
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if (cd->owner == pid) {
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refcount_inc(&cd->ref);
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mutex_unlock(&cdl->lock);
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return cd;
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} else if (!cd->owner && !free) {
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free = cd;
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}
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}
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if (!free) {
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mutex_unlock(&cdl->lock);
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return ERR_PTR(-EBUSY);
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}
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refcount_set(&free->ref, 1);
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free->owner = get_pid(pid);
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mutex_unlock(&cdl->lock);
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return free;
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}
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EXPORT_SYMBOL_GPL(host1x_memory_context_alloc);
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void host1x_memory_context_get(struct host1x_memory_context *cd)
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{
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refcount_inc(&cd->ref);
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}
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EXPORT_SYMBOL_GPL(host1x_memory_context_get);
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void host1x_memory_context_put(struct host1x_memory_context *cd)
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{
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struct host1x_memory_context_list *cdl = &cd->host->context_list;
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if (refcount_dec_and_mutex_lock(&cd->ref, &cdl->lock)) {
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put_pid(cd->owner);
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cd->owner = NULL;
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mutex_unlock(&cdl->lock);
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}
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}
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EXPORT_SYMBOL_GPL(host1x_memory_context_put);
+38
drivers/gpu/host1x/context.h
+38
drivers/gpu/host1x/context.h
···
1
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Host1x context devices
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*
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* Copyright (c) 2020, NVIDIA Corporation.
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*/
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#ifndef __HOST1X_CONTEXT_H
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#define __HOST1X_CONTEXT_H
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#include <linux/mutex.h>
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#include <linux/refcount.h>
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struct host1x;
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extern struct bus_type host1x_context_device_bus_type;
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struct host1x_memory_context_list {
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struct mutex lock;
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struct host1x_memory_context *devs;
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unsigned int len;
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};
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#ifdef CONFIG_IOMMU_API
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int host1x_memory_context_list_init(struct host1x *host1x);
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void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl);
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#else
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static inline int host1x_memory_context_list_init(struct host1x *host1x)
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{
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return 0;
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}
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static inline void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl)
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{
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}
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#endif
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#endif
+11
-1
drivers/gpu/host1x/dev.c
+11
-1
drivers/gpu/host1x/dev.c
···
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#include "bus.h"
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#include "channel.h"
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#include "context.h"
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#include "debug.h"
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#include "dev.h"
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#include "intr.h"
···
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goto iommu_exit;
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}
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err = host1x_memory_context_list_init(host);
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if (err) {
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dev_err(&pdev->dev, "failed to initialize context list\n");
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goto free_channels;
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}
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err = host1x_syncpt_init(host);
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if (err) {
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dev_err(&pdev->dev, "failed to initialize syncpts\n");
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goto free_channels;
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goto free_contexts;
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}
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err = host1x_intr_init(host, syncpt_irq);
···
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host1x_intr_deinit(host);
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deinit_syncpt:
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host1x_syncpt_deinit(host);
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free_contexts:
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host1x_memory_context_list_free(&host->context_list);
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555
free_channels:
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host1x_channel_list_free(&host->channel_list);
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iommu_exit:
···
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host1x_intr_deinit(host);
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host1x_syncpt_deinit(host);
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host1x_memory_context_list_free(&host->context_list);
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host1x_channel_list_free(&host->channel_list);
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host1x_iommu_exit(host);
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577
host1x_bo_cache_destroy(&host->cache);
+2
drivers/gpu/host1x/dev.h
+2
drivers/gpu/host1x/dev.h
···
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#include "cdma.h"
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#include "channel.h"
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#include "context.h"
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#include "intr.h"
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#include "job.h"
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#include "syncpt.h"
···
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struct mutex syncpt_mutex;
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struct host1x_channel_list channel_list;
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struct host1x_memory_context_list context_list;
145
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struct dentry *debugfs;
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+34
include/linux/host1x.h
+34
include/linux/host1x.h
···
446
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int tegra_mipi_start_calibration(struct tegra_mipi_device *device);
447
447
int tegra_mipi_finish_calibration(struct tegra_mipi_device *device);
448
448
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/* host1x memory contexts */
450
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451
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struct host1x_memory_context {
452
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struct host1x *host;
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454
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refcount_t ref;
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struct pid *owner;
456
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457
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struct device dev;
458
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u64 dma_mask;
459
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u32 stream_id;
460
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};
461
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462
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#ifdef CONFIG_IOMMU_API
463
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struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
464
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struct pid *pid);
465
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void host1x_memory_context_get(struct host1x_memory_context *cd);
466
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void host1x_memory_context_put(struct host1x_memory_context *cd);
467
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#else
468
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static inline struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
469
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struct pid *pid)
470
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{
471
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return NULL;
472
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}
473
+
474
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static inline void host1x_memory_context_get(struct host1x_memory_context *cd)
475
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{
476
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}
477
+
478
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static inline void host1x_memory_context_put(struct host1x_memory_context *cd)
479
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{
480
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}
481
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#endif
482
+
449
483
#endif