Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irqchip fixes from Thomas Gleixner:
"Another set of ARM SoC related irqchip fixes:
- Plug a memory leak in gicv3-its
- Limit features to the root gic interrupt controller
- Add a missing barrier in the gic-v3 IAR access
- Another compile test fix for sun4i"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor
irqchip/gic: Only set the EOImodeNS bit for the root controller
irqchip/gic: Only populate set_affinity for the root controller
irqchip/gicv3-its: Fix memory leak in its_free_tables()
irqchip/sun4i: Fix compilation outside of arch/arm

Linus Torvalds 10 years ago 8ab54ed6 2d23e61f

+18 -14

4 changed files

expand all

arch

arm64

include

asm

arch_gicv3.h

drivers

irqchip

irq-gic-v3-its.c

irq-gic.c

irq-sun4i.c

arch/arm64/include/asm/arch_gicv3.h

··· 103 103 u64 irqstat; 104 104 105 105 asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); 106 + dsb(sy); 106 107 return irqstat; 107 108 } 108 109

+11 -6

drivers/irqchip/irq-gic-v3-its.c

··· 66 66 unsigned long phys_base; 67 67 struct its_cmd_block *cmd_base; 68 68 struct its_cmd_block *cmd_write; 69 - void *tables[GITS_BASER_NR_REGS]; 69 + struct { 70 + void *base; 71 + u32 order; 72 + } tables[GITS_BASER_NR_REGS]; 70 73 struct its_collection *collections; 71 74 struct list_head its_device_list; 72 75 u64 flags; ··· 810 807 int i; 811 808 812 809 for (i = 0; i < GITS_BASER_NR_REGS; i++) { 813 - if (its->tables[i]) { 814 - free_page((unsigned long)its->tables[i]); 815 - its->tables[i] = NULL; 810 + if (its->tables[i].base) { 811 + free_pages((unsigned long)its->tables[i].base, 812 + its->tables[i].order); 813 + its->tables[i].base = NULL; 816 814 } 817 815 } 818 816 } ··· 894 890 goto out_free; 895 891 } 896 892 897 - its->tables[i] = base; 893 + its->tables[i].base = base; 894 + its->tables[i].order = order; 898 895 899 896 retry_baser: 900 897 val = (virt_to_phys(base) | ··· 945 940 * something is horribly wrong... 946 941 */ 947 942 free_pages((unsigned long)base, order); 948 - its->tables[i] = NULL; 943 + its->tables[i].base = NULL; 949 944 950 945 switch (psz) { 951 946 case SZ_16K:

+6 -7

drivers/irqchip/irq-gic.c

··· 384 384 .irq_unmask = gic_unmask_irq, 385 385 .irq_eoi = gic_eoi_irq, 386 386 .irq_set_type = gic_set_type, 387 - #ifdef CONFIG_SMP 388 - .irq_set_affinity = gic_set_affinity, 389 - #endif 390 387 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 391 388 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 392 389 .flags = IRQCHIP_SET_TYPE_MASKED | ··· 397 400 .irq_unmask = gic_unmask_irq, 398 401 .irq_eoi = gic_eoimode1_eoi_irq, 399 402 .irq_set_type = gic_set_type, 400 - #ifdef CONFIG_SMP 401 - .irq_set_affinity = gic_set_affinity, 402 - #endif 403 403 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 404 404 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 405 405 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, ··· 437 443 u32 bypass = 0; 438 444 u32 mode = 0; 439 445 440 - if (static_key_true(&supports_deactivate)) 446 + if (gic == &gic_data[0] && static_key_true(&supports_deactivate)) 441 447 mode = GIC_CPU_CTRL_EOImodeNS; 442 448 443 449 /* ··· 1032 1038 gic->chip = gic_chip; 1033 1039 gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr); 1034 1040 } 1041 + 1042 + #ifdef CONFIG_SMP 1043 + if (gic_nr == 0) 1044 + gic->chip.irq_set_affinity = gic_set_affinity; 1045 + #endif 1035 1046 1036 1047 #ifdef CONFIG_GIC_NON_BANKED 1037 1048 if (percpu_offset) { /* Frankein-GIC without banked registers... */

-1

drivers/irqchip/irq-sun4i.c

··· 22 22 #include <linux/of_irq.h> 23 23 24 24 #include <asm/exception.h> 25 - #include <asm/mach/irq.h> 26 25 27 26 #define SUN4I_IRQ_VECTOR_REG 0x00 28 27 #define SUN4I_IRQ_PROTECTION_REG 0x08

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