phy: qcom-qmp: Add QCM2290 USB3 PHY support

+145

2 changed files

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drivers

phy

qualcomm

phy-qcom-qmp.c

phy-qcom-qmp.h

+143

drivers/phy/qualcomm/phy-qcom-qmp.c

··· 135 135 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 136 136 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 137 137 QPHY_PCS_POWER_DOWN_CONTROL, 138 + /* PCS_MISC registers */ 139 + QPHY_PCS_MISC_TYPEC_CTRL, 138 140 /* Keep last to ensure regs_layout arrays are properly initialized */ 139 141 QPHY_LAYOUT_SIZE 140 142 }; ··· 229 227 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 230 228 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008, 231 229 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014, 230 + }; 231 + 232 + static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 233 + [QPHY_SW_RESET] = 0x00, 234 + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 235 + [QPHY_START_CTRL] = 0x08, 236 + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, 237 + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, 238 + [QPHY_PCS_STATUS] = 0x174, 239 + [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, 232 240 }; 233 241 234 242 static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { ··· 2773 2761 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 2774 2762 }; 2775 2763 2764 + static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { 2765 + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 2766 + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 2767 + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 2768 + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 2769 + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), 2770 + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), 2771 + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 2772 + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 2773 + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 2774 + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 2775 + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 2776 + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 2777 + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 2778 + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 2779 + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 2780 + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 2781 + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 2782 + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 2783 + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 2784 + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 2785 + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 2786 + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 2787 + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), 2788 + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 2789 + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 2790 + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 2791 + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 2792 + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 2793 + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 2794 + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 2795 + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 2796 + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 2797 + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 2798 + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 2799 + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 2800 + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 2801 + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), 2802 + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), 2803 + }; 2804 + 2805 + static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { 2806 + QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 2807 + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 2808 + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 2809 + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 2810 + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), 2811 + }; 2812 + 2813 + static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { 2814 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 2815 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), 2816 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 2817 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 2818 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 2819 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 2820 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 2821 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 2822 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 2823 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 2824 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 2825 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 2826 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), 2827 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 2828 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 2829 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 2830 + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), 2831 + }; 2832 + 2833 + static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { 2834 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 2835 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 2836 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 2837 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 2838 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 2839 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 2840 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 2841 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 2842 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 2843 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 2844 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 2845 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 2846 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 2847 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 2848 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 2849 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 2850 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 2851 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 2852 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 2853 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 2854 + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 2855 + }; 2856 + 2776 2857 struct qmp_phy; 2777 2858 2778 2859 /* struct qmp_phy_cfg - per-PHY initialization config */ ··· 3100 2995 "aux", "cfg_ahb", "ref" 3101 2996 }; 3102 2997 2998 + static const char * const qcm2290_usb3phy_clk_l[] = { 2999 + "cfg_ahb", "ref", "com_aux", 3000 + }; 3001 + 3103 3002 /* list of resets */ 3104 3003 static const char * const msm8996_pciephy_reset_l[] = { 3105 3004 "phy", "common", "cfg", ··· 3115 3006 3116 3007 static const char * const sc7180_usb3phy_reset_l[] = { 3117 3008 "phy", 3009 + }; 3010 + 3011 + static const char * const qcm2290_usb3phy_reset_l[] = { 3012 + "phy_phy", "phy", 3118 3013 }; 3119 3014 3120 3015 static const char * const sdm845_pciephy_reset_l[] = { ··· 4085 3972 .has_pwrdn_delay = true, 4086 3973 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 4087 3974 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 3975 + }; 3976 + 3977 + static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { 3978 + .type = PHY_TYPE_USB3, 3979 + .nlanes = 1, 3980 + 3981 + .serdes_tbl = qcm2290_usb3_serdes_tbl, 3982 + .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 3983 + .tx_tbl = qcm2290_usb3_tx_tbl, 3984 + .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 3985 + .rx_tbl = qcm2290_usb3_rx_tbl, 3986 + .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 3987 + .pcs_tbl = qcm2290_usb3_pcs_tbl, 3988 + .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 3989 + .clk_list = qcm2290_usb3phy_clk_l, 3990 + .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), 3991 + .reset_list = qcm2290_usb3phy_reset_l, 3992 + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 3993 + .vreg_list = qmp_phy_vreg_l, 3994 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3995 + .regs = qcm2290_usb3phy_regs_layout, 3996 + 3997 + .start_ctrl = SERDES_START | PCS_START, 3998 + .pwrdn_ctrl = SW_PWRDN, 3999 + .phy_status = PHYSTATUS, 4000 + 4001 + .is_dual_lane_phy = true, 4088 4002 }; 4089 4003 4090 4004 static void qcom_qmp_phy_configure_lane(void __iomem *base, ··· 5745 5605 }, { 5746 5606 .compatible = "qcom,sm8350-qmp-usb3-uni-phy", 5747 5607 .data = &sm8350_usb3_uniphy_cfg, 5608 + }, { 5609 + .compatible = "qcom,qcm2290-qmp-usb3-phy", 5610 + .data = &qcm2290_usb3phy_cfg, 5748 5611 }, 5749 5612 { }, 5750 5613 };

drivers/phy/qualcomm/phy-qcom-qmp.h

··· 169 169 #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 170 170 #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 171 171 #define QSERDES_COM_RESETSM_CNTRL 0x0b4 172 + #define QSERDES_COM_RESETSM_CNTRL2 0x0b8 172 173 #define QSERDES_COM_RESTRIM_CTRL 0x0bc 173 174 #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 174 175 #define QSERDES_COM_LOCK_CMP_EN 0x0c8 ··· 182 181 #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 183 182 #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 184 183 #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 184 + #define QSERDES_COM_INTEGLOOP_INITVAL 0x100 185 185 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 186 186 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 187 187 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110

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