Merge tag 'mmc-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

+3

Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml

··· 91 91 - enum: 92 92 - fsl,imxrt1170-usdhc 93 93 - const: fsl,imxrt1050-usdhc 94 + - items: 95 + - const: nxp,s32g3-usdhc 96 + - const: nxp,s32g2-usdhc 94 97 95 98 reg: 96 99 maxItems: 1

+16 -23

Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml

··· 12 12 properties: 13 13 compatible: 14 14 oneOf: 15 - - items: 16 - - const: renesas,sdhi-sh73a0 # R-Mobile APE6 17 - - items: 18 - - const: renesas,sdhi-r7s72100 # RZ/A1H 19 - - items: 20 - - const: renesas,sdhi-r7s9210 # SH-Mobile AG5 21 - - items: 22 - - const: renesas,sdhi-r8a73a4 # R-Mobile APE6 23 - - items: 24 - - const: renesas,sdhi-r8a7740 # R-Mobile A1 15 + - enum: 16 + - renesas,sdhi-mmc-r8a77470 # RZ/G1C 17 + - renesas,sdhi-r7s72100 # RZ/A1H 18 + - renesas,sdhi-r7s9210 # SH-Mobile AG5 19 + - renesas,sdhi-r8a73a4 # R-Mobile APE6 20 + - renesas,sdhi-r8a7740 # R-Mobile A1 21 + - renesas,sdhi-sh73a0 # R-Mobile APE6 25 22 - items: 26 23 - enum: 27 24 - renesas,sdhi-r8a7778 # R-Car M1 ··· 38 41 - renesas,sdhi-r8a7794 # R-Car E2 39 42 - const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1 40 43 - items: 41 - - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP) 42 - - items: 43 44 - enum: 44 45 - renesas,sdhi-r8a774a1 # RZ/G2M 45 46 - renesas,sdhi-r8a774b1 # RZ/G2N ··· 51 56 - renesas,sdhi-r8a77980 # R-Car V3H 52 57 - renesas,sdhi-r8a77990 # R-Car E3 53 58 - renesas,sdhi-r8a77995 # R-Car D3 54 - - renesas,sdhi-r9a07g043 # RZ/G2UL and RZ/Five 55 - - renesas,sdhi-r9a07g044 # RZ/G2{L,LC} 56 - - renesas,sdhi-r9a07g054 # RZ/V2L 57 - - renesas,sdhi-r9a08g045 # RZ/G3S 58 - - renesas,sdhi-r9a09g011 # RZ/V2M 59 59 - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 60 60 - items: 61 61 - enum: ··· 59 69 - renesas,sdhi-r8a779g0 # R-Car V4H 60 70 - renesas,sdhi-r8a779h0 # R-Car V4M 61 71 - const: renesas,rcar-gen4-sdhi # R-Car Gen4 72 + - items: 73 + - enum: 74 + - renesas,sdhi-r9a07g043 # RZ/G2UL and RZ/Five 75 + - renesas,sdhi-r9a07g044 # RZ/G2{L,LC} 76 + - renesas,sdhi-r9a07g054 # RZ/V2L 77 + - renesas,sdhi-r9a08g045 # RZ/G3S 78 + - renesas,sdhi-r9a09g011 # RZ/V2M 79 + - const: renesas,rzg2l-sdhi 62 80 63 81 reg: 64 82 maxItems: 1 ··· 118 120 properties: 119 121 compatible: 120 122 contains: 121 - enum: 122 - - renesas,sdhi-r9a07g043 123 - - renesas,sdhi-r9a07g044 124 - - renesas,sdhi-r9a07g054 125 - - renesas,sdhi-r9a08g045 126 - - renesas,sdhi-r9a09g011 123 + const: renesas,rzg2l-sdhi 127 124 then: 128 125 properties: 129 126 clocks:

+1 -1

MAINTAINERS

··· 8616 8616 F: drivers/crypto/caam/ 8617 8617 8618 8618 FREESCALE COLDFIRE M5441X MMC DRIVER 8619 - M: Angelo Dureghello <angelo.dureghello@timesys.com> 8619 + M: Angelo Dureghello <adureghello@baylibre.com> 8620 8620 L: linux-mmc@vger.kernel.org 8621 8621 S: Maintained 8622 8622 F: drivers/mmc/host/sdhci-esdhc-mcf.c

-1

drivers/bluetooth/btmrvl_sdio.c

··· 1736 1736 .probe = btmrvl_sdio_probe, 1737 1737 .remove = btmrvl_sdio_remove, 1738 1738 .drv = { 1739 - .owner = THIS_MODULE, 1740 1739 .coredump = btmrvl_sdio_coredump, 1741 1740 .pm = &btmrvl_sdio_pm_ops, 1742 1741 }

-1

drivers/bluetooth/btmtksdio.c

··· 1519 1519 .remove = btmtksdio_remove, 1520 1520 .id_table = btmtksdio_table, 1521 1521 .drv = { 1522 - .owner = THIS_MODULE, 1523 1522 .pm = BTMTKSDIO_PM_OPS, 1524 1523 } 1525 1524 };

+2 -7

drivers/memstick/host/rtsx_pci_ms.c

··· 574 574 return 0; 575 575 } 576 576 577 - static int rtsx_pci_ms_drv_remove(struct platform_device *pdev) 577 + static void rtsx_pci_ms_drv_remove(struct platform_device *pdev) 578 578 { 579 579 struct realtek_pci_ms *host = platform_get_drvdata(pdev); 580 580 struct rtsx_pcr *pcr; 581 581 struct memstick_host *msh; 582 582 int rc; 583 - 584 - if (!host) 585 - return 0; 586 583 587 584 pcr = host->pcr; 588 585 pcr->slots[RTSX_MS_CARD].p_dev = NULL; ··· 610 613 611 614 dev_dbg(&(pdev->dev), 612 615 ": Realtek PCI-E Memstick controller has been removed\n"); 613 - 614 - return 0; 615 616 } 616 617 617 618 static struct platform_device_id rtsx_pci_ms_ids[] = { ··· 623 628 624 629 static struct platform_driver rtsx_pci_ms_driver = { 625 630 .probe = rtsx_pci_ms_drv_probe, 626 - .remove = rtsx_pci_ms_drv_remove, 631 + .remove_new = rtsx_pci_ms_drv_remove, 627 632 .id_table = rtsx_pci_ms_ids, 628 633 .suspend = rtsx_pci_ms_suspend, 629 634 .resume = rtsx_pci_ms_resume,

+2 -4

drivers/memstick/host/rtsx_usb_ms.c

··· 805 805 return err; 806 806 } 807 807 808 - static int rtsx_usb_ms_drv_remove(struct platform_device *pdev) 808 + static void rtsx_usb_ms_drv_remove(struct platform_device *pdev) 809 809 { 810 810 struct rtsx_usb_ms *host = platform_get_drvdata(pdev); 811 811 struct memstick_host *msh = host->msh; ··· 840 840 ": Realtek USB Memstick controller has been removed\n"); 841 841 memstick_free_host(msh); 842 842 platform_set_drvdata(pdev, NULL); 843 - 844 - return 0; 845 843 } 846 844 847 845 static struct platform_device_id rtsx_usb_ms_ids[] = { ··· 853 855 854 856 static struct platform_driver rtsx_usb_ms_driver = { 855 857 .probe = rtsx_usb_ms_drv_probe, 856 - .remove = rtsx_usb_ms_drv_remove, 858 + .remove_new = rtsx_usb_ms_drv_remove, 857 859 .id_table = rtsx_usb_ms_ids, 858 860 .driver = { 859 861 .name = "rtsx_usb_ms",

+4 -4

drivers/mmc/core/block.c

··· 234 234 else if (card->ext_csd.boot_ro_lock & EXT_CSD_BOOT_WP_B_PWR_WP_EN) 235 235 locked = 1; 236 236 237 - ret = snprintf(buf, PAGE_SIZE, "%d\n", locked); 237 + ret = sysfs_emit(buf, "%d\n", locked); 238 238 239 239 mmc_blk_put(md); 240 240 ··· 296 296 int ret; 297 297 struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev)); 298 298 299 - ret = snprintf(buf, PAGE_SIZE, "%d\n", 300 - get_disk_ro(dev_to_disk(dev)) ^ 301 - md->read_only); 299 + ret = sysfs_emit(buf, "%d\n", 300 + get_disk_ro(dev_to_disk(dev)) ^ 301 + md->read_only); 302 302 mmc_blk_put(md); 303 303 return ret; 304 304 }

+4 -3

drivers/mmc/core/debugfs.c

··· 351 351 root = debugfs_create_dir(mmc_hostname(host), NULL); 352 352 host->debugfs_root = root; 353 353 354 - debugfs_create_file("ios", S_IRUSR, root, host, &mmc_ios_fops); 354 + debugfs_create_file("ios", 0400, root, host, &mmc_ios_fops); 355 355 debugfs_create_file("caps", 0600, root, &host->caps, &mmc_caps_fops); 356 356 debugfs_create_file("caps2", 0600, root, &host->caps2, 357 357 &mmc_caps2_fops); 358 - debugfs_create_file_unsafe("clock", S_IRUSR | S_IWUSR, root, host, 358 + debugfs_create_file_unsafe("clock", 0600, root, host, 359 359 &mmc_clock_fops); 360 360 361 361 debugfs_create_file_unsafe("err_state", 0600, root, host, ··· 388 388 root = debugfs_create_dir(mmc_card_id(card), host->debugfs_root); 389 389 card->debugfs_root = root; 390 390 391 - debugfs_create_x32("state", S_IRUSR, root, &card->state); 391 + debugfs_create_x32("state", 0400, root, &card->state); 392 + debugfs_create_x32("quirks", 0400, root, &card->quirks); 392 393 } 393 394 394 395 void mmc_remove_card_debugfs(struct mmc_card *card)

-1

drivers/mmc/core/host.c

··· 13 13 #include <linux/err.h> 14 14 #include <linux/idr.h> 15 15 #include <linux/of.h> 16 - #include <linux/of_gpio.h> 17 16 #include <linux/pagemap.h> 18 17 #include <linux/pm_wakeup.h> 19 18 #include <linux/export.h>

+56 -27

drivers/mmc/core/sd_ops.c

··· 19 19 #include "sd_ops.h" 20 20 #include "mmc_ops.h" 21 21 22 + /* 23 + * Extensive testing has shown that some specific SD cards 24 + * require an increased command timeout to be successfully 25 + * initialized. 26 + */ 27 + #define SD_APP_OP_COND_PERIOD_US (10 * 1000) /* 10ms */ 28 + #define SD_APP_OP_COND_TIMEOUT_MS 2000 /* 2s */ 29 + 30 + struct sd_app_op_cond_busy_data { 31 + struct mmc_host *host; 32 + u32 ocr; 33 + struct mmc_command *cmd; 34 + }; 35 + 22 36 int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card) 23 37 { 24 38 int err; ··· 129 115 return mmc_wait_for_app_cmd(card->host, card, &cmd); 130 116 } 131 117 118 + static int sd_app_op_cond_cb(void *cb_data, bool *busy) 119 + { 120 + struct sd_app_op_cond_busy_data *data = cb_data; 121 + struct mmc_host *host = data->host; 122 + struct mmc_command *cmd = data->cmd; 123 + u32 ocr = data->ocr; 124 + int err; 125 + 126 + *busy = false; 127 + 128 + err = mmc_wait_for_app_cmd(host, NULL, cmd); 129 + if (err) 130 + return err; 131 + 132 + /* If we're just probing, do a single pass. */ 133 + if (ocr == 0) 134 + return 0; 135 + 136 + /* Wait until reset completes. */ 137 + if (mmc_host_is_spi(host)) { 138 + if (!(cmd->resp[0] & R1_SPI_IDLE)) 139 + return 0; 140 + } else if (cmd->resp[0] & MMC_CARD_BUSY) { 141 + return 0; 142 + } 143 + 144 + *busy = true; 145 + return 0; 146 + } 147 + 132 148 int mmc_send_app_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr) 133 149 { 134 150 struct mmc_command cmd = {}; 135 - int i, err = 0; 151 + struct sd_app_op_cond_busy_data cb_data = { 152 + .host = host, 153 + .ocr = ocr, 154 + .cmd = &cmd 155 + }; 156 + int err; 136 157 137 158 cmd.opcode = SD_APP_OP_COND; 138 159 if (mmc_host_is_spi(host)) ··· 176 127 cmd.arg = ocr; 177 128 cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R3 | MMC_CMD_BCR; 178 129 179 - for (i = 100; i; i--) { 180 - err = mmc_wait_for_app_cmd(host, NULL, &cmd); 181 - if (err) 182 - break; 183 - 184 - /* if we're just probing, do a single pass */ 185 - if (ocr == 0) 186 - break; 187 - 188 - /* otherwise wait until reset completes */ 189 - if (mmc_host_is_spi(host)) { 190 - if (!(cmd.resp[0] & R1_SPI_IDLE)) 191 - break; 192 - } else { 193 - if (cmd.resp[0] & MMC_CARD_BUSY) 194 - break; 195 - } 196 - 197 - err = -ETIMEDOUT; 198 - 199 - mmc_delay(10); 200 - } 201 - 202 - if (!i) 203 - pr_err("%s: card never left busy state\n", mmc_hostname(host)); 130 + err = __mmc_poll_for_busy(host, SD_APP_OP_COND_PERIOD_US, 131 + SD_APP_OP_COND_TIMEOUT_MS, &sd_app_op_cond_cb, 132 + &cb_data); 133 + if (err) 134 + return err; 204 135 205 136 if (rocr && !mmc_host_is_spi(host)) 206 137 *rocr = cmd.resp[0]; 207 138 208 - return err; 139 + return 0; 209 140 } 210 141 211 142 static int __mmc_send_if_cond(struct mmc_host *host, u32 ocr, u8 pcie_bits,

+6 -3

drivers/mmc/core/sdio_bus.c

··· 265 265 } 266 266 267 267 /** 268 - * sdio_register_driver - register a function driver 268 + * __sdio_register_driver - register a function driver 269 269 * @drv: SDIO function driver 270 + * @owner: owning module/driver 270 271 */ 271 - int sdio_register_driver(struct sdio_driver *drv) 272 + int __sdio_register_driver(struct sdio_driver *drv, struct module *owner) 272 273 { 273 274 drv->drv.name = drv->name; 274 275 drv->drv.bus = &sdio_bus_type; 276 + drv->drv.owner = owner; 277 + 275 278 return driver_register(&drv->drv); 276 279 } 277 - EXPORT_SYMBOL_GPL(sdio_register_driver); 280 + EXPORT_SYMBOL_GPL(__sdio_register_driver); 278 281 279 282 /** 280 283 * sdio_unregister_driver - unregister a function driver

+22 -3

drivers/mmc/core/slot-gpio.c

··· 19 19 struct mmc_gpio { 20 20 struct gpio_desc *ro_gpio; 21 21 struct gpio_desc *cd_gpio; 22 - irqreturn_t (*cd_gpio_isr)(int irq, void *dev_id); 22 + irq_handler_t cd_gpio_isr; 23 23 char *ro_label; 24 24 char *cd_label; 25 25 u32 cd_debounce_delay_ms; ··· 162 162 /* Register an alternate interrupt service routine for 163 163 * the card-detect GPIO. 164 164 */ 165 - void mmc_gpio_set_cd_isr(struct mmc_host *host, 166 - irqreturn_t (*isr)(int irq, void *dev_id)) 165 + void mmc_gpio_set_cd_isr(struct mmc_host *host, irq_handler_t isr) 167 166 { 168 167 struct mmc_gpio *ctx = host->slot.handler_priv; 169 168 ··· 219 220 return 0; 220 221 } 221 222 EXPORT_SYMBOL(mmc_gpiod_request_cd); 223 + 224 + /** 225 + * mmc_gpiod_set_cd_config - set config for card-detection GPIO 226 + * @host: mmc host 227 + * @config: Generic pinconf config (from pinconf_to_config_packed()) 228 + * 229 + * This can be used by mmc host drivers to fixup a card-detection GPIO's config 230 + * (e.g. set PIN_CONFIG_BIAS_PULL_UP) after acquiring the GPIO descriptor 231 + * through mmc_gpiod_request_cd(). 232 + * 233 + * Returns: 234 + * 0 on success, or a negative errno value on error. 235 + */ 236 + int mmc_gpiod_set_cd_config(struct mmc_host *host, unsigned long config) 237 + { 238 + struct mmc_gpio *ctx = host->slot.handler_priv; 239 + 240 + return gpiod_set_config(ctx->cd_gpio, config); 241 + } 242 + EXPORT_SYMBOL(mmc_gpiod_set_cd_config); 222 243 223 244 bool mmc_can_gpio_cd(struct mmc_host *host) 224 245 {

+1

drivers/mmc/host/Kconfig

··· 233 233 depends on MMC_SDHCI_PLTFM 234 234 depends on OF 235 235 depends on COMMON_CLK 236 + select MMC_CQHCI 236 237 help 237 238 This selects Synopsys DesignWare Cores Mobile Storage Controller 238 239 support.

+132 -177

drivers/mmc/host/atmel-mci.c

··· 224 224 bool non_removable; 225 225 }; 226 226 227 - /** 228 - * struct mci_platform_data - board-specific MMC/SDcard configuration 229 - * @dma_slave: DMA slave interface to use in data transfers. 230 - * @dma_filter: Filtering function to filter the DMA channel 231 - * @slot: Per-slot configuration data. 232 - */ 233 - struct mci_platform_data { 234 - void *dma_slave; 235 - dma_filter_fn dma_filter; 236 - struct mci_slot_pdata slot[ATMCI_MAX_NR_SLOTS]; 237 - }; 238 - 239 227 struct atmel_mci_caps { 240 228 bool has_dma_conf_reg; 241 229 bool has_pdc; ··· 288 300 * rate and timeout calculations. 289 301 * @mapbase: Physical address of the MMIO registers. 290 302 * @mck: The peripheral bus clock hooked up to the MMC controller. 291 - * @pdev: Platform device associated with the MMC controller. 303 + * @dev: Device associated with the MMC controller. 304 + * @pdata: Per-slot configuration data. 292 305 * @slot: Slots sharing this MMC controller. 293 306 * @caps: MCI capabilities depending on MCI version. 294 307 * @prepare_data: function to setup MCI before data transfer which ··· 366 377 unsigned long bus_hz; 367 378 unsigned long mapbase; 368 379 struct clk *mck; 369 - struct platform_device *pdev; 380 + struct device *dev; 370 381 382 + struct mci_slot_pdata pdata[ATMCI_MAX_NR_SLOTS]; 371 383 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS]; 372 384 373 385 struct atmel_mci_caps caps; ··· 520 530 static int atmci_regs_show(struct seq_file *s, void *v) 521 531 { 522 532 struct atmel_mci *host = s->private; 533 + struct device *dev = host->dev; 523 534 u32 *buf; 524 535 int ret = 0; 525 536 ··· 529 538 if (!buf) 530 539 return -ENOMEM; 531 540 532 - pm_runtime_get_sync(&host->pdev->dev); 541 + pm_runtime_get_sync(dev); 533 542 534 543 /* 535 544 * Grab a more or less consistent snapshot. Note that we're ··· 540 549 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE); 541 550 spin_unlock_bh(&host->lock); 542 551 543 - pm_runtime_mark_last_busy(&host->pdev->dev); 544 - pm_runtime_put_autosuspend(&host->pdev->dev); 552 + pm_runtime_mark_last_busy(dev); 553 + pm_runtime_put_autosuspend(dev); 545 554 546 555 seq_printf(s, "MR:\t0x%08x%s%s ", 547 556 buf[ATMCI_MR / 4], ··· 617 626 &host->completed_events); 618 627 } 619 628 620 - #if defined(CONFIG_OF) 621 629 static const struct of_device_id atmci_dt_ids[] = { 622 630 { .compatible = "atmel,hsmci" }, 623 631 { /* sentinel */ } ··· 624 634 625 635 MODULE_DEVICE_TABLE(of, atmci_dt_ids); 626 636 627 - static struct mci_platform_data* 628 - atmci_of_init(struct platform_device *pdev) 637 + static int atmci_of_init(struct atmel_mci *host) 629 638 { 630 - struct device_node *np = pdev->dev.of_node; 639 + struct device *dev = host->dev; 640 + struct device_node *np = dev->of_node; 631 641 struct device_node *cnp; 632 - struct mci_platform_data *pdata; 633 642 u32 slot_id; 634 643 int err; 635 644 636 - if (!np) { 637 - dev_err(&pdev->dev, "device node not found\n"); 638 - return ERR_PTR(-EINVAL); 639 - } 640 - 641 - pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 642 - if (!pdata) 643 - return ERR_PTR(-ENOMEM); 645 + if (!np) 646 + return dev_err_probe(dev, -EINVAL, "device node not found\n"); 644 647 645 648 for_each_child_of_node(np, cnp) { 646 649 if (of_property_read_u32(cnp, "reg", &slot_id)) { 647 - dev_warn(&pdev->dev, "reg property is missing for %pOF\n", 648 - cnp); 650 + dev_warn(dev, "reg property is missing for %pOF\n", cnp); 649 651 continue; 650 652 } 651 653 652 654 if (slot_id >= ATMCI_MAX_NR_SLOTS) { 653 - dev_warn(&pdev->dev, "can't have more than %d slots\n", 655 + dev_warn(dev, "can't have more than %d slots\n", 654 656 ATMCI_MAX_NR_SLOTS); 655 657 of_node_put(cnp); 656 658 break; 657 659 } 658 660 659 661 if (of_property_read_u32(cnp, "bus-width", 660 - &pdata->slot[slot_id].bus_width)) 661 - pdata->slot[slot_id].bus_width = 1; 662 + &host->pdata[slot_id].bus_width)) 663 + host->pdata[slot_id].bus_width = 1; 662 664 663 - pdata->slot[slot_id].detect_pin = 664 - devm_fwnode_gpiod_get(&pdev->dev, of_fwnode_handle(cnp), 665 + host->pdata[slot_id].detect_pin = 666 + devm_fwnode_gpiod_get(dev, of_fwnode_handle(cnp), 665 667 "cd", GPIOD_IN, "cd-gpios"); 666 - err = PTR_ERR_OR_ZERO(pdata->slot[slot_id].detect_pin); 668 + err = PTR_ERR_OR_ZERO(host->pdata[slot_id].detect_pin); 667 669 if (err) { 668 670 if (err != -ENOENT) { 669 671 of_node_put(cnp); 670 - return ERR_PTR(err); 672 + return err; 671 673 } 672 - pdata->slot[slot_id].detect_pin = NULL; 674 + host->pdata[slot_id].detect_pin = NULL; 673 675 } 674 676 675 - pdata->slot[slot_id].non_removable = 677 + host->pdata[slot_id].non_removable = 676 678 of_property_read_bool(cnp, "non-removable"); 677 679 678 - pdata->slot[slot_id].wp_pin = 679 - devm_fwnode_gpiod_get(&pdev->dev, of_fwnode_handle(cnp), 680 + host->pdata[slot_id].wp_pin = 681 + devm_fwnode_gpiod_get(dev, of_fwnode_handle(cnp), 680 682 "wp", GPIOD_IN, "wp-gpios"); 681 - err = PTR_ERR_OR_ZERO(pdata->slot[slot_id].wp_pin); 683 + err = PTR_ERR_OR_ZERO(host->pdata[slot_id].wp_pin); 682 684 if (err) { 683 685 if (err != -ENOENT) { 684 686 of_node_put(cnp); 685 - return ERR_PTR(err); 687 + return err; 686 688 } 687 - pdata->slot[slot_id].wp_pin = NULL; 689 + host->pdata[slot_id].wp_pin = NULL; 688 690 } 689 691 } 690 692 691 - return pdata; 693 + return 0; 692 694 } 693 - #else /* CONFIG_OF */ 694 - static inline struct mci_platform_data* 695 - atmci_of_init(struct platform_device *dev) 696 - { 697 - return ERR_PTR(-EINVAL); 698 - } 699 - #endif 700 695 701 696 static inline unsigned int atmci_get_version(struct atmel_mci *host) 702 697 { ··· 713 738 714 739 static void atmci_timeout_timer(struct timer_list *t) 715 740 { 716 - struct atmel_mci *host; 741 + struct atmel_mci *host = from_timer(host, t, timer); 742 + struct device *dev = host->dev; 717 743 718 - host = from_timer(host, t, timer); 719 - 720 - dev_dbg(&host->pdev->dev, "software timeout\n"); 744 + dev_dbg(dev, "software timeout\n"); 721 745 722 746 if (host->mrq->cmd->data) { 723 747 host->mrq->cmd->data->error = -ETIMEDOUT; ··· 834 860 static void atmci_send_command(struct atmel_mci *host, 835 861 struct mmc_command *cmd, u32 cmd_flags) 836 862 { 863 + struct device *dev = host->dev; 837 864 unsigned int timeout_ms = cmd->busy_timeout ? cmd->busy_timeout : 838 865 ATMCI_CMD_TIMEOUT_MS; 839 866 840 867 WARN_ON(host->cmd); 841 868 host->cmd = cmd; 842 869 843 - dev_vdbg(&host->pdev->dev, 844 - "start command: ARGR=0x%08x CMDR=0x%08x\n", 845 - cmd->arg, cmd_flags); 870 + dev_vdbg(dev, "start command: ARGR=0x%08x CMDR=0x%08x\n", cmd->arg, cmd_flags); 846 871 847 872 atmci_writel(host, ATMCI_ARGR, cmd->arg); 848 873 atmci_writel(host, ATMCI_CMDR, cmd_flags); ··· 851 878 852 879 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) 853 880 { 854 - dev_dbg(&host->pdev->dev, "send stop command\n"); 881 + struct device *dev = host->dev; 882 + 883 + dev_dbg(dev, "send stop command\n"); 855 884 atmci_send_command(host, data->stop, host->stop_cmdr); 856 885 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); 857 886 } ··· 926 951 static void atmci_pdc_cleanup(struct atmel_mci *host) 927 952 { 928 953 struct mmc_data *data = host->data; 954 + struct device *dev = host->dev; 929 955 930 956 if (data) 931 - dma_unmap_sg(&host->pdev->dev, 932 - data->sg, data->sg_len, 933 - mmc_get_dma_dir(data)); 957 + dma_unmap_sg(dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); 934 958 } 935 959 936 960 /* ··· 939 965 */ 940 966 static void atmci_pdc_complete(struct atmel_mci *host) 941 967 { 968 + struct device *dev = host->dev; 942 969 int transfer_size = host->data->blocks * host->data->blksz; 943 970 int i; 944 971 ··· 956 981 957 982 atmci_pdc_cleanup(host); 958 983 959 - dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__); 984 + dev_dbg(dev, "(%s) set pending xfer complete\n", __func__); 960 985 atmci_set_pending(host, EVENT_XFER_COMPLETE); 961 986 tasklet_schedule(&host->tasklet); 962 987 } ··· 978 1003 { 979 1004 struct atmel_mci *host = arg; 980 1005 struct mmc_data *data = host->data; 1006 + struct device *dev = host->dev; 981 1007 982 - dev_vdbg(&host->pdev->dev, "DMA complete\n"); 1008 + dev_vdbg(dev, "DMA complete\n"); 983 1009 984 1010 if (host->caps.has_dma_conf_reg) 985 1011 /* Disable DMA hardware handshaking on MCI */ ··· 993 1017 * to send the stop command or waiting for NBUSY in this case. 994 1018 */ 995 1019 if (data) { 996 - dev_dbg(&host->pdev->dev, 997 - "(%s) set pending xfer complete\n", __func__); 1020 + dev_dbg(dev, "(%s) set pending xfer complete\n", __func__); 998 1021 atmci_set_pending(host, EVENT_XFER_COMPLETE); 999 1022 tasklet_schedule(&host->tasklet); 1000 1023 ··· 1067 1092 static u32 1068 1093 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data) 1069 1094 { 1095 + struct device *dev = host->dev; 1070 1096 u32 iflags, tmp; 1071 1097 int i; 1072 1098 ··· 1093 1117 1094 1118 /* Configure PDC */ 1095 1119 host->data_size = data->blocks * data->blksz; 1096 - dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, 1097 - mmc_get_dma_dir(data)); 1120 + dma_map_sg(dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); 1098 1121 1099 1122 if ((!host->caps.has_rwproof) 1100 1123 && (host->data->flags & MMC_DATA_WRITE)) { ··· 1219 1244 1220 1245 static void atmci_stop_transfer(struct atmel_mci *host) 1221 1246 { 1222 - dev_dbg(&host->pdev->dev, 1223 - "(%s) set pending xfer complete\n", __func__); 1247 + struct device *dev = host->dev; 1248 + 1249 + dev_dbg(dev, "(%s) set pending xfer complete\n", __func__); 1224 1250 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1225 1251 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1226 1252 } ··· 1237 1261 static void atmci_stop_transfer_dma(struct atmel_mci *host) 1238 1262 { 1239 1263 struct dma_chan *chan = host->data_chan; 1264 + struct device *dev = host->dev; 1240 1265 1241 1266 if (chan) { 1242 1267 dmaengine_terminate_all(chan); 1243 1268 atmci_dma_cleanup(host); 1244 1269 } else { 1245 1270 /* Data transfer was stopped by the interrupt handler */ 1246 - dev_dbg(&host->pdev->dev, 1247 - "(%s) set pending xfer complete\n", __func__); 1271 + dev_dbg(dev, "(%s) set pending xfer complete\n", __func__); 1248 1272 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1249 1273 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1250 1274 } ··· 1257 1281 static void atmci_start_request(struct atmel_mci *host, 1258 1282 struct atmel_mci_slot *slot) 1259 1283 { 1284 + struct device *dev = host->dev; 1260 1285 struct mmc_request *mrq; 1261 1286 struct mmc_command *cmd; 1262 1287 struct mmc_data *data; ··· 1273 1296 host->cmd_status = 0; 1274 1297 host->data_status = 0; 1275 1298 1276 - dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode); 1299 + dev_dbg(dev, "start request: cmd %u\n", mrq->cmd->opcode); 1277 1300 1278 1301 if (host->need_reset || host->caps.need_reset_after_xfer) { 1279 1302 iflags = atmci_readl(host, ATMCI_IMR); ··· 1352 1375 static void atmci_queue_request(struct atmel_mci *host, 1353 1376 struct atmel_mci_slot *slot, struct mmc_request *mrq) 1354 1377 { 1378 + struct device *dev = host->dev; 1379 + 1355 1380 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", 1356 1381 host->state); 1357 1382 ··· 1363 1384 host->state = STATE_SENDING_CMD; 1364 1385 atmci_start_request(host, slot); 1365 1386 } else { 1366 - dev_dbg(&host->pdev->dev, "queue request\n"); 1387 + dev_dbg(dev, "queue request\n"); 1367 1388 list_add_tail(&slot->queue_node, &host->queue); 1368 1389 } 1369 1390 spin_unlock_bh(&host->lock); ··· 1373 1394 { 1374 1395 struct atmel_mci_slot *slot = mmc_priv(mmc); 1375 1396 struct atmel_mci *host = slot->host; 1397 + struct device *dev = host->dev; 1376 1398 struct mmc_data *data; 1377 1399 1378 1400 WARN_ON(slot->mrq); 1379 - dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode); 1401 + dev_dbg(dev, "MRQ: cmd %u\n", mrq->cmd->opcode); 1380 1402 1381 1403 /* 1382 1404 * We may "know" the card is gone even though there's still an ··· 1587 1607 { 1588 1608 struct atmel_mci_slot *slot = NULL; 1589 1609 struct mmc_host *prev_mmc = host->cur_slot->mmc; 1610 + struct device *dev = host->dev; 1590 1611 1591 1612 WARN_ON(host->cmd || host->data); 1592 1613 ··· 1610 1629 slot = list_entry(host->queue.next, 1611 1630 struct atmel_mci_slot, queue_node); 1612 1631 list_del(&slot->queue_node); 1613 - dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", 1614 - mmc_hostname(slot->mmc)); 1632 + dev_vdbg(dev, "list not empty: %s is next\n", mmc_hostname(slot->mmc)); 1615 1633 host->state = STATE_SENDING_CMD; 1616 1634 atmci_start_request(host, slot); 1617 1635 } else { 1618 - dev_vdbg(&host->pdev->dev, "list empty\n"); 1636 + dev_vdbg(dev, "list empty\n"); 1619 1637 host->state = STATE_IDLE; 1620 1638 } 1621 1639 ··· 1750 1770 struct atmel_mci *host = from_tasklet(host, t, tasklet); 1751 1771 struct mmc_request *mrq = host->mrq; 1752 1772 struct mmc_data *data = host->data; 1773 + struct device *dev = host->dev; 1753 1774 enum atmel_mci_state state = host->state; 1754 1775 enum atmel_mci_state prev_state; 1755 1776 u32 status; ··· 1759 1778 1760 1779 state = host->state; 1761 1780 1762 - dev_vdbg(&host->pdev->dev, 1763 - "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", 1781 + dev_vdbg(dev, "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", 1764 1782 state, host->pending_events, host->completed_events, 1765 1783 atmci_readl(host, ATMCI_IMR)); 1766 1784 1767 1785 do { 1768 1786 prev_state = state; 1769 - dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state); 1787 + dev_dbg(dev, "FSM: state=%d\n", state); 1770 1788 1771 1789 switch (state) { 1772 1790 case STATE_IDLE: ··· 1778 1798 * END_REQUEST by default, WAITING_NOTBUSY if it's a 1779 1799 * command needing it or DATA_XFER if there is data. 1780 1800 */ 1781 - dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); 1801 + dev_dbg(dev, "FSM: cmd ready?\n"); 1782 1802 if (!atmci_test_and_clear_pending(host, 1783 1803 EVENT_CMD_RDY)) 1784 1804 break; 1785 1805 1786 - dev_dbg(&host->pdev->dev, "set completed cmd ready\n"); 1806 + dev_dbg(dev, "set completed cmd ready\n"); 1787 1807 host->cmd = NULL; 1788 1808 atmci_set_completed(host, EVENT_CMD_RDY); 1789 1809 atmci_command_complete(host, mrq->cmd); 1790 1810 if (mrq->data) { 1791 - dev_dbg(&host->pdev->dev, 1792 - "command with data transfer"); 1811 + dev_dbg(dev, "command with data transfer\n"); 1793 1812 /* 1794 1813 * If there is a command error don't start 1795 1814 * data transfer. ··· 1803 1824 } else 1804 1825 state = STATE_DATA_XFER; 1805 1826 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) { 1806 - dev_dbg(&host->pdev->dev, 1807 - "command response need waiting notbusy"); 1827 + dev_dbg(dev, "command response need waiting notbusy\n"); 1808 1828 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); 1809 1829 state = STATE_WAITING_NOTBUSY; 1810 1830 } else ··· 1814 1836 case STATE_DATA_XFER: 1815 1837 if (atmci_test_and_clear_pending(host, 1816 1838 EVENT_DATA_ERROR)) { 1817 - dev_dbg(&host->pdev->dev, "set completed data error\n"); 1839 + dev_dbg(dev, "set completed data error\n"); 1818 1840 atmci_set_completed(host, EVENT_DATA_ERROR); 1819 1841 state = STATE_END_REQUEST; 1820 1842 break; ··· 1827 1849 * to the next step which is WAITING_NOTBUSY in write 1828 1850 * case and directly SENDING_STOP in read case. 1829 1851 */ 1830 - dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n"); 1852 + dev_dbg(dev, "FSM: xfer complete?\n"); 1831 1853 if (!atmci_test_and_clear_pending(host, 1832 1854 EVENT_XFER_COMPLETE)) 1833 1855 break; 1834 1856 1835 - dev_dbg(&host->pdev->dev, 1836 - "(%s) set completed xfer complete\n", 1837 - __func__); 1857 + dev_dbg(dev, "(%s) set completed xfer complete\n", __func__); 1838 1858 atmci_set_completed(host, EVENT_XFER_COMPLETE); 1839 1859 1840 1860 if (host->caps.need_notbusy_for_read_ops || ··· 1857 1881 * included) or a write operation. In the latest case, 1858 1882 * we need to send a stop command. 1859 1883 */ 1860 - dev_dbg(&host->pdev->dev, "FSM: not busy?\n"); 1884 + dev_dbg(dev, "FSM: not busy?\n"); 1861 1885 if (!atmci_test_and_clear_pending(host, 1862 1886 EVENT_NOTBUSY)) 1863 1887 break; 1864 1888 1865 - dev_dbg(&host->pdev->dev, "set completed not busy\n"); 1889 + dev_dbg(dev, "set completed not busy\n"); 1866 1890 atmci_set_completed(host, EVENT_NOTBUSY); 1867 1891 1868 1892 if (host->data) { ··· 1892 1916 * in order to go to the end request state instead of 1893 1917 * sending stop again. 1894 1918 */ 1895 - dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n"); 1919 + dev_dbg(dev, "FSM: cmd ready?\n"); 1896 1920 if (!atmci_test_and_clear_pending(host, 1897 1921 EVENT_CMD_RDY)) 1898 1922 break; 1899 1923 1900 - dev_dbg(&host->pdev->dev, "FSM: cmd ready\n"); 1924 + dev_dbg(dev, "FSM: cmd ready\n"); 1901 1925 host->cmd = NULL; 1902 1926 data->bytes_xfered = data->blocks * data->blksz; 1903 1927 data->error = 0; ··· 2096 2120 static irqreturn_t atmci_interrupt(int irq, void *dev_id) 2097 2121 { 2098 2122 struct atmel_mci *host = dev_id; 2123 + struct device *dev = host->dev; 2099 2124 u32 status, mask, pending; 2100 2125 unsigned int pass_count = 0; 2101 2126 ··· 2108 2131 break; 2109 2132 2110 2133 if (pending & ATMCI_DATA_ERROR_FLAGS) { 2111 - dev_dbg(&host->pdev->dev, "IRQ: data error\n"); 2134 + dev_dbg(dev, "IRQ: data error\n"); 2112 2135 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS 2113 2136 | ATMCI_RXRDY | ATMCI_TXRDY 2114 2137 | ATMCI_ENDRX | ATMCI_ENDTX 2115 2138 | ATMCI_RXBUFF | ATMCI_TXBUFE); 2116 2139 2117 2140 host->data_status = status; 2118 - dev_dbg(&host->pdev->dev, "set pending data error\n"); 2141 + dev_dbg(dev, "set pending data error\n"); 2119 2142 smp_wmb(); 2120 2143 atmci_set_pending(host, EVENT_DATA_ERROR); 2121 2144 tasklet_schedule(&host->tasklet); 2122 2145 } 2123 2146 2124 2147 if (pending & ATMCI_TXBUFE) { 2125 - dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n"); 2148 + dev_dbg(dev, "IRQ: tx buffer empty\n"); 2126 2149 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE); 2127 2150 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2128 2151 /* ··· 2138 2161 atmci_pdc_complete(host); 2139 2162 } 2140 2163 } else if (pending & ATMCI_ENDTX) { 2141 - dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n"); 2164 + dev_dbg(dev, "IRQ: end of tx buffer\n"); 2142 2165 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); 2143 2166 2144 2167 if (host->data_size) { ··· 2149 2172 } 2150 2173 2151 2174 if (pending & ATMCI_RXBUFF) { 2152 - dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n"); 2175 + dev_dbg(dev, "IRQ: rx buffer full\n"); 2153 2176 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF); 2154 2177 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2155 2178 /* ··· 2165 2188 atmci_pdc_complete(host); 2166 2189 } 2167 2190 } else if (pending & ATMCI_ENDRX) { 2168 - dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n"); 2191 + dev_dbg(dev, "IRQ: end of rx buffer\n"); 2169 2192 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); 2170 2193 2171 2194 if (host->data_size) { ··· 2182 2205 * The appropriate workaround is to use the BLKE signal. 2183 2206 */ 2184 2207 if (pending & ATMCI_BLKE) { 2185 - dev_dbg(&host->pdev->dev, "IRQ: blke\n"); 2208 + dev_dbg(dev, "IRQ: blke\n"); 2186 2209 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE); 2187 2210 smp_wmb(); 2188 - dev_dbg(&host->pdev->dev, "set pending notbusy\n"); 2211 + dev_dbg(dev, "set pending notbusy\n"); 2189 2212 atmci_set_pending(host, EVENT_NOTBUSY); 2190 2213 tasklet_schedule(&host->tasklet); 2191 2214 } 2192 2215 2193 2216 if (pending & ATMCI_NOTBUSY) { 2194 - dev_dbg(&host->pdev->dev, "IRQ: not_busy\n"); 2217 + dev_dbg(dev, "IRQ: not_busy\n"); 2195 2218 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY); 2196 2219 smp_wmb(); 2197 - dev_dbg(&host->pdev->dev, "set pending notbusy\n"); 2220 + dev_dbg(dev, "set pending notbusy\n"); 2198 2221 atmci_set_pending(host, EVENT_NOTBUSY); 2199 2222 tasklet_schedule(&host->tasklet); 2200 2223 } ··· 2205 2228 atmci_write_data_pio(host); 2206 2229 2207 2230 if (pending & ATMCI_CMDRDY) { 2208 - dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n"); 2231 + dev_dbg(dev, "IRQ: cmd ready\n"); 2209 2232 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY); 2210 2233 host->cmd_status = status; 2211 2234 smp_wmb(); 2212 - dev_dbg(&host->pdev->dev, "set pending cmd rdy\n"); 2235 + dev_dbg(dev, "set pending cmd rdy\n"); 2213 2236 atmci_set_pending(host, EVENT_CMD_RDY); 2214 2237 tasklet_schedule(&host->tasklet); 2215 2238 } ··· 2241 2264 struct mci_slot_pdata *slot_data, unsigned int id, 2242 2265 u32 sdc_reg, u32 sdio_irq) 2243 2266 { 2267 + struct device *dev = host->dev; 2244 2268 struct mmc_host *mmc; 2245 2269 struct atmel_mci_slot *slot; 2246 2270 int ret; 2247 2271 2248 - mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); 2272 + mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), dev); 2249 2273 if (!mmc) 2250 2274 return -ENOMEM; 2251 2275 ··· 2365 2387 2366 2388 static int atmci_configure_dma(struct atmel_mci *host) 2367 2389 { 2368 - host->dma.chan = dma_request_chan(&host->pdev->dev, "rxtx"); 2390 + struct device *dev = host->dev; 2369 2391 2370 - if (PTR_ERR(host->dma.chan) == -ENODEV) { 2371 - struct mci_platform_data *pdata = host->pdev->dev.platform_data; 2372 - dma_cap_mask_t mask; 2373 - 2374 - if (!pdata || !pdata->dma_filter) 2375 - return -ENODEV; 2376 - 2377 - dma_cap_zero(mask); 2378 - dma_cap_set(DMA_SLAVE, mask); 2379 - 2380 - host->dma.chan = dma_request_channel(mask, pdata->dma_filter, 2381 - pdata->dma_slave); 2382 - if (!host->dma.chan) 2383 - host->dma.chan = ERR_PTR(-ENODEV); 2384 - } 2385 - 2392 + host->dma.chan = dma_request_chan(dev, "rxtx"); 2386 2393 if (IS_ERR(host->dma.chan)) 2387 2394 return PTR_ERR(host->dma.chan); 2388 2395 2389 - dev_info(&host->pdev->dev, "using %s for DMA transfers\n", 2390 - dma_chan_name(host->dma.chan)); 2396 + dev_info(dev, "using %s for DMA transfers\n", dma_chan_name(host->dma.chan)); 2391 2397 2392 2398 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR; 2393 2399 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ··· 2391 2429 */ 2392 2430 static void atmci_get_cap(struct atmel_mci *host) 2393 2431 { 2432 + struct device *dev = host->dev; 2394 2433 unsigned int version; 2395 2434 2396 2435 version = atmci_get_version(host); 2397 - dev_info(&host->pdev->dev, 2398 - "version: 0x%x\n", version); 2436 + dev_info(dev, "version: 0x%x\n", version); 2399 2437 2400 2438 host->caps.has_dma_conf_reg = false; 2401 2439 host->caps.has_pdc = true; ··· 2436 2474 break; 2437 2475 default: 2438 2476 host->caps.has_pdc = false; 2439 - dev_warn(&host->pdev->dev, 2440 - "Unmanaged mci version, set minimum capabilities\n"); 2477 + dev_warn(dev, "Unmanaged mci version, set minimum capabilities\n"); 2441 2478 break; 2442 2479 } 2443 2480 } 2444 2481 2445 2482 static int atmci_probe(struct platform_device *pdev) 2446 2483 { 2447 - struct mci_platform_data *pdata; 2484 + struct device *dev = &pdev->dev; 2448 2485 struct atmel_mci *host; 2449 2486 struct resource *regs; 2450 2487 unsigned int nr_slots; ··· 2453 2492 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2454 2493 if (!regs) 2455 2494 return -ENXIO; 2456 - pdata = pdev->dev.platform_data; 2457 - if (!pdata) { 2458 - pdata = atmci_of_init(pdev); 2459 - if (IS_ERR(pdata)) { 2460 - dev_err(&pdev->dev, "platform data not available\n"); 2461 - return PTR_ERR(pdata); 2462 - } 2463 - } 2464 2495 2465 2496 irq = platform_get_irq(pdev, 0); 2466 2497 if (irq < 0) 2467 2498 return irq; 2468 2499 2469 - host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 2500 + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 2470 2501 if (!host) 2471 2502 return -ENOMEM; 2472 2503 2473 - host->pdev = pdev; 2504 + host->dev = dev; 2474 2505 spin_lock_init(&host->lock); 2475 2506 INIT_LIST_HEAD(&host->queue); 2476 2507 2477 - host->mck = devm_clk_get(&pdev->dev, "mci_clk"); 2508 + ret = atmci_of_init(host); 2509 + if (ret) 2510 + return dev_err_probe(dev, ret, "Slot information not available\n"); 2511 + 2512 + host->mck = devm_clk_get(dev, "mci_clk"); 2478 2513 if (IS_ERR(host->mck)) 2479 2514 return PTR_ERR(host->mck); 2480 2515 2481 - host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs)); 2516 + host->regs = devm_ioremap(dev, regs->start, resource_size(regs)); 2482 2517 if (!host->regs) 2483 2518 return -ENOMEM; 2484 2519 ··· 2489 2532 2490 2533 tasklet_setup(&host->tasklet, atmci_tasklet_func); 2491 2534 2492 - ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); 2535 + ret = request_irq(irq, atmci_interrupt, 0, dev_name(dev), host); 2493 2536 if (ret) { 2494 2537 clk_disable_unprepare(host->mck); 2495 2538 return ret; ··· 2505 2548 host->submit_data = &atmci_submit_data_dma; 2506 2549 host->stop_transfer = &atmci_stop_transfer_dma; 2507 2550 } else if (host->caps.has_pdc) { 2508 - dev_info(&pdev->dev, "using PDC\n"); 2551 + dev_info(dev, "using PDC\n"); 2509 2552 host->prepare_data = &atmci_prepare_data_pdc; 2510 2553 host->submit_data = &atmci_submit_data_pdc; 2511 2554 host->stop_transfer = &atmci_stop_transfer_pdc; 2512 2555 } else { 2513 - dev_info(&pdev->dev, "using PIO\n"); 2556 + dev_info(dev, "using PIO\n"); 2514 2557 host->prepare_data = &atmci_prepare_data; 2515 2558 host->submit_data = &atmci_submit_data; 2516 2559 host->stop_transfer = &atmci_stop_transfer; ··· 2520 2563 2521 2564 timer_setup(&host->timer, atmci_timeout_timer, 0); 2522 2565 2523 - pm_runtime_get_noresume(&pdev->dev); 2524 - pm_runtime_set_active(&pdev->dev); 2525 - pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY); 2526 - pm_runtime_use_autosuspend(&pdev->dev); 2527 - pm_runtime_enable(&pdev->dev); 2566 + pm_runtime_get_noresume(dev); 2567 + pm_runtime_set_active(dev); 2568 + pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_DELAY); 2569 + pm_runtime_use_autosuspend(dev); 2570 + pm_runtime_enable(dev); 2528 2571 2529 2572 /* We need at least one slot to succeed */ 2530 2573 nr_slots = 0; 2531 2574 ret = -ENODEV; 2532 - if (pdata->slot[0].bus_width) { 2533 - ret = atmci_init_slot(host, &pdata->slot[0], 2575 + if (host->pdata[0].bus_width) { 2576 + ret = atmci_init_slot(host, &host->pdata[0], 2534 2577 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA); 2535 2578 if (!ret) { 2536 2579 nr_slots++; 2537 2580 host->buf_size = host->slot[0]->mmc->max_req_size; 2538 2581 } 2539 2582 } 2540 - if (pdata->slot[1].bus_width) { 2541 - ret = atmci_init_slot(host, &pdata->slot[1], 2583 + if (host->pdata[1].bus_width) { 2584 + ret = atmci_init_slot(host, &host->pdata[1], 2542 2585 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB); 2543 2586 if (!ret) { 2544 2587 nr_slots++; ··· 2549 2592 } 2550 2593 2551 2594 if (!nr_slots) { 2552 - dev_err(&pdev->dev, "init failed: no slot defined\n"); 2595 + dev_err_probe(dev, ret, "init failed: no slot defined\n"); 2553 2596 goto err_init_slot; 2554 2597 } 2555 2598 2556 2599 if (!host->caps.has_rwproof) { 2557 - host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size, 2600 + host->buffer = dma_alloc_coherent(dev, host->buf_size, 2558 2601 &host->buf_phys_addr, 2559 2602 GFP_KERNEL); 2560 2603 if (!host->buffer) { 2561 - ret = -ENOMEM; 2562 - dev_err(&pdev->dev, "buffer allocation failed\n"); 2604 + ret = dev_err_probe(dev, -ENOMEM, "buffer allocation failed\n"); 2563 2605 goto err_dma_alloc; 2564 2606 } 2565 2607 } 2566 2608 2567 - dev_info(&pdev->dev, 2568 - "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", 2569 - host->mapbase, irq, nr_slots); 2609 + dev_info(dev, "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", 2610 + host->mapbase, irq, nr_slots); 2570 2611 2571 - pm_runtime_mark_last_busy(&host->pdev->dev); 2572 - pm_runtime_put_autosuspend(&pdev->dev); 2612 + pm_runtime_mark_last_busy(dev); 2613 + pm_runtime_put_autosuspend(dev); 2573 2614 2574 2615 return 0; 2575 2616 ··· 2579 2624 err_init_slot: 2580 2625 clk_disable_unprepare(host->mck); 2581 2626 2582 - pm_runtime_disable(&pdev->dev); 2583 - pm_runtime_put_noidle(&pdev->dev); 2627 + pm_runtime_disable(dev); 2628 + pm_runtime_put_noidle(dev); 2584 2629 2585 2630 del_timer_sync(&host->timer); 2586 2631 if (!IS_ERR(host->dma.chan)) ··· 2593 2638 static void atmci_remove(struct platform_device *pdev) 2594 2639 { 2595 2640 struct atmel_mci *host = platform_get_drvdata(pdev); 2641 + struct device *dev = &pdev->dev; 2596 2642 unsigned int i; 2597 2643 2598 - pm_runtime_get_sync(&pdev->dev); 2644 + pm_runtime_get_sync(dev); 2599 2645 2600 2646 if (host->buffer) 2601 - dma_free_coherent(&pdev->dev, host->buf_size, 2602 - host->buffer, host->buf_phys_addr); 2647 + dma_free_coherent(dev, host->buf_size, host->buffer, host->buf_phys_addr); 2603 2648 2604 2649 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { 2605 2650 if (host->slot[i]) ··· 2618 2663 2619 2664 clk_disable_unprepare(host->mck); 2620 2665 2621 - pm_runtime_disable(&pdev->dev); 2622 - pm_runtime_put_noidle(&pdev->dev); 2666 + pm_runtime_disable(dev); 2667 + pm_runtime_put_noidle(dev); 2623 2668 } 2624 2669 2625 2670 #ifdef CONFIG_PM ··· 2656 2701 .driver = { 2657 2702 .name = "atmel_mci", 2658 2703 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2659 - .of_match_table = of_match_ptr(atmci_dt_ids), 2704 + .of_match_table = atmci_dt_ids, 2660 2705 .pm = &atmci_dev_pm_ops, 2661 2706 }, 2662 2707 };

+8 -3

drivers/mmc/host/cqhci-core.c

··· 474 474 return sg_count; 475 475 } 476 476 477 - static void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, 478 - bool dma64) 477 + void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, 478 + bool dma64) 479 479 { 480 480 __le32 *attr = (__le32 __force *)desc; 481 481 ··· 495 495 dataddr[0] = cpu_to_le32(addr); 496 496 } 497 497 } 498 + EXPORT_SYMBOL(cqhci_set_tran_desc); 498 499 499 500 static int cqhci_prep_tran_desc(struct mmc_request *mrq, 500 501 struct cqhci_host *cq_host, int tag) ··· 523 522 524 523 if ((i+1) == sg_count) 525 524 end = true; 526 - cqhci_set_tran_desc(desc, addr, len, end, dma64); 525 + if (cq_host->ops->set_tran_desc) 526 + cq_host->ops->set_tran_desc(cq_host, &desc, addr, len, end, dma64); 527 + else 528 + cqhci_set_tran_desc(desc, addr, len, end, dma64); 529 + 527 530 desc += cq_host->trans_desc_len; 528 531 } 529 532

+4

drivers/mmc/host/cqhci.h

··· 293 293 int (*program_key)(struct cqhci_host *cq_host, 294 294 const union cqhci_crypto_cfg_entry *cfg, int slot); 295 295 #endif 296 + void (*set_tran_desc)(struct cqhci_host *cq_host, u8 **desc, 297 + dma_addr_t addr, int len, bool end, bool dma64); 298 + 296 299 }; 297 300 298 301 static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg) ··· 321 318 int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64); 322 319 struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev); 323 320 int cqhci_deactivate(struct mmc_host *mmc); 321 + void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, bool dma64); 324 322 static inline int cqhci_suspend(struct mmc_host *mmc) 325 323 { 326 324 return cqhci_deactivate(mmc);

+2 -2

drivers/mmc/host/davinci_mmc.c

··· 1337 1337 return ret; 1338 1338 } 1339 1339 1340 - static void __exit davinci_mmcsd_remove(struct platform_device *pdev) 1340 + static void davinci_mmcsd_remove(struct platform_device *pdev) 1341 1341 { 1342 1342 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1343 1343 ··· 1392 1392 .of_match_table = davinci_mmc_dt_ids, 1393 1393 }, 1394 1394 .probe = davinci_mmcsd_probe, 1395 - .remove_new = __exit_p(davinci_mmcsd_remove), 1395 + .remove_new = davinci_mmcsd_remove, 1396 1396 .id_table = davinci_mmc_devtype, 1397 1397 }; 1398 1398

-1

drivers/mmc/host/dw_mmc-hi3798cv200.c

··· 87 87 goto tuning_out; 88 88 89 89 prev_err = err; 90 - err = 0; 91 90 } 92 91 93 92 tuning_out:

-1

drivers/mmc/host/dw_mmc-hi3798mv200.c

··· 133 133 goto tuning_out; 134 134 135 135 prev_err = err; 136 - err = 0; 137 136 } 138 137 139 138 tuning_out:

-1

drivers/mmc/host/mtk-sd.c

··· 13 13 #include <linux/ioport.h> 14 14 #include <linux/irq.h> 15 15 #include <linux/of.h> 16 - #include <linux/of_gpio.h> 17 16 #include <linux/pinctrl/consumer.h> 18 17 #include <linux/platform_device.h> 19 18 #include <linux/pm.h>

+3

drivers/mmc/host/renesas_sdhi_core.c

··· 589 589 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); 590 590 priv->needs_adjust_hs400 = false; 591 591 renesas_sdhi_set_clock(host, host->clk_cache); 592 + 593 + /* Ensure default value for this driver. */ 594 + renesas_sdhi_sdbuf_width(host, 16); 592 595 } else if (priv->scc_ctl) { 593 596 renesas_sdhi_scc_reset(host, priv); 594 597 }

+5 -4

drivers/mmc/host/renesas_sdhi_internal_dmac.c

··· 210 210 .manual_tap_correction = true, 211 211 }; 212 212 213 - static const struct renesas_sdhi_quirks sdhi_quirks_r9a09g011 = { 213 + static const struct renesas_sdhi_quirks sdhi_quirks_rzg2l = { 214 214 .fixed_addr_mode = true, 215 215 .hs400_disabled = true, 216 216 }; ··· 255 255 .quirks = &sdhi_quirks_r8a77990, 256 256 }; 257 257 258 - static const struct renesas_sdhi_of_data_with_quirks of_r9a09g011_compatible = { 258 + static const struct renesas_sdhi_of_data_with_quirks of_rzg2l_compatible = { 259 259 .of_data = &of_data_rcar_gen3, 260 - .quirks = &sdhi_quirks_r9a09g011, 260 + .quirks = &sdhi_quirks_rzg2l, 261 261 }; 262 262 263 263 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = { ··· 283 283 { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, }, 284 284 { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, 285 285 { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, }, 286 - { .compatible = "renesas,sdhi-r9a09g011", .data = &of_r9a09g011_compatible, }, 286 + { .compatible = "renesas,sdhi-r9a09g011", .data = &of_rzg2l_compatible, }, 287 + { .compatible = "renesas,rzg2l-sdhi", .data = &of_rzg2l_compatible, }, 287 288 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 288 289 { .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, }, 289 290 {},

+55 -6

drivers/mmc/host/sdhci-acpi.c

··· 10 10 #include <linux/export.h> 11 11 #include <linux/module.h> 12 12 #include <linux/device.h> 13 + #include <linux/pinctrl/pinconf-generic.h> 13 14 #include <linux/platform_device.h> 14 15 #include <linux/ioport.h> 15 16 #include <linux/io.h> ··· 81 80 enum { 82 81 DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP = BIT(0), 83 82 DMI_QUIRK_SD_NO_WRITE_PROTECT = BIT(1), 83 + DMI_QUIRK_SD_CD_ACTIVE_HIGH = BIT(2), 84 + DMI_QUIRK_SD_CD_ENABLE_PULL_UP = BIT(3), 84 85 }; 85 86 86 87 static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c) ··· 722 719 }; 723 720 MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids); 724 721 722 + /* Please keep this list sorted alphabetically */ 725 723 static const struct dmi_system_id sdhci_acpi_quirks[] = { 724 + { 725 + /* 726 + * The Acer Aspire Switch 10 (SW5-012) microSD slot always 727 + * reports the card being write-protected even though microSD 728 + * cards do not have a write-protect switch at all. 729 + */ 730 + .matches = { 731 + DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 732 + DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"), 733 + }, 734 + .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT, 735 + }, 736 + { 737 + /* Asus T100TA, needs pull-up for cd but DSDT GpioInt has NoPull set */ 738 + .matches = { 739 + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 740 + DMI_MATCH(DMI_PRODUCT_NAME, "T100TA"), 741 + }, 742 + .driver_data = (void *)DMI_QUIRK_SD_CD_ENABLE_PULL_UP, 743 + }, 726 744 { 727 745 /* 728 746 * The Lenovo Miix 320-10ICR has a bug in the _PS0 method of ··· 760 736 }, 761 737 { 762 738 /* 763 - * The Acer Aspire Switch 10 (SW5-012) microSD slot always 764 - * reports the card being write-protected even though microSD 765 - * cards do not have a write-protect switch at all. 739 + * Lenovo Yoga Tablet 2 Pro 1380F/L (13" Android version) this 740 + * has broken WP reporting and an inverted CD signal. 741 + * Note this has more or less the same BIOS as the Lenovo Yoga 742 + * Tablet 2 830F/L or 1050F/L (8" and 10" Android), but unlike 743 + * the 830 / 1050 models which share the same mainboard this 744 + * model has a different mainboard and the inverted CD and 745 + * broken WP are unique to this board. 766 746 */ 767 747 .matches = { 768 - DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 769 - DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"), 748 + DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."), 749 + DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"), 750 + DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"), 751 + /* Full match so as to NOT match the 830/1050 BIOS */ 752 + DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21.X64.0005.R00.1504101516"), 770 753 }, 771 - .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT, 754 + .driver_data = (void *)(DMI_QUIRK_SD_NO_WRITE_PROTECT | 755 + DMI_QUIRK_SD_CD_ACTIVE_HIGH), 772 756 }, 773 757 { 774 758 /* ··· 786 754 .matches = { 787 755 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 788 756 DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA ENCORE 2 WT8-B"), 757 + }, 758 + .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT, 759 + }, 760 + { 761 + /* 762 + * The Toshiba WT10-A's microSD slot always reports the card being 763 + * write-protected. 764 + */ 765 + .matches = { 766 + DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 767 + DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA WT10-A"), 789 768 }, 790 769 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT, 791 770 }, ··· 909 866 if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) { 910 867 bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL); 911 868 869 + if (quirks & DMI_QUIRK_SD_CD_ACTIVE_HIGH) 870 + host->mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 871 + 912 872 err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0); 913 873 if (err) { 914 874 if (err == -EPROBE_DEFER) 915 875 goto err_free; 916 876 dev_warn(dev, "failed to setup card detect gpio\n"); 917 877 c->use_runtime_pm = false; 878 + } else if (quirks & DMI_QUIRK_SD_CD_ENABLE_PULL_UP) { 879 + mmc_gpiod_set_cd_config(host->mmc, 880 + PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 20000)); 918 881 } 919 882 920 883 if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP)

+1 -1

drivers/mmc/host/sdhci-esdhc-mcf.c

··· 335 335 data->blksz * data->blocks); 336 336 } 337 337 338 - static struct sdhci_ops sdhci_esdhc_ops = { 338 + static const struct sdhci_ops sdhci_esdhc_ops = { 339 339 .reset = esdhc_mcf_reset, 340 340 .set_clock = esdhc_mcf_pltfm_set_clock, 341 341 .get_max_clock = esdhc_mcf_pltfm_get_max_clock,

+302 -3

drivers/mmc/host/sdhci-of-dwcmshc.c

··· 21 21 #include <linux/sizes.h> 22 22 23 23 #include "sdhci-pltfm.h" 24 + #include "cqhci.h" 24 25 25 26 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16) 26 27 ··· 53 52 #define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */ 54 53 #define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */ 55 54 55 + /* DWC IP vendor area 2 pointer */ 56 + #define DWCMSHC_P_VENDOR_AREA2 0xea 57 + 56 58 /* Sophgo CV18XX specific Registers */ 57 59 #define CV18XX_SDHCI_MSHC_CTRL 0x00 58 60 #define CV18XX_EMMC_FUNC_EN BIT(0) ··· 69 65 #define CV18XX_PHY_RX_SRC_INVERT_RX_CLK 0x1 70 66 #define CV18XX_SDHCI_PHY_CONFIG 0x4c 71 67 #define CV18XX_PHY_TX_BPS BIT(0) 68 + 69 + #define CV18XX_TUNE_MAX 128 70 + #define CV18XX_TUNE_STEP 1 71 + #define CV18XX_RETRY_TUNING_MAX 50 72 72 73 73 /* Rockchip specific Registers */ 74 74 #define DWCMSHC_EMMC_DLL_CTRL 0x800 ··· 189 181 #define BOUNDARY_OK(addr, len) \ 190 182 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) 191 183 184 + #define DWCMSHC_SDHCI_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 185 + SDHCI_TRNS_BLK_CNT_EN | \ 186 + SDHCI_TRNS_DMA) 187 + 192 188 enum dwcmshc_rk_type { 193 189 DWCMSHC_RK3568, 194 190 DWCMSHC_RK3588, ··· 208 196 209 197 struct dwcmshc_priv { 210 198 struct clk *bus_clk; 211 - int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */ 199 + int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */ 200 + int vendor_specific_area2; /* P_VENDOR_SPECIFIC_AREA2 reg */ 201 + 212 202 void *priv; /* pointer to SoC private stuff */ 213 203 u16 delay_line; 214 204 u16 flags; ··· 469 455 sdhci_writel(host, vendor, reg); 470 456 } 471 457 458 + static int dwcmshc_execute_tuning(struct mmc_host *mmc, u32 opcode) 459 + { 460 + int err = sdhci_execute_tuning(mmc, opcode); 461 + struct sdhci_host *host = mmc_priv(mmc); 462 + 463 + if (err) 464 + return err; 465 + 466 + /* 467 + * Tuning can leave the IP in an active state (Buffer Read Enable bit 468 + * set) which prevents the entry to low power states (i.e. S0i3). Data 469 + * reset will clear it. 470 + */ 471 + sdhci_reset(host, SDHCI_RESET_DATA); 472 + 473 + return 0; 474 + } 475 + 476 + static u32 dwcmshc_cqe_irq_handler(struct sdhci_host *host, u32 intmask) 477 + { 478 + int cmd_error = 0; 479 + int data_error = 0; 480 + 481 + if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 482 + return intmask; 483 + 484 + cqhci_irq(host->mmc, intmask, cmd_error, data_error); 485 + 486 + return 0; 487 + } 488 + 489 + static void dwcmshc_sdhci_cqe_enable(struct mmc_host *mmc) 490 + { 491 + struct sdhci_host *host = mmc_priv(mmc); 492 + u8 ctrl; 493 + 494 + sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 495 + 496 + sdhci_cqe_enable(mmc); 497 + 498 + /* 499 + * The "DesignWare Cores Mobile Storage Host Controller 500 + * DWC_mshc / DWC_mshc_lite Databook" says: 501 + * when Host Version 4 Enable" is 1 in Host Control 2 register, 502 + * SDHCI_CTRL_ADMA32 bit means ADMA2 is selected. 503 + * Selection of 32-bit/64-bit System Addressing: 504 + * either 32-bit or 64-bit system addressing is selected by 505 + * 64-bit Addressing bit in Host Control 2 register. 506 + * 507 + * On the other hand the "DesignWare Cores Mobile Storage Host 508 + * Controller DWC_mshc / DWC_mshc_lite User Guide" says, that we have to 509 + * set DMA_SEL to ADMA2 _only_ mode in the Host Control 2 register. 510 + */ 511 + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 512 + ctrl &= ~SDHCI_CTRL_DMA_MASK; 513 + ctrl |= SDHCI_CTRL_ADMA32; 514 + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 515 + } 516 + 517 + static void dwcmshc_set_tran_desc(struct cqhci_host *cq_host, u8 **desc, 518 + dma_addr_t addr, int len, bool end, bool dma64) 519 + { 520 + int tmplen, offset; 521 + 522 + if (likely(!len || BOUNDARY_OK(addr, len))) { 523 + cqhci_set_tran_desc(*desc, addr, len, end, dma64); 524 + return; 525 + } 526 + 527 + offset = addr & (SZ_128M - 1); 528 + tmplen = SZ_128M - offset; 529 + cqhci_set_tran_desc(*desc, addr, tmplen, false, dma64); 530 + 531 + addr += tmplen; 532 + len -= tmplen; 533 + *desc += cq_host->trans_desc_len; 534 + cqhci_set_tran_desc(*desc, addr, len, end, dma64); 535 + } 536 + 537 + static void dwcmshc_cqhci_dumpregs(struct mmc_host *mmc) 538 + { 539 + sdhci_dumpregs(mmc_priv(mmc)); 540 + } 541 + 472 542 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) 473 543 { 474 544 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ··· 784 686 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); 785 687 } 786 688 689 + static void cv18xx_sdhci_set_tap(struct sdhci_host *host, int tap) 690 + { 691 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 692 + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 693 + u16 clk; 694 + u32 val; 695 + 696 + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 697 + clk &= ~SDHCI_CLOCK_CARD_EN; 698 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 699 + 700 + val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 701 + val &= ~CV18XX_LATANCY_1T; 702 + sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 703 + 704 + val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) | 705 + FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) | 706 + FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, tap)); 707 + sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); 708 + 709 + sdhci_writel(host, 0, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 710 + 711 + clk |= SDHCI_CLOCK_CARD_EN; 712 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 713 + usleep_range(1000, 2000); 714 + } 715 + 716 + static int cv18xx_retry_tuning(struct mmc_host *mmc, u32 opcode, int *cmd_error) 717 + { 718 + int ret, retry = 0; 719 + 720 + while (retry < CV18XX_RETRY_TUNING_MAX) { 721 + ret = mmc_send_tuning(mmc, opcode, NULL); 722 + if (ret) 723 + return ret; 724 + retry++; 725 + } 726 + 727 + return 0; 728 + } 729 + 730 + static void cv18xx_sdhci_post_tuning(struct sdhci_host *host) 731 + { 732 + u32 val; 733 + 734 + val = sdhci_readl(host, SDHCI_INT_STATUS); 735 + val |= SDHCI_INT_DATA_AVAIL; 736 + sdhci_writel(host, val, SDHCI_INT_STATUS); 737 + 738 + sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 739 + } 740 + 741 + static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 742 + { 743 + int min, max, avg, ret; 744 + int win_length, target_min, target_max, target_win_length; 745 + 746 + min = max = 0; 747 + target_win_length = 0; 748 + 749 + sdhci_reset_tuning(host); 750 + 751 + while (max < CV18XX_TUNE_MAX) { 752 + /* find the mininum delay first which can pass tuning */ 753 + while (min < CV18XX_TUNE_MAX) { 754 + cv18xx_sdhci_set_tap(host, min); 755 + if (!cv18xx_retry_tuning(host->mmc, opcode, NULL)) 756 + break; 757 + min += CV18XX_TUNE_STEP; 758 + } 759 + 760 + /* find the maxinum delay which can not pass tuning */ 761 + max = min + CV18XX_TUNE_STEP; 762 + while (max < CV18XX_TUNE_MAX) { 763 + cv18xx_sdhci_set_tap(host, max); 764 + if (cv18xx_retry_tuning(host->mmc, opcode, NULL)) { 765 + max -= CV18XX_TUNE_STEP; 766 + break; 767 + } 768 + max += CV18XX_TUNE_STEP; 769 + } 770 + 771 + win_length = max - min + 1; 772 + /* get the largest pass window */ 773 + if (win_length > target_win_length) { 774 + target_win_length = win_length; 775 + target_min = min; 776 + target_max = max; 777 + } 778 + 779 + /* continue to find the next pass window */ 780 + min = max + CV18XX_TUNE_STEP; 781 + } 782 + 783 + cv18xx_sdhci_post_tuning(host); 784 + 785 + /* use average delay to get the best timing */ 786 + avg = (target_min + target_max) / 2; 787 + cv18xx_sdhci_set_tap(host, avg); 788 + ret = mmc_send_tuning(host->mmc, opcode, NULL); 789 + 790 + dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 791 + ret ? "failed" : "passed", avg, ret); 792 + 793 + return ret; 794 + } 795 + 787 796 static const struct sdhci_ops sdhci_dwcmshc_ops = { 788 797 .set_clock = sdhci_set_clock, 789 798 .set_bus_width = sdhci_set_bus_width, ··· 898 693 .get_max_clock = dwcmshc_get_max_clock, 899 694 .reset = sdhci_reset, 900 695 .adma_write_desc = dwcmshc_adma_write_desc, 696 + .irq = dwcmshc_cqe_irq_handler, 901 697 }; 902 698 903 699 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { ··· 918 712 .reset = th1520_sdhci_reset, 919 713 .adma_write_desc = dwcmshc_adma_write_desc, 920 714 .voltage_switch = dwcmshc_phy_1_8v_init, 921 - .platform_execute_tuning = &th1520_execute_tuning, 715 + .platform_execute_tuning = th1520_execute_tuning, 922 716 }; 923 717 924 718 static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = { ··· 928 722 .get_max_clock = dwcmshc_get_max_clock, 929 723 .reset = cv18xx_sdhci_reset, 930 724 .adma_write_desc = dwcmshc_adma_write_desc, 725 + .platform_execute_tuning = cv18xx_sdhci_execute_tuning, 931 726 }; 932 727 933 728 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { ··· 965 758 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 966 759 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 967 760 }; 761 + 762 + static const struct cqhci_host_ops dwcmshc_cqhci_ops = { 763 + .enable = dwcmshc_sdhci_cqe_enable, 764 + .disable = sdhci_cqe_disable, 765 + .dumpregs = dwcmshc_cqhci_dumpregs, 766 + .set_tran_desc = dwcmshc_set_tran_desc, 767 + }; 768 + 769 + static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev) 770 + { 771 + struct cqhci_host *cq_host; 772 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 773 + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 774 + bool dma64 = false; 775 + u16 clk; 776 + int err; 777 + 778 + host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 779 + cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 780 + if (!cq_host) { 781 + dev_err(mmc_dev(host->mmc), "Unable to setup CQE: not enough memory\n"); 782 + goto dsbl_cqe_caps; 783 + } 784 + 785 + /* 786 + * For dwcmshc host controller we have to enable internal clock 787 + * before access to some registers from Vendor Specific Area 2. 788 + */ 789 + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 790 + clk |= SDHCI_CLOCK_INT_EN; 791 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 792 + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 793 + if (!(clk & SDHCI_CLOCK_INT_EN)) { 794 + dev_err(mmc_dev(host->mmc), "Unable to setup CQE: internal clock enable error\n"); 795 + goto free_cq_host; 796 + } 797 + 798 + cq_host->mmio = host->ioaddr + priv->vendor_specific_area2; 799 + cq_host->ops = &dwcmshc_cqhci_ops; 800 + 801 + /* Enable using of 128-bit task descriptors */ 802 + dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 803 + if (dma64) { 804 + dev_dbg(mmc_dev(host->mmc), "128-bit task descriptors\n"); 805 + cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 806 + } 807 + err = cqhci_init(cq_host, host->mmc, dma64); 808 + if (err) { 809 + dev_err(mmc_dev(host->mmc), "Unable to setup CQE: error %d\n", err); 810 + goto int_clock_disable; 811 + } 812 + 813 + dev_dbg(mmc_dev(host->mmc), "CQE init done\n"); 814 + 815 + return; 816 + 817 + int_clock_disable: 818 + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 819 + clk &= ~SDHCI_CLOCK_INT_EN; 820 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 821 + 822 + free_cq_host: 823 + devm_kfree(&pdev->dev, cq_host); 824 + 825 + dsbl_cqe_caps: 826 + host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD); 827 + } 968 828 969 829 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 970 830 { ··· 1137 863 struct rk35xx_priv *rk_priv = NULL; 1138 864 const struct sdhci_pltfm_data *pltfm_data; 1139 865 int err; 1140 - u32 extra; 866 + u32 extra, caps; 1141 867 1142 868 pltfm_data = device_get_match_data(&pdev->dev); 1143 869 if (!pltfm_data) { ··· 1188 914 1189 915 host->mmc_host_ops.request = dwcmshc_request; 1190 916 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; 917 + host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning; 1191 918 1192 919 if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) { 1193 920 rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL); ··· 1238 963 sdhci_enable_v4_mode(host); 1239 964 #endif 1240 965 966 + caps = sdhci_readl(host, SDHCI_CAPABILITIES); 967 + if (caps & SDHCI_CAN_64BIT_V4) 968 + sdhci_enable_v4_mode(host); 969 + 1241 970 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1242 971 1243 972 pm_runtime_get_noresume(dev); ··· 1251 972 err = sdhci_setup_host(host); 1252 973 if (err) 1253 974 goto err_rpm; 975 + 976 + /* Setup Command Queue Engine if enabled */ 977 + if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 978 + priv->vendor_specific_area2 = 979 + sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2); 980 + 981 + dwcmshc_cqhci_init(host, pdev); 982 + } 1254 983 1255 984 if (rk_priv) 1256 985 dwcmshc_rk35xx_postinit(host, priv); ··· 1332 1045 1333 1046 pm_runtime_resume(dev); 1334 1047 1048 + if (host->mmc->caps2 & MMC_CAP2_CQE) { 1049 + ret = cqhci_suspend(host->mmc); 1050 + if (ret) 1051 + return ret; 1052 + } 1053 + 1335 1054 ret = sdhci_suspend_host(host); 1336 1055 if (ret) 1337 1056 return ret; ··· 1381 1088 ret = sdhci_resume_host(host); 1382 1089 if (ret) 1383 1090 goto disable_rockchip_clks; 1091 + 1092 + if (host->mmc->caps2 & MMC_CAP2_CQE) { 1093 + ret = cqhci_resume(host->mmc); 1094 + if (ret) 1095 + goto disable_rockchip_clks; 1096 + } 1384 1097 1385 1098 return 0; 1386 1099

+1 -1

drivers/mmc/host/sdhci-omap.c

··· 925 925 __sdhci_set_timeout(host, cmd); 926 926 } 927 927 928 - static struct sdhci_ops sdhci_omap_ops = { 928 + static const struct sdhci_ops sdhci_omap_ops = { 929 929 .set_clock = sdhci_omap_set_clock, 930 930 .set_power = sdhci_omap_set_power, 931 931 .enable_dma = sdhci_omap_enable_dma,

+18 -28

drivers/mmc/host/sdhci-pci-gli.c

··· 25 25 #define GLI_9750_WT_EN_ON 0x1 26 26 #define GLI_9750_WT_EN_OFF 0x0 27 27 28 - #define PCI_GLI_9750_PM_CTRL 0xFC 29 - #define PCI_GLI_9750_PM_STATE GENMASK(1, 0) 30 - 31 - #define PCI_GLI_9750_CORRERR_MASK 0x214 32 - #define PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12) 33 - 34 28 #define SDHCI_GLI_9750_CFG2 0x848 35 29 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) 36 30 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F ··· 145 151 146 152 #define PCI_GLI_9755_MISC 0x78 147 153 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) 148 - 149 - #define PCI_GLI_9755_PM_CTRL 0xFC 150 - #define PCI_GLI_9755_PM_STATE GENMASK(1, 0) 151 - 152 - #define PCI_GLI_9755_CORRERR_MASK 0x214 153 - #define PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12) 154 154 155 155 #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 156 156 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) ··· 535 547 { 536 548 struct sdhci_pci_slot *slot = sdhci_priv(host); 537 549 struct pci_dev *pdev; 550 + int aer; 538 551 u32 value; 539 552 540 553 pdev = slot->chip->pdev; ··· 550 561 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); 551 562 552 563 /* toggle PM state to allow GL9750 to enter ASPM L1.2 */ 553 - pci_read_config_dword(pdev, PCI_GLI_9750_PM_CTRL, &value); 554 - value |= PCI_GLI_9750_PM_STATE; 555 - pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); 556 - value &= ~PCI_GLI_9750_PM_STATE; 557 - pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); 564 + pci_set_power_state(pdev, PCI_D3hot); 565 + pci_set_power_state(pdev, PCI_D0); 558 566 559 567 /* mask the replay timer timeout of AER */ 560 - pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value); 561 - value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT; 562 - pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value); 568 + aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 569 + if (aer) { 570 + pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value); 571 + value |= PCI_ERR_COR_REP_TIMER; 572 + pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value); 573 + } 563 574 564 575 gl9750_wt_off(host); 565 576 } ··· 734 745 static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 735 746 { 736 747 struct pci_dev *pdev = slot->chip->pdev; 748 + int aer; 737 749 u32 value; 738 750 739 751 gl9755_wt_on(pdev); ··· 765 775 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); 766 776 767 777 /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ 768 - pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value); 769 - value |= PCI_GLI_9755_PM_STATE; 770 - pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); 771 - value &= ~PCI_GLI_9755_PM_STATE; 772 - pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); 778 + pci_set_power_state(pdev, PCI_D3hot); 779 + pci_set_power_state(pdev, PCI_D0); 773 780 774 781 /* mask the replay timer timeout of AER */ 775 - pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value); 776 - value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT; 777 - pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value); 782 + aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 783 + if (aer) { 784 + pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value); 785 + value |= PCI_ERR_COR_REP_TIMER; 786 + pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value); 787 + } 778 788 779 789 gl9755_wt_off(pdev); 780 790 }

+18 -17

drivers/mmc/host/sdhci-s3c.c

··· 17 17 #include <linux/slab.h> 18 18 #include <linux/clk.h> 19 19 #include <linux/io.h> 20 - #include <linux/gpio.h> 21 20 #include <linux/module.h> 22 21 #include <linux/of.h> 23 - #include <linux/of_gpio.h> 24 22 #include <linux/pm.h> 25 23 #include <linux/pm_runtime.h> 26 24 ··· 130 132 * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data 131 133 * @sdhci_quirks: sdhci host specific quirks. 132 134 * @no_divider: no or non-standard internal clock divider. 135 + * @ops: sdhci_ops to use for this variant 133 136 * 134 137 * Specifies platform specific configuration of sdhci controller. 135 138 * Note: A structure for driver specific platform data is used for future 136 139 * expansion of its usage. 137 140 */ 138 141 struct sdhci_s3c_drv_data { 139 - unsigned int sdhci_quirks; 140 - bool no_divider; 142 + unsigned int sdhci_quirks; 143 + bool no_divider; 144 + const struct sdhci_ops *ops; 141 145 }; 142 146 143 147 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) ··· 414 414 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 415 415 } 416 416 417 - static struct sdhci_ops sdhci_s3c_ops = { 417 + static const struct sdhci_ops sdhci_s3c_ops_s3c6410 = { 418 418 .get_max_clock = sdhci_s3c_get_max_clk, 419 419 .set_clock = sdhci_s3c_set_clock, 420 420 .get_min_clock = sdhci_s3c_get_min_clock, 421 + .set_bus_width = sdhci_set_bus_width, 422 + .reset = sdhci_reset, 423 + .set_uhs_signaling = sdhci_set_uhs_signaling, 424 + }; 425 + 426 + static const struct sdhci_ops sdhci_s3c_ops_exynos4 __maybe_unused = { 427 + .get_max_clock = sdhci_cmu_get_max_clock, 428 + .set_clock = sdhci_cmu_set_clock, 429 + .get_min_clock = sdhci_cmu_get_min_clock, 421 430 .set_bus_width = sdhci_set_bus_width, 422 431 .reset = sdhci_reset, 423 432 .set_uhs_signaling = sdhci_set_uhs_signaling, ··· 455 446 return 0; 456 447 } 457 448 458 - if (of_get_named_gpio(node, "cd-gpios", 0)) 449 + if (of_property_present(node, "cd-gpios")) 459 450 return 0; 460 451 461 452 /* assuming internal card detect that will be configured by pinctrl */ ··· 571 562 pdata->cfg_gpio(pdev, pdata->max_width); 572 563 573 564 host->hw_name = "samsung-hsmmc"; 574 - host->ops = &sdhci_s3c_ops; 565 + host->ops = &sdhci_s3c_ops_s3c6410; 575 566 host->quirks = 0; 576 567 host->quirks2 = 0; 577 568 host->irq = irq; ··· 581 572 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; 582 573 if (drv_data) { 583 574 host->quirks |= drv_data->sdhci_quirks; 575 + host->ops = drv_data->ops; 584 576 sc->no_divider = drv_data->no_divider; 585 577 } 586 578 ··· 628 618 629 619 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ 630 620 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 631 - 632 - /* 633 - * If controller does not have internal clock divider, 634 - * we can use overriding functions instead of default. 635 - */ 636 - if (sc->no_divider) { 637 - sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; 638 - sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; 639 - sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; 640 - } 641 621 642 622 /* It supports additional host capabilities if needed */ 643 623 if (pdata->host_caps) ··· 760 760 #ifdef CONFIG_OF 761 761 static const struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { 762 762 .no_divider = true, 763 + .ops = &sdhci_s3c_ops_exynos4, 763 764 }; 764 765 765 766 static const struct of_device_id sdhci_s3c_dt_match[] = {

+1 -2

drivers/mmc/host/sdhci-sprd.c

··· 13 13 #include <linux/mmc/mmc.h> 14 14 #include <linux/module.h> 15 15 #include <linux/of.h> 16 - #include <linux/of_gpio.h> 17 16 #include <linux/pinctrl/consumer.h> 18 17 #include <linux/platform_device.h> 19 18 #include <linux/pm_runtime.h> ··· 439 440 } 440 441 } 441 442 442 - static struct sdhci_ops sdhci_sprd_ops = { 443 + static const struct sdhci_ops sdhci_sprd_ops = { 443 444 .read_l = sdhci_sprd_readl, 444 445 .write_l = sdhci_sprd_writel, 445 446 .write_w = sdhci_sprd_writew,

+8 -2

drivers/mmc/host/sdhci.c

··· 3439 3439 host->data->error = -EILSEQ; 3440 3440 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) 3441 3441 sdhci_err_stats_inc(host, DAT_CRC); 3442 - } else if ((intmask & SDHCI_INT_DATA_CRC) && 3442 + } else if ((intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_TUNING_ERROR)) && 3443 3443 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 3444 3444 != MMC_BUS_TEST_R) { 3445 3445 host->data->error = -EILSEQ; 3446 3446 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) 3447 3447 sdhci_err_stats_inc(host, DAT_CRC); 3448 + if (intmask & SDHCI_INT_TUNING_ERROR) { 3449 + u16 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 3450 + 3451 + ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 3452 + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 3453 + } 3448 3454 } else if (intmask & SDHCI_INT_ADMA_ERROR) { 3449 3455 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc), 3450 3456 intmask); ··· 3985 3979 } else 3986 3980 *cmd_error = 0; 3987 3981 3988 - if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) { 3982 + if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | SDHCI_INT_TUNING_ERROR)) { 3989 3983 *data_error = -EILSEQ; 3990 3984 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) 3991 3985 sdhci_err_stats_inc(host, DAT_CRC);

+2 -1

drivers/mmc/host/sdhci.h

··· 158 158 #define SDHCI_INT_BUS_POWER 0x00800000 159 159 #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 160 160 #define SDHCI_INT_ADMA_ERROR 0x02000000 161 + #define SDHCI_INT_TUNING_ERROR 0x04000000 161 162 162 163 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 163 164 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 ··· 170 169 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 171 170 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 172 171 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 173 - SDHCI_INT_BLK_GAP) 172 + SDHCI_INT_BLK_GAP | SDHCI_INT_TUNING_ERROR) 174 173 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 175 174 176 175 #define SDHCI_CQE_INT_ERR_MASK ( \

+141 -41

drivers/mmc/host/sdhci_am654.c

··· 141 141 142 142 struct sdhci_am654_data { 143 143 struct regmap *base; 144 - int otap_del_sel[ARRAY_SIZE(td)]; 145 - int itap_del_sel[ARRAY_SIZE(td)]; 144 + u32 otap_del_sel[ARRAY_SIZE(td)]; 145 + u32 itap_del_sel[ARRAY_SIZE(td)]; 146 + u32 itap_del_ena[ARRAY_SIZE(td)]; 146 147 int clkbuf_sel; 147 148 int trm_icp; 148 149 int drv_strength; 149 150 int strb_sel; 150 151 u32 flags; 151 152 u32 quirks; 153 + bool dll_enable; 152 154 153 155 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 156 + }; 157 + 158 + struct window { 159 + u8 start; 160 + u8 end; 161 + u8 length; 154 162 }; 155 163 156 164 struct sdhci_am654_driver_data { ··· 240 232 } 241 233 242 234 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 243 - u32 itapdly) 235 + u32 itapdly, u32 enable) 244 236 { 245 237 /* Set ITAPCHGWIN before writing to ITAPDLY */ 246 238 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 247 239 1 << ITAPCHGWIN_SHIFT); 240 + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 241 + enable << ITAPDLYENA_SHIFT); 248 242 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 249 243 itapdly << ITAPDLYSEL_SHIFT); 250 244 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); ··· 263 253 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 264 254 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 265 255 266 - sdhci_am654_write_itapdly(sdhci_am654, 267 - sdhci_am654->itap_del_sel[timing]); 256 + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], 257 + sdhci_am654->itap_del_ena[timing]); 268 258 } 269 259 270 260 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) ··· 273 263 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 274 264 unsigned char timing = host->mmc->ios.timing; 275 265 u32 otap_del_sel; 276 - u32 otap_del_ena; 277 266 u32 mask, val; 278 267 279 268 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 280 269 281 270 sdhci_set_clock(host, clock); 282 271 283 - /* Setup DLL Output TAP delay */ 272 + /* Setup Output TAP delay */ 284 273 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 285 - otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 286 274 287 275 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 288 - val = (otap_del_ena << OTAPDLYENA_SHIFT) | 276 + val = (0x1 << OTAPDLYENA_SHIFT) | 289 277 (otap_del_sel << OTAPDLYSEL_SHIFT); 290 278 291 279 /* Write to STRBSEL for HS400 speed mode */ ··· 298 290 299 291 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 300 292 301 - if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) 293 + if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { 302 294 sdhci_am654_setup_dll(host, clock); 303 - else 295 + sdhci_am654->dll_enable = true; 296 + 297 + if (timing == MMC_TIMING_MMC_HS400) { 298 + sdhci_am654->itap_del_ena[timing] = 0x1; 299 + sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1]; 300 + } 301 + 302 + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], 303 + sdhci_am654->itap_del_ena[timing]); 304 + } else { 304 305 sdhci_am654_setup_delay_chain(sdhci_am654, timing); 306 + sdhci_am654->dll_enable = false; 307 + } 305 308 306 309 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 307 310 sdhci_am654->clkbuf_sel); ··· 325 306 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 326 307 unsigned char timing = host->mmc->ios.timing; 327 308 u32 otap_del_sel; 309 + u32 itap_del_ena; 310 + u32 itap_del_sel; 328 311 u32 mask, val; 329 312 330 - /* Setup DLL Output TAP delay */ 313 + /* Setup Output TAP delay */ 331 314 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 332 315 333 316 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 334 317 val = (0x1 << OTAPDLYENA_SHIFT) | 335 318 (otap_del_sel << OTAPDLYSEL_SHIFT); 336 - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 337 319 320 + /* Setup Input TAP delay */ 321 + itap_del_ena = sdhci_am654->itap_del_ena[timing]; 322 + itap_del_sel = sdhci_am654->itap_del_sel[timing]; 323 + 324 + mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK; 325 + val |= (itap_del_ena << ITAPDLYENA_SHIFT) | 326 + (itap_del_sel << ITAPDLYSEL_SHIFT); 327 + 328 + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 329 + 1 << ITAPCHGWIN_SHIFT); 330 + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 331 + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 338 332 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 339 333 sdhci_am654->clkbuf_sel); 340 334 ··· 440 408 return 0; 441 409 } 442 410 443 - #define ITAP_MAX 32 411 + #define ITAPDLY_LENGTH 32 412 + #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) 413 + 414 + static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window 415 + *fail_window, u8 num_fails, bool circular_buffer) 416 + { 417 + u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; 418 + u8 first_fail_start = 0, last_fail_end = 0; 419 + struct device *dev = mmc_dev(host->mmc); 420 + struct window pass_window = {0, 0, 0}; 421 + int prev_fail_end = -1; 422 + u8 i; 423 + 424 + if (!num_fails) 425 + return ITAPDLY_LAST_INDEX >> 1; 426 + 427 + if (fail_window->length == ITAPDLY_LENGTH) { 428 + dev_err(dev, "No passing ITAPDLY, return 0\n"); 429 + return 0; 430 + } 431 + 432 + first_fail_start = fail_window->start; 433 + last_fail_end = fail_window[num_fails - 1].end; 434 + 435 + for (i = 0; i < num_fails; i++) { 436 + start_fail = fail_window[i].start; 437 + end_fail = fail_window[i].end; 438 + pass_length = start_fail - (prev_fail_end + 1); 439 + 440 + if (pass_length > pass_window.length) { 441 + pass_window.start = prev_fail_end + 1; 442 + pass_window.length = pass_length; 443 + } 444 + prev_fail_end = end_fail; 445 + } 446 + 447 + if (!circular_buffer) 448 + pass_length = ITAPDLY_LAST_INDEX - last_fail_end; 449 + else 450 + pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start; 451 + 452 + if (pass_length > pass_window.length) { 453 + pass_window.start = last_fail_end + 1; 454 + pass_window.length = pass_length; 455 + } 456 + 457 + if (!circular_buffer) 458 + itap = pass_window.start + (pass_window.length >> 1); 459 + else 460 + itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; 461 + 462 + return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap; 463 + } 464 + 444 465 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 445 466 u32 opcode) 446 467 { 447 468 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 448 469 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 449 - int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len; 450 - u32 itap; 470 + unsigned char timing = host->mmc->ios.timing; 471 + struct window fail_window[ITAPDLY_LENGTH]; 472 + u8 curr_pass, itap; 473 + u8 fail_index = 0; 474 + u8 prev_pass = 1; 475 + 476 + memset(fail_window, 0, sizeof(fail_window)); 451 477 452 478 /* Enable ITAPDLY */ 453 - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 454 - 1 << ITAPDLYENA_SHIFT); 479 + sdhci_am654->itap_del_ena[timing] = 0x1; 455 480 456 - for (itap = 0; itap < ITAP_MAX; itap++) { 457 - sdhci_am654_write_itapdly(sdhci_am654, itap); 481 + for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { 482 + sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); 458 483 459 - cur_val = !mmc_send_tuning(host->mmc, opcode, NULL); 460 - if (cur_val && !prev_val) 461 - pass_window = itap; 484 + curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); 462 485 463 - if (!cur_val) 464 - fail_len++; 486 + if (!curr_pass && prev_pass) 487 + fail_window[fail_index].start = itap; 465 488 466 - prev_val = cur_val; 489 + if (!curr_pass) { 490 + fail_window[fail_index].end = itap; 491 + fail_window[fail_index].length++; 492 + } 493 + 494 + if (curr_pass && !prev_pass) 495 + fail_index++; 496 + 497 + prev_pass = curr_pass; 467 498 } 468 - /* 469 - * Having determined the length of the failing window and start of 470 - * the passing window calculate the length of the passing window and 471 - * set the final value halfway through it considering the range as a 472 - * circular buffer 473 - */ 474 - pass_len = ITAP_MAX - fail_len; 475 - itap = (pass_window + (pass_len >> 1)) % ITAP_MAX; 476 - sdhci_am654_write_itapdly(sdhci_am654, itap); 499 + 500 + if (fail_window[fail_index].length != 0) 501 + fail_index++; 502 + 503 + itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, 504 + sdhci_am654->dll_enable); 505 + 506 + sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); 507 + 508 + /* Save ITAPDLY */ 509 + sdhci_am654->itap_del_sel[timing] = itap; 477 510 478 511 return 0; 479 512 } 480 513 481 - static struct sdhci_ops sdhci_am654_ops = { 514 + static const struct sdhci_ops sdhci_am654_ops = { 482 515 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 483 516 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 484 517 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, ··· 573 476 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 574 477 }; 575 478 576 - static struct sdhci_ops sdhci_j721e_8bit_ops = { 479 + static const struct sdhci_ops sdhci_j721e_8bit_ops = { 577 480 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 578 481 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 579 482 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, ··· 597 500 .flags = DLL_PRESENT | DLL_CALIB, 598 501 }; 599 502 600 - static struct sdhci_ops sdhci_j721e_4bit_ops = { 503 + static const struct sdhci_ops sdhci_j721e_4bit_ops = { 601 504 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 602 505 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 603 506 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, ··· 687 590 host->mmc->caps2 &= ~td[i].capability; 688 591 } 689 592 690 - if (td[i].itap_binding) 691 - device_property_read_u32(dev, td[i].itap_binding, 692 - &sdhci_am654->itap_del_sel[i]); 593 + if (td[i].itap_binding) { 594 + ret = device_property_read_u32(dev, td[i].itap_binding, 595 + &sdhci_am654->itap_del_sel[i]); 596 + if (!ret) 597 + sdhci_am654->itap_del_ena[i] = 0x1; 598 + } 693 599 } 694 600 695 601 return 0;

+1 -20

drivers/net/wireless/ath/ath10k/sdio.c

··· 2667 2667 .probe = ath10k_sdio_probe, 2668 2668 .remove = ath10k_sdio_remove, 2669 2669 .drv = { 2670 - .owner = THIS_MODULE, 2671 2670 .pm = ATH10K_SDIO_PM_OPS, 2672 2671 }, 2673 2672 }; 2674 - 2675 - static int __init ath10k_sdio_init(void) 2676 - { 2677 - int ret; 2678 - 2679 - ret = sdio_register_driver(&ath10k_sdio_driver); 2680 - if (ret) 2681 - pr_err("sdio driver registration failed: %d\n", ret); 2682 - 2683 - return ret; 2684 - } 2685 - 2686 - static void __exit ath10k_sdio_exit(void) 2687 - { 2688 - sdio_unregister_driver(&ath10k_sdio_driver); 2689 - } 2690 - 2691 - module_init(ath10k_sdio_init); 2692 - module_exit(ath10k_sdio_exit); 2673 + module_sdio_driver(ath10k_sdio_driver); 2693 2674 2694 2675 MODULE_AUTHOR("Qualcomm Atheros"); 2695 2676 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN SDIO devices");

-1

drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c

··· 1238 1238 .name = KBUILD_MODNAME, 1239 1239 .id_table = brcmf_sdmmc_ids, 1240 1240 .drv = { 1241 - .owner = THIS_MODULE, 1242 1241 .pm = pm_sleep_ptr(&brcmf_sdio_pm_ops), 1243 1242 .coredump = brcmf_dev_coredump, 1244 1243 },

-1

drivers/net/wireless/marvell/mwifiex/sdio.c

··· 979 979 .probe = mwifiex_sdio_probe, 980 980 .remove = mwifiex_sdio_remove, 981 981 .drv = { 982 - .owner = THIS_MODULE, 983 982 .coredump = mwifiex_sdio_coredump, 984 983 .pm = &mwifiex_sdio_pm_ops, 985 984 }

-1

drivers/net/wireless/silabs/wfx/bus_sdio.c

··· 267 267 .probe = wfx_sdio_probe, 268 268 .remove = wfx_sdio_remove, 269 269 .drv = { 270 - .owner = THIS_MODULE, 271 270 .of_match_table = wfx_sdio_of_match, 272 271 } 273 272 };

+4 -1

include/linux/mmc/sdio_func.h

··· 106 106 .class = (dev_class), \ 107 107 .vendor = SDIO_ANY_ID, .device = SDIO_ANY_ID 108 108 109 - extern int sdio_register_driver(struct sdio_driver *); 109 + /* use a macro to avoid include chaining to get THIS_MODULE */ 110 + #define sdio_register_driver(drv) \ 111 + __sdio_register_driver(drv, THIS_MODULE) 112 + extern int __sdio_register_driver(struct sdio_driver *, struct module *); 110 113 extern void sdio_unregister_driver(struct sdio_driver *); 111 114 112 115 /**

+3 -3

include/linux/mmc/slot-gpio.h

··· 8 8 #ifndef MMC_SLOT_GPIO_H 9 9 #define MMC_SLOT_GPIO_H 10 10 11 + #include <linux/interrupt.h> 11 12 #include <linux/types.h> 12 - #include <linux/irqreturn.h> 13 13 14 14 struct mmc_host; 15 15 ··· 21 21 unsigned int debounce); 22 22 int mmc_gpiod_request_ro(struct mmc_host *host, const char *con_id, 23 23 unsigned int idx, unsigned int debounce); 24 - void mmc_gpio_set_cd_isr(struct mmc_host *host, 25 - irqreturn_t (*isr)(int irq, void *dev_id)); 24 + int mmc_gpiod_set_cd_config(struct mmc_host *host, unsigned long config); 25 + void mmc_gpio_set_cd_isr(struct mmc_host *host, irq_handler_t isr); 26 26 int mmc_gpio_set_cd_wake(struct mmc_host *host, bool on); 27 27 void mmc_gpiod_request_cd_irq(struct mmc_host *host); 28 28 bool mmc_can_gpio_cd(struct mmc_host *host);

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