Merge tag 'drm-fixes-2021-03-19' of git://anongit.freedesktop.org/drm/drm

+2 -32

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

··· 1507 1507 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1508 1508 || pipe_ctx->stream->update_flags.bits.gamut_remap 1509 1509 || pipe_ctx->stream->update_flags.bits.out_csc) { 1510 - struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 1511 - 1512 - if (mpc->funcs->set_gamut_remap) { 1513 - int i; 1514 - int mpcc_id = hubp->inst; 1515 - struct mpc_grph_gamut_adjustment adjust; 1516 - bool enable_remap_dpp = false; 1517 - 1518 - memset(&adjust, 0, sizeof(adjust)); 1519 - adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 1520 - 1521 - /* save the enablement of gamut remap for dpp */ 1522 - enable_remap_dpp = pipe_ctx->stream->gamut_remap_matrix.enable_remap; 1523 - 1524 - /* force bypass gamut remap for dpp/cm */ 1525 - pipe_ctx->stream->gamut_remap_matrix.enable_remap = false; 1526 - dc->hwss.program_gamut_remap(pipe_ctx); 1527 - 1528 - /* restore gamut remap flag and use this remap into mpc */ 1529 - pipe_ctx->stream->gamut_remap_matrix.enable_remap = enable_remap_dpp; 1530 - 1531 - /* build remap matrix for top plane if enabled */ 1532 - if (enable_remap_dpp && pipe_ctx->top_pipe == NULL) { 1533 - adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 1534 - for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 1535 - adjust.temperature_matrix[i] = 1536 - pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 1537 - } 1538 - mpc->funcs->set_gamut_remap(mpc, mpcc_id, &adjust); 1539 - } else 1540 - /* dpp/cm gamut remap*/ 1541 - dc->hwss.program_gamut_remap(pipe_ctx); 1510 + /* dpp/cm gamut remap*/ 1511 + dc->hwss.program_gamut_remap(pipe_ctx); 1542 1512 1543 1513 /*call the dcn2 method which uses mpc csc*/ 1544 1514 dc->hwss.program_output_csc(dc,

+5

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

··· 1595 1595 dcn2_1_soc.num_chans = bw_params->num_channels; 1596 1596 1597 1597 ASSERT(clk_table->num_entries); 1598 + /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */ 1599 + for (i = 0; i < dcn2_1_soc.num_states + 1; i++) { 1600 + clock_limits[i] = dcn2_1_soc.clock_limits[i]; 1601 + } 1602 + 1598 1603 for (i = 0; i < clk_table->num_entries; i++) { 1599 1604 /* loop backwards*/ 1600 1605 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {

+18 -8

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

··· 113 113 struct pwl_result_data *rgb_resulted; 114 114 struct pwl_result_data *rgb; 115 115 struct pwl_result_data *rgb_plus_1; 116 + struct pwl_result_data *rgb_minus_1; 116 117 struct fixed31_32 end_value; 117 118 118 119 int32_t region_start, region_end; ··· 141 140 region_start = -MAX_LOW_POINT; 142 141 region_end = NUMBER_REGIONS - MAX_LOW_POINT; 143 142 } else { 144 - /* 10 segments 143 + /* 11 segments 145 144 * segment is from 2^-10 to 2^0 146 145 * There are less than 256 points, for optimization 147 146 */ ··· 155 154 seg_distr[7] = 4; 156 155 seg_distr[8] = 4; 157 156 seg_distr[9] = 4; 157 + seg_distr[10] = 1; 158 158 159 159 region_start = -10; 160 - region_end = 0; 160 + region_end = 1; 161 161 } 162 162 163 163 for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++) ··· 190 188 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 191 189 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 192 190 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 191 + 192 + rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red; 193 + rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green; 194 + rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue; 193 195 194 196 // All 3 color channels have same x 195 197 corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2), ··· 265 259 266 260 rgb = rgb_resulted; 267 261 rgb_plus_1 = rgb_resulted + 1; 262 + rgb_minus_1 = rgb; 268 263 269 264 i = 1; 270 265 while (i != hw_points + 1) { 271 - if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 272 - rgb_plus_1->red = rgb->red; 273 - if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 274 - rgb_plus_1->green = rgb->green; 275 - if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 276 - rgb_plus_1->blue = rgb->blue; 266 + if (i >= hw_points - 1) { 267 + if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 268 + rgb_plus_1->red = dc_fixpt_add(rgb->red, rgb_minus_1->delta_red); 269 + if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 270 + rgb_plus_1->green = dc_fixpt_add(rgb->green, rgb_minus_1->delta_green); 271 + if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 272 + rgb_plus_1->blue = dc_fixpt_add(rgb->blue, rgb_minus_1->delta_blue); 273 + } 277 274 278 275 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 279 276 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); ··· 292 283 } 293 284 294 285 ++rgb_plus_1; 286 + rgb_minus_1 = rgb; 295 287 ++rgb; 296 288 ++i; 297 289 }

+5 -8

drivers/gpu/drm/i915/i915_perf.c

··· 603 603 { 604 604 int report_size = stream->oa_buffer.format_size; 605 605 struct drm_i915_perf_record_header header; 606 - u32 sample_flags = stream->sample_flags; 607 606 608 607 header.type = DRM_I915_PERF_RECORD_SAMPLE; 609 608 header.pad = 0; ··· 616 617 return -EFAULT; 617 618 buf += sizeof(header); 618 619 619 - if (sample_flags & SAMPLE_OA_REPORT) { 620 - if (copy_to_user(buf, report, report_size)) 621 - return -EFAULT; 622 - } 620 + if (copy_to_user(buf, report, report_size)) 621 + return -EFAULT; 623 622 624 623 (*offset) += header.size; 625 624 ··· 2679 2682 2680 2683 stream->perf->ops.oa_enable(stream); 2681 2684 2682 - if (stream->periodic) 2685 + if (stream->sample_flags & SAMPLE_OA_REPORT) 2683 2686 hrtimer_start(&stream->poll_check_timer, 2684 2687 ns_to_ktime(stream->poll_oa_period), 2685 2688 HRTIMER_MODE_REL_PINNED); ··· 2742 2745 { 2743 2746 stream->perf->ops.oa_disable(stream); 2744 2747 2745 - if (stream->periodic) 2748 + if (stream->sample_flags & SAMPLE_OA_REPORT) 2746 2749 hrtimer_cancel(&stream->poll_check_timer); 2747 2750 } 2748 2751 ··· 3025 3028 * disabled stream as an error. In particular it might otherwise lead 3026 3029 * to a deadlock for blocking file descriptors... 3027 3030 */ 3028 - if (!stream->enabled) 3031 + if (!stream->enabled || !(stream->sample_flags & SAMPLE_OA_REPORT)) 3029 3032 return -EIO; 3030 3033 3031 3034 if (!(file->f_flags & O_NONBLOCK)) {

+22 -1

drivers/gpu/drm/i915/i915_reg.h

··· 3316 3316 3317 3317 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 3318 3318 #define ILK_FBCQ_DIS (1 << 22) 3319 - #define ILK_PABSTRETCH_DIS (1 << 21) 3319 + #define ILK_PABSTRETCH_DIS REG_BIT(21) 3320 + #define ILK_SABSTRETCH_DIS REG_BIT(20) 3321 + #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 3322 + #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 3323 + #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 3324 + #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 3325 + #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 3326 + #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 3327 + #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 3328 + #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 3329 + #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 3330 + #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 3320 3331 3321 3332 3322 3333 /* ··· 8050 8039 8051 8040 #define _CHICKEN_PIPESL_1_A 0x420b0 8052 8041 #define _CHICKEN_PIPESL_1_B 0x420b4 8042 + #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 8043 + #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 8044 + #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 8045 + #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 8046 + #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 8047 + #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 8048 + #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 8049 + #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 8050 + #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 8051 + #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 8053 8052 #define HSW_FBCQ_DIS (1 << 22) 8054 8053 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 8055 8054 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)

+15 -1

drivers/gpu/drm/i915/intel_pm.c

··· 7245 7245 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1, 7246 7246 intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); 7247 7247 7248 - /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 7249 7248 for_each_pipe(dev_priv, pipe) { 7249 + /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 7250 7250 intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe), 7251 7251 intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe)) | 7252 7252 BDW_DPRS_MASK_VBLANK_SRD); 7253 + 7254 + /* Undocumented but fixes async flip + VT-d corruption */ 7255 + if (intel_vtd_active()) 7256 + intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe), 7257 + HSW_PRI_STRETCH_MAX_MASK, HSW_PRI_STRETCH_MAX_X1); 7253 7258 } 7254 7259 7255 7260 /* WaVSRefCountFullforceMissDisable:bdw */ ··· 7290 7285 7291 7286 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) 7292 7287 { 7288 + enum pipe pipe; 7289 + 7293 7290 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 7294 7291 intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A), 7295 7292 intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) | 7296 7293 HSW_FBCQ_DIS); 7294 + 7295 + for_each_pipe(dev_priv, pipe) { 7296 + /* Undocumented but fixes async flip + VT-d corruption */ 7297 + if (intel_vtd_active()) 7298 + intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe), 7299 + HSW_PRI_STRETCH_MAX_MASK, HSW_PRI_STRETCH_MAX_X1); 7300 + } 7297 7301 7298 7302 /* This is required by WaCatErrorRejectionIssue:hsw */ 7299 7303 intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,

+8

drivers/gpu/drm/nouveau/nouveau_bo.c

··· 551 551 552 552 if (!ttm_dma) 553 553 return; 554 + if (!ttm_dma->pages) { 555 + NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma); 556 + return; 557 + } 554 558 555 559 /* Don't waste time looping if the object is coherent */ 556 560 if (nvbo->force_coherent) ··· 587 583 588 584 if (!ttm_dma) 589 585 return; 586 + if (!ttm_dma->pages) { 587 + NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma); 588 + return; 589 + } 590 590 591 591 /* Don't waste time looping if the object is coherent */ 592 592 if (nvbo->force_coherent)

+4 -3

drivers/gpu/drm/omapdrm/dss/dsi.c

··· 2149 2149 const struct mipi_dsi_msg *msg) 2150 2150 { 2151 2151 struct mipi_dsi_packet pkt; 2152 + int ret; 2152 2153 u32 r; 2153 2154 2154 - r = mipi_dsi_create_packet(&pkt, msg); 2155 - if (r < 0) 2156 - return r; 2155 + ret = mipi_dsi_create_packet(&pkt, msg); 2156 + if (ret < 0) 2157 + return ret; 2157 2158 2158 2159 WARN_ON(!dsi_bus_is_locked(dsi)); 2159 2160

+4 -2

include/drm/ttm/ttm_bo_api.h

··· 612 612 static inline void ttm_bo_unpin(struct ttm_buffer_object *bo) 613 613 { 614 614 dma_resv_assert_held(bo->base.resv); 615 - WARN_ON_ONCE(!bo->pin_count); 616 615 WARN_ON_ONCE(!kref_read(&bo->kref)); 617 - --bo->pin_count; 616 + if (bo->pin_count) 617 + --bo->pin_count; 618 + else 619 + WARN_ON_ONCE(true); 618 620 } 619 621 620 622 int ttm_mem_evict_first(struct ttm_bo_device *bdev,

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