Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

phy: tegra: xusb: Support sleepwalk for Tegra234

Add new registers programming in sleepwalk sequence for Tegra234:
MASTER_ENABLE_A/B/C/D in XUSB_AO_UTMIP_SLEEPWALK.

Signed-off-by: Henry Lin <henryl@nvidia.com>
Signed-off-by: Haotien Hsu <haotienh@nvidia.com>
Link: https://lore.kernel.org/r/20230309061708.4156383-1-haotienh@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Henry Lin and committed by
Vinod Koul
8b798761 5e4d267f

+21
+20
drivers/phy/tegra/xusb-tegra186.c
··· 145 145 #define MODE_HS MODE(0) 146 146 #define MODE_RST MODE(1) 147 147 148 + #define XUSB_AO_UTMIP_SLEEPWALK_STATUS(x) (0xa0 + (x) * 4) 149 + 148 150 #define XUSB_AO_UTMIP_SLEEPWALK_CFG(x) (0xd0 + (x) * 4) 149 151 #define XUSB_AO_UHSIC_SLEEPWALK_CFG(x) (0xf0 + (x) * 4) 150 152 #define FAKE_USBOP_VAL BIT(0) ··· 174 172 #define AP_A BIT(4) 175 173 #define AN_A BIT(5) 176 174 #define HIGHZ_A BIT(6) 175 + #define MASTER_ENABLE_A BIT(7) 177 176 /* phase B */ 178 177 #define USBOP_RPD_B BIT(8) 179 178 #define USBON_RPD_B BIT(9) 180 179 #define AP_B BIT(12) 181 180 #define AN_B BIT(13) 182 181 #define HIGHZ_B BIT(14) 182 + #define MASTER_ENABLE_B BIT(15) 183 183 /* phase C */ 184 184 #define USBOP_RPD_C BIT(16) 185 185 #define USBON_RPD_C BIT(17) 186 186 #define AP_C BIT(20) 187 187 #define AN_C BIT(21) 188 188 #define HIGHZ_C BIT(22) 189 + #define MASTER_ENABLE_C BIT(23) 189 190 /* phase D */ 190 191 #define USBOP_RPD_D BIT(24) 191 192 #define USBON_RPD_D BIT(25) 192 193 #define AP_D BIT(28) 193 194 #define AN_D BIT(29) 194 195 #define HIGHZ_D BIT(30) 196 + #define MASTER_ENABLE_D BIT(31) 197 + #define MASTER_ENABLE_B_C_D \ 198 + (MASTER_ENABLE_B | MASTER_ENABLE_C | MASTER_ENABLE_D) 195 199 196 200 #define XUSB_AO_UHSIC_SLEEPWALK(x) (0x120 + (x) * 4) 197 201 /* phase A */ ··· 425 417 value |= HIGHZ_A; 426 418 value |= AP_A; 427 419 value |= AN_B | AN_C | AN_D; 420 + if (padctl->soc->supports_lp_cfg_en) 421 + value |= MASTER_ENABLE_B_C_D; 428 422 break; 429 423 430 424 case USB_SPEED_LOW: ··· 434 424 value |= HIGHZ_A; 435 425 value |= AN_A; 436 426 value |= AP_B | AP_C | AP_D; 427 + if (padctl->soc->supports_lp_cfg_en) 428 + value |= MASTER_ENABLE_B_C_D; 437 429 break; 438 430 439 431 default: ··· 499 487 value &= ~WAKE_VAL(~0); 500 488 value |= WAKE_VAL_NONE; 501 489 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 490 + 491 + if (padctl->soc->supports_lp_cfg_en) { 492 + /* disable the four stages of sleepwalk */ 493 + value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK(index)); 494 + value &= ~(MASTER_ENABLE_A | MASTER_ENABLE_B_C_D); 495 + ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index)); 496 + } 502 497 503 498 /* power down the line state detectors of the port */ 504 499 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index)); ··· 1692 1673 .supports_gen2 = true, 1693 1674 .poll_trk_completed = true, 1694 1675 .trk_hw_mode = true, 1676 + .supports_lp_cfg_en = true, 1695 1677 }; 1696 1678 EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc); 1697 1679 #endif
+1
drivers/phy/tegra/xusb.h
··· 434 434 bool need_fake_usb3_port; 435 435 bool poll_trk_completed; 436 436 bool trk_hw_mode; 437 + bool supports_lp_cfg_en; 437 438 }; 438 439 439 440 struct tegra_xusb_padctl {