tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"Nothing too crazy or exciting:

- two MAINTAINERS entries that I didn't see the point in delaying.
- one drm mst fix to stop sending uninitialised data to monitors
- two amdgpu fixes
- one radeon mst tiling fix
- one vmwgfx regression fix
- one virtio warning fix.

I have found one locking problem that needs a bit of reorg to fix, but
I'm not sure it's worth putting in -fixes as I don't think we've seen
it hit in the real world ever, I just found it using the virtio-gpu
driver when working on it. I'll possibly send it next week once I've
time to discuss with Daniel"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/virtio: use %llu format string form atomic64_t
MAINTAINERS: Add myself as maintainer for the gma500 driver
MAINTAINERS: add a maintainer for the atmel-hlcdc DRM driver
drm/amdgpu: Keep the pflip interrupts always enabled v7
drm/amdgpu: adjust default dispclk (v2)
drm/dp/mst: make mst i2c transfer code more robust.
drm/radeon: attach tile property to mst connector
drm/vmwgfx: Fix kernel NULL pointer dereference on older hardware

Linus Torvalds 8b7b56f3 ebb65c81

+115 -16
+15
MAINTAINERS
··· 3591 3591 F: include/drm/i915* 3592 3592 F: include/uapi/drm/i915* 3593 3593 3594 + DRM DRIVERS FOR ATMEL HLCDC 3595 + M: Boris Brezillon <boris.brezillon@free-electrons.com> 3596 + L: dri-devel@lists.freedesktop.org 3597 + S: Supported 3598 + F: drivers/gpu/drm/atmel-hlcdc/ 3599 + F: Documentation/devicetree/bindings/drm/atmel/ 3600 + 3594 3601 DRM DRIVERS FOR EXYNOS 3595 3602 M: Inki Dae <inki.dae@samsung.com> 3596 3603 M: Joonyoung Shim <jy0922.shim@samsung.com> ··· 3625 3618 S: Maintained 3626 3619 F: drivers/gpu/drm/imx/ 3627 3620 F: Documentation/devicetree/bindings/drm/imx/ 3621 + 3622 + DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets) 3623 + M: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> 3624 + L: dri-devel@lists.freedesktop.org 3625 + T: git git://github.com/patjak/drm-gma500 3626 + S: Maintained 3627 + F: drivers/gpu/drm/gma500 3628 + F: include/drm/gma500* 3628 3629 3629 3630 DRM DRIVERS FOR NVIDIA TEGRA 3630 3631 M: Thierry Reding <thierry.reding@gmail.com>
+6 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
··· 672 672 /* disp clock */ 673 673 adev->clock.default_dispclk = 674 674 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 675 - if (adev->clock.default_dispclk == 0) 676 - adev->clock.default_dispclk = 54000; /* 540 Mhz */ 675 + /* set a reasonable default for DP */ 676 + if (adev->clock.default_dispclk < 53900) { 677 + DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 678 + adev->clock.default_dispclk / 100); 679 + adev->clock.default_dispclk = 60000; 680 + } 677 681 adev->clock.dp_extclk = 678 682 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 679 683 adev->clock.current_dispclk = adev->clock.default_dispclk;
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
··· 85 85 /* We borrow the event spin lock for protecting flip_status */ 86 86 spin_lock_irqsave(&crtc->dev->event_lock, flags); 87 87 88 - /* set the proper interrupt */ 89 - amdgpu_irq_get(adev, &adev->pageflip_irq, work->crtc_id); 90 88 /* do the flip (mmio) */ 91 89 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base); 92 90 /* set the flip status */
+28 -2
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
··· 255 255 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 256 256 } 257 257 258 + static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev) 259 + { 260 + unsigned i; 261 + 262 + /* Enable pflip interrupts */ 263 + for (i = 0; i < adev->mode_info.num_crtc; i++) 264 + amdgpu_irq_get(adev, &adev->pageflip_irq, i); 265 + } 266 + 267 + static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 268 + { 269 + unsigned i; 270 + 271 + /* Disable pflip interrupts */ 272 + for (i = 0; i < adev->mode_info.num_crtc; i++) 273 + amdgpu_irq_put(adev, &adev->pageflip_irq, i); 274 + } 275 + 258 276 /** 259 277 * dce_v10_0_page_flip - pageflip callback. 260 278 * ··· 2681 2663 dce_v10_0_vga_enable(crtc, true); 2682 2664 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2683 2665 dce_v10_0_vga_enable(crtc, false); 2684 - /* Make sure VBLANK interrupt is still enabled */ 2666 + /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2685 2667 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2686 2668 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2669 + amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2687 2670 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); 2688 2671 dce_v10_0_crtc_load_lut(crtc); 2689 2672 break; ··· 3044 3025 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3045 3026 } 3046 3027 3028 + dce_v10_0_pageflip_interrupt_init(adev); 3029 + 3047 3030 return 0; 3048 3031 } 3049 3032 ··· 3060 3039 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3061 3040 } 3062 3041 3042 + dce_v10_0_pageflip_interrupt_fini(adev); 3043 + 3063 3044 return 0; 3064 3045 } 3065 3046 ··· 3072 3049 amdgpu_atombios_scratch_regs_save(adev); 3073 3050 3074 3051 dce_v10_0_hpd_fini(adev); 3052 + 3053 + dce_v10_0_pageflip_interrupt_fini(adev); 3075 3054 3076 3055 return 0; 3077 3056 } ··· 3099 3074 3100 3075 /* initialize hpd */ 3101 3076 dce_v10_0_hpd_init(adev); 3077 + 3078 + dce_v10_0_pageflip_interrupt_init(adev); 3102 3079 3103 3080 return 0; 3104 3081 } ··· 3396 3369 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3397 3370 3398 3371 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); 3399 - amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id); 3400 3372 queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); 3401 3373 3402 3374 return 0;
+28 -2
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
··· 233 233 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 234 234 } 235 235 236 + static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) 237 + { 238 + unsigned i; 239 + 240 + /* Enable pflip interrupts */ 241 + for (i = 0; i < adev->mode_info.num_crtc; i++) 242 + amdgpu_irq_get(adev, &adev->pageflip_irq, i); 243 + } 244 + 245 + static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 246 + { 247 + unsigned i; 248 + 249 + /* Disable pflip interrupts */ 250 + for (i = 0; i < adev->mode_info.num_crtc; i++) 251 + amdgpu_irq_put(adev, &adev->pageflip_irq, i); 252 + } 253 + 236 254 /** 237 255 * dce_v11_0_page_flip - pageflip callback. 238 256 * ··· 2658 2640 dce_v11_0_vga_enable(crtc, true); 2659 2641 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2660 2642 dce_v11_0_vga_enable(crtc, false); 2661 - /* Make sure VBLANK interrupt is still enabled */ 2643 + /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2662 2644 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2663 2645 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2646 + amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2664 2647 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); 2665 2648 dce_v11_0_crtc_load_lut(crtc); 2666 2649 break; ··· 3019 3000 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3020 3001 } 3021 3002 3003 + dce_v11_0_pageflip_interrupt_init(adev); 3004 + 3022 3005 return 0; 3023 3006 } 3024 3007 ··· 3035 3014 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3036 3015 } 3037 3016 3017 + dce_v11_0_pageflip_interrupt_fini(adev); 3018 + 3038 3019 return 0; 3039 3020 } 3040 3021 ··· 3047 3024 amdgpu_atombios_scratch_regs_save(adev); 3048 3025 3049 3026 dce_v11_0_hpd_fini(adev); 3027 + 3028 + dce_v11_0_pageflip_interrupt_fini(adev); 3050 3029 3051 3030 return 0; 3052 3031 } ··· 3075 3050 3076 3051 /* initialize hpd */ 3077 3052 dce_v11_0_hpd_init(adev); 3053 + 3054 + dce_v11_0_pageflip_interrupt_init(adev); 3078 3055 3079 3056 return 0; 3080 3057 } ··· 3372 3345 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3373 3346 3374 3347 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); 3375 - amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id); 3376 3348 queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); 3377 3349 3378 3350 return 0;
+28 -2
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
··· 204 204 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 205 205 } 206 206 207 + static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev) 208 + { 209 + unsigned i; 210 + 211 + /* Enable pflip interrupts */ 212 + for (i = 0; i < adev->mode_info.num_crtc; i++) 213 + amdgpu_irq_get(adev, &adev->pageflip_irq, i); 214 + } 215 + 216 + static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 217 + { 218 + unsigned i; 219 + 220 + /* Disable pflip interrupts */ 221 + for (i = 0; i < adev->mode_info.num_crtc; i++) 222 + amdgpu_irq_put(adev, &adev->pageflip_irq, i); 223 + } 224 + 207 225 /** 208 226 * dce_v8_0_page_flip - pageflip callback. 209 227 * ··· 2593 2575 dce_v8_0_vga_enable(crtc, true); 2594 2576 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2595 2577 dce_v8_0_vga_enable(crtc, false); 2596 - /* Make sure VBLANK interrupt is still enabled */ 2578 + /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2597 2579 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2598 2580 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2581 + amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2599 2582 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); 2600 2583 dce_v8_0_crtc_load_lut(crtc); 2601 2584 break; ··· 2952 2933 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2953 2934 } 2954 2935 2936 + dce_v8_0_pageflip_interrupt_init(adev); 2937 + 2955 2938 return 0; 2956 2939 } 2957 2940 ··· 2968 2947 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2969 2948 } 2970 2949 2950 + dce_v8_0_pageflip_interrupt_fini(adev); 2951 + 2971 2952 return 0; 2972 2953 } 2973 2954 ··· 2980 2957 amdgpu_atombios_scratch_regs_save(adev); 2981 2958 2982 2959 dce_v8_0_hpd_fini(adev); 2960 + 2961 + dce_v8_0_pageflip_interrupt_fini(adev); 2983 2962 2984 2963 return 0; 2985 2964 } ··· 3005 2980 3006 2981 /* initialize hpd */ 3007 2982 dce_v8_0_hpd_init(adev); 2983 + 2984 + dce_v8_0_pageflip_interrupt_init(adev); 3008 2985 3009 2986 return 0; 3010 2987 } ··· 3403 3376 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3404 3377 3405 3378 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); 3406 - amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id); 3407 3379 queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); 3408 3380 3409 3381 return 0;
+2 -1
drivers/gpu/drm/drm_dp_mst_topology.c
··· 2801 2801 if (msgs[num - 1].flags & I2C_M_RD) 2802 2802 reading = true; 2803 2803 2804 - if (!reading) { 2804 + if (!reading || (num - 1 > DP_REMOTE_I2C_READ_MAX_TRANSACTIONS)) { 2805 2805 DRM_DEBUG_KMS("Unsupported I2C transaction for MST device\n"); 2806 2806 ret = -EIO; 2807 2807 goto out; 2808 2808 } 2809 2809 2810 + memset(&msg, 0, sizeof(msg)); 2810 2811 msg.req_type = DP_REMOTE_I2C_READ; 2811 2812 msg.u.i2c_read.num_transactions = num - 1; 2812 2813 msg.u.i2c_read.port_number = port->port_num;
+1
drivers/gpu/drm/radeon/radeon_dp_mst.c
··· 283 283 radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master); 284 284 285 285 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); 286 + drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); 286 287 drm_mode_connector_set_path_property(connector, pathprop); 287 288 288 289 return connector;
+2 -2
drivers/gpu/drm/virtio/virtgpu_debugfs.c
··· 34 34 struct drm_info_node *node = (struct drm_info_node *) m->private; 35 35 struct virtio_gpu_device *vgdev = node->minor->dev->dev_private; 36 36 37 - seq_printf(m, "fence %ld %lld\n", 38 - atomic64_read(&vgdev->fence_drv.last_seq), 37 + seq_printf(m, "fence %llu %lld\n", 38 + (u64)atomic64_read(&vgdev->fence_drv.last_seq), 39 39 vgdev->fence_drv.sync_seq); 40 40 return 0; 41 41 }
+1 -1
drivers/gpu/drm/virtio/virtgpu_fence.c
··· 61 61 { 62 62 struct virtio_gpu_fence *fence = to_virtio_fence(f); 63 63 64 - snprintf(str, size, "%lu", atomic64_read(&fence->drv->last_seq)); 64 + snprintf(str, size, "%llu", (u64)atomic64_read(&fence->drv->last_seq)); 65 65 } 66 66 67 67 static const struct fence_ops virtio_fence_ops = {
+2 -1
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
··· 657 657 struct vmw_resource *res = &user_srf->srf.res; 658 658 659 659 *p_base = NULL; 660 - ttm_base_object_unref(&user_srf->backup_base); 660 + if (user_srf->backup_base) 661 + ttm_base_object_unref(&user_srf->backup_base); 661 662 vmw_resource_unreference(&res); 662 663 } 663 664
+2 -1
include/drm/drm_dp_mst_helper.h
··· 253 253 u8 *bytes; 254 254 }; 255 255 256 + #define DP_REMOTE_I2C_READ_MAX_TRANSACTIONS 4 256 257 struct drm_dp_remote_i2c_read { 257 258 u8 num_transactions; 258 259 u8 port_number; ··· 263 262 u8 *bytes; 264 263 u8 no_stop_bit; 265 264 u8 i2c_transaction_delay; 266 - } transactions[4]; 265 + } transactions[DP_REMOTE_I2C_READ_MAX_TRANSACTIONS]; 267 266 u8 read_i2c_device_id; 268 267 u8 num_bytes_read; 269 268 };