Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2021-08-20-3' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Regularly scheduled fixes. The ttm one solves a problem of GPU drivers
failing to load if debugfs is off in Kconfig, otherwise the i915 and
mediatek, and amdgpu fixes all fairly normal.
Nouveau has a couple of display fixes, but it has a fix for a
longstanding race condition in it's memory manager code, and the fix
mostly removes some code that wasn't working properly and has no
userspace users. This fix makes the diffstat kinda larger but in a
good (negative line-count) way.
core:
- fix drm_wait_vblank uapi copying bug
ttm:
- fix debugfs init when debugfs is off
amdgpu:
- vega10 SMU workload fix
- DCN VM fix
- DCN 3.01 watermark fix
amdkfd:
- SVM fix
nouveau:
- ampere display fixes
- remove MM misfeature to fix a longstanding race condition
i915:
- tweaked display workaround for all PCHs
- eDP MSO pipe sanity for ADL-P fix
- remove unused symbol export
mediatek:
- AAL output size setting
- Delete component in remove function"
* tag 'drm-fixes-2021-08-20-3' of git://anongit.freedesktop.org/drm/drm:
drm/amd/display: Use DCN30 watermark calc for DCN301
drm/i915/dp: remove superfluous EXPORT_SYMBOL()
drm/i915/edp: fix eDP MSO pipe sanity checks for ADL-P
drm/i915: Tweaked Wa_14010685332 for all PCHs
drm/nouveau: rip out nvkm_client.super
drm/nouveau: block a bunch of classes from userspace
drm/nouveau/fifo/nv50-: rip out dma channels
drm/nouveau/kms/nv50: workaround EFI GOP window channel format differences
drm/nouveau/disp: power down unused DP links during init
drm/nouveau: recognise GA107
drm: Copy drm_wait_vblank to user before returning
drm/amd/display: Ensure DCN save after VM setup
drm/amdkfd: fix random KFDSVMRangeTest.SetGetAttributesTest test failure
drm/amd/pm: change the workload type for some cards
Revert "drm/amd/pm: fix workload mismatch on vega10"
drm: ttm: Don't bail from ttm_global_init if debugfs_create_dir fails
drm/mediatek: Add component_del in OVL and COLOR remove function
drm/mediatek: Add AAL output size configuration
+224
-477
+8
drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+8
drivers/gpu/drm/amd/amdkfd/kfd_svm.c
···
3026
3026
pr_debug("svms 0x%p [0x%llx 0x%llx] nattr 0x%x\n", &p->svms, start,
3027
3027
start + size - 1, nattr);
3028
3028
3029
+
/* Flush pending deferred work to avoid racing with deferred actions from
3030
+
* previous memory map changes (e.g. munmap). Concurrent memory map changes
3031
+
* can still race with get_attr because we don't hold the mmap lock. But that
3032
+
* would be a race condition in the application anyway, and undefined
3033
+
* behaviour is acceptable in that case.
3034
+
*/
3035
+
flush_work(&p->svms.deferred_list_work);
3036
+
3029
3037
mmap_read_lock(mm);
3030
3038
if (!svm_range_is_valid(mm, start, size)) {
3031
3039
pr_debug("invalid range\n");
+6
drivers/gpu/drm/amd/display/dc/core/dc.c
+6
drivers/gpu/drm/amd/display/dc/core/dc.c
···
1530
1530
if (dc->hwss.z10_restore)
1531
1531
dc->hwss.z10_restore(dc);
1532
1532
}
1533
+
1534
+
void dc_z10_save_init(struct dc *dc)
1535
+
{
1536
+
if (dc->hwss.z10_save_init)
1537
+
dc->hwss.z10_save_init(dc);
1538
+
}
1533
1539
#endif
1534
1540
/*
1535
1541
* Applies given context to HW and copy it into current context.
+3
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
+3
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
+1
drivers/gpu/drm/amd/display/dc/dc.h
+1
drivers/gpu/drm/amd/display/dc/dc.h
+1
-95
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+1
-95
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
···
1622
1622
dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
1623
1623
}
1624
1624
1625
-
static void calculate_wm_set_for_vlevel(
1626
-
int vlevel,
1627
-
struct wm_range_table_entry *table_entry,
1628
-
struct dcn_watermarks *wm_set,
1629
-
struct display_mode_lib *dml,
1630
-
display_e2e_pipe_params_st *pipes,
1631
-
int pipe_cnt)
1632
-
{
1633
-
double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1634
-
1635
-
ASSERT(vlevel < dml->soc.num_states);
1636
-
/* only pipe 0 is read for voltage and dcf/soc clocks */
1637
-
pipes[0].clks_cfg.voltage = vlevel;
1638
-
pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1639
-
pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1640
-
1641
-
dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1642
-
dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1643
-
dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
1644
-
1645
-
wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1646
-
wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1647
-
wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1648
-
wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1649
-
wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1650
-
wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1651
-
wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1652
-
wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1653
-
dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1654
-
1655
-
}
1656
-
1657
-
static void dcn301_calculate_wm_and_dlg(
1658
-
struct dc *dc, struct dc_state *context,
1659
-
display_e2e_pipe_params_st *pipes,
1660
-
int pipe_cnt,
1661
-
int vlevel_req)
1662
-
{
1663
-
int i, pipe_idx;
1664
-
int vlevel, vlevel_max;
1665
-
struct wm_range_table_entry *table_entry;
1666
-
struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1667
-
1668
-
ASSERT(bw_params);
1669
-
1670
-
vlevel_max = bw_params->clk_table.num_entries - 1;
1671
-
1672
-
/* WM Set D */
1673
-
table_entry = &bw_params->wm_table.entries[WM_D];
1674
-
if (table_entry->wm_type == WM_TYPE_RETRAINING)
1675
-
vlevel = 0;
1676
-
else
1677
-
vlevel = vlevel_max;
1678
-
calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1679
-
&context->bw_ctx.dml, pipes, pipe_cnt);
1680
-
/* WM Set C */
1681
-
table_entry = &bw_params->wm_table.entries[WM_C];
1682
-
vlevel = min(max(vlevel_req, 2), vlevel_max);
1683
-
calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1684
-
&context->bw_ctx.dml, pipes, pipe_cnt);
1685
-
/* WM Set B */
1686
-
table_entry = &bw_params->wm_table.entries[WM_B];
1687
-
vlevel = min(max(vlevel_req, 1), vlevel_max);
1688
-
calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1689
-
&context->bw_ctx.dml, pipes, pipe_cnt);
1690
-
1691
-
/* WM Set A */
1692
-
table_entry = &bw_params->wm_table.entries[WM_A];
1693
-
vlevel = min(vlevel_req, vlevel_max);
1694
-
calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1695
-
&context->bw_ctx.dml, pipes, pipe_cnt);
1696
-
1697
-
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1698
-
if (!context->res_ctx.pipe_ctx[i].stream)
1699
-
continue;
1700
-
1701
-
pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
1702
-
pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1703
-
1704
-
if (dc->config.forced_clocks) {
1705
-
pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1706
-
pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1707
-
}
1708
-
if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
1709
-
pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1710
-
if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1711
-
pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1712
-
1713
-
pipe_idx++;
1714
-
}
1715
-
1716
-
dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1717
-
}
1718
-
1719
1625
static struct resource_funcs dcn301_res_pool_funcs = {
1720
1626
.destroy = dcn301_destroy_resource_pool,
1721
1627
.link_enc_create = dcn301_link_encoder_create,
1722
1628
.panel_cntl_create = dcn301_panel_cntl_create,
1723
1629
.validate_bandwidth = dcn30_validate_bandwidth,
1724
-
.calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg,
1630
+
.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1725
1631
.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1726
1632
.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1727
1633
.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+12
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+12
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
···
404
404
&pipe_ctx->stream_res.encoder_info_frame);
405
405
}
406
406
}
407
+
void dcn31_z10_save_init(struct dc *dc)
408
+
{
409
+
union dmub_rb_cmd cmd;
410
+
411
+
memset(&cmd, 0, sizeof(cmd));
412
+
cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
413
+
cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT;
414
+
415
+
dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
416
+
dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
417
+
dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
418
+
}
407
419
408
420
void dcn31_z10_restore(struct dc *dc)
409
421
{
+1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
+1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
···
44
44
void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx);
45
45
46
46
void dcn31_z10_restore(struct dc *dc);
47
+
void dcn31_z10_save_init(struct dc *dc);
47
48
48
49
void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
49
50
int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);
+1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
+1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
···
97
97
.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
98
98
.set_pipe = dcn21_set_pipe,
99
99
.z10_restore = dcn31_z10_restore,
100
+
.z10_save_init = dcn31_z10_save_init,
100
101
.is_abm_supported = dcn31_is_abm_supported,
101
102
.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
102
103
.update_visual_confirm_color = dcn20_update_visual_confirm_color,
+1
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+1
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+5
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+5
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+14
-1
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+14
-1
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
···
5127
5127
return size;
5128
5128
}
5129
5129
5130
+
static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr)
5131
+
{
5132
+
struct amdgpu_device *adev = hwmgr->adev;
5133
+
5134
+
return (adev->pdev->device == 0x6860);
5135
+
}
5136
+
5130
5137
static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
5131
5138
{
5132
5139
struct vega10_hwmgr *data = hwmgr->backend;
···
5170
5163
}
5171
5164
5172
5165
out:
5173
-
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5166
+
if (vega10_get_power_profile_mode_quirks(hwmgr))
5167
+
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5168
+
1 << power_profile_mode,
5169
+
NULL);
5170
+
else
5171
+
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5174
5172
(!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1),
5175
5173
NULL);
5174
+
5176
5175
hwmgr->power_profile_mode = power_profile_mode;
5177
5176
5178
5177
return 0;
+1
-3
drivers/gpu/drm/drm_ioc32.c
+1
-3
drivers/gpu/drm/drm_ioc32.c
···
855
855
req.request.sequence = req32.request.sequence;
856
856
req.request.signal = req32.request.signal;
857
857
err = drm_ioctl_kernel(file, drm_wait_vblank_ioctl, &req, DRM_UNLOCKED);
858
-
if (err)
859
-
return err;
860
858
861
859
req32.reply.type = req.reply.type;
862
860
req32.reply.sequence = req.reply.sequence;
···
863
865
if (copy_to_user(argp, &req32, sizeof(req32)))
864
866
return -EFAULT;
865
867
866
-
return 0;
868
+
return err;
867
869
}
868
870
869
871
#if defined(CONFIG_X86)
+12
-12
drivers/gpu/drm/i915/display/intel_ddi.c
+12
-12
drivers/gpu/drm/i915/display/intel_ddi.c
···
2463
2463
}
2464
2464
}
2465
2465
2466
+
/* Splitter enable for eDP MSO is limited to certain pipes. */
2467
+
static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2468
+
{
2469
+
if (IS_ALDERLAKE_P(i915))
2470
+
return BIT(PIPE_A) | BIT(PIPE_B);
2471
+
else
2472
+
return BIT(PIPE_A);
2473
+
}
2474
+
2466
2475
static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2467
2476
struct intel_crtc_state *pipe_config)
2468
2477
{
···
2489
2480
if (!pipe_config->splitter.enable)
2490
2481
return;
2491
2482
2492
-
/* Splitter enable is supported for pipe A only. */
2493
-
if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) {
2483
+
if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2494
2484
pipe_config->splitter.enable = false;
2495
2485
return;
2496
2486
}
···
2521
2513
return;
2522
2514
2523
2515
if (crtc_state->splitter.enable) {
2524
-
/* Splitter enable is supported for pipe A only. */
2525
-
if (drm_WARN_ON(&i915->drm, pipe != PIPE_A))
2526
-
return;
2527
-
2528
2516
dss1 |= SPLITTER_ENABLE;
2529
2517
dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2530
2518
if (crtc_state->splitter.link_count == 2)
···
4747
4743
4748
4744
dig_port->hpd_pulse = intel_dp_hpd_pulse;
4749
4745
4750
-
/* Splitter enable for eDP MSO is limited to certain pipes. */
4751
-
if (dig_port->dp.mso_link_count) {
4752
-
encoder->pipe_mask = BIT(PIPE_A);
4753
-
if (IS_ALDERLAKE_P(dev_priv))
4754
-
encoder->pipe_mask |= BIT(PIPE_B);
4755
-
}
4746
+
if (dig_port->dp.mso_link_count)
4747
+
encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
4756
4748
}
4757
4749
4758
4750
/* In theory we don't need the encoder->type check, but leave it just in
+8
-8
drivers/gpu/drm/i915/display/intel_display_power.c
+8
-8
drivers/gpu/drm/i915/display/intel_display_power.c
···
6387
6387
if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
6388
6388
IS_BROXTON(i915)) {
6389
6389
bxt_enable_dc9(i915);
6390
-
/* Tweaked Wa_14010685332:icp,jsp,mcc */
6391
-
if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)
6392
-
intel_de_rmw(i915, SOUTH_CHICKEN1,
6393
-
SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
6394
6390
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
6395
6391
hsw_enable_pc8(i915);
6396
6392
}
6393
+
6394
+
/* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
6395
+
if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
6396
+
intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
6397
6397
}
6398
6398
6399
6399
void intel_display_power_resume_early(struct drm_i915_private *i915)
···
6402
6402
IS_BROXTON(i915)) {
6403
6403
gen9_sanitize_dc_state(i915);
6404
6404
bxt_disable_dc9(i915);
6405
-
/* Tweaked Wa_14010685332:icp,jsp,mcc */
6406
-
if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)
6407
-
intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
6408
-
6409
6405
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
6410
6406
hsw_disable_pc8(i915);
6411
6407
}
6408
+
6409
+
/* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */
6410
+
if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
6411
+
intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
6412
6412
}
6413
6413
6414
6414
void intel_display_power_suspend(struct drm_i915_private *i915)
-1
drivers/gpu/drm/i915/display/intel_dp_link_training.c
-1
drivers/gpu/drm/i915/display/intel_dp_link_training.c
-21
drivers/gpu/drm/i915/i915_irq.c
-21
drivers/gpu/drm/i915/i915_irq.c
···
3064
3064
spin_unlock_irq(&dev_priv->irq_lock);
3065
3065
}
3066
3066
3067
-
static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
3068
-
{
3069
-
struct intel_uncore *uncore = &dev_priv->uncore;
3070
-
3071
-
/*
3072
-
* Wa_14010685332:cnp/cmp,tgp,adp
3073
-
* TODO: Clarify which platforms this applies to
3074
-
* TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
3075
-
* on earlier platforms and whether the workaround is also needed for runtime suspend/resume
3076
-
*/
3077
-
if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
3078
-
(INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
3079
-
intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
3080
-
SBCLK_RUN_REFCLK_DIS);
3081
-
intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
3082
-
}
3083
-
}
3084
-
3085
3067
static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
3086
3068
{
3087
3069
struct intel_uncore *uncore = &dev_priv->uncore;
···
3097
3115
if (HAS_PCH_SPLIT(dev_priv))
3098
3116
ibx_irq_reset(dev_priv);
3099
3117
3100
-
cnp_display_clock_wa(dev_priv);
3101
3118
}
3102
3119
3103
3120
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
···
3140
3159
3141
3160
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3142
3161
GEN3_IRQ_RESET(uncore, SDE);
3143
-
3144
-
cnp_display_clock_wa(dev_priv);
3145
3162
}
3146
3163
3147
3164
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
+2
drivers/gpu/drm/mediatek/mtk_disp_color.c
+2
drivers/gpu/drm/mediatek/mtk_disp_color.c
+2
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+2
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+2
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+2
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
···
34
34
35
35
#define DISP_AAL_EN 0x0000
36
36
#define DISP_AAL_SIZE 0x0030
37
+
#define DISP_AAL_OUTPUT_SIZE 0x04d8
37
38
38
39
#define DISP_DITHER_EN 0x0000
39
40
#define DITHER_EN BIT(0)
···
198
197
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
199
198
200
199
mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
200
+
mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_OUTPUT_SIZE);
201
201
}
202
202
203
203
static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
+27
drivers/gpu/drm/nouveau/dispnv50/disp.c
+27
drivers/gpu/drm/nouveau/dispnv50/disp.c
···
2237
2237
interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2238
2238
}
2239
2239
2240
+
/* Finish updating head(s)...
2241
+
*
2242
+
* NVD is rather picky about both where window assignments can change,
2243
+
* *and* about certain core and window channel states matching.
2244
+
*
2245
+
* The EFI GOP driver on newer GPUs configures window channels with a
2246
+
* different output format to what we do, and the core channel update
2247
+
* in the assign_windows case above would result in a state mismatch.
2248
+
*
2249
+
* Delay some of the head update until after that point to workaround
2250
+
* the issue. This only affects the initial modeset.
2251
+
*
2252
+
* TODO: handle this better when adding flexible window mapping
2253
+
*/
2254
+
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2255
+
struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2256
+
struct nv50_head *head = nv50_head(crtc);
2257
+
2258
+
NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2259
+
asyh->set.mask, asyh->clr.mask);
2260
+
2261
+
if (asyh->set.mask) {
2262
+
nv50_head_flush_set_wndw(head, asyh);
2263
+
interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2264
+
}
2265
+
}
2266
+
2240
2267
/* Update plane(s). */
2241
2268
for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2242
2269
struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
+9
-4
drivers/gpu/drm/nouveau/dispnv50/head.c
+9
-4
drivers/gpu/drm/nouveau/dispnv50/head.c
···
50
50
}
51
51
52
52
void
53
-
nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
53
+
nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh)
54
54
{
55
-
if (asyh->set.view ) head->func->view (head, asyh);
56
-
if (asyh->set.mode ) head->func->mode (head, asyh);
57
-
if (asyh->set.core ) head->func->core_set(head, asyh);
58
55
if (asyh->set.olut ) {
59
56
asyh->olut.offset = nv50_lut_load(&head->olut,
60
57
asyh->olut.buffer,
···
59
62
asyh->olut.load);
60
63
head->func->olut_set(head, asyh);
61
64
}
65
+
}
66
+
67
+
void
68
+
nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
69
+
{
70
+
if (asyh->set.view ) head->func->view (head, asyh);
71
+
if (asyh->set.mode ) head->func->mode (head, asyh);
72
+
if (asyh->set.core ) head->func->core_set(head, asyh);
62
73
if (asyh->set.curs ) head->func->curs_set(head, asyh);
63
74
if (asyh->set.base ) head->func->base (head, asyh);
64
75
if (asyh->set.ovly ) head->func->ovly (head, asyh);
+1
drivers/gpu/drm/nouveau/dispnv50/head.h
+1
drivers/gpu/drm/nouveau/dispnv50/head.h
···
21
21
22
22
struct nv50_head *nv50_head_create(struct drm_device *, int index);
23
23
void nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh);
24
+
void nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh);
24
25
void nv50_head_flush_clr(struct nv50_head *head,
25
26
struct nv50_head_atom *asyh, bool flush);
26
27
+2
-1
drivers/gpu/drm/nouveau/include/nvif/cl0080.h
+2
-1
drivers/gpu/drm/nouveau/include/nvif/cl0080.h
-2
drivers/gpu/drm/nouveau/include/nvif/class.h
-2
drivers/gpu/drm/nouveau/include/nvif/class.h
···
61
61
#define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e
62
62
#define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e
63
63
#define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e
64
-
#define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e
65
-
#define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e
66
64
67
65
#define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f
68
66
#define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f
-1
drivers/gpu/drm/nouveau/include/nvif/client.h
-1
drivers/gpu/drm/nouveau/include/nvif/client.h
+1
-1
drivers/gpu/drm/nouveau/include/nvif/driver.h
+1
-1
drivers/gpu/drm/nouveau/include/nvif/driver.h
···
11
11
void (*fini)(void *priv);
12
12
int (*suspend)(void *priv);
13
13
int (*resume)(void *priv);
14
-
int (*ioctl)(void *priv, bool super, void *data, u32 size, void **hack);
14
+
int (*ioctl)(void *priv, void *data, u32 size, void **hack);
15
15
void __iomem *(*map)(void *priv, u64 handle, u32 size);
16
16
void (*unmap)(void *priv, void __iomem *ptr, u32 size);
17
17
bool keep;
-1
drivers/gpu/drm/nouveau/include/nvkm/core/client.h
-1
drivers/gpu/drm/nouveau/include/nvkm/core/client.h
+1
-1
drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h
+1
-1
drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h
-1
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
-1
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
···
15
15
u8 refd:3; /* Current page type (index, or NONE for unreferenced). */
16
16
bool used:1; /* Region allocated. */
17
17
bool part:1; /* Region was split from an allocated region by map(). */
18
-
bool user:1; /* Region user-allocated. */
19
18
bool busy:1; /* Region busy (for temporarily preventing user access). */
20
19
bool mapped:1; /* Region contains valid pages. */
21
20
struct nvkm_memory *memory; /* Memory currently mapped into VMA. */
-2
drivers/gpu/drm/nouveau/nouveau_abi16.c
-2
drivers/gpu/drm/nouveau/nouveau_abi16.c
···
570
570
}
571
571
572
572
client->route = NVDRM_OBJECT_ABI16;
573
-
client->super = true;
574
573
ret = nvif_object_ctor(&chan->chan->user, "abi16Ntfy", info->handle,
575
574
NV_DMA_IN_MEMORY, &args, sizeof(args),
576
575
&ntfy->object);
577
-
client->super = false;
578
576
client->route = NVDRM_OBJECT_NVIF;
579
577
if (ret)
580
578
goto done;
+2
-17
drivers/gpu/drm/nouveau/nouveau_chan.c
+2
-17
drivers/gpu/drm/nouveau/nouveau_chan.c
···
86
86
struct nouveau_channel *chan = *pchan;
87
87
if (chan) {
88
88
struct nouveau_cli *cli = (void *)chan->user.client;
89
-
bool super;
90
-
91
-
if (cli) {
92
-
super = cli->base.super;
93
-
cli->base.super = true;
94
-
}
95
89
96
90
if (chan->fence)
97
91
nouveau_fence(chan->drm)->context_del(chan);
···
105
111
nouveau_bo_unpin(chan->push.buffer);
106
112
nouveau_bo_ref(NULL, &chan->push.buffer);
107
113
kfree(chan);
108
-
109
-
if (cli)
110
-
cli->base.super = super;
111
114
}
112
115
*pchan = NULL;
113
116
}
···
503
512
struct nouveau_channel **pchan)
504
513
{
505
514
struct nouveau_cli *cli = (void *)device->object.client;
506
-
bool super;
507
515
int ret;
508
516
509
517
/* hack until fencenv50 is fixed, and agp access relaxed */
510
-
super = cli->base.super;
511
-
cli->base.super = true;
512
-
513
518
ret = nouveau_channel_ind(drm, device, arg0, priv, pchan);
514
519
if (ret) {
515
520
NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
516
521
ret = nouveau_channel_dma(drm, device, pchan);
517
522
if (ret) {
518
523
NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
519
-
goto done;
524
+
return ret;
520
525
}
521
526
}
522
527
···
520
533
if (ret) {
521
534
NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
522
535
nouveau_channel_del(pchan);
523
-
goto done;
536
+
return ret;
524
537
}
525
538
526
539
ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst);
527
540
if (ret)
528
541
nouveau_channel_del(pchan);
529
542
530
-
done:
531
-
cli->base.super = super;
532
543
return ret;
533
544
}
534
545
+1
-2
drivers/gpu/drm/nouveau/nouveau_drm.c
+1
-2
drivers/gpu/drm/nouveau/nouveau_drm.c
···
244
244
ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE,
245
245
&(struct nv_device_v0) {
246
246
.device = ~0,
247
+
.priv = true,
247
248
}, sizeof(struct nv_device_v0),
248
249
&cli->device);
249
250
if (ret) {
···
1086
1085
ret = nouveau_cli_init(drm, name, cli);
1087
1086
if (ret)
1088
1087
goto done;
1089
-
1090
-
cli->base.super = false;
1091
1088
1092
1089
fpriv->driver_priv = cli;
1093
1090
+1
-14
drivers/gpu/drm/nouveau/nouveau_mem.c
+1
-14
drivers/gpu/drm/nouveau/nouveau_mem.c
···
41
41
struct gf100_vmm_map_v0 gf100;
42
42
} args;
43
43
u32 argc = 0;
44
-
bool super;
45
-
int ret;
46
44
47
45
switch (vmm->object.oclass) {
48
46
case NVIF_CLASS_VMM_NV04:
···
71
73
return -ENOSYS;
72
74
}
73
75
74
-
super = vmm->object.client->super;
75
-
vmm->object.client->super = true;
76
-
ret = nvif_vmm_map(vmm, vma->addr, mem->mem.size, &args, argc,
77
-
&mem->mem, 0);
78
-
vmm->object.client->super = super;
79
-
return ret;
76
+
return nvif_vmm_map(vmm, vma->addr, mem->mem.size, &args, argc, &mem->mem, 0);
80
77
}
81
78
82
79
void
···
92
99
struct nouveau_drm *drm = cli->drm;
93
100
struct nvif_mmu *mmu = &cli->mmu;
94
101
struct nvif_mem_ram_v0 args = {};
95
-
bool super = cli->base.super;
96
102
u8 type;
97
103
int ret;
98
104
···
114
122
args.dma = tt->dma_address;
115
123
116
124
mutex_lock(&drm->master.lock);
117
-
cli->base.super = true;
118
125
ret = nvif_mem_ctor_type(mmu, "ttmHostMem", cli->mem->oclass, type, PAGE_SHIFT,
119
126
reg->num_pages << PAGE_SHIFT,
120
127
&args, sizeof(args), &mem->mem);
121
-
cli->base.super = super;
122
128
mutex_unlock(&drm->master.lock);
123
129
return ret;
124
130
}
···
128
138
struct nouveau_cli *cli = mem->cli;
129
139
struct nouveau_drm *drm = cli->drm;
130
140
struct nvif_mmu *mmu = &cli->mmu;
131
-
bool super = cli->base.super;
132
141
u64 size = ALIGN(reg->num_pages << PAGE_SHIFT, 1 << page);
133
142
int ret;
134
143
135
144
mutex_lock(&drm->master.lock);
136
-
cli->base.super = true;
137
145
switch (cli->mem->oclass) {
138
146
case NVIF_CLASS_MEM_GF100:
139
147
ret = nvif_mem_ctor_type(mmu, "ttmVram", cli->mem->oclass,
···
155
167
WARN_ON(1);
156
168
break;
157
169
}
158
-
cli->base.super = super;
159
170
mutex_unlock(&drm->master.lock);
160
171
161
172
reg->start = mem->mem.addr >> PAGE_SHIFT;
+2
-2
drivers/gpu/drm/nouveau/nouveau_nvif.c
+2
-2
drivers/gpu/drm/nouveau/nouveau_nvif.c
···
52
52
}
53
53
54
54
static int
55
-
nvkm_client_ioctl(void *priv, bool super, void *data, u32 size, void **hack)
55
+
nvkm_client_ioctl(void *priv, void *data, u32 size, void **hack)
56
56
{
57
-
return nvkm_ioctl(priv, super, data, size, hack);
57
+
return nvkm_ioctl(priv, data, size, hack);
58
58
}
59
59
60
60
static int
-9
drivers/gpu/drm/nouveau/nouveau_svm.c
-9
drivers/gpu/drm/nouveau/nouveau_svm.c
···
237
237
nouveau_svmm_invalidate(struct nouveau_svmm *svmm, u64 start, u64 limit)
238
238
{
239
239
if (limit > start) {
240
-
bool super = svmm->vmm->vmm.object.client->super;
241
-
svmm->vmm->vmm.object.client->super = true;
242
240
nvif_object_mthd(&svmm->vmm->vmm.object, NVIF_VMM_V0_PFNCLR,
243
241
&(struct nvif_vmm_pfnclr_v0) {
244
242
.addr = start,
245
243
.size = limit - start,
246
244
}, sizeof(struct nvif_vmm_pfnclr_v0));
247
-
svmm->vmm->vmm.object.client->super = super;
248
245
}
249
246
}
250
247
···
631
634
NVIF_VMM_PFNMAP_V0_A |
632
635
NVIF_VMM_PFNMAP_V0_HOST;
633
636
634
-
svmm->vmm->vmm.object.client->super = true;
635
637
ret = nvif_object_ioctl(&svmm->vmm->vmm.object, args, size, NULL);
636
-
svmm->vmm->vmm.object.client->super = false;
637
638
mutex_unlock(&svmm->mutex);
638
639
639
640
unlock_page(page);
···
697
702
698
703
nouveau_hmm_convert_pfn(drm, &range, args);
699
704
700
-
svmm->vmm->vmm.object.client->super = true;
701
705
ret = nvif_object_ioctl(&svmm->vmm->vmm.object, args, size, NULL);
702
-
svmm->vmm->vmm.object.client->super = false;
703
706
mutex_unlock(&svmm->mutex);
704
707
705
708
out:
···
921
928
922
929
mutex_lock(&svmm->mutex);
923
930
924
-
svmm->vmm->vmm.object.client->super = true;
925
931
ret = nvif_object_ioctl(&svmm->vmm->vmm.object, args, sizeof(*args) +
926
932
npages * sizeof(args->p.phys[0]), NULL);
927
-
svmm->vmm->vmm.object.client->super = false;
928
933
929
934
mutex_unlock(&svmm->mutex);
930
935
}
+44
-13
drivers/gpu/drm/nouveau/nouveau_usif.c
+44
-13
drivers/gpu/drm/nouveau/nouveau_usif.c
···
32
32
#include <nvif/event.h>
33
33
#include <nvif/ioctl.h>
34
34
35
+
#include <nvif/class.h>
36
+
#include <nvif/cl0080.h>
37
+
35
38
struct usif_notify_p {
36
39
struct drm_pending_event base;
37
40
struct {
···
264
261
}
265
262
266
263
static int
267
-
usif_object_new(struct drm_file *f, void *data, u32 size, void *argv, u32 argc)
264
+
usif_object_new(struct drm_file *f, void *data, u32 size, void *argv, u32 argc, bool parent_abi16)
268
265
{
269
266
struct nouveau_cli *cli = nouveau_cli(f);
270
267
struct nvif_client *client = &cli->base;
···
274
271
struct usif_object *object;
275
272
int ret = -ENOSYS;
276
273
274
+
if ((ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true)))
275
+
return ret;
276
+
277
+
switch (args->v0.oclass) {
278
+
case NV_DMA_FROM_MEMORY:
279
+
case NV_DMA_TO_MEMORY:
280
+
case NV_DMA_IN_MEMORY:
281
+
return -EINVAL;
282
+
case NV_DEVICE: {
283
+
union {
284
+
struct nv_device_v0 v0;
285
+
} *args = data;
286
+
287
+
if ((ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false)))
288
+
return ret;
289
+
290
+
args->v0.priv = false;
291
+
break;
292
+
}
293
+
default:
294
+
if (!parent_abi16)
295
+
return -EINVAL;
296
+
break;
297
+
}
298
+
277
299
if (!(object = kmalloc(sizeof(*object), GFP_KERNEL)))
278
300
return -ENOMEM;
279
301
list_add(&object->head, &cli->objects);
280
302
281
-
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
282
-
object->route = args->v0.route;
283
-
object->token = args->v0.token;
284
-
args->v0.route = NVDRM_OBJECT_USIF;
285
-
args->v0.token = (unsigned long)(void *)object;
286
-
ret = nvif_client_ioctl(client, argv, argc);
287
-
args->v0.token = object->token;
288
-
args->v0.route = object->route;
303
+
object->route = args->v0.route;
304
+
object->token = args->v0.token;
305
+
args->v0.route = NVDRM_OBJECT_USIF;
306
+
args->v0.token = (unsigned long)(void *)object;
307
+
ret = nvif_client_ioctl(client, argv, argc);
308
+
if (ret) {
309
+
usif_object_dtor(object);
310
+
return ret;
289
311
}
290
312
291
-
if (ret)
292
-
usif_object_dtor(object);
293
-
return ret;
313
+
args->v0.token = object->token;
314
+
args->v0.route = object->route;
315
+
return 0;
294
316
}
295
317
296
318
int
···
329
301
struct nvif_ioctl_v0 v0;
330
302
} *argv = data;
331
303
struct usif_object *object;
304
+
bool abi16 = false;
332
305
u8 owner;
333
306
int ret;
334
307
···
360
331
mutex_unlock(&cli->mutex);
361
332
goto done;
362
333
}
334
+
335
+
abi16 = true;
363
336
}
364
337
365
338
switch (argv->v0.type) {
366
339
case NVIF_IOCTL_V0_NEW:
367
-
ret = usif_object_new(filp, data, size, argv, argc);
340
+
ret = usif_object_new(filp, data, size, argv, argc, abi16);
368
341
break;
369
342
case NVIF_IOCTL_V0_NTFY_NEW:
370
343
ret = usif_notify_new(filp, data, size, argv, argc);
+1
-2
drivers/gpu/drm/nouveau/nvif/client.c
+1
-2
drivers/gpu/drm/nouveau/nvif/client.c
···
32
32
int
33
33
nvif_client_ioctl(struct nvif_client *client, void *data, u32 size)
34
34
{
35
-
return client->driver->ioctl(client->object.priv, client->super, data, size, NULL);
35
+
return client->driver->ioctl(client->object.priv, data, size, NULL);
36
36
}
37
37
38
38
int
···
80
80
client->object.client = client;
81
81
client->object.handle = ~0;
82
82
client->route = NVIF_IOCTL_V0_ROUTE_NVIF;
83
-
client->super = true;
84
83
client->driver = parent->driver;
85
84
86
85
if (ret == 0) {
+1
-2
drivers/gpu/drm/nouveau/nvif/object.c
+1
-2
drivers/gpu/drm/nouveau/nvif/object.c
+1
-3
drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
+1
-3
drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
···
426
426
}
427
427
428
428
int
429
-
nvkm_ioctl(struct nvkm_client *client, bool supervisor,
430
-
void *data, u32 size, void **hack)
429
+
nvkm_ioctl(struct nvkm_client *client, void *data, u32 size, void **hack)
431
430
{
432
431
struct nvkm_object *object = &client->object;
433
432
union {
···
434
435
} *args = data;
435
436
int ret = -ENOSYS;
436
437
437
-
client->super = supervisor;
438
438
nvif_ioctl(object, "size %d\n", size);
439
439
440
440
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) {
+21
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+21
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
···
2624
2624
.dma = { 0x00000001, gv100_dma_new },
2625
2625
};
2626
2626
2627
+
static const struct nvkm_device_chip
2628
+
nv177_chipset = {
2629
+
.name = "GA107",
2630
+
.bar = { 0x00000001, tu102_bar_new },
2631
+
.bios = { 0x00000001, nvkm_bios_new },
2632
+
.devinit = { 0x00000001, ga100_devinit_new },
2633
+
.fb = { 0x00000001, ga102_fb_new },
2634
+
.gpio = { 0x00000001, ga102_gpio_new },
2635
+
.i2c = { 0x00000001, gm200_i2c_new },
2636
+
.imem = { 0x00000001, nv50_instmem_new },
2637
+
.mc = { 0x00000001, ga100_mc_new },
2638
+
.mmu = { 0x00000001, tu102_mmu_new },
2639
+
.pci = { 0x00000001, gp100_pci_new },
2640
+
.privring = { 0x00000001, gm200_privring_new },
2641
+
.timer = { 0x00000001, gk20a_timer_new },
2642
+
.top = { 0x00000001, ga100_top_new },
2643
+
.disp = { 0x00000001, ga102_disp_new },
2644
+
.dma = { 0x00000001, gv100_dma_new },
2645
+
};
2646
+
2627
2647
static int
2628
2648
nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size,
2629
2649
struct nvkm_notify *notify)
···
3069
3049
case 0x168: device->chip = &nv168_chipset; break;
3070
3050
case 0x172: device->chip = &nv172_chipset; break;
3071
3051
case 0x174: device->chip = &nv174_chipset; break;
3052
+
case 0x177: device->chip = &nv177_chipset; break;
3072
3053
default:
3073
3054
if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) {
3074
3055
switch (device->chipset) {
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c
+1
drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h
+1
drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h
+9
drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c
+9
drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c
···
22
22
* Authors: Ben Skeggs
23
23
*/
24
24
#include "outp.h"
25
+
#include "dp.h"
25
26
#include "ior.h"
26
27
27
28
#include <subdev/bios.h>
···
258
257
if (!ior->arm.head || ior->arm.proto != proto) {
259
258
OUTP_DBG(outp, "no heads (%x %d %d)", ior->arm.head,
260
259
ior->arm.proto, proto);
260
+
261
+
/* The EFI GOP driver on Ampere can leave unused DP links routed,
262
+
* which we don't expect. The DisableLT IED script *should* get
263
+
* us back to where we need to be.
264
+
*/
265
+
if (ior->func->route.get && !ior->arm.head && outp->info.type == DCB_OUTPUT_DP)
266
+
nvkm_dp_disable(outp, ior);
267
+
261
268
return;
262
269
}
263
270
-15
drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c
-15
drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c
···
26
26
#include <core/client.h>
27
27
#include <core/gpuobj.h>
28
28
#include <subdev/fb.h>
29
-
#include <subdev/instmem.h>
30
29
31
30
#include <nvif/cl0002.h>
32
31
#include <nvif/unpack.h>
···
71
72
union {
72
73
struct nv_dma_v0 v0;
73
74
} *args = *pdata;
74
-
struct nvkm_device *device = dma->engine.subdev.device;
75
-
struct nvkm_client *client = oclass->client;
76
75
struct nvkm_object *parent = oclass->parent;
77
-
struct nvkm_instmem *instmem = device->imem;
78
-
struct nvkm_fb *fb = device->fb;
79
76
void *data = *pdata;
80
77
u32 size = *psize;
81
78
int ret = -ENOSYS;
···
104
109
dmaobj->target = NV_MEM_TARGET_VM;
105
110
break;
106
111
case NV_DMA_V0_TARGET_VRAM:
107
-
if (!client->super) {
108
-
if (dmaobj->limit >= fb->ram->size - instmem->reserved)
109
-
return -EACCES;
110
-
if (device->card_type >= NV_50)
111
-
return -EACCES;
112
-
}
113
112
dmaobj->target = NV_MEM_TARGET_VRAM;
114
113
break;
115
114
case NV_DMA_V0_TARGET_PCI:
116
-
if (!client->super)
117
-
return -EACCES;
118
115
dmaobj->target = NV_MEM_TARGET_PCI;
119
116
break;
120
117
case NV_DMA_V0_TARGET_PCI_US:
121
118
case NV_DMA_V0_TARGET_AGP:
122
-
if (!client->super)
123
-
return -EACCES;
124
119
dmaobj->target = NV_MEM_TARGET_PCI_NOSNOOP;
125
120
break;
126
121
default:
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
···
27
27
nvkm-y += nvkm/engine/fifo/dmanv10.o
28
28
nvkm-y += nvkm/engine/fifo/dmanv17.o
29
29
nvkm-y += nvkm/engine/fifo/dmanv40.o
30
-
nvkm-y += nvkm/engine/fifo/dmanv50.o
31
-
nvkm-y += nvkm/engine/fifo/dmag84.o
32
30
33
31
nvkm-y += nvkm/engine/fifo/gpfifonv50.o
34
32
nvkm-y += nvkm/engine/fifo/gpfifog84.o
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
···
48
48
int g84_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push,
49
49
const struct nvkm_oclass *, struct nv50_fifo_chan *);
50
50
51
-
extern const struct nvkm_fifo_chan_oclass nv50_fifo_dma_oclass;
52
51
extern const struct nvkm_fifo_chan_oclass nv50_fifo_gpfifo_oclass;
53
-
extern const struct nvkm_fifo_chan_oclass g84_fifo_dma_oclass;
54
52
extern const struct nvkm_fifo_chan_oclass g84_fifo_gpfifo_oclass;
55
53
#endif
-94
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c
-94
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c
···
1
-
/*
2
-
* Copyright 2012 Red Hat Inc.
3
-
*
4
-
* Permission is hereby granted, free of charge, to any person obtaining a
5
-
* copy of this software and associated documentation files (the "Software"),
6
-
* to deal in the Software without restriction, including without limitation
7
-
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
-
* and/or sell copies of the Software, and to permit persons to whom the
9
-
* Software is furnished to do so, subject to the following conditions:
10
-
*
11
-
* The above copyright notice and this permission notice shall be included in
12
-
* all copies or substantial portions of the Software.
13
-
*
14
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
-
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
-
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
-
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
-
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
-
* OTHER DEALINGS IN THE SOFTWARE.
21
-
*
22
-
* Authors: Ben Skeggs
23
-
*/
24
-
#include "channv50.h"
25
-
26
-
#include <core/client.h>
27
-
#include <core/ramht.h>
28
-
29
-
#include <nvif/class.h>
30
-
#include <nvif/cl826e.h>
31
-
#include <nvif/unpack.h>
32
-
33
-
static int
34
-
g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
35
-
void *data, u32 size, struct nvkm_object **pobject)
36
-
{
37
-
struct nvkm_object *parent = oclass->parent;
38
-
union {
39
-
struct g82_channel_dma_v0 v0;
40
-
} *args = data;
41
-
struct nv50_fifo *fifo = nv50_fifo(base);
42
-
struct nv50_fifo_chan *chan;
43
-
int ret = -ENOSYS;
44
-
45
-
nvif_ioctl(parent, "create channel dma size %d\n", size);
46
-
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
47
-
nvif_ioctl(parent, "create channel dma vers %d vmm %llx "
48
-
"pushbuf %llx offset %016llx\n",
49
-
args->v0.version, args->v0.vmm, args->v0.pushbuf,
50
-
args->v0.offset);
51
-
if (!args->v0.pushbuf)
52
-
return -EINVAL;
53
-
} else
54
-
return ret;
55
-
56
-
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
57
-
return -ENOMEM;
58
-
*pobject = &chan->base.object;
59
-
60
-
ret = g84_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
61
-
oclass, chan);
62
-
if (ret)
63
-
return ret;
64
-
65
-
args->v0.chid = chan->base.chid;
66
-
67
-
nvkm_kmap(chan->ramfc);
68
-
nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
69
-
nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
70
-
nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
71
-
nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
72
-
nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078);
73
-
nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
74
-
nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
75
-
nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff);
76
-
nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
77
-
nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
78
-
nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);
79
-
nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
80
-
(4 << 24) /* SEARCH_FULL */ |
81
-
(chan->ramht->gpuobj->node->offset >> 4));
82
-
nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10);
83
-
nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12);
84
-
nvkm_done(chan->ramfc);
85
-
return 0;
86
-
}
87
-
88
-
const struct nvkm_fifo_chan_oclass
89
-
g84_fifo_dma_oclass = {
90
-
.base.oclass = G82_CHANNEL_DMA,
91
-
.base.minver = 0,
92
-
.base.maxver = 0,
93
-
.ctor = g84_fifo_dma_new,
94
-
};
-92
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c
-92
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c
···
1
-
/*
2
-
* Copyright 2012 Red Hat Inc.
3
-
*
4
-
* Permission is hereby granted, free of charge, to any person obtaining a
5
-
* copy of this software and associated documentation files (the "Software"),
6
-
* to deal in the Software without restriction, including without limitation
7
-
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
-
* and/or sell copies of the Software, and to permit persons to whom the
9
-
* Software is furnished to do so, subject to the following conditions:
10
-
*
11
-
* The above copyright notice and this permission notice shall be included in
12
-
* all copies or substantial portions of the Software.
13
-
*
14
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
-
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
-
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
-
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
-
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
-
* OTHER DEALINGS IN THE SOFTWARE.
21
-
*
22
-
* Authors: Ben Skeggs
23
-
*/
24
-
#include "channv50.h"
25
-
26
-
#include <core/client.h>
27
-
#include <core/ramht.h>
28
-
29
-
#include <nvif/class.h>
30
-
#include <nvif/cl506e.h>
31
-
#include <nvif/unpack.h>
32
-
33
-
static int
34
-
nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
35
-
void *data, u32 size, struct nvkm_object **pobject)
36
-
{
37
-
struct nvkm_object *parent = oclass->parent;
38
-
union {
39
-
struct nv50_channel_dma_v0 v0;
40
-
} *args = data;
41
-
struct nv50_fifo *fifo = nv50_fifo(base);
42
-
struct nv50_fifo_chan *chan;
43
-
int ret = -ENOSYS;
44
-
45
-
nvif_ioctl(parent, "create channel dma size %d\n", size);
46
-
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
47
-
nvif_ioctl(parent, "create channel dma vers %d vmm %llx "
48
-
"pushbuf %llx offset %016llx\n",
49
-
args->v0.version, args->v0.vmm, args->v0.pushbuf,
50
-
args->v0.offset);
51
-
if (!args->v0.pushbuf)
52
-
return -EINVAL;
53
-
} else
54
-
return ret;
55
-
56
-
if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
57
-
return -ENOMEM;
58
-
*pobject = &chan->base.object;
59
-
60
-
ret = nv50_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
61
-
oclass, chan);
62
-
if (ret)
63
-
return ret;
64
-
65
-
args->v0.chid = chan->base.chid;
66
-
67
-
nvkm_kmap(chan->ramfc);
68
-
nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
69
-
nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
70
-
nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
71
-
nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
72
-
nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078);
73
-
nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
74
-
nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
75
-
nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff);
76
-
nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
77
-
nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
78
-
nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);
79
-
nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
80
-
(4 << 24) /* SEARCH_FULL */ |
81
-
(chan->ramht->gpuobj->node->offset >> 4));
82
-
nvkm_done(chan->ramfc);
83
-
return 0;
84
-
}
85
-
86
-
const struct nvkm_fifo_chan_oclass
87
-
nv50_fifo_dma_oclass = {
88
-
.base.oclass = NV50_CHANNEL_DMA,
89
-
.base.minver = 0,
90
-
.base.maxver = 0,
91
-
.ctor = nv50_fifo_dma_new,
92
-
};
-1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
-1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
···
341
341
"runlist %016llx priv %d\n",
342
342
args->v0.version, args->v0.vmm, args->v0.ioffset,
343
343
args->v0.ilength, args->v0.runlist, args->v0.priv);
344
-
if (args->v0.priv && !oclass->client->super)
345
-
return -EINVAL;
346
344
return gk104_fifo_gpfifo_new_(fifo,
347
345
&args->v0.runlist,
348
346
&args->v0.chid,
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c
···
226
226
"runlist %016llx priv %d\n",
227
227
args->v0.version, args->v0.vmm, args->v0.ioffset,
228
228
args->v0.ilength, args->v0.runlist, args->v0.priv);
229
-
if (args->v0.priv && !oclass->client->super)
230
-
return -EINVAL;
231
229
return gv100_fifo_gpfifo_new_(&gv100_fifo_gpfifo, fifo,
232
230
&args->v0.runlist,
233
231
&args->v0.chid,
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c
···
65
65
"runlist %016llx priv %d\n",
66
66
args->v0.version, args->v0.vmm, args->v0.ioffset,
67
67
args->v0.ilength, args->v0.runlist, args->v0.priv);
68
-
if (args->v0.priv && !oclass->client->super)
69
-
return -EINVAL;
70
68
return gv100_fifo_gpfifo_new_(&tu102_fifo_gpfifo, fifo,
71
69
&args->v0.runlist,
72
70
&args->v0.chid,
-1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
-1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
+2
-4
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c
+2
-4
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.c
···
41
41
42
42
object = nvkm_object_search(client, handle, &nvkm_umem);
43
43
if (IS_ERR(object)) {
44
-
if (client->super && client != master) {
44
+
if (client != master) {
45
45
spin_lock(&master->lock);
46
46
list_for_each_entry(umem, &master->umem, head) {
47
47
if (umem->object.object == handle) {
···
53
53
}
54
54
} else {
55
55
umem = nvkm_umem(object);
56
-
if (!umem->priv || client->super)
57
-
memory = nvkm_memory_ref(umem->memory);
56
+
memory = nvkm_memory_ref(umem->memory);
58
57
}
59
58
60
59
return memory ? memory : ERR_PTR(-ENOENT);
···
166
167
nvkm_object_ctor(&nvkm_umem, oclass, &umem->object);
167
168
umem->mmu = mmu;
168
169
umem->type = mmu->type[type].type;
169
-
umem->priv = oclass->client->super;
170
170
INIT_LIST_HEAD(&umem->head);
171
171
*pobject = &umem->object;
172
172
-1
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.h
-1
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.h
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.c
+6
-21
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c
+6
-21
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.c
···
45
45
static int
46
46
nvkm_uvmm_mthd_pfnclr(struct nvkm_uvmm *uvmm, void *argv, u32 argc)
47
47
{
48
-
struct nvkm_client *client = uvmm->object.client;
49
48
union {
50
49
struct nvif_vmm_pfnclr_v0 v0;
51
50
} *args = argv;
···
58
59
} else
59
60
return ret;
60
61
61
-
if (!client->super)
62
-
return -ENOENT;
63
-
64
62
if (size) {
65
63
mutex_lock(&vmm->mutex);
66
64
ret = nvkm_vmm_pfn_unmap(vmm, addr, size);
···
70
74
static int
71
75
nvkm_uvmm_mthd_pfnmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc)
72
76
{
73
-
struct nvkm_client *client = uvmm->object.client;
74
77
union {
75
78
struct nvif_vmm_pfnmap_v0 v0;
76
79
} *args = argv;
···
88
93
} else
89
94
return ret;
90
95
91
-
if (!client->super)
92
-
return -ENOENT;
93
-
94
96
if (size) {
95
97
mutex_lock(&vmm->mutex);
96
98
ret = nvkm_vmm_pfn_map(vmm, page, addr, size, phys);
···
100
108
static int
101
109
nvkm_uvmm_mthd_unmap(struct nvkm_uvmm *uvmm, void *argv, u32 argc)
102
110
{
103
-
struct nvkm_client *client = uvmm->object.client;
104
111
union {
105
112
struct nvif_vmm_unmap_v0 v0;
106
113
} *args = argv;
···
121
130
goto done;
122
131
}
123
132
124
-
if (ret = -ENOENT, (!vma->user && !client->super) || vma->busy) {
125
-
VMM_DEBUG(vmm, "denied %016llx: %d %d %d", addr,
126
-
vma->user, !client->super, vma->busy);
133
+
if (ret = -ENOENT, vma->busy) {
134
+
VMM_DEBUG(vmm, "denied %016llx: %d", addr, vma->busy);
127
135
goto done;
128
136
}
129
137
···
171
181
goto fail;
172
182
}
173
183
174
-
if (ret = -ENOENT, (!vma->user && !client->super) || vma->busy) {
175
-
VMM_DEBUG(vmm, "denied %016llx: %d %d %d", addr,
176
-
vma->user, !client->super, vma->busy);
184
+
if (ret = -ENOENT, vma->busy) {
185
+
VMM_DEBUG(vmm, "denied %016llx: %d", addr, vma->busy);
177
186
goto fail;
178
187
}
179
188
···
219
230
static int
220
231
nvkm_uvmm_mthd_put(struct nvkm_uvmm *uvmm, void *argv, u32 argc)
221
232
{
222
-
struct nvkm_client *client = uvmm->object.client;
223
233
union {
224
234
struct nvif_vmm_put_v0 v0;
225
235
} *args = argv;
···
240
252
goto done;
241
253
}
242
254
243
-
if (ret = -ENOENT, (!vma->user && !client->super) || vma->busy) {
244
-
VMM_DEBUG(vmm, "denied %016llx: %d %d %d", addr,
245
-
vma->user, !client->super, vma->busy);
255
+
if (ret = -ENOENT, vma->busy) {
256
+
VMM_DEBUG(vmm, "denied %016llx: %d", addr, vma->busy);
246
257
goto done;
247
258
}
248
259
···
255
268
static int
256
269
nvkm_uvmm_mthd_get(struct nvkm_uvmm *uvmm, void *argv, u32 argc)
257
270
{
258
-
struct nvkm_client *client = uvmm->object.client;
259
271
union {
260
272
struct nvif_vmm_get_v0 v0;
261
273
} *args = argv;
···
283
297
return ret;
284
298
285
299
args->v0.addr = vma->addr;
286
-
vma->user = !client->super;
287
300
return ret;
288
301
}
289
302
+1
-5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
+1
-5
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c
···
774
774
new->refd = vma->refd;
775
775
new->used = vma->used;
776
776
new->part = vma->part;
777
-
new->user = vma->user;
778
777
new->busy = vma->busy;
779
778
new->mapped = vma->mapped;
780
779
list_add(&new->head, &vma->head);
···
950
951
static void
951
952
nvkm_vma_dump(struct nvkm_vma *vma)
952
953
{
953
-
printk(KERN_ERR "%016llx %016llx %c%c%c%c%c%c%c%c%c %p\n",
954
+
printk(KERN_ERR "%016llx %016llx %c%c%c%c%c%c%c%c %p\n",
954
955
vma->addr, (u64)vma->size,
955
956
vma->used ? '-' : 'F',
956
957
vma->mapref ? 'R' : '-',
···
958
959
vma->page != NVKM_VMA_PAGE_NONE ? '0' + vma->page : '-',
959
960
vma->refd != NVKM_VMA_PAGE_NONE ? '0' + vma->refd : '-',
960
961
vma->part ? 'P' : '-',
961
-
vma->user ? 'U' : '-',
962
962
vma->busy ? 'B' : '-',
963
963
vma->mapped ? 'M' : '-',
964
964
vma->memory);
···
1022
1024
vma->mapref = true;
1023
1025
vma->sparse = false;
1024
1026
vma->used = true;
1025
-
vma->user = true;
1026
1027
nvkm_vmm_node_insert(vmm, vma);
1027
1028
list_add_tail(&vma->head, &vmm->list);
1028
1029
return 0;
···
1612
1615
vma->page = NVKM_VMA_PAGE_NONE;
1613
1616
vma->refd = NVKM_VMA_PAGE_NONE;
1614
1617
vma->used = false;
1615
-
vma->user = false;
1616
1618
nvkm_vmm_put_region(vmm, vma);
1617
1619
}
1618
1620
+7
-9
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
+7
-9
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c
···
534
534
gp100_vmm_mthd(struct nvkm_vmm *vmm,
535
535
struct nvkm_client *client, u32 mthd, void *argv, u32 argc)
536
536
{
537
-
if (client->super) {
538
-
switch (mthd) {
539
-
case GP100_VMM_VN_FAULT_REPLAY:
540
-
return gp100_vmm_fault_replay(vmm, argv, argc);
541
-
case GP100_VMM_VN_FAULT_CANCEL:
542
-
return gp100_vmm_fault_cancel(vmm, argv, argc);
543
-
default:
544
-
break;
545
-
}
537
+
switch (mthd) {
538
+
case GP100_VMM_VN_FAULT_REPLAY:
539
+
return gp100_vmm_fault_replay(vmm, argv, argc);
540
+
case GP100_VMM_VN_FAULT_CANCEL:
541
+
return gp100_vmm_fault_cancel(vmm, argv, argc);
542
+
default:
543
+
break;
546
544
}
547
545
return -EINVAL;
548
546
}
-2
drivers/gpu/drm/ttm/ttm_device.c
-2
drivers/gpu/drm/ttm/ttm_device.c