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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge tag 'spi-fix-v7.1-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"There's two main series here, fixing issues that came up in the
Microchip QSPI and Freescale i.MX drivers. Both of those could result
in some quite noticable issues if they were encountered in production.
We also have one minor documentation fix in the ch341 driver"
* tag 'spi-fix-v7.1-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: ch341: correct company name in MODULE_DESCRIPTION
spi: microchip-core-qspi: remove some inline markings
spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations
spi: microchip-core-qspi: control built-in cs manually
spi: imx: Propagate prepare_transfer() error from spi_imx_setupxfer()
spi: imx: Fix UAF on package-1 prepare failure in spi_imx_dma_data_prepare()
spi: imx: Fix precedence bug in spi_imx_dma_max_wml_find()
+83
-25
+1
-1
drivers/spi/spi-ch341.c
+1
-1
drivers/spi/spi-ch341.c
+3
-4
drivers/spi/spi-imx.c
+3
-4
drivers/spi/spi-imx.c
···
1382
1382
spi_imx->target_burst = t->len;
1383
1383
}
1384
1384
1385
-
spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t);
1386
-
1387
-
return 0;
1385
+
return spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t);
1388
1386
}
1389
1387
1390
1388
static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
···
1707
1709
kfree(spi_imx->dma_data[0].dma_tx_buf);
1708
1710
kfree(spi_imx->dma_data[0].dma_rx_buf);
1709
1711
kfree(spi_imx->dma_data);
1712
+
return ret;
1710
1713
}
1711
1714
}
1712
1715
···
1835
1836
unsigned int i;
1836
1837
1837
1838
for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1838
-
if (!dma_data->dma_len % (i * bytes_per_word))
1839
+
if (!(dma_data->dma_len % (i * bytes_per_word)))
1839
1840
break;
1840
1841
}
1841
1842
/* Use 1 as wml in case no available burst length got */
+79
-20
drivers/spi/spi-microchip-core-qspi.c
+79
-20
drivers/spi/spi-microchip-core-qspi.c
···
74
74
#define STATUS_FLAGSX4 BIT(8)
75
75
#define STATUS_MASK GENMASK(8, 0)
76
76
77
+
/*
78
+
* QSPI Direct Access register defines
79
+
*/
80
+
#define DIRECT_ACCESS_EN_SSEL BIT(0)
81
+
#define DIRECT_ACCESS_OP_SSEL BIT(1)
82
+
#define DIRECT_ACCESS_OP_SSEL_SHIFT 1
83
+
77
84
#define BYTESUPPER_MASK GENMASK(31, 16)
78
85
#define BYTESLOWER_MASK GENMASK(15, 0)
79
86
···
165
158
return 0;
166
159
}
167
160
168
-
static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi)
161
+
static void mchp_coreqspi_set_cs(struct spi_device *spi, bool enable)
162
+
{
163
+
struct mchp_coreqspi *qspi = spi_controller_get_devdata(spi->controller);
164
+
u32 val;
165
+
166
+
val = readl(qspi->regs + REG_DIRECT_ACCESS);
167
+
168
+
val &= ~DIRECT_ACCESS_OP_SSEL;
169
+
val |= !enable << DIRECT_ACCESS_OP_SSEL_SHIFT;
170
+
171
+
writel(val, qspi->regs + REG_DIRECT_ACCESS);
172
+
}
173
+
174
+
static int mchp_coreqspi_setup(struct spi_device *spi)
175
+
{
176
+
struct mchp_coreqspi *qspi = spi_controller_get_devdata(spi->controller);
177
+
u32 val;
178
+
179
+
/*
180
+
* Active low devices need to be specifically set to their inactive
181
+
* states during probe.
182
+
*/
183
+
if (spi->mode & SPI_CS_HIGH)
184
+
return 0;
185
+
186
+
val = readl(qspi->regs + REG_DIRECT_ACCESS);
187
+
val |= DIRECT_ACCESS_OP_SSEL;
188
+
writel(val, qspi->regs + REG_DIRECT_ACCESS);
189
+
190
+
return 0;
191
+
}
192
+
193
+
static void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi)
169
194
{
170
195
u32 control, data;
171
196
···
233
194
}
234
195
}
235
196
236
-
static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi)
197
+
static void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi)
237
198
{
238
199
u32 control, data;
239
200
···
261
222
}
262
223
}
263
224
264
-
static inline void mchp_coreqspi_write_read_op(struct mchp_coreqspi *qspi)
225
+
static void mchp_coreqspi_write_read_op(struct mchp_coreqspi *qspi)
265
226
{
266
227
u32 control, data;
267
228
···
419
380
return 0;
420
381
}
421
382
422
-
static int mchp_coreqspi_setup_op(struct spi_device *spi_dev)
423
-
{
424
-
struct spi_controller *ctlr = spi_dev->controller;
425
-
struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
426
-
u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
427
-
428
-
control |= (CONTROL_MASTER | CONTROL_ENABLE);
429
-
control &= ~CONTROL_CLKIDLE;
430
-
writel_relaxed(control, qspi->regs + REG_CONTROL);
431
-
432
-
return 0;
433
-
}
434
-
435
-
static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, const struct spi_mem_op *op)
383
+
static void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, const struct spi_mem_op *op)
436
384
{
437
385
u32 idle_cycles = 0;
438
386
int total_bytes, cmd_bytes, frames, ctrl;
···
509
483
510
484
reinit_completion(&qspi->data_completion);
511
485
mchp_coreqspi_config_op(qspi, op);
486
+
mchp_coreqspi_set_cs(mem->spi, true);
512
487
if (op->cmd.opcode) {
513
488
qspi->txbuf = &opcode;
514
489
qspi->rxbuf = NULL;
···
550
523
err = -ETIMEDOUT;
551
524
552
525
error:
526
+
mchp_coreqspi_set_cs(mem->spi, false);
553
527
mutex_unlock(&qspi->op_lock);
554
528
mchp_coreqspi_disable_ints(qspi);
555
529
···
690
662
struct spi_transfer *t)
691
663
{
692
664
struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
665
+
bool dual_quad = false;
693
666
694
667
qspi->tx_len = t->len;
668
+
669
+
if (t->tx_nbits == SPI_NBITS_QUAD || t->rx_nbits == SPI_NBITS_QUAD ||
670
+
t->tx_nbits == SPI_NBITS_DUAL ||
671
+
t->rx_nbits == SPI_NBITS_DUAL)
672
+
dual_quad = true;
695
673
696
674
if (t->tx_buf)
697
675
qspi->txbuf = (u8 *)t->tx_buf;
698
676
699
677
if (!t->rx_buf) {
700
678
mchp_coreqspi_write_op(qspi);
701
-
} else {
679
+
} else if (!dual_quad) {
702
680
qspi->rxbuf = (u8 *)t->rx_buf;
703
681
qspi->rx_len = t->len;
704
682
mchp_coreqspi_write_read_op(qspi);
683
+
} else {
684
+
qspi->rxbuf = (u8 *)t->rx_buf;
685
+
qspi->rx_len = t->len;
686
+
mchp_coreqspi_read_op(qspi);
705
687
}
706
688
707
689
return 0;
···
724
686
struct device *dev = &pdev->dev;
725
687
struct device_node *np = dev->of_node;
726
688
int ret;
689
+
u32 num_cs, val;
727
690
728
691
ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*qspi));
729
692
if (!ctlr)
···
757
718
return ret;
758
719
}
759
720
721
+
/*
722
+
* The IP core only has a single CS, any more have to be provided via
723
+
* gpios
724
+
*/
725
+
if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs))
726
+
num_cs = 1;
727
+
728
+
ctlr->num_chipselect = num_cs;
729
+
760
730
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
761
731
ctlr->mem_ops = &mchp_coreqspi_mem_ops;
762
732
ctlr->mem_caps = &mchp_coreqspi_mem_caps;
763
-
ctlr->setup = mchp_coreqspi_setup_op;
764
733
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
765
734
SPI_TX_DUAL | SPI_TX_QUAD;
766
735
ctlr->dev.of_node = np;
···
776
729
ctlr->prepare_message = mchp_coreqspi_prepare_message;
777
730
ctlr->unprepare_message = mchp_coreqspi_unprepare_message;
778
731
ctlr->transfer_one = mchp_coreqspi_transfer_one;
779
-
ctlr->num_chipselect = 2;
732
+
ctlr->setup = mchp_coreqspi_setup;
733
+
ctlr->set_cs = mchp_coreqspi_set_cs;
780
734
ctlr->use_gpio_descriptors = true;
735
+
736
+
val = readl_relaxed(qspi->regs + REG_CONTROL);
737
+
val |= (CONTROL_MASTER | CONTROL_ENABLE);
738
+
writel_relaxed(val, qspi->regs + REG_CONTROL);
739
+
740
+
/*
741
+
* Put cs into software controlled mode
742
+
*/
743
+
val = readl_relaxed(qspi->regs + REG_DIRECT_ACCESS);
744
+
val |= DIRECT_ACCESS_EN_SSEL;
745
+
writel(val, qspi->regs + REG_DIRECT_ACCESS);
781
746
782
747
ret = spi_register_controller(ctlr);
783
748
if (ret)