tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle:
"Another round of MIPS fixes for 4.2.

Things are looking quite decent at this stage but the recent work on
the FPU support took its toll:

- fix an incorrect overly restrictive ifdef

- select O32 64-bit FP support for O32 binary compatibility

- remove workarounds for Sibyte SB1250 Pass1 parts. There are rare
fixing the workarounds is not worth the effort.

- patch up an outdated and now incorrect comment"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: fpu.h: Allow 64-bit FPU on a 64-bit MIPS R6 CPU
MIPS: SB1: Remove support for Pass 1 parts.
MIPS: Require O32 FP64 support for MIPS64 with O32 compat
MIPS: asm-offset.c: Patch up various comments refering to the old filename.

Linus Torvalds 8bff8399 ff72bf7a

+7 -38
+1 -5
arch/mips/Kconfig
··· 1427 1427 select CPU_SUPPORTS_HIGHMEM 1428 1428 select CPU_SUPPORTS_MSA 1429 1429 select GENERIC_CSUM 1430 + select MIPS_O32_FP64_SUPPORT if MIPS32_O32 1430 1431 help 1431 1432 Choose this option to build a kernel for release 6 or later of the 1432 1433 MIPS64 architecture. New MIPS processors, starting with the Warrior ··· 2262 2261 2263 2262 config MIPS_CPC 2264 2263 bool 2265 - 2266 - config SB1_PASS_1_WORKAROUNDS 2267 - bool 2268 - depends on CPU_SB1_PASS_1 2269 - default y 2270 2264 2271 2265 config SB1_PASS_2_WORKAROUNDS 2272 2266 bool
-7
arch/mips/Makefile
··· 181 181 cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) 182 182 cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) 183 183 184 - ifdef CONFIG_CPU_SB1 185 - ifdef CONFIG_SB1_PASS_1_WORKAROUNDS 186 - KBUILD_AFLAGS_MODULE += -msb1-pass1-workarounds 187 - KBUILD_CFLAGS_MODULE += -msb1-pass1-workarounds 188 - endif 189 - endif 190 - 191 184 # For smartmips configurations, there are hundreds of warnings due to ISA overrides 192 185 # in assembly and header files. smartmips is only supported for MIPS32r1 onwards 193 186 # and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or
+1 -1
arch/mips/include/asm/fpu.h
··· 74 74 goto fr_common; 75 75 76 76 case FPU_64BIT: 77 - #if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6) \ 77 + #if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \ 78 78 || defined(CONFIG_64BIT)) 79 79 /* we only have a 32-bit FPU */ 80 80 return SIGFPE;
+1 -2
arch/mips/include/asm/mach-sibyte/war.h
··· 13 13 #define R4600_V2_HIT_CACHEOP_WAR 0 14 14 #define R5432_CP0_INTERRUPT_WAR 0 15 15 16 - #if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ 17 - defined(CONFIG_SB1_PASS_2_WORKAROUNDS) 16 + #if defined(CONFIG_SB1_PASS_2_WORKAROUNDS) 18 17 19 18 #ifndef __ASSEMBLY__ 20 19 extern int sb1250_m3_workaround_needed(void);
+2 -2
arch/mips/include/uapi/asm/sigcontext.h
··· 16 16 17 17 /* 18 18 * Keep this struct definition in sync with the sigcontext fragment 19 - * in arch/mips/tools/offset.c 19 + * in arch/mips/kernel/asm-offsets.c 20 20 */ 21 21 struct sigcontext { 22 22 unsigned int sc_regmask; /* Unused */ ··· 46 46 #include <linux/posix_types.h> 47 47 /* 48 48 * Keep this struct definition in sync with the sigcontext fragment 49 - * in arch/mips/tools/offset.c 49 + * in arch/mips/kernel/asm-offsets.c 50 50 * 51 51 * Warning: this structure illdefined with sc_badvaddr being just an unsigned 52 52 * int so it was changed to unsigned long in 2.6.0-test1. This may break
+1 -1
arch/mips/kernel/asm-offsets.c
··· 1 1 /* 2 - * offset.c: Calculate pt_regs and task_struct offsets. 2 + * asm-offsets.c: Calculate pt_regs and task_struct offsets. 3 3 * 4 4 * Copyright (C) 1996 David S. Miller 5 5 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
-5
arch/mips/sibyte/Kconfig
··· 81 81 prompt "SiByte SOC Stepping" 82 82 depends on SIBYTE_SB1xxx_SOC 83 83 84 - config CPU_SB1_PASS_1 85 - bool "1250 Pass1" 86 - depends on SIBYTE_SB1250 87 - select CPU_HAS_PREFETCH 88 - 89 84 config CPU_SB1_PASS_2_1250 90 85 bool "1250 An" 91 86 depends on SIBYTE_SB1250
+1 -4
arch/mips/sibyte/common/bus_watcher.c
··· 81 81 { 82 82 u32 status, l2_err, memio_err; 83 83 84 - #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS 85 - /* Destructive read, clears register and interrupt */ 86 - status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); 87 - #elif defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) 84 + #if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) 88 85 /* Use non-destructive register */ 89 86 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG)); 90 87 #elif defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
-2
arch/mips/sibyte/sb1250/setup.c
··· 202 202 203 203 switch (war_pass) { 204 204 case K_SYS_REVISION_BCM1250_PASS1: 205 - #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS 206 205 printk("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, " 207 206 "and the kernel doesn't have the proper " 208 207 "workarounds compiled in. @@@@\n"); 209 208 bad_config = 1; 210 - #endif 211 209 break; 212 210 case K_SYS_REVISION_BCM1250_PASS2: 213 211 /* Pass 2 - easiest as default for now - so many numbers */
-9
drivers/net/ethernet/broadcom/sb1250-mac.c
··· 1508 1508 __raw_writeq(reg, port); 1509 1509 port = s->sbm_base + R_MAC_ETHERNET_ADDR; 1510 1510 1511 - #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS 1512 - /* 1513 - * Pass1 SOCs do not receive packets addressed to the 1514 - * destination address in the R_MAC_ETHERNET_ADDR register. 1515 - * Set the value to zero. 1516 - */ 1517 - __raw_writeq(0, port); 1518 - #else 1519 1511 __raw_writeq(reg, port); 1520 - #endif 1521 1512 1522 1513 /* 1523 1514 * Set the receive filter for no packets, and write values