tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'iommu-fixes-v4.7-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

Pull IOMMU fixes from Joerg Roedel:
"Three patches queued up:

- Fix for ARM-SMMU to add a missing iommu-ops callback which is
required by common iommu code

- Fix for the rockchip iommu where the wrong MMUs got the commands

- A regression fix for the Intel VT-d driver. The regression only
showed up on X58 chipsets with more than one iommu. These chipsets
seem to require that QI is enabled on all IOMMUs before it can be
used"

* tag 'iommu-fixes-v4.7-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/vt-d: Enable QI on all IOMMUs before setting root entry
iommu/rockchip: Fix zap cache during device attach
iommu/arm-smmu: Wire up map_sg for arm-smmu-v3

Linus Torvalds 8c256155 7af9a170

+14 -6
+1
drivers/iommu/arm-smmu-v3.c
··· 1941 1941 .attach_dev = arm_smmu_attach_dev, 1942 1942 .map = arm_smmu_map, 1943 1943 .unmap = arm_smmu_unmap, 1944 + .map_sg = default_iommu_map_sg, 1944 1945 .iova_to_phys = arm_smmu_iova_to_phys, 1945 1946 .add_device = arm_smmu_add_device, 1946 1947 .remove_device = arm_smmu_remove_device,
+12 -5
drivers/iommu/intel-iommu.c
··· 3222 3222 } 3223 3223 } 3224 3224 3225 - iommu_flush_write_buffer(iommu); 3226 - iommu_set_root_entry(iommu); 3227 - iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); 3228 - iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); 3229 - 3230 3225 if (!ecap_pass_through(iommu->ecap)) 3231 3226 hw_pass_through = 0; 3232 3227 #ifdef CONFIG_INTEL_IOMMU_SVM 3233 3228 if (pasid_enabled(iommu)) 3234 3229 intel_svm_alloc_pasid_tables(iommu); 3235 3230 #endif 3231 + } 3232 + 3233 + /* 3234 + * Now that qi is enabled on all iommus, set the root entry and flush 3235 + * caches. This is required on some Intel X58 chipsets, otherwise the 3236 + * flush_context function will loop forever and the boot hangs. 3237 + */ 3238 + for_each_active_iommu(iommu, drhd) { 3239 + iommu_flush_write_buffer(iommu); 3240 + iommu_set_root_entry(iommu); 3241 + iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); 3242 + iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); 3236 3243 } 3237 3244 3238 3245 if (iommu_pass_through)
+1 -1
drivers/iommu/rockchip-iommu.c
··· 815 815 dte_addr = virt_to_phys(rk_domain->dt); 816 816 for (i = 0; i < iommu->num_mmu; i++) { 817 817 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr); 818 - rk_iommu_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 818 + rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 819 819 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); 820 820 } 821 821