Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner:
- a few simple fixes for fallout from the recent gic-v3 changes
- a workaround for a Cavium thunderX erratum
- a bugfix for the pic32 irqchip to make external interrupts work proper
- a missing return value in the generic IPI management code
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/irq-pic32-evic: Fix bug with external interrupts.
irqchip/gicv3-its: numa: Enable workaround for Cavium thunderx erratum 23144
irqchip/gic-v3: Fix quiescence check in gic_enable_redist
irqchip/gic-v3: Fix copy+paste mistakes in defines
irqchip/gic-v3: Fix ICC_SGI1R_EL1.INTID decoding mask
genirq: Fix missing return value in irq_destroy_ipi()
+63
-8
+1
Documentation/arm64/silicon-errata.txt
+1
Documentation/arm64/silicon-errata.txt
···
56
56
| ARM | MMU-500 | #841119,#826419 | N/A |
57
57
| | | | |
58
58
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
59
+
| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
59
60
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
60
61
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
61
62
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
+9
arch/arm64/Kconfig
+9
arch/arm64/Kconfig
···
438
438
439
439
If unsure, say Y.
440
440
441
+
config CAVIUM_ERRATUM_23144
442
+
bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
443
+
depends on NUMA
444
+
default y
445
+
help
446
+
ITS SYNC command hang for cross node io and collections/cpu mapping.
447
+
448
+
If unsure, say Y.
449
+
441
450
config CAVIUM_ERRATUM_23154
442
451
bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
443
452
default y
+47
-2
drivers/irqchip/irq-gic-v3-its.c
+47
-2
drivers/irqchip/irq-gic-v3-its.c
···
41
41
42
42
#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43
43
#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
44
+
#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
44
45
45
46
#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
46
47
···
83
82
u64 flags;
84
83
u32 ite_size;
85
84
u32 device_ids;
85
+
int numa_node;
86
86
};
87
87
88
88
#define ITS_ITT_ALIGN SZ_256
···
615
613
static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
616
614
bool force)
617
615
{
618
-
unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
616
+
unsigned int cpu;
617
+
const struct cpumask *cpu_mask = cpu_online_mask;
619
618
struct its_device *its_dev = irq_data_get_irq_chip_data(d);
620
619
struct its_collection *target_col;
621
620
u32 id = its_get_event_id(d);
621
+
622
+
/* lpi cannot be routed to a redistributor that is on a foreign node */
623
+
if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
624
+
if (its_dev->its->numa_node >= 0) {
625
+
cpu_mask = cpumask_of_node(its_dev->its->numa_node);
626
+
if (!cpumask_intersects(mask_val, cpu_mask))
627
+
return -EINVAL;
628
+
}
629
+
}
630
+
631
+
cpu = cpumask_any_and(mask_val, cpu_mask);
622
632
623
633
if (cpu >= nr_cpu_ids)
624
634
return -EINVAL;
···
1115
1101
list_for_each_entry(its, &its_nodes, entry) {
1116
1102
u64 target;
1117
1103
1104
+
/* avoid cross node collections and its mapping */
1105
+
if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1106
+
struct device_node *cpu_node;
1107
+
1108
+
cpu_node = of_get_cpu_node(cpu, NULL);
1109
+
if (its->numa_node != NUMA_NO_NODE &&
1110
+
its->numa_node != of_node_to_nid(cpu_node))
1111
+
continue;
1112
+
}
1113
+
1118
1114
/*
1119
1115
* We now have to bind each collection to its target
1120
1116
* redistributor.
···
1375
1351
{
1376
1352
struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1377
1353
u32 event = its_get_event_id(d);
1354
+
const struct cpumask *cpu_mask = cpu_online_mask;
1355
+
1356
+
/* get the cpu_mask of local node */
1357
+
if (its_dev->its->numa_node >= 0)
1358
+
cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1378
1359
1379
1360
/* Bind the LPI to the first possible CPU */
1380
-
its_dev->event_map.col_map[event] = cpumask_first(cpu_online_mask);
1361
+
its_dev->event_map.col_map[event] = cpumask_first(cpu_mask);
1381
1362
1382
1363
/* Map the GIC IRQ and event to the device */
1383
1364
its_send_mapvi(its_dev, d->hwirq, event);
···
1472
1443
its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
1473
1444
}
1474
1445
1446
+
static void __maybe_unused its_enable_quirk_cavium_23144(void *data)
1447
+
{
1448
+
struct its_node *its = data;
1449
+
1450
+
its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
1451
+
}
1452
+
1475
1453
static const struct gic_quirk its_quirks[] = {
1476
1454
#ifdef CONFIG_CAVIUM_ERRATUM_22375
1477
1455
{
···
1486
1450
.iidr = 0xa100034c, /* ThunderX pass 1.x */
1487
1451
.mask = 0xffff0fff,
1488
1452
.init = its_enable_quirk_cavium_22375,
1453
+
},
1454
+
#endif
1455
+
#ifdef CONFIG_CAVIUM_ERRATUM_23144
1456
+
{
1457
+
.desc = "ITS: Cavium erratum 23144",
1458
+
.iidr = 0xa100034c, /* ThunderX pass 1.x */
1459
+
.mask = 0xffff0fff,
1460
+
.init = its_enable_quirk_cavium_23144,
1489
1461
},
1490
1462
#endif
1491
1463
{
···
1558
1514
its->base = its_base;
1559
1515
its->phys_base = res.start;
1560
1516
its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1517
+
its->numa_node = of_node_to_nid(node);
1561
1518
1562
1519
its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
1563
1520
if (!its->cmd_base) {
+1
-1
drivers/irqchip/irq-gic-v3.c
+1
-1
drivers/irqchip/irq-gic-v3.c
+1
-1
drivers/irqchip/irq-pic32-evic.c
+1
-1
drivers/irqchip/irq-pic32-evic.c
···
91
91
/* set polarity for external interrupts only */
92
92
for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {
93
93
if (priv->ext_irqs[i] == data->hwirq) {
94
-
ret = pic32_set_ext_polarity(i + 1, flow_type);
94
+
ret = pic32_set_ext_polarity(i, flow_type);
95
95
if (ret)
96
96
return ret;
97
97
}
+3
-3
include/linux/irqchip/arm-gic-v3.h
+3
-3
include/linux/irqchip/arm-gic-v3.h
···
305
305
#define ICC_SGI1R_AFFINITY_1_SHIFT 16
306
306
#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
307
307
#define ICC_SGI1R_SGI_ID_SHIFT 24
308
-
#define ICC_SGI1R_SGI_ID_MASK (0xff << ICC_SGI1R_SGI_ID_SHIFT)
308
+
#define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
309
309
#define ICC_SGI1R_AFFINITY_2_SHIFT 32
310
-
#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
310
+
#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
311
311
#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
312
312
#define ICC_SGI1R_AFFINITY_3_SHIFT 48
313
-
#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
313
+
#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
314
314
315
315
#include <asm/arch_gicv3.h>
316
316