Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue
Tony Nguyen says:
====================
ice: remaining TSPLL cleanups
These are the remaining patches from the "ice: Separate TSPLL from PTP
and cleanup" series [1] with control flow macros removed. What remains
are cleanups and some minor improvements.
[1] https://lore.kernel.org/netdev/20250618174231.3100231-1-anthony.l.nguyen@intel.com/
* '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
ice: default to TIME_REF instead of TXCO on E825-C
ice: move TSPLL init calls to ice_ptp.c
ice: fall back to TCXO on TSPLL lock fail
ice: wait before enabling TSPLL
ice: add multiple TSPLL helpers
ice: use bitfields instead of unions for CGU regs
ice: read TSPLL registers again before reporting status
ice: clear time_sync_en field for E825-C during reprogramming
====================
Link: https://patch.msgid.link/20250626162921.1173068-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+315
-357
+1
-1
drivers/net/ethernet/intel/ice/ice_common.c
+1
-1
drivers/net/ethernet/intel/ice/ice_common.c
+32
-180
drivers/net/ethernet/intel/ice/ice_common.h
+32
-180
drivers/net/ethernet/intel/ice/ice_common.h
···
39
39
#define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT)
40
40
#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)
41
41
42
-
#define ICE_CGU_R9 0x24
43
-
union ice_cgu_r9 {
44
-
struct {
45
-
u32 time_ref_freq_sel : 3;
46
-
u32 clk_eref1_en : 1;
47
-
u32 clk_eref0_en : 1;
48
-
u32 time_ref_en : 1;
49
-
u32 time_sync_en : 1;
50
-
u32 one_pps_out_en : 1;
51
-
u32 clk_ref_synce_en : 1;
52
-
u32 clk_synce1_en : 1;
53
-
u32 clk_synce0_en : 1;
54
-
u32 net_clk_ref1_en : 1;
55
-
u32 net_clk_ref0_en : 1;
56
-
u32 clk_synce1_amp : 2;
57
-
u32 misc6 : 1;
58
-
u32 clk_synce0_amp : 2;
59
-
u32 one_pps_out_amp : 2;
60
-
u32 misc24 : 12;
61
-
};
62
-
u32 val;
63
-
};
42
+
#define ICE_CGU_R9 0x24
43
+
#define ICE_CGU_R9_TIME_REF_FREQ_SEL GENMASK(2, 0)
44
+
#define ICE_CGU_R9_CLK_EREF0_EN BIT(4)
45
+
#define ICE_CGU_R9_TIME_REF_EN BIT(5)
46
+
#define ICE_CGU_R9_TIME_SYNC_EN BIT(6)
47
+
#define ICE_CGU_R9_ONE_PPS_OUT_EN BIT(7)
48
+
#define ICE_CGU_R9_ONE_PPS_OUT_AMP GENMASK(19, 18)
64
49
65
-
#define ICE_CGU_R16 0x40
66
-
union ice_cgu_r16 {
67
-
struct {
68
-
u32 synce_remndr : 6;
69
-
u32 synce_phlmt_en : 1;
70
-
u32 misc13 : 17;
71
-
u32 ck_refclkfreq : 8;
72
-
};
73
-
u32 val;
74
-
};
50
+
#define ICE_CGU_R16 0x40
51
+
#define ICE_CGU_R16_TSPLL_CK_REFCLKFREQ GENMASK(31, 24)
75
52
76
-
#define ICE_CGU_R19 0x4c
77
-
union ice_cgu_r19_e82x {
78
-
struct {
79
-
u32 fbdiv_intgr : 8;
80
-
u32 fdpll_ulck_thr : 5;
81
-
u32 misc15 : 3;
82
-
u32 ndivratio : 4;
83
-
u32 tspll_iref_ndivratio : 3;
84
-
u32 misc19 : 1;
85
-
u32 japll_ndivratio : 4;
86
-
u32 japll_iref_ndivratio : 3;
87
-
u32 misc27 : 1;
88
-
};
89
-
u32 val;
90
-
};
53
+
#define ICE_CGU_R19 0x4C
54
+
#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E82X GENMASK(7, 0)
55
+
#define ICE_CGU_R19_TSPLL_FBDIV_INTGR_E825 GENMASK(9, 0)
56
+
#define ICE_CGU_R19_TSPLL_NDIVRATIO GENMASK(19, 16)
91
57
92
-
union ice_cgu_r19_e825 {
93
-
struct {
94
-
u32 tspll_fbdiv_intgr : 10;
95
-
u32 fdpll_ulck_thr : 5;
96
-
u32 misc15 : 1;
97
-
u32 tspll_ndivratio : 4;
98
-
u32 tspll_iref_ndivratio : 3;
99
-
u32 misc19 : 1;
100
-
u32 japll_ndivratio : 4;
101
-
u32 japll_postdiv_pdivratio : 3;
102
-
u32 misc27 : 1;
103
-
};
104
-
u32 val;
105
-
};
58
+
#define ICE_CGU_R22 0x58
59
+
#define ICE_CGU_R22_TIME1588CLK_DIV GENMASK(23, 20)
60
+
#define ICE_CGU_R22_TIME1588CLK_DIV2 BIT(30)
106
61
107
-
#define ICE_CGU_R22 0x58
108
-
union ice_cgu_r22 {
109
-
struct {
110
-
u32 fdpll_frac_div_out_nc : 2;
111
-
u32 fdpll_lock_int_for : 1;
112
-
u32 synce_hdov_int_for : 1;
113
-
u32 synce_lock_int_for : 1;
114
-
u32 fdpll_phlead_slip_nc : 1;
115
-
u32 fdpll_acc1_ovfl_nc : 1;
116
-
u32 fdpll_acc2_ovfl_nc : 1;
117
-
u32 synce_status_nc : 6;
118
-
u32 fdpll_acc1f_ovfl : 1;
119
-
u32 misc18 : 1;
120
-
u32 fdpllclk_div : 4;
121
-
u32 time1588clk_div : 4;
122
-
u32 synceclk_div : 4;
123
-
u32 synceclk_sel_div2 : 1;
124
-
u32 fdpllclk_sel_div2 : 1;
125
-
u32 time1588clk_sel_div2 : 1;
126
-
u32 misc3 : 1;
127
-
};
128
-
u32 val;
129
-
};
62
+
#define ICE_CGU_R23 0x5C
63
+
#define ICE_CGU_R24 0x60
64
+
#define ICE_CGU_R24_FBDIV_FRAC GENMASK(21, 0)
65
+
#define ICE_CGU_R23_R24_TSPLL_ENABLE BIT(24)
66
+
#define ICE_CGU_R23_R24_REF1588_CK_DIV GENMASK(30, 27)
67
+
#define ICE_CGU_R23_R24_TIME_REF_SEL BIT(31)
130
68
131
-
#define ICE_CGU_R23 0x5C
132
-
union ice_cgu_r23 {
133
-
struct {
134
-
u32 cgupll_fbdiv_intgr : 10;
135
-
u32 ux56pll_fbdiv_intgr : 10;
136
-
u32 misc20 : 4;
137
-
u32 ts_pll_enable : 1;
138
-
u32 time_sync_tspll_align_sel : 1;
139
-
u32 ext_synce_sel : 1;
140
-
u32 ref1588_ck_div : 4;
141
-
u32 time_ref_sel : 1;
69
+
#define ICE_CGU_BW_TDC 0x31C
70
+
#define ICE_CGU_BW_TDC_PLLLOCK_SEL GENMASK(30, 29)
142
71
143
-
};
144
-
u32 val;
145
-
};
72
+
#define ICE_CGU_RO_LOCK 0x3F0
73
+
#define ICE_CGU_RO_LOCK_TRUE_LOCK BIT(12)
74
+
#define ICE_CGU_RO_LOCK_UNLOCK BIT(13)
146
75
147
-
#define ICE_CGU_R24 0x60
148
-
union ice_cgu_r24 {
149
-
struct {
150
-
u32 fbdiv_frac : 22;
151
-
u32 misc20 : 2;
152
-
u32 ts_pll_enable : 1;
153
-
u32 time_sync_tspll_align_sel : 1;
154
-
u32 ext_synce_sel : 1;
155
-
u32 ref1588_ck_div : 4;
156
-
u32 time_ref_sel : 1;
157
-
};
158
-
u32 val;
159
-
};
76
+
#define ICE_CGU_CNTR_BIST 0x344
77
+
#define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_0 BIT(15)
78
+
#define ICE_CGU_CNTR_BIST_PLLLOCK_SEL_1 BIT(16)
160
79
161
-
#define TSPLL_CNTR_BIST_SETTINGS 0x344
162
-
union tspll_cntr_bist_settings {
163
-
struct {
164
-
u32 i_irefgen_settling_time_cntr_7_0 : 8;
165
-
u32 i_irefgen_settling_time_ro_standby_1_0 : 2;
166
-
u32 reserved195 : 5;
167
-
u32 i_plllock_sel_0 : 1;
168
-
u32 i_plllock_sel_1 : 1;
169
-
u32 i_plllock_cnt_6_0 : 7;
170
-
u32 i_plllock_cnt_10_7 : 4;
171
-
u32 reserved200 : 4;
172
-
};
173
-
u32 val;
174
-
};
175
-
176
-
#define TSPLL_RO_BWM_LF 0x370
177
-
union tspll_ro_bwm_lf {
178
-
struct {
179
-
u32 bw_freqov_high_cri_7_0 : 8;
180
-
u32 bw_freqov_high_cri_9_8 : 2;
181
-
u32 biascaldone_cri : 1;
182
-
u32 plllock_gain_tran_cri : 1;
183
-
u32 plllock_true_lock_cri : 1;
184
-
u32 pllunlock_flag_cri : 1;
185
-
u32 afcerr_cri : 1;
186
-
u32 afcdone_cri : 1;
187
-
u32 feedfwrdgain_cal_cri_7_0 : 8;
188
-
u32 m2fbdivmod_cri_7_0 : 8;
189
-
};
190
-
u32 val;
191
-
};
192
-
193
-
#define TSPLL_RO_LOCK_E825C 0x3f0
194
-
union tspll_ro_lock_e825c {
195
-
struct {
196
-
u32 bw_freqov_high_cri_7_0 : 8;
197
-
u32 bw_freqov_high_cri_9_8 : 2;
198
-
u32 reserved455 : 1;
199
-
u32 plllock_gain_tran_cri : 1;
200
-
u32 plllock_true_lock_cri : 1;
201
-
u32 pllunlock_flag_cri : 1;
202
-
u32 afcerr_cri : 1;
203
-
u32 afcdone_cri : 1;
204
-
u32 feedfwrdgain_cal_cri_7_0 : 8;
205
-
u32 reserved462 : 8;
206
-
};
207
-
u32 val;
208
-
};
209
-
210
-
#define TSPLL_BW_TDC_E825C 0x31c
211
-
union tspll_bw_tdc_e825c {
212
-
struct {
213
-
u32 i_tdc_offset_lock_1_0 : 2;
214
-
u32 i_bbthresh1_2_0 : 3;
215
-
u32 i_bbthresh2_2_0 : 3;
216
-
u32 i_tdcsel_1_0 : 2;
217
-
u32 i_tdcovccorr_en_h : 1;
218
-
u32 i_divretimeren : 1;
219
-
u32 i_bw_ampmeas_window : 1;
220
-
u32 i_bw_lowerbound_2_0 : 3;
221
-
u32 i_bw_upperbound_2_0 : 3;
222
-
u32 i_bw_mode_1_0 : 2;
223
-
u32 i_ft_mode_sel_2_0 : 3;
224
-
u32 i_bwphase_4_0 : 5;
225
-
u32 i_plllock_sel_1_0 : 2;
226
-
u32 i_afc_divratio : 1;
227
-
};
228
-
u32 val;
229
-
};
80
+
#define ICE_CGU_RO_BWM_LF 0x370
81
+
#define ICE_CGU_RO_BWM_LF_TRUE_LOCK BIT(12)
230
82
231
83
int ice_init_hw(struct ice_hw *hw);
232
84
void ice_deinit_hw(struct ice_hw *hw);
+11
drivers/net/ethernet/intel/ice/ice_ptp.c
+11
drivers/net/ethernet/intel/ice/ice_ptp.c
···
2892
2892
if (err)
2893
2893
return err;
2894
2894
2895
+
err = ice_tspll_init(hw);
2896
+
if (err)
2897
+
return err;
2898
+
2895
2899
/* Acquire the global hardware lock */
2896
2900
if (!ice_ptp_lock(hw)) {
2897
2901
err = -EBUSY;
···
3059
3055
err = ice_ptp_init_phc(hw);
3060
3056
if (err) {
3061
3057
dev_err(ice_pf_to_dev(pf), "Failed to initialize PHC, err %d\n",
3058
+
err);
3059
+
return err;
3060
+
}
3061
+
3062
+
err = ice_tspll_init(hw);
3063
+
if (err) {
3064
+
dev_err(ice_pf_to_dev(pf), "Failed to initialize CGU, status %d\n",
3062
3065
err);
3063
3066
return err;
3064
3067
}
+1
-21
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+1
-21
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
···
2116
2116
}
2117
2117
2118
2118
/**
2119
-
* ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization
2120
-
* @hw: pointer to HW struct
2121
-
*
2122
-
* Perform E825-specific PTP hardware clock initialization steps.
2123
-
*
2124
-
* Return: 0 on success, negative error code otherwise.
2125
-
*/
2126
-
static int ice_ptp_init_phc_e825(struct ice_hw *hw)
2127
-
{
2128
-
/* Initialize the Clock Generation Unit */
2129
-
return ice_tspll_init(hw);
2130
-
}
2131
-
2132
-
/**
2133
2119
* ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status
2134
2120
* @hw: pointer to the HW struct
2135
2121
* @ts_status: the timestamp mask pointer
···
2774
2788
*/
2775
2789
static int ice_ptp_init_phc_e82x(struct ice_hw *hw)
2776
2790
{
2777
-
int err;
2778
2791
u32 val;
2779
2792
2780
2793
/* Enable reading switch and PHY registers over the sideband queue */
···
2782
2797
val = rd32(hw, PF_SB_REM_DEV_CTL);
2783
2798
val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0);
2784
2799
wr32(hw, PF_SB_REM_DEV_CTL, val);
2785
-
2786
-
/* Initialize the Clock Generation Unit */
2787
-
err = ice_tspll_init(hw);
2788
-
if (err)
2789
-
return err;
2790
2800
2791
2801
/* Set window length for all the ports */
2792
2802
return ice_ptp_set_vernier_wl(hw);
···
5564
5584
case ICE_MAC_GENERIC:
5565
5585
return ice_ptp_init_phc_e82x(hw);
5566
5586
case ICE_MAC_GENERIC_3K_E825:
5567
-
return ice_ptp_init_phc_e825(hw);
5587
+
return 0;
5568
5588
default:
5569
5589
return -EOPNOTSUPP;
5570
5590
}
+270
-155
drivers/net/ethernet/intel/ice/ice_tspll.c
+270
-155
drivers/net/ethernet/intel/ice/ice_tspll.c
···
72
72
}
73
73
74
74
/**
75
+
* ice_tspll_default_freq - Return default frequency for a MAC type
76
+
* @mac_type: MAC type
77
+
*
78
+
* Return: default TSPLL frequency for a correct MAC type, -ERANGE otherwise.
79
+
*/
80
+
static enum ice_tspll_freq ice_tspll_default_freq(enum ice_mac_type mac_type)
81
+
{
82
+
switch (mac_type) {
83
+
case ICE_MAC_GENERIC:
84
+
return ICE_TSPLL_FREQ_25_000;
85
+
case ICE_MAC_GENERIC_3K_E825:
86
+
return ICE_TSPLL_FREQ_156_250;
87
+
default:
88
+
return -ERANGE;
89
+
}
90
+
}
91
+
92
+
/**
93
+
* ice_tspll_check_params - Check if TSPLL params are correct
94
+
* @hw: Pointer to the HW struct
95
+
* @clk_freq: Clock frequency to program
96
+
* @clk_src: Clock source to select (TIME_REF or TCXO)
97
+
*
98
+
* Return: true if TSPLL params are correct, false otherwise.
99
+
*/
100
+
static bool ice_tspll_check_params(struct ice_hw *hw,
101
+
enum ice_tspll_freq clk_freq,
102
+
enum ice_clk_src clk_src)
103
+
{
104
+
if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
105
+
dev_warn(ice_hw_to_dev(hw), "Invalid TSPLL frequency %u\n",
106
+
clk_freq);
107
+
return false;
108
+
}
109
+
110
+
if (clk_src >= NUM_ICE_CLK_SRC) {
111
+
dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
112
+
clk_src);
113
+
return false;
114
+
}
115
+
116
+
if ((hw->mac_type == ICE_MAC_GENERIC_3K_E825 ||
117
+
clk_src == ICE_CLK_SRC_TCXO) &&
118
+
clk_freq != ice_tspll_default_freq(hw->mac_type)) {
119
+
dev_warn(ice_hw_to_dev(hw), "Unsupported frequency for this clock source\n");
120
+
return false;
121
+
}
122
+
123
+
return true;
124
+
}
125
+
126
+
/**
75
127
* ice_tspll_clk_src_str - Convert time_ref_src to string
76
128
* @clk_src: Clock source
77
129
*
···
179
127
static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
180
128
enum ice_clk_src clk_src)
181
129
{
182
-
union tspll_ro_bwm_lf bwm_lf;
183
-
union ice_cgu_r19_e82x dw19;
184
-
union ice_cgu_r22 dw22;
185
-
union ice_cgu_r24 dw24;
186
-
union ice_cgu_r9 dw9;
130
+
u32 val, r9, r24;
187
131
int err;
188
132
189
-
if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
190
-
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
191
-
clk_freq);
192
-
return -EINVAL;
193
-
}
194
-
195
-
if (clk_src >= NUM_ICE_CLK_SRC) {
196
-
dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
197
-
clk_src);
198
-
return -EINVAL;
199
-
}
200
-
201
-
if (clk_src == ICE_CLK_SRC_TCXO && clk_freq != ICE_TSPLL_FREQ_25_000) {
202
-
dev_warn(ice_hw_to_dev(hw),
203
-
"TCXO only supports 25 MHz frequency\n");
204
-
return -EINVAL;
205
-
}
206
-
207
-
err = ice_read_cgu_reg(hw, ICE_CGU_R9, &dw9.val);
133
+
err = ice_read_cgu_reg(hw, ICE_CGU_R9, &r9);
208
134
if (err)
209
135
return err;
210
136
211
-
err = ice_read_cgu_reg(hw, ICE_CGU_R24, &dw24.val);
137
+
err = ice_read_cgu_reg(hw, ICE_CGU_R24, &r24);
212
138
if (err)
213
139
return err;
214
140
215
-
err = ice_read_cgu_reg(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
141
+
err = ice_read_cgu_reg(hw, ICE_CGU_RO_BWM_LF, &val);
216
142
if (err)
217
143
return err;
218
144
219
-
ice_tspll_log_cfg(hw, dw24.ts_pll_enable, dw24.time_ref_sel,
220
-
dw9.time_ref_freq_sel, bwm_lf.plllock_true_lock_cri,
145
+
ice_tspll_log_cfg(hw, !!FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r24),
146
+
FIELD_GET(ICE_CGU_R23_R24_TIME_REF_SEL, r24),
147
+
FIELD_GET(ICE_CGU_R9_TIME_REF_FREQ_SEL, r9),
148
+
!!FIELD_GET(ICE_CGU_RO_BWM_LF_TRUE_LOCK, val),
221
149
false);
222
150
223
151
/* Disable the PLL before changing the clock source or frequency */
224
-
if (dw24.ts_pll_enable) {
225
-
dw24.ts_pll_enable = 0;
152
+
if (FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r24)) {
153
+
r24 &= ~ICE_CGU_R23_R24_TSPLL_ENABLE;
226
154
227
-
err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
155
+
err = ice_write_cgu_reg(hw, ICE_CGU_R24, r24);
228
156
if (err)
229
157
return err;
230
158
}
231
159
232
160
/* Set the frequency */
233
-
dw9.time_ref_freq_sel = clk_freq;
234
-
err = ice_write_cgu_reg(hw, ICE_CGU_R9, dw9.val);
161
+
r9 &= ~ICE_CGU_R9_TIME_REF_FREQ_SEL;
162
+
r9 |= FIELD_PREP(ICE_CGU_R9_TIME_REF_FREQ_SEL, clk_freq);
163
+
err = ice_write_cgu_reg(hw, ICE_CGU_R9, r9);
235
164
if (err)
236
165
return err;
237
166
238
167
/* Configure the TSPLL feedback divisor */
239
-
err = ice_read_cgu_reg(hw, ICE_CGU_R19, &dw19.val);
168
+
err = ice_read_cgu_reg(hw, ICE_CGU_R19, &val);
240
169
if (err)
241
170
return err;
242
171
243
-
dw19.fbdiv_intgr = e82x_tspll_params[clk_freq].feedback_div;
244
-
dw19.ndivratio = 1;
172
+
val &= ~(ICE_CGU_R19_TSPLL_FBDIV_INTGR_E82X | ICE_CGU_R19_TSPLL_NDIVRATIO);
173
+
val |= FIELD_PREP(ICE_CGU_R19_TSPLL_FBDIV_INTGR_E82X,
174
+
e82x_tspll_params[clk_freq].feedback_div);
175
+
val |= FIELD_PREP(ICE_CGU_R19_TSPLL_NDIVRATIO, 1);
245
176
246
-
err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
177
+
err = ice_write_cgu_reg(hw, ICE_CGU_R19, val);
247
178
if (err)
248
179
return err;
249
180
250
181
/* Configure the TSPLL post divisor */
251
-
err = ice_read_cgu_reg(hw, ICE_CGU_R22, &dw22.val);
182
+
err = ice_read_cgu_reg(hw, ICE_CGU_R22, &val);
252
183
if (err)
253
184
return err;
254
185
255
-
dw22.time1588clk_div = e82x_tspll_params[clk_freq].post_pll_div;
256
-
dw22.time1588clk_sel_div2 = 0;
186
+
val &= ~(ICE_CGU_R22_TIME1588CLK_DIV |
187
+
ICE_CGU_R22_TIME1588CLK_DIV2);
188
+
val |= FIELD_PREP(ICE_CGU_R22_TIME1588CLK_DIV,
189
+
e82x_tspll_params[clk_freq].post_pll_div);
257
190
258
-
err = ice_write_cgu_reg(hw, ICE_CGU_R22, dw22.val);
191
+
err = ice_write_cgu_reg(hw, ICE_CGU_R22, val);
259
192
if (err)
260
193
return err;
261
194
262
195
/* Configure the TSPLL pre divisor and clock source */
263
-
err = ice_read_cgu_reg(hw, ICE_CGU_R24, &dw24.val);
196
+
err = ice_read_cgu_reg(hw, ICE_CGU_R24, &r24);
264
197
if (err)
265
198
return err;
266
199
267
-
dw24.ref1588_ck_div = e82x_tspll_params[clk_freq].refclk_pre_div;
268
-
dw24.fbdiv_frac = e82x_tspll_params[clk_freq].frac_n_div;
269
-
dw24.time_ref_sel = clk_src;
200
+
r24 &= ~(ICE_CGU_R23_R24_REF1588_CK_DIV | ICE_CGU_R24_FBDIV_FRAC |
201
+
ICE_CGU_R23_R24_TIME_REF_SEL);
202
+
r24 |= FIELD_PREP(ICE_CGU_R23_R24_REF1588_CK_DIV,
203
+
e82x_tspll_params[clk_freq].refclk_pre_div);
204
+
r24 |= FIELD_PREP(ICE_CGU_R24_FBDIV_FRAC,
205
+
e82x_tspll_params[clk_freq].frac_n_div);
206
+
r24 |= FIELD_PREP(ICE_CGU_R23_R24_TIME_REF_SEL, clk_src);
270
207
271
-
err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
208
+
err = ice_write_cgu_reg(hw, ICE_CGU_R24, r24);
272
209
if (err)
273
210
return err;
211
+
212
+
/* Wait to ensure everything is stable */
213
+
usleep_range(10, 20);
274
214
275
215
/* Finally, enable the PLL */
276
-
dw24.ts_pll_enable = 1;
216
+
r24 |= ICE_CGU_R23_R24_TSPLL_ENABLE;
277
217
278
-
err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
218
+
err = ice_write_cgu_reg(hw, ICE_CGU_R24, r24);
279
219
if (err)
280
220
return err;
281
221
282
-
/* Wait to verify if the PLL locks */
283
-
usleep_range(1000, 5000);
222
+
/* Wait at least 1 ms to verify if the PLL locks */
223
+
usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
284
224
285
-
err = ice_read_cgu_reg(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
225
+
err = ice_read_cgu_reg(hw, ICE_CGU_RO_BWM_LF, &val);
286
226
if (err)
287
227
return err;
288
228
289
-
if (!bwm_lf.plllock_true_lock_cri) {
290
-
dev_warn(ice_hw_to_dev(hw), "TSPLL failed to lock\n");
229
+
if (!(val & ICE_CGU_RO_BWM_LF_TRUE_LOCK)) {
230
+
dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
291
231
return -EBUSY;
292
232
}
293
233
294
-
ice_tspll_log_cfg(hw, dw24.ts_pll_enable, clk_src, clk_freq, true,
295
-
true);
234
+
err = ice_read_cgu_reg(hw, ICE_CGU_R9, &r9);
235
+
if (err)
236
+
return err;
237
+
err = ice_read_cgu_reg(hw, ICE_CGU_R24, &r24);
238
+
if (err)
239
+
return err;
240
+
241
+
ice_tspll_log_cfg(hw, !!FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r24),
242
+
FIELD_GET(ICE_CGU_R23_R24_TIME_REF_SEL, r24),
243
+
FIELD_GET(ICE_CGU_R9_TIME_REF_FREQ_SEL, r9),
244
+
true, true);
296
245
297
246
return 0;
298
247
}
···
309
256
*/
310
257
static int ice_tspll_dis_sticky_bits_e82x(struct ice_hw *hw)
311
258
{
312
-
union tspll_cntr_bist_settings cntr_bist;
259
+
u32 val;
313
260
int err;
314
261
315
-
err = ice_read_cgu_reg(hw, TSPLL_CNTR_BIST_SETTINGS, &cntr_bist.val);
262
+
err = ice_read_cgu_reg(hw, ICE_CGU_CNTR_BIST, &val);
316
263
if (err)
317
264
return err;
318
265
319
-
/* Disable sticky lock detection so lock err reported is accurate */
320
-
cntr_bist.i_plllock_sel_0 = 0;
321
-
cntr_bist.i_plllock_sel_1 = 0;
266
+
val &= ~(ICE_CGU_CNTR_BIST_PLLLOCK_SEL_0 |
267
+
ICE_CGU_CNTR_BIST_PLLLOCK_SEL_1);
322
268
323
-
return ice_write_cgu_reg(hw, TSPLL_CNTR_BIST_SETTINGS, cntr_bist.val);
269
+
return ice_write_cgu_reg(hw, ICE_CGU_CNTR_BIST, val);
324
270
}
325
271
326
272
/**
···
340
288
static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
341
289
enum ice_clk_src clk_src)
342
290
{
343
-
union tspll_ro_lock_e825c ro_lock;
344
-
union ice_cgu_r19_e825 dw19;
345
-
union ice_cgu_r16 dw16;
346
-
union ice_cgu_r23 dw23;
347
-
union ice_cgu_r22 dw22;
348
-
union ice_cgu_r9 dw9;
291
+
u32 val, r9, r23;
349
292
int err;
350
293
351
-
if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
352
-
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
353
-
clk_freq);
354
-
return -EINVAL;
355
-
}
356
-
357
-
if (clk_src >= NUM_ICE_CLK_SRC) {
358
-
dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
359
-
clk_src);
360
-
return -EINVAL;
361
-
}
362
-
363
-
if (clk_freq != ICE_TSPLL_FREQ_156_250) {
364
-
dev_warn(ice_hw_to_dev(hw), "Adapter only supports 156.25 MHz frequency\n");
365
-
return -EINVAL;
366
-
}
367
-
368
-
err = ice_read_cgu_reg(hw, ICE_CGU_R9, &dw9.val);
294
+
err = ice_read_cgu_reg(hw, ICE_CGU_R9, &r9);
369
295
if (err)
370
296
return err;
371
297
372
-
err = ice_read_cgu_reg(hw, ICE_CGU_R16, &dw16.val);
298
+
err = ice_read_cgu_reg(hw, ICE_CGU_R23, &r23);
373
299
if (err)
374
300
return err;
375
301
376
-
err = ice_read_cgu_reg(hw, ICE_CGU_R23, &dw23.val);
302
+
err = ice_read_cgu_reg(hw, ICE_CGU_RO_LOCK, &val);
377
303
if (err)
378
304
return err;
379
305
380
-
err = ice_read_cgu_reg(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
381
-
if (err)
382
-
return err;
383
-
384
-
ice_tspll_log_cfg(hw, dw23.ts_pll_enable, dw23.time_ref_sel,
385
-
dw9.time_ref_freq_sel,
386
-
ro_lock.plllock_true_lock_cri, false);
306
+
ice_tspll_log_cfg(hw, !!FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r23),
307
+
FIELD_GET(ICE_CGU_R23_R24_TIME_REF_SEL, r23),
308
+
FIELD_GET(ICE_CGU_R9_TIME_REF_FREQ_SEL, r9),
309
+
!!FIELD_GET(ICE_CGU_RO_LOCK_TRUE_LOCK, val),
310
+
false);
387
311
388
312
/* Disable the PLL before changing the clock source or frequency */
389
-
if (dw23.ts_pll_enable) {
390
-
dw23.ts_pll_enable = 0;
313
+
if (FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r23)) {
314
+
r23 &= ~ICE_CGU_R23_R24_TSPLL_ENABLE;
391
315
392
-
err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
316
+
err = ice_write_cgu_reg(hw, ICE_CGU_R23, r23);
393
317
if (err)
394
318
return err;
395
319
}
396
320
397
-
/* Set the frequency */
398
-
dw9.time_ref_freq_sel = clk_freq;
321
+
if (FIELD_GET(ICE_CGU_R9_TIME_SYNC_EN, r9)) {
322
+
r9 &= ~ICE_CGU_R9_TIME_SYNC_EN;
399
323
400
-
/* Enable the correct receiver */
401
-
if (clk_src == ICE_CLK_SRC_TCXO) {
402
-
dw9.time_ref_en = 0;
403
-
dw9.clk_eref0_en = 1;
404
-
} else {
405
-
dw9.time_ref_en = 1;
406
-
dw9.clk_eref0_en = 0;
324
+
err = ice_write_cgu_reg(hw, ICE_CGU_R9, r9);
325
+
if (err)
326
+
return err;
407
327
}
408
-
err = ice_write_cgu_reg(hw, ICE_CGU_R9, dw9.val);
328
+
329
+
/* Set the frequency and enable the correct receiver */
330
+
r9 &= ~(ICE_CGU_R9_TIME_REF_FREQ_SEL | ICE_CGU_R9_CLK_EREF0_EN |
331
+
ICE_CGU_R9_TIME_REF_EN);
332
+
r9 |= FIELD_PREP(ICE_CGU_R9_TIME_REF_FREQ_SEL, clk_freq);
333
+
if (clk_src == ICE_CLK_SRC_TCXO)
334
+
r9 |= ICE_CGU_R9_CLK_EREF0_EN;
335
+
else
336
+
r9 |= ICE_CGU_R9_TIME_REF_EN;
337
+
r9 |= ICE_CGU_R9_TIME_SYNC_EN;
338
+
err = ice_write_cgu_reg(hw, ICE_CGU_R9, r9);
409
339
if (err)
410
340
return err;
411
341
412
342
/* Choose the referenced frequency */
413
-
dw16.ck_refclkfreq = ICE_TSPLL_CK_REFCLKFREQ_E825;
414
-
err = ice_write_cgu_reg(hw, ICE_CGU_R16, dw16.val);
343
+
err = ice_read_cgu_reg(hw, ICE_CGU_R16, &val);
344
+
if (err)
345
+
return err;
346
+
val &= ~ICE_CGU_R16_TSPLL_CK_REFCLKFREQ;
347
+
val |= FIELD_PREP(ICE_CGU_R16_TSPLL_CK_REFCLKFREQ,
348
+
ICE_TSPLL_CK_REFCLKFREQ_E825);
349
+
err = ice_write_cgu_reg(hw, ICE_CGU_R16, val);
415
350
if (err)
416
351
return err;
417
352
418
353
/* Configure the TSPLL feedback divisor */
419
-
err = ice_read_cgu_reg(hw, ICE_CGU_R19, &dw19.val);
354
+
err = ice_read_cgu_reg(hw, ICE_CGU_R19, &val);
420
355
if (err)
421
356
return err;
422
357
423
-
dw19.tspll_fbdiv_intgr = ICE_TSPLL_FBDIV_INTGR_E825;
424
-
dw19.tspll_ndivratio = ICE_TSPLL_NDIVRATIO_E825;
358
+
val &= ~(ICE_CGU_R19_TSPLL_FBDIV_INTGR_E825 |
359
+
ICE_CGU_R19_TSPLL_NDIVRATIO);
360
+
val |= FIELD_PREP(ICE_CGU_R19_TSPLL_FBDIV_INTGR_E825,
361
+
ICE_TSPLL_FBDIV_INTGR_E825);
362
+
val |= FIELD_PREP(ICE_CGU_R19_TSPLL_NDIVRATIO,
363
+
ICE_TSPLL_NDIVRATIO_E825);
425
364
426
-
err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
365
+
err = ice_write_cgu_reg(hw, ICE_CGU_R19, val);
427
366
if (err)
428
367
return err;
429
368
430
-
/* Configure the TSPLL post divisor */
431
-
err = ice_read_cgu_reg(hw, ICE_CGU_R22, &dw22.val);
369
+
/* Configure the TSPLL post divisor, these two are constant */
370
+
err = ice_read_cgu_reg(hw, ICE_CGU_R22, &val);
432
371
if (err)
433
372
return err;
434
373
435
-
/* These two are constant for E825C */
436
-
dw22.time1588clk_div = 5;
437
-
dw22.time1588clk_sel_div2 = 0;
374
+
val &= ~(ICE_CGU_R22_TIME1588CLK_DIV |
375
+
ICE_CGU_R22_TIME1588CLK_DIV2);
376
+
val |= FIELD_PREP(ICE_CGU_R22_TIME1588CLK_DIV, 5);
438
377
439
-
err = ice_write_cgu_reg(hw, ICE_CGU_R22, dw22.val);
378
+
err = ice_write_cgu_reg(hw, ICE_CGU_R22, val);
440
379
if (err)
441
380
return err;
442
381
443
-
/* Configure the TSPLL pre divisor and clock source */
444
-
err = ice_read_cgu_reg(hw, ICE_CGU_R23, &dw23.val);
382
+
/* Configure the TSPLL pre divisor (constant) and clock source */
383
+
err = ice_read_cgu_reg(hw, ICE_CGU_R23, &r23);
445
384
if (err)
446
385
return err;
447
386
448
-
dw23.ref1588_ck_div = 0;
449
-
dw23.time_ref_sel = clk_src;
387
+
r23 &= ~(ICE_CGU_R23_R24_REF1588_CK_DIV | ICE_CGU_R23_R24_TIME_REF_SEL);
388
+
r23 |= FIELD_PREP(ICE_CGU_R23_R24_TIME_REF_SEL, clk_src);
450
389
451
-
err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
390
+
err = ice_write_cgu_reg(hw, ICE_CGU_R23, r23);
452
391
if (err)
453
392
return err;
454
393
···
448
405
if (err)
449
406
return err;
450
407
408
+
/* Wait to ensure everything is stable */
409
+
usleep_range(10, 20);
410
+
451
411
/* Finally, enable the PLL */
452
-
dw23.ts_pll_enable = 1;
412
+
r23 |= ICE_CGU_R23_R24_TSPLL_ENABLE;
453
413
454
-
err = ice_write_cgu_reg(hw, ICE_CGU_R23, dw23.val);
414
+
err = ice_write_cgu_reg(hw, ICE_CGU_R23, r23);
455
415
if (err)
456
416
return err;
457
417
458
-
/* Wait to verify if the PLL locks */
459
-
usleep_range(1000, 5000);
418
+
/* Wait at least 1 ms to verify if the PLL locks */
419
+
usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
460
420
461
-
err = ice_read_cgu_reg(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
421
+
err = ice_read_cgu_reg(hw, ICE_CGU_RO_LOCK, &val);
462
422
if (err)
463
423
return err;
464
424
465
-
if (!ro_lock.plllock_true_lock_cri) {
466
-
dev_warn(ice_hw_to_dev(hw), "TSPLL failed to lock\n");
425
+
if (!(val & ICE_CGU_RO_LOCK_TRUE_LOCK)) {
426
+
dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
467
427
return -EBUSY;
468
428
}
469
429
470
-
ice_tspll_log_cfg(hw, dw23.ts_pll_enable, clk_src, clk_freq, true,
471
-
true);
430
+
err = ice_read_cgu_reg(hw, ICE_CGU_R9, &r9);
431
+
if (err)
432
+
return err;
433
+
err = ice_read_cgu_reg(hw, ICE_CGU_R23, &r23);
434
+
if (err)
435
+
return err;
436
+
437
+
ice_tspll_log_cfg(hw, !!FIELD_GET(ICE_CGU_R23_R24_TSPLL_ENABLE, r23),
438
+
FIELD_GET(ICE_CGU_R23_R24_TIME_REF_SEL, r23),
439
+
FIELD_GET(ICE_CGU_R9_TIME_REF_FREQ_SEL, r9),
440
+
true, true);
472
441
473
442
return 0;
474
443
}
···
496
441
*/
497
442
static int ice_tspll_dis_sticky_bits_e825c(struct ice_hw *hw)
498
443
{
499
-
union tspll_bw_tdc_e825c bw_tdc;
444
+
u32 val;
500
445
int err;
501
446
502
-
err = ice_read_cgu_reg(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
447
+
err = ice_read_cgu_reg(hw, ICE_CGU_BW_TDC, &val);
503
448
if (err)
504
449
return err;
505
450
506
-
bw_tdc.i_plllock_sel_1_0 = 0;
451
+
val &= ~ICE_CGU_BW_TDC_PLLLOCK_SEL;
507
452
508
-
return ice_write_cgu_reg(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
453
+
return ice_write_cgu_reg(hw, ICE_CGU_BW_TDC, val);
509
454
}
510
-
511
-
#define ICE_ONE_PPS_OUT_AMP_MAX 3
512
455
513
456
/**
514
457
* ice_tspll_cfg_pps_out_e825c - Enable/disable 1PPS output and set amplitude
···
517
464
*/
518
465
int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable)
519
466
{
520
-
union ice_cgu_r9 r9;
467
+
u32 val;
521
468
int err;
522
469
523
-
err = ice_read_cgu_reg(hw, ICE_CGU_R9, &r9.val);
470
+
err = ice_read_cgu_reg(hw, ICE_CGU_R9, &val);
524
471
if (err)
525
472
return err;
526
473
527
-
r9.one_pps_out_en = enable;
528
-
r9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX;
529
-
return ice_write_cgu_reg(hw, ICE_CGU_R9, r9.val);
474
+
val &= ~(ICE_CGU_R9_ONE_PPS_OUT_EN | ICE_CGU_R9_ONE_PPS_OUT_AMP);
475
+
val |= FIELD_PREP(ICE_CGU_R9_ONE_PPS_OUT_EN, enable) |
476
+
ICE_CGU_R9_ONE_PPS_OUT_AMP;
477
+
478
+
return ice_write_cgu_reg(hw, ICE_CGU_R9, val);
479
+
}
480
+
481
+
/**
482
+
* ice_tspll_cfg - Configure the Clock Generation Unit TSPLL
483
+
* @hw: Pointer to the HW struct
484
+
* @clk_freq: Clock frequency to program
485
+
* @clk_src: Clock source to select (TIME_REF, or TCXO)
486
+
*
487
+
* Configure the Clock Generation Unit with the desired clock frequency and
488
+
* time reference, enabling the TSPLL which drives the PTP hardware clock.
489
+
*
490
+
* Return: 0 on success, -ERANGE on unsupported MAC type, other negative error
491
+
* codes when failed to configure CGU.
492
+
*/
493
+
static int ice_tspll_cfg(struct ice_hw *hw, enum ice_tspll_freq clk_freq,
494
+
enum ice_clk_src clk_src)
495
+
{
496
+
switch (hw->mac_type) {
497
+
case ICE_MAC_GENERIC:
498
+
return ice_tspll_cfg_e82x(hw, clk_freq, clk_src);
499
+
case ICE_MAC_GENERIC_3K_E825:
500
+
return ice_tspll_cfg_e825c(hw, clk_freq, clk_src);
501
+
default:
502
+
return -ERANGE;
503
+
}
504
+
}
505
+
506
+
/**
507
+
* ice_tspll_dis_sticky_bits - disable TSPLL sticky bits
508
+
* @hw: Pointer to the HW struct
509
+
*
510
+
* Configure the Clock Generation Unit TSPLL sticky bits so they don't latch on
511
+
* losing TSPLL lock, but always show current state.
512
+
*
513
+
* Return: 0 on success, -ERANGE on unsupported MAC type.
514
+
*/
515
+
static int ice_tspll_dis_sticky_bits(struct ice_hw *hw)
516
+
{
517
+
switch (hw->mac_type) {
518
+
case ICE_MAC_GENERIC:
519
+
return ice_tspll_dis_sticky_bits_e82x(hw);
520
+
case ICE_MAC_GENERIC_3K_E825:
521
+
return ice_tspll_dis_sticky_bits_e825c(hw);
522
+
default:
523
+
return -ERANGE;
524
+
}
530
525
}
531
526
532
527
/**
···
588
487
int ice_tspll_init(struct ice_hw *hw)
589
488
{
590
489
struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
490
+
enum ice_tspll_freq tspll_freq;
491
+
enum ice_clk_src clk_src;
591
492
int err;
592
493
593
-
/* Disable sticky lock detection so lock err reported is accurate. */
594
-
if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
595
-
err = ice_tspll_dis_sticky_bits_e825c(hw);
596
-
else
597
-
err = ice_tspll_dis_sticky_bits_e82x(hw);
494
+
/* Only E822, E823 and E825 products support TSPLL */
495
+
if (hw->mac_type != ICE_MAC_GENERIC &&
496
+
hw->mac_type != ICE_MAC_GENERIC_3K_E825)
497
+
return 0;
498
+
499
+
tspll_freq = (enum ice_tspll_freq)ts_info->time_ref;
500
+
clk_src = (enum ice_clk_src)ts_info->clk_src;
501
+
if (!ice_tspll_check_params(hw, tspll_freq, clk_src))
502
+
return -EINVAL;
503
+
504
+
/* Disable sticky lock detection so lock status reported is accurate */
505
+
err = ice_tspll_dis_sticky_bits(hw);
598
506
if (err)
599
507
return err;
600
508
601
509
/* Configure the TSPLL using the parameters from the function
602
510
* capabilities.
603
511
*/
604
-
if (hw->mac_type == ICE_MAC_GENERIC_3K_E825)
605
-
err = ice_tspll_cfg_e825c(hw, ts_info->time_ref,
606
-
(enum ice_clk_src)ts_info->clk_src);
607
-
else
608
-
err = ice_tspll_cfg_e82x(hw, ts_info->time_ref,
609
-
(enum ice_clk_src)ts_info->clk_src);
512
+
err = ice_tspll_cfg(hw, tspll_freq, clk_src);
513
+
if (err) {
514
+
dev_warn(ice_hw_to_dev(hw), "Failed to lock TSPLL to predefined frequency. Retrying with fallback frequency.\n");
515
+
516
+
/* Try to lock to internal TCXO as a fallback. */
517
+
tspll_freq = ice_tspll_default_freq(hw->mac_type);
518
+
clk_src = ICE_CLK_SRC_TCXO;
519
+
err = ice_tspll_cfg(hw, tspll_freq, clk_src);
520
+
if (err)
521
+
dev_warn(ice_hw_to_dev(hw), "Failed to lock TSPLL to fallback frequency.\n");
522
+
}
610
523
611
524
return err;
612
525
}