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phy: marvell: phy-mvebu-cp110-comphy: improve eth_port1 on comphy4

According to the CN9100_MPP_information document, CP_SRD4 (comphy 4)
supports 2500 BASE-X and 5000 BASE-R for ETH_PORT1. I was able to test
that 2500 BASE-X is indeed supported. Unfortunately, our HW does not
support 5000 BASE-R, but I assume from the document that it does, so I
set the muxing there too to 0x1.

Signed-off-by: Stefan Eichenberger <eichest@gmail.com>
Link: https://lore.kernel.org/r/20240711131612.98952-1-eichest@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Stefan Eichenberger and committed by
Vinod Koul 8c9f085a 4e92d504

+2 -2
+2 -2
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
··· 244 244 GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H), 245 245 GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), 246 246 ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII), 247 - ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_2500BASEX), 248 - ETH_CONF(4, 1, PHY_INTERFACE_MODE_5GBASER, -1, COMPHY_FW_MODE_XFI), 247 + ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_2500BASEX), 248 + ETH_CONF(4, 1, PHY_INTERFACE_MODE_5GBASER, 0x1, COMPHY_FW_MODE_XFI), 249 249 ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI), 250 250 /* lane 5 */ 251 251 ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),