Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'x86_microcode_for_v7.0_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 microcode loader update from Borislav Petkov:
- Since debugging the microcode loader makes sense on baremetal too (it
was used in a guest only until now), extend it to be able to do that
too
* tag 'x86_microcode_for_v7.0_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/microcode/AMD: Allow loader debugging to be enabled on baremetal too
+20
-9
+5
-3
arch/x86/Kconfig
+5
-3
arch/x86/Kconfig
···
1380
1380
default n
1381
1381
depends on MICROCODE
1382
1382
help
1383
-
Enable code which allows for debugging the microcode loader in
1384
-
a guest. Meaning the patch loading is simulated but everything else
1383
+
Enable code which allows to debug the microcode loader. When running
1384
+
in a guest the patch loading is simulated but everything else
1385
1385
related to patch parsing and handling is done as on baremetal with
1386
-
the purpose of debugging solely the software side of things.
1386
+
the purpose of debugging solely the software side of things. On
1387
+
baremetal, it simply dumps additional debugging information during
1388
+
normal operation.
1387
1389
1388
1390
You almost certainly want to say n here.
1389
1391
+2
-2
arch/x86/kernel/cpu/microcode/amd.c
+2
-2
arch/x86/kernel/cpu/microcode/amd.c
···
322
322
{
323
323
u32 rev, dummy __always_unused;
324
324
325
-
if (IS_ENABLED(CONFIG_MICROCODE_DBG)) {
325
+
if (IS_ENABLED(CONFIG_MICROCODE_DBG) && hypervisor_present) {
326
326
int cpu = smp_processor_id();
327
327
328
328
if (!microcode_rev[cpu]) {
···
714
714
invlpg(p_addr_end);
715
715
}
716
716
717
-
if (IS_ENABLED(CONFIG_MICROCODE_DBG))
717
+
if (IS_ENABLED(CONFIG_MICROCODE_DBG) && hypervisor_present)
718
718
microcode_rev[smp_processor_id()] = mc->hdr.patch_id;
719
719
720
720
/* verify patch application was successful */
+12
-4
arch/x86/kernel/cpu/microcode/core.c
+12
-4
arch/x86/kernel/cpu/microcode/core.c
···
57
57
u32 base_rev;
58
58
u32 microcode_rev[NR_CPUS] = {};
59
59
60
+
bool hypervisor_present;
61
+
60
62
/*
61
63
* Synchronization.
62
64
*
···
119
117
* Disable when:
120
118
*
121
119
* 1) The CPU does not support CPUID.
122
-
*
120
+
*/
121
+
if (!cpuid_feature()) {
122
+
dis_ucode_ldr = true;
123
+
return dis_ucode_ldr;
124
+
}
125
+
126
+
/*
123
127
* 2) Bit 31 in CPUID[1]:ECX is clear
124
128
* The bit is reserved for hypervisor use. This is still not
125
129
* completely accurate as XEN PV guests don't see that CPUID bit
···
135
127
* 3) Certain AMD patch levels are not allowed to be
136
128
* overwritten.
137
129
*/
138
-
if (!cpuid_feature() ||
139
-
((native_cpuid_ecx(1) & BIT(31)) &&
140
-
!IS_ENABLED(CONFIG_MICROCODE_DBG)) ||
130
+
hypervisor_present = native_cpuid_ecx(1) & BIT(31);
131
+
132
+
if ((hypervisor_present && !IS_ENABLED(CONFIG_MICROCODE_DBG)) ||
141
133
amd_check_current_patch_level())
142
134
dis_ucode_ldr = true;
143
135