tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'mlx5-misc-patches-2024-10-31'

Tariq Toukan says:

====================
mlx5 misc patches 2024-10-31

First patch by Cosmin fixes an issue in a recent commit.

Followed by 2 patches by Yevgeny that organize and rename the files
under the steering directory.

Finally, 2 patches by William that save the creation of the unused
egress-XDP_REDIRECT send queue on non-uplink representor.
====================

Link: https://patch.msgid.link/20241031125856.530927-1-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski 8d1807a9 9ff75a23

+177 -121
+38 -25
drivers/net/ethernet/mellanox/mlx5/core/Makefile
··· 109 109 en_accel/fs_tcp.o en_accel/ktls.o en_accel/ktls_txrx.o \ 110 110 en_accel/ktls_tx.o en_accel/ktls_rx.o 111 111 112 - mlx5_core-$(CONFIG_MLX5_SW_STEERING) += steering/dr_domain.o steering/dr_table.o \ 113 - steering/dr_matcher.o steering/dr_rule.o \ 114 - steering/dr_icm_pool.o steering/dr_buddy.o \ 115 - steering/dr_ste.o steering/dr_send.o \ 116 - steering/dr_ste_v0.o steering/dr_ste_v1.o \ 117 - steering/dr_ste_v2.o \ 118 - steering/dr_cmd.o steering/dr_fw.o \ 119 - steering/dr_action.o steering/fs_dr.o \ 120 - steering/dr_definer.o steering/dr_ptrn.o \ 121 - steering/dr_arg.o steering/dr_dbg.o lib/smfs.o 112 + # 113 + # SW Steering 114 + # 115 + mlx5_core-$(CONFIG_MLX5_SW_STEERING) += steering/sws/dr_domain.o \ 116 + steering/sws/dr_table.o \ 117 + steering/sws/dr_matcher.o \ 118 + steering/sws/dr_rule.o \ 119 + steering/sws/dr_icm_pool.o \ 120 + steering/sws/dr_buddy.o \ 121 + steering/sws/dr_ste.o \ 122 + steering/sws/dr_send.o \ 123 + steering/sws/dr_ste_v0.o \ 124 + steering/sws/dr_ste_v1.o \ 125 + steering/sws/dr_ste_v2.o \ 126 + steering/sws/dr_cmd.o \ 127 + steering/sws/dr_fw.o \ 128 + steering/sws/dr_action.o \ 129 + steering/sws/dr_definer.o \ 130 + steering/sws/dr_ptrn.o \ 131 + steering/sws/dr_arg.o \ 132 + steering/sws/dr_dbg.o \ 133 + steering/sws/fs_dr.o \ 134 + lib/smfs.o 122 135 123 136 # 124 137 # HW Steering 125 138 # 126 - mlx5_core-$(CONFIG_MLX5_HW_STEERING) += steering/hws/mlx5hws_cmd.o \ 127 - steering/hws/mlx5hws_context.o \ 128 - steering/hws/mlx5hws_pat_arg.o \ 129 - steering/hws/mlx5hws_buddy.o \ 130 - steering/hws/mlx5hws_pool.o \ 131 - steering/hws/mlx5hws_table.o \ 132 - steering/hws/mlx5hws_action.o \ 133 - steering/hws/mlx5hws_rule.o \ 134 - steering/hws/mlx5hws_matcher.o \ 135 - steering/hws/mlx5hws_send.o \ 136 - steering/hws/mlx5hws_definer.o \ 137 - steering/hws/mlx5hws_bwc.o \ 138 - steering/hws/mlx5hws_debug.o \ 139 - steering/hws/mlx5hws_vport.o \ 140 - steering/hws/mlx5hws_bwc_complex.o 139 + mlx5_core-$(CONFIG_MLX5_HW_STEERING) += steering/hws/cmd.o \ 140 + steering/hws/context.o \ 141 + steering/hws/pat_arg.o \ 142 + steering/hws/buddy.o \ 143 + steering/hws/pool.o \ 144 + steering/hws/table.o \ 145 + steering/hws/action.o \ 146 + steering/hws/rule.o \ 147 + steering/hws/matcher.o \ 148 + steering/hws/send.o \ 149 + steering/hws/definer.o \ 150 + steering/hws/bwc.o \ 151 + steering/hws/debug.o \ 152 + steering/hws/vport.o \ 153 + steering/hws/bwc_complex.o 141 154 142 155 143 156 #
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/en.h
··· 755 755 u8 lag_port; 756 756 757 757 /* XDP_REDIRECT */ 758 - struct mlx5e_xdpsq xdpsq; 758 + struct mlx5e_xdpsq *xdpsq; 759 759 760 760 /* AF_XDP zero-copy */ 761 761 struct mlx5e_rq xskrq;
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c
··· 865 865 if (unlikely(sq_num >= priv->channels.num)) 866 866 return -ENXIO; 867 867 868 - sq = &priv->channels.c[sq_num]->xdpsq; 868 + sq = priv->channels.c[sq_num]->xdpsq; 869 869 870 870 for (i = 0; i < n; i++) { 871 871 struct mlx5e_xmit_data_frags xdptxdf = {};
+54 -19
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
··· 2086 2086 mlx5e_free_xdpsq(sq); 2087 2087 } 2088 2088 2089 + static struct mlx5e_xdpsq *mlx5e_open_xdpredirect_sq(struct mlx5e_channel *c, 2090 + struct mlx5e_params *params, 2091 + struct mlx5e_channel_param *cparam, 2092 + struct mlx5e_create_cq_param *ccp) 2093 + { 2094 + struct mlx5e_xdpsq *xdpsq; 2095 + int err; 2096 + 2097 + xdpsq = kvzalloc_node(sizeof(*xdpsq), GFP_KERNEL, c->cpu); 2098 + if (!xdpsq) 2099 + return ERR_PTR(-ENOMEM); 2100 + 2101 + err = mlx5e_open_cq(c->mdev, params->tx_cq_moderation, 2102 + &cparam->xdp_sq.cqp, ccp, &xdpsq->cq); 2103 + if (err) 2104 + goto err_free_xdpsq; 2105 + 2106 + err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, xdpsq, true); 2107 + if (err) 2108 + goto err_close_xdpsq_cq; 2109 + 2110 + return xdpsq; 2111 + 2112 + err_close_xdpsq_cq: 2113 + mlx5e_close_cq(&xdpsq->cq); 2114 + err_free_xdpsq: 2115 + kvfree(xdpsq); 2116 + 2117 + return ERR_PTR(err); 2118 + } 2119 + 2120 + static void mlx5e_close_xdpredirect_sq(struct mlx5e_xdpsq *xdpsq) 2121 + { 2122 + mlx5e_close_xdpsq(xdpsq); 2123 + mlx5e_close_cq(&xdpsq->cq); 2124 + kvfree(xdpsq); 2125 + } 2126 + 2089 2127 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev, 2090 2128 struct net_device *netdev, 2091 2129 struct workqueue_struct *workqueue, ··· 2514 2476 struct mlx5e_params *params, 2515 2477 struct mlx5e_channel_param *cparam) 2516 2478 { 2479 + const struct net_device_ops *netdev_ops = c->netdev->netdev_ops; 2517 2480 struct dim_cq_moder icocq_moder = {0, 0}; 2518 2481 struct mlx5e_create_cq_param ccp; 2519 2482 int err; ··· 2535 2496 if (err) 2536 2497 goto err_close_icosq_cq; 2537 2498 2538 - err = mlx5e_open_cq(c->mdev, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp, 2539 - &c->xdpsq.cq); 2540 - if (err) 2541 - goto err_close_tx_cqs; 2499 + if (netdev_ops->ndo_xdp_xmit) { 2500 + c->xdpsq = mlx5e_open_xdpredirect_sq(c, params, cparam, &ccp); 2501 + if (IS_ERR(c->xdpsq)) { 2502 + err = PTR_ERR(c->xdpsq); 2503 + goto err_close_tx_cqs; 2504 + } 2505 + } 2542 2506 2543 2507 err = mlx5e_open_cq(c->mdev, params->rx_cq_moderation, &cparam->rq.cqp, &ccp, 2544 2508 &c->rq.cq); 2545 2509 if (err) 2546 - goto err_close_xdp_tx_cqs; 2510 + goto err_close_xdpredirect_sq; 2547 2511 2548 2512 err = c->xdp ? mlx5e_open_cq(c->mdev, params->tx_cq_moderation, &cparam->xdp_sq.cqp, 2549 2513 &ccp, &c->rq_xdpsq.cq) : 0; ··· 2558 2516 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq, 2559 2517 mlx5e_async_icosq_err_cqe_work); 2560 2518 if (err) 2561 - goto err_close_xdpsq_cq; 2519 + goto err_close_rq_xdpsq_cq; 2562 2520 2563 2521 mutex_init(&c->icosq_recovery_lock); 2564 2522 ··· 2582 2540 goto err_close_rq; 2583 2541 } 2584 2542 2585 - err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true); 2586 - if (err) 2587 - goto err_close_xdp_sq; 2588 - 2589 2543 return 0; 2590 - 2591 - err_close_xdp_sq: 2592 - if (c->xdp) 2593 - mlx5e_close_xdpsq(&c->rq_xdpsq); 2594 2544 2595 2545 err_close_rq: 2596 2546 mlx5e_close_rq(&c->rq); ··· 2596 2562 err_close_async_icosq: 2597 2563 mlx5e_close_icosq(&c->async_icosq); 2598 2564 2599 - err_close_xdpsq_cq: 2565 + err_close_rq_xdpsq_cq: 2600 2566 if (c->xdp) 2601 2567 mlx5e_close_cq(&c->rq_xdpsq.cq); 2602 2568 2603 2569 err_close_rx_cq: 2604 2570 mlx5e_close_cq(&c->rq.cq); 2605 2571 2606 - err_close_xdp_tx_cqs: 2607 - mlx5e_close_cq(&c->xdpsq.cq); 2572 + err_close_xdpredirect_sq: 2573 + if (c->xdpsq) 2574 + mlx5e_close_xdpredirect_sq(c->xdpsq); 2608 2575 2609 2576 err_close_tx_cqs: 2610 2577 mlx5e_close_tx_cqs(c); ··· 2621 2586 2622 2587 static void mlx5e_close_queues(struct mlx5e_channel *c) 2623 2588 { 2624 - mlx5e_close_xdpsq(&c->xdpsq); 2625 2589 if (c->xdp) 2626 2590 mlx5e_close_xdpsq(&c->rq_xdpsq); 2627 2591 /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */ ··· 2633 2599 if (c->xdp) 2634 2600 mlx5e_close_cq(&c->rq_xdpsq.cq); 2635 2601 mlx5e_close_cq(&c->rq.cq); 2636 - mlx5e_close_cq(&c->xdpsq.cq); 2602 + if (c->xdpsq) 2603 + mlx5e_close_xdpredirect_sq(c->xdpsq); 2637 2604 mlx5e_close_tx_cqs(c); 2638 2605 mlx5e_close_cq(&c->icosq.cq); 2639 2606 mlx5e_close_cq(&c->async_icosq.cq);
+2 -1
drivers/net/ethernet/mellanox/mlx5/core/en_rep.c
··· 600 600 if (c->xdp) 601 601 sqs[num_sqs++] = c->rq_xdpsq.sqn; 602 602 603 - sqs[num_sqs++] = c->xdpsq.sqn; 603 + if (c->xdpsq) 604 + sqs[num_sqs++] = c->xdpsq->sqn; 604 605 } 605 606 } 606 607 if (ptp_sq) {
+4 -2
drivers/net/ethernet/mellanox/mlx5/core/en_txrx.c
··· 165 165 if (unlikely(!budget)) 166 166 goto out; 167 167 168 - busy |= mlx5e_poll_xdpsq_cq(&c->xdpsq.cq); 168 + if (c->xdpsq) 169 + busy |= mlx5e_poll_xdpsq_cq(&c->xdpsq->cq); 169 170 170 171 if (c->xdp) 171 172 busy |= mlx5e_poll_xdpsq_cq(&c->rq_xdpsq.cq); ··· 237 236 mlx5e_cq_arm(&rq->cq); 238 237 mlx5e_cq_arm(&c->icosq.cq); 239 238 mlx5e_cq_arm(&c->async_icosq.cq); 240 - mlx5e_cq_arm(&c->xdpsq.cq); 239 + if (c->xdpsq) 240 + mlx5e_cq_arm(&c->xdpsq->cq); 241 241 242 242 if (xsk_open) { 243 243 mlx5e_handle_rx_dim(xskrq);
+3
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
··· 951 951 952 952 int mlx5_esw_qos_init(struct mlx5_eswitch *esw) 953 953 { 954 + if (esw->qos.domain) 955 + return 0; /* Nothing to change. */ 956 + 954 957 return esw_qos_domain_init(esw); 955 958 } 956 959
+9 -7
drivers/net/ethernet/mellanox/mlx5/core/eswitch.c
··· 1485 1485 1486 1486 err = mlx5_esw_qos_init(esw); 1487 1487 if (err) 1488 - goto err_qos_init; 1488 + goto err_esw_init; 1489 1489 1490 1490 if (esw->mode == MLX5_ESWITCH_LEGACY) { 1491 1491 err = esw_legacy_enable(esw); ··· 1495 1495 } 1496 1496 1497 1497 if (err) 1498 - goto err_esw_enable; 1498 + goto err_esw_init; 1499 1499 1500 1500 esw->fdb_table.flags |= MLX5_ESW_FDB_CREATED; 1501 1501 ··· 1509 1509 1510 1510 return 0; 1511 1511 1512 - err_esw_enable: 1513 - mlx5_esw_qos_cleanup(esw); 1514 - err_qos_init: 1512 + err_esw_init: 1515 1513 mlx5_eq_notifier_unregister(esw->dev, &esw->nb); 1516 1514 mlx5_esw_acls_ns_cleanup(esw); 1517 1515 return err; ··· 1638 1640 1639 1641 if (esw->mode == MLX5_ESWITCH_OFFLOADS) 1640 1642 devl_rate_nodes_destroy(devlink); 1641 - mlx5_esw_qos_cleanup(esw); 1642 1643 } 1643 1644 1644 1645 void mlx5_eswitch_disable(struct mlx5_eswitch *esw) ··· 1881 1884 if (err) 1882 1885 goto reps_err; 1883 1886 1887 + esw->mode = MLX5_ESWITCH_LEGACY; 1888 + err = mlx5_esw_qos_init(esw); 1889 + if (err) 1890 + goto reps_err; 1891 + 1884 1892 mutex_init(&esw->offloads.encap_tbl_lock); 1885 1893 hash_init(esw->offloads.encap_tbl); 1886 1894 mutex_init(&esw->offloads.decap_tbl_lock); ··· 1899 1897 refcount_set(&esw->qos.refcnt, 0); 1900 1898 1901 1899 esw->enabled_vports = 0; 1902 - esw->mode = MLX5_ESWITCH_LEGACY; 1903 1900 esw->offloads.inline_mode = MLX5_INLINE_MODE_NONE; 1904 1901 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) && 1905 1902 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap)) ··· 1935 1934 1936 1935 esw_info(esw->dev, "cleanup\n"); 1937 1936 1937 + mlx5_esw_qos_cleanup(esw); 1938 1938 destroy_workqueue(esw->work_queue); 1939 1939 WARN_ON(refcount_read(&esw->qos.refcnt)); 1940 1940 mutex_destroy(&esw->state_lock);
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h
··· 37 37 #include <linux/mlx5/fs.h> 38 38 #include <linux/rhashtable.h> 39 39 #include <linux/llist.h> 40 - #include <steering/fs_dr.h> 40 + #include <steering/sws/fs_dr.h> 41 41 42 42 #define FDB_TC_MAX_CHAIN 3 43 43 #define FDB_FT_CHAIN (FDB_TC_MAX_CHAIN + 1)
+2 -2
drivers/net/ethernet/mellanox/mlx5/core/lib/smfs.h
··· 4 4 #ifndef __MLX5_LIB_SMFS_H__ 5 5 #define __MLX5_LIB_SMFS_H__ 6 6 7 - #include "steering/mlx5dr.h" 8 - #include "steering/dr_types.h" 7 + #include "steering/sws/mlx5dr.h" 8 + #include "steering/sws/dr_types.h" 9 9 10 10 struct mlx5dr_matcher * 11 11 mlx5_smfs_matcher_create(struct mlx5dr_table *table, u32 priority, struct mlx5_flow_spec *spec);
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_action.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_arg.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_arg.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_buddy.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_buddy.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_cmd.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_cmd.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_dbg.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_dbg.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_dbg.h drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_dbg.h
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_definer.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_definer.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_domain.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_fw.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_icm_pool.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_icm_pool.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_matcher.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ptrn.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ptrn.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_rule.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste.h
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste_v0.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste_v1.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.h drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste_v1.h
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v2.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste_v2.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_table.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_table.c
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_types.h
drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c drivers/net/ethernet/mellanox/mlx5/core/steering/sws/fs_dr.c
drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.h drivers/net/ethernet/mellanox/mlx5/core/steering/sws/fs_dr.h
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_action.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 6 6 #define MLX5HWS_ACTION_METER_INIT_COLOR_OFFSET 1 7 7
+3 -3
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_action.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #ifndef MLX5HWS_ACTION_H_ 5 - #define MLX5HWS_ACTION_H_ 4 + #ifndef HWS_ACTION_H_ 5 + #define HWS_ACTION_H_ 6 6 7 7 /* Max number of STEs needed for a rule (including match) */ 8 8 #define MLX5HWS_ACTION_MAX_STE 20 ··· 304 304 htonl(num_of_actions << 29); 305 305 } 306 306 307 - #endif /* MLX5HWS_ACTION_H_ */ 307 + #endif /* HWS_ACTION_H_ */
+2 -2
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_buddy.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/buddy.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 5 - #include "mlx5hws_buddy.h" 4 + #include "internal.h" 5 + #include "buddy.h" 6 6 7 7 static int hws_buddy_init(struct mlx5hws_buddy_mem *buddy, u32 max_order) 8 8 {
+3 -3
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_buddy.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/buddy.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #ifndef MLX5HWS_BUDDY_H_ 5 - #define MLX5HWS_BUDDY_H_ 4 + #ifndef HWS_BUDDY_H_ 5 + #define HWS_BUDDY_H_ 6 6 7 7 struct mlx5hws_buddy_mem { 8 8 unsigned long **bitmap; ··· 18 18 19 19 void mlx5hws_buddy_free_mem(struct mlx5hws_buddy_mem *buddy, u32 seg, u32 order); 20 20 21 - #endif /* MLX5HWS_BUDDY_H_ */ 21 + #endif /* HWS_BUDDY_H_ */
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_bwc.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 6 6 static u16 hws_bwc_gen_queue_idx(struct mlx5hws_context *ctx) 7 7 {
+3 -3
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_bwc.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #ifndef MLX5HWS_BWC_H_ 5 - #define MLX5HWS_BWC_H_ 4 + #ifndef HWS_BWC_H_ 5 + #define HWS_BWC_H_ 6 6 7 7 #define MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG 1 8 8 #define MLX5HWS_BWC_MATCHER_SIZE_LOG_STEP 1 ··· 70 70 return idx + mlx5hws_bwc_queues(ctx); 71 71 } 72 72 73 - #endif /* MLX5HWS_BWC_H_ */ 73 + #endif /* HWS_BWC_H_ */
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_bwc_complex.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 6 6 bool mlx5hws_bwc_match_params_is_complex(struct mlx5hws_context *ctx, 7 7 u8 match_criteria_enable,
+3 -3
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_bwc_complex.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc_complex.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #ifndef MLX5HWS_BWC_COMPLEX_H_ 5 - #define MLX5HWS_BWC_COMPLEX_H_ 4 + #ifndef HWS_BWC_COMPLEX_H_ 5 + #define HWS_BWC_COMPLEX_H_ 6 6 7 7 bool mlx5hws_bwc_match_params_is_complex(struct mlx5hws_context *ctx, 8 8 u8 match_criteria_enable, ··· 26 26 27 27 int mlx5hws_bwc_rule_destroy_complex(struct mlx5hws_bwc_rule *bwc_rule); 28 28 29 - #endif /* MLX5HWS_BWC_COMPLEX_H_ */ 29 + #endif /* HWS_BWC_COMPLEX_H_ */
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_cmd.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 6 6 static enum mlx5_ifc_flow_destination_type 7 7 hws_cmd_dest_type_to_ifc_dest_type(enum mlx5_flow_destination_type type)
+3 -3
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_cmd.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/cmd.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #ifndef MLX5HWS_CMD_H_ 5 - #define MLX5HWS_CMD_H_ 4 + #ifndef HWS_CMD_H_ 5 + #define HWS_CMD_H_ 6 6 7 7 #define WIRE_PORT 0xFFFF 8 8 ··· 358 358 int mlx5hws_cmd_query_gvmi(struct mlx5_core_dev *mdev, bool other_function, 359 359 u16 vport_number, u16 *gvmi); 360 360 361 - #endif /* MLX5HWS_CMD_H_ */ 361 + #endif /* HWS_CMD_H_ */
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_context.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/context.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA CORPORATION. All rights reserved. */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 6 6 bool mlx5hws_context_cap_dynamic_reparse(struct mlx5hws_context *ctx) 7 7 {
+3 -3
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_context.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/context.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #ifndef MLX5HWS_CONTEXT_H_ 5 - #define MLX5HWS_CONTEXT_H_ 4 + #ifndef HWS_CONTEXT_H_ 5 + #define HWS_CONTEXT_H_ 6 6 7 7 enum mlx5hws_context_flags { 8 8 MLX5HWS_CONTEXT_FLAG_HWS_SUPPORT = 1 << 0, ··· 62 62 63 63 u8 mlx5hws_context_get_reparse_mode(struct mlx5hws_context *ctx); 64 64 65 - #endif /* MLX5HWS_CONTEXT_H_ */ 65 + #endif /* HWS_CONTEXT_H_ */
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_debug.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c
··· 5 5 #include <linux/kernel.h> 6 6 #include <linux/seq_file.h> 7 7 #include <linux/version.h> 8 - #include "mlx5hws_internal.h" 8 + #include "internal.h" 9 9 10 10 static int 11 11 hws_debug_dump_matcher_template_definer(struct seq_file *f,
+3 -3
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_debug.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #ifndef MLX5HWS_DEBUG_H_ 5 - #define MLX5HWS_DEBUG_H_ 4 + #ifndef HWS_DEBUG_H_ 5 + #define HWS_DEBUG_H_ 6 6 7 7 #define HWS_DEBUG_FORMAT_VERSION "1.0" 8 8 ··· 37 37 void mlx5hws_debug_init_dump(struct mlx5hws_context *ctx); 38 38 void mlx5hws_debug_uninit_dump(struct mlx5hws_context *ctx); 39 39 40 - #endif /* MLX5HWS_DEBUG_H_ */ 40 + #endif /* HWS_DEBUG_H_ */
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_definer.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 6 6 /* Pattern tunnel Layer bits. */ 7 7 #define MLX5_FLOW_LAYER_VXLAN BIT(12)
+3 -3
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_definer.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #ifndef MLX5HWS_DEFINER_H_ 5 - #define MLX5HWS_DEFINER_H_ 4 + #ifndef HWS_DEFINER_H_ 5 + #define HWS_DEFINER_H_ 6 6 7 7 /* Max available selecotrs */ 8 8 #define DW_SELECTORS 9 ··· 831 831 u32 *match_param, 832 832 int *fc_sz); 833 833 834 - #endif /* MLX5HWS_DEFINER_H_ */ 834 + #endif /* HWS_DEFINER_H_ */
+18 -18
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_internal.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/internal.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #ifndef MLX5HWS_INTERNAL_H_ 5 - #define MLX5HWS_INTERNAL_H_ 4 + #ifndef HWS_INTERNAL_H_ 5 + #define HWS_INTERNAL_H_ 6 6 7 7 #include <linux/mlx5/transobj.h> 8 8 #include <linux/mlx5/vport.h> ··· 10 10 #include "wq.h" 11 11 #include "lib/mlx5.h" 12 12 13 - #include "mlx5hws_prm.h" 13 + #include "prm.h" 14 14 #include "mlx5hws.h" 15 - #include "mlx5hws_pool.h" 16 - #include "mlx5hws_vport.h" 17 - #include "mlx5hws_context.h" 18 - #include "mlx5hws_table.h" 19 - #include "mlx5hws_send.h" 20 - #include "mlx5hws_rule.h" 21 - #include "mlx5hws_cmd.h" 22 - #include "mlx5hws_action.h" 23 - #include "mlx5hws_definer.h" 24 - #include "mlx5hws_matcher.h" 25 - #include "mlx5hws_debug.h" 26 - #include "mlx5hws_pat_arg.h" 27 - #include "mlx5hws_bwc.h" 28 - #include "mlx5hws_bwc_complex.h" 15 + #include "pool.h" 16 + #include "vport.h" 17 + #include "context.h" 18 + #include "table.h" 19 + #include "send.h" 20 + #include "rule.h" 21 + #include "cmd.h" 22 + #include "action.h" 23 + #include "definer.h" 24 + #include "matcher.h" 25 + #include "debug.h" 26 + #include "pat_arg.h" 27 + #include "bwc.h" 28 + #include "bwc_complex.h" 29 29 30 30 #define W_SIZE 2 31 31 #define DW_SIZE 4 ··· 56 56 return (val + align - 1) & ~(align - 1); 57 57 } 58 58 59 - #endif /* MLX5HWS_INTERNAL_H_ */ 59 + #endif /* HWS_INTERNAL_H_ */
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_matcher.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 6 6 enum mlx5hws_matcher_rtc_type { 7 7 HWS_MATCHER_RTC_TYPE_MATCH,
+3 -3
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_matcher.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #ifndef MLX5HWS_MATCHER_H_ 5 - #define MLX5HWS_MATCHER_H_ 4 + #ifndef HWS_MATCHER_H_ 5 + #define HWS_MATCHER_H_ 6 6 7 7 /* We calculated that concatenating a collision table to the main table with 8 8 * 3% of the main table rows will be enough resources for high insertion ··· 104 104 return matcher->attr.insert_mode == MLX5HWS_MATCHER_INSERT_BY_INDEX; 105 105 } 106 106 107 - #endif /* MLX5HWS_MATCHER_H_ */ 107 + #endif /* HWS_MATCHER_H_ */
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_pat_arg.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 6 6 enum mlx5hws_arg_chunk_size 7 7 mlx5hws_arg_data_size_to_arg_log_size(u16 data_size)
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_pat_arg.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.h
+2 -2
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_pool.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 5 - #include "mlx5hws_buddy.h" 4 + #include "internal.h" 5 + #include "buddy.h" 6 6 7 7 static void hws_pool_free_one_resource(struct mlx5hws_pool_resource *resource) 8 8 {
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_pool.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.h
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_prm.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/prm.h
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_rule.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 6 6 static void hws_rule_skip(struct mlx5hws_matcher *matcher, 7 7 struct mlx5hws_match_template *mt,
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_rule.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.h
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_send.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/send.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 #include "lib/clock.h" 6 6 7 7 enum { CQ_OK = 0, CQ_EMPTY = -1, CQ_POLL_ERR = -2 };
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_send.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/send.h
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_table.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 6 6 u32 mlx5hws_table_get_id(struct mlx5hws_table *tbl) 7 7 {
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_table.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/table.h
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_vport.c drivers/net/ethernet/mellanox/mlx5/core/steering/hws/vport.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 2 /* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ 3 3 4 - #include "mlx5hws_internal.h" 4 + #include "internal.h" 5 5 6 6 int mlx5hws_vport_init_vports(struct mlx5hws_context *ctx) 7 7 {
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_vport.h drivers/net/ethernet/mellanox/mlx5/core/steering/hws/vport.h
drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h drivers/net/ethernet/mellanox/mlx5/core/steering/sws/mlx5_ifc_dr.h
drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h drivers/net/ethernet/mellanox/mlx5/core/steering/sws/mlx5_ifc_dr_ste_v1.h
drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h drivers/net/ethernet/mellanox/mlx5/core/steering/sws/mlx5dr.h