Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
octeon_ep: support to fetch firmware info
Add support to fetch firmware info such as heartbeat miss count,
heartbeat interval. This shall be used for heartbeat monitor.
Signed-off-by: Shinas Rasheed <srasheed@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
authored by
Shinas Rasheed
and committed by
David S. Miller
8d6198a1
d692873c
+77
-17
+3
-7
drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
+3
-7
drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
···
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#define CTRL_MBOX_MAX_PF 128
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#define CTRL_MBOX_SZ ((size_t)(0x400000 / CTRL_MBOX_MAX_PF))
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-
#define FW_HB_INTERVAL_IN_SECS 1
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-
#define FW_HB_MISS_COUNT 10
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-
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/* Names of Hardware non-queue generic interrupts */
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static char *cn93_non_ioq_msix_names[] = {
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"epf_ire_rint",
···
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link = PCI_DEVFN(PCI_SLOT(oct->pdev->devfn), link);
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}
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conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr +
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-
(0x400000ull * 7) +
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+
CN93_PEM_BAR4_INDEX_OFFSET +
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(link * CTRL_MBOX_SZ);
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-
conf->hb_interval = FW_HB_INTERVAL_IN_SECS;
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-
conf->max_hb_miss_cnt = FW_HB_MISS_COUNT;
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-
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+
conf->fw_info.hb_interval = OCTEP_DEFAULT_FW_HB_INTERVAL;
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+
conf->fw_info.hb_miss_count = OCTEP_DEFAULT_FW_HB_MISS_COUNT;
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}
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/* Setup registers for a hardware Tx Queue */
+17
-5
drivers/net/ethernet/marvell/octeon_ep/octep_config.h
+17
-5
drivers/net/ethernet/marvell/octeon_ep/octep_config.h
···
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/* Default MTU */
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#define OCTEP_DEFAULT_MTU 1500
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+
/* pf heartbeat interval in milliseconds */
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+
#define OCTEP_DEFAULT_FW_HB_INTERVAL 1000
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+
/* pf heartbeat miss count */
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#define OCTEP_DEFAULT_FW_HB_MISS_COUNT 20
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+
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/* Macros to get octeon config params */
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#define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
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#define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
···
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void __iomem *barmem_addr;
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};
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+
/* Info from firmware */
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+
struct octep_fw_info {
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/* interface pkind */
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u16 pkind;
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+
/* heartbeat interval in milliseconds */
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u16 hb_interval;
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+
/* heartbeat miss count */
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u16 hb_miss_count;
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};
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+
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/* Data Structure to hold configuration limits and active config */
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struct octep_config {
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/* Input Queue attributes. */
···
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/* ctrl mbox config */
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struct octep_ctrl_mbox_config ctrl_mbox_cfg;
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-
/* Configured maximum heartbeat miss count */
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u32 max_hb_miss_cnt;
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-
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-
/* Configured firmware heartbeat interval in secs */
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-
u32 hb_interval;
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+
/* fw info */
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struct octep_fw_info fw_info;
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};
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#endif /* _OCTEP_CONFIG_H_ */
+23
-1
drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.c
+23
-1
drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.c
···
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/* Control plane version in which OCTEP_CTRL_NET_H2F_CMD was added */
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static const u32 octep_ctrl_net_h2f_cmd_versions[OCTEP_CTRL_NET_H2F_CMD_MAX] = {
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-
[OCTEP_CTRL_NET_H2F_CMD_INVALID ... OCTEP_CTRL_NET_H2F_CMD_LINK_INFO] =
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+
[OCTEP_CTRL_NET_H2F_CMD_INVALID ... OCTEP_CTRL_NET_H2F_CMD_GET_INFO] =
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OCTEP_CP_VERSION(1, 0, 0)
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};
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···
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else if (msg.hdr.s.flags & OCTEP_CTRL_MBOX_MSG_HDR_FLAG_NOTIFY)
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process_mbox_notify(oct, &msg);
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}
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+
}
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+
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+
int octep_ctrl_net_get_info(struct octep_device *oct, int vfid,
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struct octep_fw_info *info)
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{
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struct octep_ctrl_net_wait_data d = {0};
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struct octep_ctrl_net_h2f_resp *resp;
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struct octep_ctrl_net_h2f_req *req;
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int err;
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+
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req = &d.data.req;
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init_send_req(&d.msg, req, 0, vfid);
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req->hdr.s.cmd = OCTEP_CTRL_NET_H2F_CMD_GET_INFO;
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req->link_info.cmd = OCTEP_CTRL_NET_CMD_GET;
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err = octep_send_mbox_req(oct, &d, true);
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if (err < 0)
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return err;
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+
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resp = &d.data.resp;
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memcpy(info, &resp->info.fw_info, sizeof(struct octep_fw_info));
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375
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return 0;
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}
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int octep_ctrl_net_uninit(struct octep_device *oct)
+18
drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.h
+18
drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_net.h
···
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OCTEP_CTRL_NET_H2F_CMD_LINK_STATUS,
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OCTEP_CTRL_NET_H2F_CMD_RX_STATE,
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OCTEP_CTRL_NET_H2F_CMD_LINK_INFO,
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OCTEP_CTRL_NET_H2F_CMD_GET_INFO,
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OCTEP_CTRL_NET_H2F_CMD_MAX
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};
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···
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u16 state;
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};
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+
/* get info request */
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struct octep_ctrl_net_h2f_resp_cmd_get_info {
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struct octep_fw_info fw_info;
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};
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+
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/* Host to fw response data */
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struct octep_ctrl_net_h2f_resp {
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union octep_ctrl_net_resp_hdr hdr;
···
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struct octep_ctrl_net_h2f_resp_cmd_state link;
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struct octep_ctrl_net_h2f_resp_cmd_state rx;
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struct octep_ctrl_net_link_info link_info;
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struct octep_ctrl_net_h2f_resp_cmd_get_info info;
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};
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} __packed;
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···
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* @param oct: non-null pointer to struct octep_device.
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*/
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void octep_ctrl_net_recv_fw_messages(struct octep_device *oct);
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+
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/** Get info from firmware.
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*
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* @param oct: non-null pointer to struct octep_device.
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* @param vfid: Index of virtual function.
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* @param info: non-null pointer to struct octep_fw_info.
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*
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* return value: 0 on success, -errno on failure.
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*/
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int octep_ctrl_net_get_info(struct octep_device *oct, int vfid,
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struct octep_fw_info *info);
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/** Uninitialize data for ctrl net.
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*
+12
-4
drivers/net/ethernet/marvell/octeon_ep/octep_main.c
+12
-4
drivers/net/ethernet/marvell/octeon_ep/octep_main.c
···
918
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int miss_cnt;
919
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miss_cnt = atomic_inc_return(&oct->hb_miss_cnt);
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-
if (miss_cnt < oct->conf->max_hb_miss_cnt) {
921
+
if (miss_cnt < oct->conf->fw_info.hb_miss_count) {
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queue_delayed_work(octep_wq, &oct->hb_task,
923
-
msecs_to_jiffies(oct->conf->hb_interval * 1000));
923
+
msecs_to_jiffies(oct->conf->fw_info.hb_interval));
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return;
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}
926
926
···
1013
1013
1014
1014
atomic_set(&oct->hb_miss_cnt, 0);
1015
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INIT_DELAYED_WORK(&oct->hb_task, octep_hb_timeout_task);
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-
queue_delayed_work(octep_wq, &oct->hb_task,
1017
-
msecs_to_jiffies(oct->conf->hb_interval * 1000));
1016
+
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1017
return 0;
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1020
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unsupported_dev:
···
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1143
dev_err(&pdev->dev, "Device setup failed\n");
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goto err_octep_config;
1144
1145
}
1146
+
1147
+
octep_ctrl_net_get_info(octep_dev, OCTEP_CTRL_NET_INVALID_VFID,
1148
+
&octep_dev->conf->fw_info);
1149
+
dev_info(&octep_dev->pdev->dev, "Heartbeat interval %u msecs Heartbeat miss count %u\n",
1150
+
octep_dev->conf->fw_info.hb_interval,
1151
+
octep_dev->conf->fw_info.hb_miss_count);
1152
+
queue_delayed_work(octep_wq, &octep_dev->hb_task,
1153
+
msecs_to_jiffies(octep_dev->conf->fw_info.hb_interval));
1154
+
1145
1155
INIT_WORK(&octep_dev->tx_timeout_task, octep_tx_timeout_task);
1146
1156
INIT_WORK(&octep_dev->ctrl_mbox_task, octep_ctrl_mbox_task);
1147
1157
INIT_DELAYED_WORK(&octep_dev->intr_poll_task, octep_intr_poll_task);
+4
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
+4
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
···
370
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/* bit 1 for firmware heartbeat interrupt */
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#define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1)
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+
#define CN93_PEM_BAR4_INDEX 7
374
+
#define CN93_PEM_BAR4_INDEX_SIZE 0x400000ULL
375
+
#define CN93_PEM_BAR4_INDEX_OFFSET (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR4_INDEX_SIZE)
376
+
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#endif /* _OCTEP_REGS_CN9K_PF_H_ */