tjh.dev / kernel
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net: dsa: microchip: lan9371/2: add 100BaseTX PHY support

On the LAN9371 and LAN9372, the 4th internal PHY is a 100BaseTX PHY
instead of a 100BaseT1 PHY. The 100BaseTX PHYs have a different base
register offset.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Acked-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Lucas Stach and committed by
David S. Miller 8d7330b3 df18948d

+6
+1
drivers/net/dsa/microchip/ksz_common.h
··· 22 22 /* all KSZ switches count ports from 1 */ 23 23 #define KSZ_PORT_1 0 24 24 #define KSZ_PORT_2 1 25 + #define KSZ_PORT_4 3 25 26 26 27 struct ksz_device; 27 28 struct ksz_port;
+4
drivers/net/dsa/microchip/lan937x_main.c
··· 55 55 u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; 56 56 u16 temp; 57 57 58 + if ((dev->info->chip_id == LAN9371_CHIP_ID || 59 + dev->info->chip_id == LAN9372_CHIP_ID) && addr == KSZ_PORT_4) 60 + addr_base = REG_PORT_TX_PHY_CTRL_BASE; 61 + 58 62 /* get register address based on the logical port */ 59 63 temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); 60 64
+1
drivers/net/dsa/microchip/lan937x_reg.h
··· 147 147 148 148 /* 1 - Phy */ 149 149 #define REG_PORT_T1_PHY_CTRL_BASE 0x0100 150 + #define REG_PORT_TX_PHY_CTRL_BASE 0x0280 150 151 151 152 /* 3 - xMII */ 152 153 #define PORT_SGMII_SEL BIT(7)