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drm/amd/display: add pstate schedule admissibility flags and frame-time utility

[Why]
Core needs to track pstate schedule admissibility for different global
change scenarios (fclk, temp read, PPT) and requires a reusable way to compute
per-stream frame time from timing parameters.

[How]
Extend dml2_core_internal_mode_support_info with:
fclk_pstate_schedule_admissible
temp_read_pstate_schedule_admissible
ppt_pstate_schedule_admissible
Add dummy_double_array[3][DML2_MAX_PLANES] to
dml2_core_calcs_mode_support_locals.
Introduce dml2_core_utils_get_frame_time_us() in dml2_core_utils.c and export
it in dml2_core_utils.h to compute frame time in microseconds from stream
timing (vline time * (vactive + vblank)).

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Wenjing Liu and committed by
Alex Deucher 8d7d0fd7 dd2308c1

+14
+5
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h
··· 269 269 bool global_dram_clock_change_supported; 270 270 bool global_fclk_change_supported; 271 271 bool global_temp_read_or_ppt_supported; 272 + bool fclk_pstate_schedule_admissible; 273 + bool temp_read_pstate_schedule_admissible; 274 + bool ppt_pstate_schedule_admissible; 272 275 bool USRRetrainingSupport; 273 276 bool AvgBandwidthSupport; 274 277 bool UrgVactiveBandwidthSupport; ··· 1066 1063 bool dummy_boolean_array[2][DML2_MAX_PLANES]; 1067 1064 double dummy_single[3]; 1068 1065 double dummy_single_array[DML2_MAX_PLANES]; 1066 + double dummy_double_array[3][DML2_MAX_PLANES]; 1067 + enum dml2_pstate_method dummy_pstate_method_array[DML2_MAX_PLANES]; 1069 1068 struct dml2_core_internal_watermarks dummy_watermark; 1070 1069 double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1071 1070 double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
+8
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
··· 786 786 return false; 787 787 } 788 788 } 789 + 790 + double dml2_core_utils_get_frame_time_us(const struct dml2_stream_parameters *stream) 791 + { 792 + double otg_vline_time_us = (double)stream->timing.h_total / (double)stream->timing.pixel_clock_khz * 1000.0; 793 + double non_vtotal = stream->timing.vblank_nom + stream->timing.v_active; 794 + double frame_time_us = non_vtotal * otg_vline_time_us; 795 + return frame_time_us; 796 + }
+1
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h
··· 39 39 bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate); 40 40 bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate); 41 41 bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode); 42 + double dml2_core_utils_get_frame_time_us(const struct dml2_stream_parameters *stream); 42 43 43 44 #endif /* __DML2_CORE_UTILS_H__ */