Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge ACPICA material for 6.20 to satisfy dependencies
+492
-36
+3
drivers/acpi/acpica/acpredef.h
+3
drivers/acpi/acpica/acpredef.h
···
587
587
METHOD_RETURNS(ACPI_RTYPE_PACKAGE)}}, /* Variable-length (Pkgs) each (var Ints) */
588
588
PACKAGE_INFO(ACPI_PTYPE2_MIN, ACPI_RTYPE_INTEGER, 5, 0, 0, 0),
589
589
590
+
{{"_VDM", METHOD_0ARGS,
591
+
METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
592
+
590
593
{{"_HRV", METHOD_0ARGS,
591
594
METHOD_RETURNS(ACPI_RTYPE_INTEGER)}},
592
595
+3
-1
drivers/acpi/acpica/evregion.c
+3
-1
drivers/acpi/acpica/evregion.c
···
163
163
return_ACPI_STATUS(AE_NOT_EXIST);
164
164
}
165
165
166
-
if (region_obj->region.space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
166
+
if (field_obj
167
+
&& region_obj->region.space_id ==
168
+
ACPI_ADR_SPACE_PLATFORM_COMM) {
167
169
struct acpi_pcc_info *ctx =
168
170
handler_desc->address_space.context;
169
171
+24
-27
drivers/acpi/acpica/exoparg3.c
+24
-27
drivers/acpi/acpica/exoparg3.c
···
10
10
#include <acpi/acpi.h>
11
11
#include "accommon.h"
12
12
#include "acinterp.h"
13
+
#include <acpi/acoutput.h>
13
14
#include "acparser.h"
14
15
#include "amlcode.h"
15
16
···
52
51
acpi_status acpi_ex_opcode_3A_0T_0R(struct acpi_walk_state *walk_state)
53
52
{
54
53
union acpi_operand_object **operand = &walk_state->operands[0];
55
-
struct acpi_signal_fatal_info *fatal;
56
-
acpi_status status = AE_OK;
54
+
struct acpi_signal_fatal_info fatal;
57
55
58
56
ACPI_FUNCTION_TRACE_STR(ex_opcode_3A_0T_0R,
59
57
acpi_ps_get_opcode_name(walk_state->opcode));
···
60
60
switch (walk_state->opcode) {
61
61
case AML_FATAL_OP: /* Fatal (fatal_type fatal_code fatal_arg) */
62
62
63
-
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
64
-
"FatalOp: Type %X Code %X Arg %X "
65
-
"<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n",
66
-
(u32)operand[0]->integer.value,
67
-
(u32)operand[1]->integer.value,
68
-
(u32)operand[2]->integer.value));
63
+
fatal.type = (u32)operand[0]->integer.value;
64
+
fatal.code = (u32)operand[1]->integer.value;
65
+
fatal.argument = (u32)operand[2]->integer.value;
69
66
70
-
fatal = ACPI_ALLOCATE(sizeof(struct acpi_signal_fatal_info));
71
-
if (fatal) {
72
-
fatal->type = (u32) operand[0]->integer.value;
73
-
fatal->code = (u32) operand[1]->integer.value;
74
-
fatal->argument = (u32) operand[2]->integer.value;
75
-
}
67
+
ACPI_BIOS_ERROR((AE_INFO,
68
+
"Fatal ACPI BIOS error (Type 0x%X Code 0x%X Arg 0x%X)\n",
69
+
fatal.type, fatal.code, fatal.argument));
76
70
77
71
/* Always signal the OS! */
78
72
79
-
status = acpi_os_signal(ACPI_SIGNAL_FATAL, fatal);
73
+
acpi_os_signal(ACPI_SIGNAL_FATAL, &fatal);
80
74
81
-
/* Might return while OS is shutting down, just continue */
82
-
83
-
ACPI_FREE(fatal);
84
-
goto cleanup;
75
+
#ifndef ACPI_CONTINUE_ON_FATAL
76
+
/*
77
+
* Might return while OS is shutting down, so abort the AML execution
78
+
* by returning an error.
79
+
*/
80
+
return_ACPI_STATUS(AE_ERROR);
81
+
#else
82
+
/*
83
+
* The alstests require that the Fatal() opcode does not return an error.
84
+
*/
85
+
return_ACPI_STATUS(AE_OK);
86
+
#endif
85
87
86
88
case AML_EXTERNAL_OP:
87
89
/*
···
95
93
* wrong if an external opcode ever gets here.
96
94
*/
97
95
ACPI_ERROR((AE_INFO, "Executed External Op"));
98
-
status = AE_OK;
99
-
goto cleanup;
96
+
97
+
return_ACPI_STATUS(AE_OK);
100
98
101
99
default:
102
100
103
101
ACPI_ERROR((AE_INFO, "Unknown AML opcode 0x%X",
104
102
walk_state->opcode));
105
103
106
-
status = AE_AML_BAD_OPCODE;
107
-
goto cleanup;
104
+
return_ACPI_STATUS(AE_AML_BAD_OPCODE);
108
105
}
109
-
110
-
cleanup:
111
-
112
-
return_ACPI_STATUS(status);
113
106
}
114
107
115
108
/*******************************************************************************
+1
-1
drivers/acpi/acpica/nsxfname.c
+1
-1
drivers/acpi/acpica/nsxfname.c
+1
-1
drivers/acpi/acpica/utobject.c
+1
-1
drivers/acpi/acpica/utobject.c
+5
-1
drivers/acpi/acpica/utosi.c
+5
-1
drivers/acpi/acpica/utosi.c
···
92
92
{"Processor Device", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
93
93
{"3.0 Thermal Model", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
94
94
{"3.0 _SCP Extensions", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
95
-
{"Processor Aggregator Device", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0}
95
+
{"Processor Aggregator Device", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0},
96
+
97
+
/* See https://learn.microsoft.com/en-us/windows-hardware/drivers/display/automatic-display-switch */
98
+
99
+
{"DisplayMux", NULL, ACPI_OSI_OPTIONAL_FEATURE, 0}
96
100
};
97
101
98
102
/*******************************************************************************
+1
-1
include/acpi/acpixf.h
+1
-1
include/acpi/acpixf.h
+257
include/acpi/actbl1.h
+257
include/acpi/actbl1.h
···
37
37
#define ACPI_SIG_DBGP "DBGP" /* Debug Port table */
38
38
#define ACPI_SIG_DMAR "DMAR" /* DMA Remapping table */
39
39
#define ACPI_SIG_DRTM "DRTM" /* Dynamic Root of Trust for Measurement table */
40
+
#define ACPI_SIG_DTPR "DTPR" /* DMA TXT Protection Ranges table */
40
41
#define ACPI_SIG_ECDT "ECDT" /* Embedded Controller Boot Resources Table */
41
42
#define ACPI_SIG_EINJ "EINJ" /* Error Injection table */
42
43
#define ACPI_SIG_ERST "ERST" /* Error Record Serialization Table */
···
998
997
struct acpi_drtm_dps_id {
999
998
u32 dps_id_length;
1000
999
u8 dps_id[16];
1000
+
};
1001
+
1002
+
/*******************************************************************************
1003
+
*
1004
+
* DTPR - DMA TXT Protection Ranges Table
1005
+
* Version 1
1006
+
*
1007
+
* Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA Protection
1008
+
* Ranges",
1009
+
* Revision 0.73, August 2021
1010
+
*
1011
+
******************************************************************************/
1012
+
1013
+
struct acpi_table_dtpr {
1014
+
struct acpi_table_header header;
1015
+
u32 flags; /* 36 */
1016
+
u32 ins_cnt;
1017
+
};
1018
+
1019
+
struct acpi_tpr_array {
1020
+
u64 base;
1021
+
};
1022
+
1023
+
struct acpi_tpr_instance {
1024
+
u32 flags;
1025
+
u32 tpr_cnt;
1026
+
};
1027
+
1028
+
struct acpi_tpr_aux_sr {
1029
+
u32 srl_cnt;
1030
+
};
1031
+
1032
+
/*
1033
+
* TPRn_BASE (ACPI_TPRN_BASE_REG)
1034
+
*
1035
+
* Specifies the start address of TPRn region. TPR region address and size must
1036
+
* be with 1MB resolution. These bits are compared with the result of the
1037
+
* TPRn_LIMIT[63:20], which is applied to the incoming address, to
1038
+
* determine if an access fall within the TPRn defined region.
1039
+
*
1040
+
* Minimal TPRn_Base resolution is 1MB. Applied to the incoming address, to
1041
+
* determine if an access fall within the TPRn defined region. Width is
1042
+
* determined by a bus width which can be obtained via CPUID
1043
+
* function 0x80000008.
1044
+
*/
1045
+
1046
+
typedef u64 ACPI_TPRN_BASE_REG;
1047
+
1048
+
/* TPRn_BASE Register Bit Masks */
1049
+
1050
+
/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */
1051
+
#define ACPI_TPRN_BASE_RW_SHIFT 3
1052
+
1053
+
#define ACPI_TPRN_BASE_RW_MASK ((u64) 1 << ACPI_TPRN_BASE_RW_SHIFT)
1054
+
1055
+
/*
1056
+
* Bit 4 - Enable: 0 – TPRn address range enabled;
1057
+
* 1 – TPRn address range disabled.
1058
+
*/
1059
+
#define ACPI_TPRN_BASE_ENABLE_SHIFT 4
1060
+
1061
+
#define ACPI_TPRN_BASE_ENABLE_MASK ((u64) 1 << ACPI_TPRN_BASE_ENABLE_SHIFT)
1062
+
1063
+
/* Bits 63:20 - tpr_base_rw */
1064
+
#define ACPI_TPRN_BASE_ADDR_SHIFT 20
1065
+
1066
+
#define ACPI_TPRN_BASE_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \
1067
+
ACPI_TPRN_BASE_ADDR_SHIFT)
1068
+
1069
+
/* TPRn_BASE Register Bit Handlers*/
1070
+
1071
+
/*
1072
+
* GET_TPRN_BASE_RW:
1073
+
*
1074
+
* Read RW bit from TPRn Base register - bit 3.
1075
+
*
1076
+
* Input:
1077
+
* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
1078
+
*
1079
+
* Output:
1080
+
*
1081
+
* Returns RW bit value (u64).
1082
+
*/
1083
+
#define GET_TPRN_BASE_RW(reg) (((u64) reg & ACPI_TPRN_BASE_RW_MASK) >> \
1084
+
ACPI_TPRN_BASE_RW_SHIFT)
1085
+
1086
+
/*
1087
+
* GET_TPRN_BASE_ENABLE:
1088
+
*
1089
+
* Read Enable bit from TPRn Base register - bit 4.
1090
+
*
1091
+
* Input:
1092
+
* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
1093
+
*
1094
+
* Output:
1095
+
*
1096
+
* Returns Enable bit value (u64).
1097
+
*/
1098
+
#define GET_TPRN_BASE_ENABLE(reg) (((u64) reg & ACPI_TPRN_BASE_ENABLE_MASK) \
1099
+
>> ACPI_TPRN_BASE_ENABLE_SHIFT)
1100
+
1101
+
/*
1102
+
* GET_TPRN_BASE_ADDR:
1103
+
*
1104
+
* Read TPRn Base Register address from bits 63:20.
1105
+
*
1106
+
* Input:
1107
+
* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
1108
+
*
1109
+
* Output:
1110
+
*
1111
+
* Returns TPRn Base Register address (u64).
1112
+
*/
1113
+
#define GET_TPRN_BASE_ADDR(reg) (((u64) reg & ACPI_TPRN_BASE_ADDR_MASK) \
1114
+
>> ACPI_TPRN_BASE_ADDR_SHIFT)
1115
+
1116
+
/*
1117
+
* SET_TPRN_BASE_RW:
1118
+
*
1119
+
* Set RW bit in TPRn Base register - bit 3.
1120
+
*
1121
+
* Input:
1122
+
* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
1123
+
* - val (represents RW value to be set (u64))
1124
+
*/
1125
+
#define SET_TPRN_BASE_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
1126
+
ACPI_TPRN_BASE_RW_SHIFT, \
1127
+
ACPI_TPRN_BASE_RW_MASK, val);
1128
+
1129
+
/*
1130
+
* SET_TPRN_BASE_ENABLE:
1131
+
*
1132
+
* Set Enable bit in TPRn Base register - bit 4.
1133
+
*
1134
+
* Input:
1135
+
* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
1136
+
* - val (represents Enable value to be set (u64))
1137
+
*/
1138
+
#define SET_TPRN_BASE_ENABLE(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
1139
+
ACPI_TPRN_BASE_ENABLE_SHIFT, \
1140
+
ACPI_TPRN_BASE_ENABLE_MASK, val);
1141
+
1142
+
/*
1143
+
* SET_TPRN_BASE_ADDR:
1144
+
*
1145
+
* Set TPRn Base Register address - bits 63:20
1146
+
*
1147
+
* Input
1148
+
* - reg (represents TPRn Base Register (ACPI_TPRN_BASE_REG))
1149
+
* - val (represents address value to be set (u64))
1150
+
*/
1151
+
#define SET_TPRN_BASE_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
1152
+
ACPI_TPRN_BASE_ADDR_SHIFT, \
1153
+
ACPI_TPRN_BASE_ADDR_MASK, val);
1154
+
1155
+
/*
1156
+
* TPRn_LIMIT
1157
+
*
1158
+
* This register defines an isolated region of memory that can be enabled
1159
+
* to prohibit certain system agents from accessing memory. When an agent
1160
+
* sends a request upstream, whether snooped or not, a TPR prevents that
1161
+
* transaction from changing the state of memory.
1162
+
*
1163
+
* Minimal TPRn_Limit resolution is 1MB. Width is determined by a bus width.
1164
+
*/
1165
+
1166
+
typedef u64 ACPI_TPRN_LIMIT_REG;
1167
+
1168
+
/* TPRn_LIMIT Register Bit Masks */
1169
+
1170
+
/* Bit 3 - RW: access: 1 == RO, 0 == RW register (for TPR must be RW) */
1171
+
#define ACPI_TPRN_LIMIT_RW_SHIFT 3
1172
+
1173
+
#define ACPI_TPRN_LIMIT_RW_MASK ((u64) 1 << ACPI_TPRN_LIMIT_RW_SHIFT)
1174
+
1175
+
/* Bits 63:20 - tpr_limit_rw */
1176
+
#define ACPI_TPRN_LIMIT_ADDR_SHIFT 20
1177
+
1178
+
#define ACPI_TPRN_LIMIT_ADDR_MASK ((u64) 0xFFFFFFFFFFF << \
1179
+
ACPI_TPRN_LIMIT_ADDR_SHIFT)
1180
+
1181
+
/* TPRn_LIMIT Register Bit Handlers*/
1182
+
1183
+
/*
1184
+
* GET_TPRN_LIMIT_RW:
1185
+
*
1186
+
* Read RW bit from TPRn Limit register - bit 3.
1187
+
*
1188
+
* Input:
1189
+
* - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
1190
+
*
1191
+
* Output:
1192
+
*
1193
+
* Returns RW bit value (u64).
1194
+
*/
1195
+
#define GET_TPRN_LIMIT_RW(reg) (((u64) reg & ACPI_TPRN_LIMIT_RW_MASK) \
1196
+
>> ACPI_TPRN_LIMIT_RW_SHIFT)
1197
+
1198
+
/*
1199
+
* GET_TPRN_LIMIT_ADDR:
1200
+
*
1201
+
* Read TPRn Limit Register address from bits 63:20.
1202
+
*
1203
+
* Input:
1204
+
* - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
1205
+
*
1206
+
* Output:
1207
+
*
1208
+
* Returns TPRn Limit Register address (u64).
1209
+
*/
1210
+
#define GET_TPRN_LIMIT_ADDR(reg) (((u64) reg & ACPI_TPRN_LIMIT_ADDR_MASK) \
1211
+
>> ACPI_TPRN_LIMIT_ADDR_SHIFT)
1212
+
1213
+
/*
1214
+
* SET_TPRN_LIMIT_RW:
1215
+
*
1216
+
* Set RW bit in TPRn Limit register - bit 3.
1217
+
*
1218
+
* Input:
1219
+
* - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
1220
+
* - val (represents RW value to be set (u64))
1221
+
*/
1222
+
#define SET_TPRN_LIMIT_RW(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
1223
+
ACPI_TPRN_LIMIT_RW_SHIFT, \
1224
+
ACPI_TPRN_LIMIT_RW_MASK, val);
1225
+
1226
+
/*
1227
+
* SET_TPRN_LIMIT_ADDR:
1228
+
*
1229
+
* Set TPRn Limit Register address - bits 63:20.
1230
+
*
1231
+
* Input:
1232
+
* - reg (represents TPRn Limit Register (ACPI_TPRN_LIMIT_REG))
1233
+
* - val (represents address value to be set (u64))
1234
+
*/
1235
+
#define SET_TPRN_LIMIT_ADDR(reg, val) ACPI_REGISTER_INSERT_VALUE(reg, \
1236
+
ACPI_TPRN_LIMIT_ADDR_SHIFT, \
1237
+
ACPI_TPRN_LIMIT_ADDR_MASK, val);
1238
+
1239
+
/*
1240
+
* SERIALIZE_REQUEST
1241
+
*
1242
+
* This register is used to request serialization of non-coherent DMA
1243
+
* transactions. OS shall issue it before changing of TPR settings
1244
+
* (base / size).
1245
+
*/
1246
+
1247
+
struct acpi_tpr_serialize_request {
1248
+
u64 sr_register;
1249
+
/*
1250
+
* BIT 1 - Status of serialization request (RO)
1251
+
* 0 == register idle, 1 == serialization in progress
1252
+
* BIT 2 - Control field to initiate serialization (RW)
1253
+
* 0 == normal, 1 == initialize serialization
1254
+
* (self-clear to allow multiple serialization requests)
1255
+
*/
1001
1256
};
1002
1257
1003
1258
/*******************************************************************************
+190
-4
include/acpi/actbl2.h
+190
-4
include/acpi/actbl2.h
···
31
31
#define ACPI_SIG_CDAT "CDAT" /* Coherent Device Attribute Table */
32
32
#define ACPI_SIG_ERDT "ERDT" /* Enhanced Resource Director Technology */
33
33
#define ACPI_SIG_IORT "IORT" /* IO Remapping Table */
34
+
#define ACPI_SIG_IOVT "IOVT" /* I/O Virtualization Table */
34
35
#define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */
36
+
#define ACPI_SIG_KEYP "KEYP" /* Key Programming Interface for IDE */
35
37
#define ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */
36
38
#define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */
37
39
#define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */
···
682
680
ACPI_IORT_NODE_SMMU_V3 = 0x04,
683
681
ACPI_IORT_NODE_PMCG = 0x05,
684
682
ACPI_IORT_NODE_RMR = 0x06,
683
+
ACPI_IORT_NODE_IWB = 0x07,
685
684
};
686
685
687
686
struct acpi_iort_id_mapping {
···
859
856
u64 base_address;
860
857
u64 length;
861
858
u32 reserved;
859
+
};
860
+
861
+
struct acpi_iort_iwb {
862
+
u64 base_address;
863
+
u16 iwb_index; /* Unique IWB identifier matching with the IWB GSI namespace. */
864
+
char device_name[]; /* Path of the IWB namespace object */
865
+
};
866
+
867
+
/*******************************************************************************
868
+
*
869
+
* IOVT - I/O Virtualization Table
870
+
*
871
+
* Conforms to "LoongArch I/O Virtualization Table",
872
+
* Version 0.1, October 2024
873
+
*
874
+
******************************************************************************/
875
+
876
+
struct acpi_table_iovt {
877
+
struct acpi_table_header header; /* Common ACPI table header */
878
+
u16 iommu_count;
879
+
u16 iommu_offset;
880
+
u8 reserved[8];
881
+
};
882
+
883
+
/* IOVT subtable header */
884
+
885
+
struct acpi_iovt_header {
886
+
u16 type;
887
+
u16 length;
888
+
};
889
+
890
+
/* Values for Type field above */
891
+
892
+
enum acpi_iovt_iommu_type {
893
+
ACPI_IOVT_IOMMU_V1 = 0x00,
894
+
ACPI_IOVT_IOMMU_RESERVED = 0x01 /* 1 and greater are reserved */
895
+
};
896
+
897
+
/* IOVT subtables */
898
+
899
+
struct acpi_iovt_iommu {
900
+
struct acpi_iovt_header header;
901
+
u32 flags;
902
+
u16 segment;
903
+
u16 phy_width; /* Physical Address Width */
904
+
u16 virt_width; /* Virtual Address Width */
905
+
u16 max_page_level;
906
+
u64 page_size;
907
+
u32 device_id;
908
+
u64 base_address;
909
+
u32 address_space_size;
910
+
u8 interrupt_type;
911
+
u8 reserved[3];
912
+
u32 gsi_number;
913
+
u32 proximity_domain;
914
+
u32 max_device_num;
915
+
u32 device_entry_num;
916
+
u32 device_entry_offset;
917
+
};
918
+
919
+
struct acpi_iovt_device_entry {
920
+
u8 type;
921
+
u8 length;
922
+
u8 flags;
923
+
u8 reserved[3];
924
+
u16 device_id;
925
+
};
926
+
927
+
enum acpi_iovt_device_entry_type {
928
+
ACPI_IOVT_DEVICE_ENTRY_SINGLE = 0x00,
929
+
ACPI_IOVT_DEVICE_ENTRY_START = 0x01,
930
+
ACPI_IOVT_DEVICE_ENTRY_END = 0x02,
931
+
ACPI_IOVT_DEVICE_ENTRY_RESERVED = 0x03 /* 3 and greater are reserved */
862
932
};
863
933
864
934
/*******************************************************************************
···
1143
1067
1144
1068
/*******************************************************************************
1145
1069
*
1070
+
* KEYP - Key Programming Interface for Root Complex Integrity and Data
1071
+
* Encryption (IDE)
1072
+
* Version 1
1073
+
*
1074
+
* Conforms to "Key Programming Interface for Root Complex Integrity and Data
1075
+
* Encryption (IDE)" document. See under ACPI-Related Documents.
1076
+
*
1077
+
******************************************************************************/
1078
+
struct acpi_table_keyp {
1079
+
struct acpi_table_header header; /* Common ACPI table header */
1080
+
u32 reserved;
1081
+
};
1082
+
1083
+
/* KEYP common subtable header */
1084
+
1085
+
struct acpi_keyp_common_header {
1086
+
u8 type;
1087
+
u8 reserved;
1088
+
u16 length;
1089
+
};
1090
+
1091
+
/* Values for Type field above */
1092
+
1093
+
enum acpi_keyp_type {
1094
+
ACPI_KEYP_TYPE_CONFIG_UNIT = 0,
1095
+
};
1096
+
1097
+
/* Root Port Information Structure */
1098
+
1099
+
struct acpi_keyp_rp_info {
1100
+
u16 segment;
1101
+
u8 bus;
1102
+
u8 devfn;
1103
+
};
1104
+
1105
+
/* Key Configuration Unit Structure */
1106
+
1107
+
struct acpi_keyp_config_unit {
1108
+
struct acpi_keyp_common_header header;
1109
+
u8 protocol_type;
1110
+
u8 version;
1111
+
u8 root_port_count;
1112
+
u8 flags;
1113
+
u64 register_base_address;
1114
+
struct acpi_keyp_rp_info rp_info[];
1115
+
};
1116
+
1117
+
enum acpi_keyp_protocol_type {
1118
+
ACPI_KEYP_PROTO_TYPE_INVALID = 0,
1119
+
ACPI_KEYP_PROTO_TYPE_PCIE,
1120
+
ACPI_KEYP_PROTO_TYPE_CXL,
1121
+
ACPI_KEYP_PROTO_TYPE_RESERVED
1122
+
};
1123
+
1124
+
#define ACPI_KEYP_F_TVM_USABLE (1)
1125
+
1126
+
/*******************************************************************************
1127
+
*
1146
1128
* LPIT - Low Power Idle Table
1147
1129
*
1148
1130
* Conforms to "ACPI Low Power Idle Table (LPIT)" July 2014.
···
1301
1167
ACPI_MADT_TYPE_IMSIC = 25,
1302
1168
ACPI_MADT_TYPE_APLIC = 26,
1303
1169
ACPI_MADT_TYPE_PLIC = 27,
1304
-
ACPI_MADT_TYPE_RESERVED = 28, /* 28 to 0x7F are reserved */
1170
+
ACPI_MADT_TYPE_GICV5_IRS = 28,
1171
+
ACPI_MADT_TYPE_GICV5_ITS = 29,
1172
+
ACPI_MADT_TYPE_GICV5_ITS_TRANSLATE = 30,
1173
+
ACPI_MADT_TYPE_RESERVED = 31, /* 31 to 0x7F are reserved */
1305
1174
ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */
1306
1175
};
1307
1176
···
1426
1289
u8 reserved[3]; /* reserved - must be zero */
1427
1290
};
1428
1291
1429
-
/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 + ACPI 6.5 changes) */
1292
+
/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 + ACPI 6.5 + ACPI 6.7 changes) */
1430
1293
1431
1294
struct acpi_madt_generic_interrupt {
1432
1295
struct acpi_subtable_header header;
···
1447
1310
u8 reserved2[1];
1448
1311
u16 spe_interrupt; /* ACPI 6.3 */
1449
1312
u16 trbe_interrupt; /* ACPI 6.5 */
1313
+
u16 iaffid; /* ACPI 6.7 */
1314
+
u32 irs_id;
1450
1315
};
1451
1316
1452
1317
/* Masks for Flags field above */
···
1471
1332
u8 reserved2[3]; /* reserved - must be zero */
1472
1333
};
1473
1334
1474
-
/* Values for Version field above */
1335
+
/* Values for Version field above and Version field in acpi_madt_gicv5_irs */
1475
1336
1476
1337
enum acpi_madt_gic_version {
1477
1338
ACPI_MADT_GIC_VERSION_NONE = 0,
···
1479
1340
ACPI_MADT_GIC_VERSION_V2 = 2,
1480
1341
ACPI_MADT_GIC_VERSION_V3 = 3,
1481
1342
ACPI_MADT_GIC_VERSION_V4 = 4,
1482
-
ACPI_MADT_GIC_VERSION_RESERVED = 5 /* 5 and greater are reserved */
1343
+
ACPI_MADT_GIC_VERSION_V5 = 5,
1344
+
ACPI_MADT_GIC_VERSION_RESERVED = 6 /* 6 and greater are reserved */
1483
1345
};
1484
1346
1485
1347
/* 13: Generic MSI Frame (ACPI 5.1) */
···
1749
1609
u32 size;
1750
1610
u64 base_addr;
1751
1611
u32 gsi_base;
1612
+
};
1613
+
1614
+
/* 28: Arm GICv5 IRS (ACPI 6.7) */
1615
+
struct acpi_madt_gicv5_irs {
1616
+
struct acpi_subtable_header header;
1617
+
u8 version;
1618
+
u8 reserved;
1619
+
u32 irs_id;
1620
+
u32 flags;
1621
+
u32 reserved2;
1622
+
u64 config_base_address;
1623
+
u64 setlpi_base_address;
1624
+
};
1625
+
1626
+
#define ACPI_MADT_IRS_NON_COHERENT (1)
1627
+
1628
+
/* 29: Arm GICv5 ITS Config Frame (ACPI 6.7) */
1629
+
struct acpi_madt_gicv5_translator {
1630
+
struct acpi_subtable_header header;
1631
+
u8 flags;
1632
+
u8 reserved; /* reserved - must be zero */
1633
+
u32 translator_id;
1634
+
u64 base_address;
1635
+
};
1636
+
1637
+
#define ACPI_MADT_GICV5_ITS_NON_COHERENT (1)
1638
+
1639
+
/* 30: Arm GICv5 ITS Translate Frame (ACPI 6.7) */
1640
+
struct acpi_madt_gicv5_translate_frame {
1641
+
struct acpi_subtable_header header;
1642
+
u16 reserved; /* reserved - must be zero */
1643
+
u32 linked_translator_id;
1644
+
u32 translate_frame_id;
1645
+
u32 reserved2;
1646
+
u64 base_address;
1752
1647
};
1753
1648
1754
1649
/* 80: OEM data */
···
3001
2826
/* 1: Cache Type Structure for PPTT version 3 */
3002
2827
3003
2828
struct acpi_pptt_cache_v1 {
2829
+
struct acpi_subtable_header header;
2830
+
u16 reserved;
2831
+
u32 flags;
2832
+
u32 next_level_of_cache;
2833
+
u32 size;
2834
+
u32 number_of_sets;
2835
+
u8 associativity;
2836
+
u8 attributes;
2837
+
u16 line_size;
3004
2838
u32 cache_id;
3005
2839
};
3006
2840
···
3249
3065
u32 flags;
3250
3066
u32 scrub_params_out;
3251
3067
u32 scrub_params_in;
3068
+
u32 ext_scrub_params;
3069
+
u8 scrub_rate_desc[256];
3252
3070
};
3253
3071
3254
3072
/* Masks for Flags field above */
+1
include/acpi/actbl3.h
+1
include/acpi/actbl3.h
···
238
238
#define ACPI_SRAT_MEM_ENABLED (1) /* 00: Use affinity structure */
239
239
#define ACPI_SRAT_MEM_HOT_PLUGGABLE (1<<1) /* 01: Memory region is hot pluggable */
240
240
#define ACPI_SRAT_MEM_NON_VOLATILE (1<<2) /* 02: Memory region is non-volatile */
241
+
#define ACPI_SRAT_MEM_SPEC_PURPOSE (1<<3) /* 03: Memory is intended for specific-purpose usage */
241
242
242
243
/* 2: Processor Local X2_APIC Affinity (ACPI 4.0) */
243
244
+6
include/acpi/acuuid.h
+6
include/acpi/acuuid.h
···
37
37
#define UUID_DEVICE_LABELING "e5c937d0-3553-4d7a-9117-ea4d19c3434d"
38
38
#define UUID_PHYSICAL_PRESENCE "3dddfaa6-361b-4eb4-a424-8d10089d1653"
39
39
40
+
/* TPM */
41
+
#define UUID_HARDWARE_INFORMATION "cf8e16a5-c1e8-4e25-b712-4f54a96702c8"
42
+
#define UUID_START_METHOD "6bbf6cab-5463-4714-b7cd-f0203c0368d4"
43
+
#define UUID_MEMORY_CLEAR "376054ed-cc13-4675-901c-4756d7f2d45d"
44
+
40
45
/* NVDIMM - NFIT table */
41
46
42
47
#define UUID_NFIT_DIMM "4309ac30-0d11-11e4-9191-0800200c9a66"
···
76
71
#define UUID_USB4_CAPABILITIES "23a0d13a-26ab-486c-9c5f-0ffa525a575a"
77
72
#define UUID_1ST_FUNCTION_ID "893f00a6-660c-494e-bcfd-3043f4fb67c0"
78
73
#define UUID_2ND_FUNCTION_ID "107ededd-d381-4fd7-8da9-08e9a6c79644"
74
+
#define UUID_FAN_TRIP_POINTS "a7611840-99fe-41ae-a488-35c75926c8eb"
79
75
#endif /* __ACUUID_H__ */