Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm/tegra/for-5.20-rc1' of https://gitlab.freedesktop.org/drm/tegra into drm-next
drm/tegra: Changes for v5.20-rc1
The bulk of these changes adds support for context isolation for the
various supported host1x engines, as well as support for the hardware
found on the new Tegra234 SoC generation.
There's also a couple of fixes and cleanups. To round things off, the
device tree bindings are converted to the new json-schema format that
allows DTBs to be validated.
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Thierry Reding <thierry.reding@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220708181136.673789-1-thierry.reding@gmail.com
+3815
-1579
-41
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
-41
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
···
1
-
NVIDIA Tegra MIPI pad calibration controller
2
-
3
-
Required properties:
4
-
- compatible: "nvidia,tegra<chip>-mipi"
5
-
- reg: Physical base address and length of the controller's registers.
6
-
- clocks: Must contain an entry for each entry in clock-names.
7
-
See ../clocks/clock-bindings.txt for details.
8
-
- clock-names: Must include the following entries:
9
-
- mipi-cal
10
-
- #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads
11
-
that need to be calibrated for a given device.
12
-
13
-
User nodes need to contain an nvidia,mipi-calibrate property that has a
14
-
phandle to refer to the calibration controller node and a bitmask of the pads
15
-
that need to be calibrated.
16
-
17
-
Example:
18
-
19
-
mipi: mipi@700e3000 {
20
-
compatible = "nvidia,tegra114-mipi";
21
-
reg = <0x700e3000 0x100>;
22
-
clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
23
-
clock-names = "mipi-cal";
24
-
#nvidia,mipi-calibrate-cells = <1>;
25
-
};
26
-
27
-
...
28
-
29
-
host1x@50000000 {
30
-
...
31
-
32
-
dsi@54300000 {
33
-
...
34
-
35
-
nvidia,mipi-calibrate = <&mipi 0x060>;
36
-
37
-
...
38
-
};
39
-
40
-
...
41
-
};
+74
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
+74
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra MIPI pad calibration controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^mipi@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra114-mipi
20
+
- nvidia,tegra210-mipi
21
+
- nvidia,tegra186-mipi
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: module clock
29
+
30
+
clock-names:
31
+
items:
32
+
- const: mipi-cal
33
+
34
+
power-domains:
35
+
maxItems: 1
36
+
37
+
"#nvidia,mipi-calibrate-cells":
38
+
description: The number of cells in a MIPI calibration specifier.
39
+
Should be 1. The single cell specifies a bitmask of the pads that
40
+
need to be calibrated for a given device.
41
+
$ref: "/schemas/types.yaml#/definitions/uint32"
42
+
const: 1
43
+
44
+
additionalProperties: false
45
+
46
+
required:
47
+
- compatible
48
+
- reg
49
+
- clocks
50
+
- "#nvidia,mipi-calibrate-cells"
51
+
52
+
examples:
53
+
- |
54
+
#include <dt-bindings/clock/tegra114-car.h>
55
+
56
+
mipi@700e3000 {
57
+
compatible = "nvidia,tegra114-mipi";
58
+
reg = <0x700e3000 0x100>;
59
+
clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
60
+
clock-names = "mipi-cal";
61
+
#nvidia,mipi-calibrate-cells = <1>;
62
+
};
63
+
64
+
dsia: dsi@54300000 {
65
+
compatible = "nvidia,tegra114-dsi";
66
+
reg = <0x54300000 0x00040000>;
67
+
clocks = <&tegra_car TEGRA114_CLK_DSIA>,
68
+
<&tegra_car TEGRA114_CLK_DSIALP>,
69
+
<&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
70
+
clock-names = "dsi", "lp", "parent";
71
+
resets = <&tegra_car 48>;
72
+
reset-names = "dsi";
73
+
nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
74
+
};
+152
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
+152
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra DisplayPort AUX Interface
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description: |
14
+
The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
15
+
pins which can be assigned to either the DPAUX channel or to an I2C
16
+
controller.
17
+
18
+
When configured for DisplayPort AUX operation, the DPAUX controller
19
+
can also be used to communicate with a DisplayPort device using the
20
+
AUX channel.
21
+
22
+
properties:
23
+
$nodename:
24
+
pattern: "^dpaux@[0-9a-f]+$"
25
+
26
+
compatible:
27
+
oneOf:
28
+
- enum:
29
+
- nvidia,tegra124-dpaux
30
+
- nvidia,tegra210-dpaux
31
+
- nvidia,tegra186-dpaux
32
+
- nvidia,tegra194-dpaux
33
+
34
+
- items:
35
+
- const: nvidia,tegra132-dpaux
36
+
- const: nvidia,tegra124-dpaux
37
+
38
+
reg:
39
+
maxItems: 1
40
+
41
+
interrupts:
42
+
maxItems: 1
43
+
44
+
clocks:
45
+
items:
46
+
- description: clock input for the DPAUX hardware
47
+
- description: reference clock
48
+
49
+
clock-names:
50
+
items:
51
+
- const: dpaux
52
+
- const: parent
53
+
54
+
resets:
55
+
items:
56
+
- description: module reset
57
+
58
+
reset-names:
59
+
items:
60
+
- const: dpaux
61
+
62
+
power-domains:
63
+
maxItems: 1
64
+
65
+
i2c-bus:
66
+
description: Subnode where I2C slave devices are listed. This
67
+
subnode must be always present. If there are no I2C slave
68
+
devices, an empty node should be added. See ../../i2c/i2c.yaml
69
+
for more information.
70
+
type: object
71
+
72
+
aux-bus:
73
+
$ref: /schemas/display/dp-aux-bus.yaml#
74
+
75
+
vdd-supply:
76
+
description: phandle of a supply that powers the DisplayPort
77
+
link
78
+
79
+
patternProperties:
80
+
"^pinmux-[a-z0-9]+$":
81
+
description:
82
+
Since only three configurations are possible, only three child
83
+
nodes are needed to describe the pin mux'ing options for the
84
+
DPAUX pads. Furthermore, given that the pad functions are only
85
+
applicable to a single set of pads, the child nodes only need
86
+
to describe the pad group the functions are being applied to
87
+
rather than the individual pads.
88
+
type: object
89
+
properties:
90
+
groups:
91
+
const: dpaux-io
92
+
93
+
function:
94
+
enum:
95
+
- aux
96
+
- i2c
97
+
- off
98
+
99
+
additionalProperties: false
100
+
101
+
required:
102
+
- groups
103
+
- function
104
+
105
+
additionalProperties: false
106
+
107
+
required:
108
+
- compatible
109
+
- reg
110
+
- interrupts
111
+
- clocks
112
+
- clock-names
113
+
- resets
114
+
- reset-names
115
+
116
+
examples:
117
+
- |
118
+
#include <dt-bindings/clock/tegra210-car.h>
119
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
120
+
121
+
dpaux: dpaux@545c0000 {
122
+
compatible = "nvidia,tegra210-dpaux";
123
+
reg = <0x545c0000 0x00040000>;
124
+
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
125
+
clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
126
+
<&tegra_car TEGRA210_CLK_PLL_DP>;
127
+
clock-names = "dpaux", "parent";
128
+
resets = <&tegra_car 181>;
129
+
reset-names = "dpaux";
130
+
power-domains = <&pd_sor>;
131
+
status = "disabled";
132
+
133
+
state_dpaux_aux: pinmux-aux {
134
+
groups = "dpaux-io";
135
+
function = "aux";
136
+
};
137
+
138
+
state_dpaux_i2c: pinmux-i2c {
139
+
groups = "dpaux-io";
140
+
function = "i2c";
141
+
};
142
+
143
+
state_dpaux_off: pinmux-off {
144
+
groups = "dpaux-io";
145
+
function = "off";
146
+
};
147
+
148
+
i2c-bus {
149
+
#address-cells = <1>;
150
+
#size-cells = <0>;
151
+
};
152
+
};
+197
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
+197
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra SOR Output Encoder
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description: |
14
+
The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
15
+
and DP outputs.
16
+
17
+
properties:
18
+
$nodename:
19
+
pattern: "^sor@[0-9a-f]+$"
20
+
21
+
compatible:
22
+
oneOf:
23
+
- enum:
24
+
- nvidia,tegra124-sor
25
+
- nvidia,tegra210-sor
26
+
- nvidia,tegra210-sor1
27
+
- nvidia,tegra186-sor
28
+
- nvidia,tegra186-sor1
29
+
- nvidia,tegra194-sor
30
+
31
+
- items:
32
+
- const: nvidia,tegra132-sor
33
+
- const: nvidia,tegra124-sor
34
+
35
+
reg:
36
+
maxItems: 1
37
+
38
+
interrupts:
39
+
maxItems: 1
40
+
41
+
clocks:
42
+
minItems: 5
43
+
maxItems: 6
44
+
45
+
clock-names:
46
+
minItems: 5
47
+
maxItems: 6
48
+
49
+
resets:
50
+
items:
51
+
- description: module reset
52
+
53
+
reset-names:
54
+
items:
55
+
- const: sor
56
+
57
+
power-domains:
58
+
maxItems: 1
59
+
60
+
avdd-io-hdmi-dp-supply:
61
+
description: I/O supply for HDMI/DP
62
+
63
+
vdd-hdmi-dp-pll-supply:
64
+
description: PLL supply for HDMI/DP
65
+
66
+
hdmi-supply:
67
+
description: +5.0V HDMI connector supply, required for HDMI
68
+
69
+
# Tegra186 and later
70
+
nvidia,interface:
71
+
description: index of the SOR interface
72
+
$ref: "/schemas/types.yaml#/definitions/uint32"
73
+
74
+
nvidia,ddc-i2c-bus:
75
+
description: phandle of an I2C controller used for DDC EDID
76
+
probing
77
+
$ref: "/schemas/types.yaml#/definitions/phandle"
78
+
79
+
nvidia,hpd-gpio:
80
+
description: specifies a GPIO used for hotplug detection
81
+
maxItems: 1
82
+
83
+
nvidia,edid:
84
+
description: supplies a binary EDID blob
85
+
$ref: "/schemas/types.yaml#/definitions/uint8-array"
86
+
87
+
nvidia,panel:
88
+
description: phandle of a display panel, required for eDP
89
+
$ref: "/schemas/types.yaml#/definitions/phandle"
90
+
91
+
nvidia,xbar-cfg:
92
+
description: 5 cells containing the crossbar configuration.
93
+
Each lane of the SOR, identified by the cell's index, is
94
+
mapped via the crossbar to the pad specified by the cell's
95
+
value.
96
+
$ref: "/schemas/types.yaml#/definitions/uint32-array"
97
+
98
+
# optional when driving an eDP output
99
+
nvidia,dpaux:
100
+
description: phandle to a DispayPort AUX interface
101
+
$ref: "/schemas/types.yaml#/definitions/phandle"
102
+
103
+
allOf:
104
+
- if:
105
+
properties:
106
+
compatible:
107
+
contains:
108
+
enum:
109
+
- nvidia,tegra186-sor
110
+
- nvidia,tegra194-sor
111
+
then:
112
+
properties:
113
+
clocks:
114
+
items:
115
+
- description: clock input for the SOR hardware
116
+
- description: SOR output clock
117
+
- description: input for the pixel clock
118
+
- description: reference clock for the SOR clock
119
+
- description: safe reference clock for the SOR clock
120
+
during power up
121
+
- description: SOR pad output clock
122
+
123
+
clock-names:
124
+
items:
125
+
- const: sor
126
+
- enum:
127
+
- source # deprecated
128
+
- out
129
+
- const: parent
130
+
- const: dp
131
+
- const: safe
132
+
- const: pad
133
+
else:
134
+
properties:
135
+
clocks:
136
+
items:
137
+
- description: clock input for the SOR hardware
138
+
- description: SOR output clock
139
+
- description: input for the pixel clock
140
+
- description: reference clock for the SOR clock
141
+
- description: safe reference clock for the SOR clock
142
+
during power up
143
+
144
+
clock-names:
145
+
items:
146
+
- const: sor
147
+
- enum:
148
+
- source # deprecated
149
+
- out
150
+
- const: parent
151
+
- const: dp
152
+
- const: safe
153
+
154
+
additionalProperties: false
155
+
156
+
required:
157
+
- compatible
158
+
- reg
159
+
- interrupts
160
+
- clocks
161
+
- clock-names
162
+
- resets
163
+
- reset-names
164
+
- avdd-io-hdmi-dp-supply
165
+
- vdd-hdmi-dp-pll-supply
166
+
167
+
examples:
168
+
- |
169
+
#include <dt-bindings/clock/tegra210-car.h>
170
+
#include <dt-bindings/gpio/tegra-gpio.h>
171
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
172
+
173
+
sor0: sor@54540000 {
174
+
compatible = "nvidia,tegra210-sor";
175
+
reg = <0x54540000 0x00040000>;
176
+
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
177
+
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
178
+
<&tegra_car TEGRA210_CLK_SOR0_OUT>,
179
+
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
180
+
<&tegra_car TEGRA210_CLK_PLL_DP>,
181
+
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
182
+
clock-names = "sor", "out", "parent", "dp", "safe";
183
+
resets = <&tegra_car 182>;
184
+
reset-names = "sor";
185
+
pinctrl-0 = <&state_dpaux_aux>;
186
+
pinctrl-1 = <&state_dpaux_i2c>;
187
+
pinctrl-2 = <&state_dpaux_off>;
188
+
pinctrl-names = "aux", "i2c", "off";
189
+
power-domains = <&pd_sor>;
190
+
191
+
avdd-io-hdmi-dp-supply = <&avdd_1v05>;
192
+
vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
193
+
hdmi-supply = <&vdd_hdmi>;
194
+
195
+
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
196
+
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>;
197
+
};
+72
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
+72
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Video Image Composer
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^vic@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
oneOf:
19
+
- enum:
20
+
- nvidia,tegra124-vic
21
+
- nvidia,tegra210-vic
22
+
- nvidia,tegra186-vic
23
+
- nvidia,tegra194-vic
24
+
- nvidia,tegra234-vic
25
+
26
+
- items:
27
+
- const: nvidia,tegra132-vic
28
+
- const: nvidia,tegra124-vic
29
+
30
+
reg:
31
+
maxItems: 1
32
+
33
+
interrupts:
34
+
maxItems: 1
35
+
36
+
clocks:
37
+
items:
38
+
- description: clock input for the VIC hardware
39
+
40
+
clock-names:
41
+
items:
42
+
- const: vic
43
+
44
+
resets:
45
+
items:
46
+
- description: module reset
47
+
48
+
reset-names:
49
+
items:
50
+
- const: vic
51
+
52
+
power-domains:
53
+
maxItems: 1
54
+
55
+
iommus:
56
+
maxItems: 1
57
+
58
+
interconnects:
59
+
description: Description of the interconnect paths for the VIC;
60
+
see ../interconnect/interconnect.txt for details.
61
+
items:
62
+
- description: memory read client for VIC
63
+
- description: memory write client for VIC
64
+
65
+
interconnect-names:
66
+
items:
67
+
- const: dma-mem # read
68
+
- const: write
69
+
70
+
dma-coherent: true
71
+
72
+
additionalProperties: false
+85
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
+85
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra186 (and later) Display Controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^display@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra186-dc
20
+
- nvidia,tegra194-dc
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
clocks:
29
+
items:
30
+
- description: display controller pixel clock
31
+
32
+
clock-names:
33
+
items:
34
+
- const: dc
35
+
36
+
resets:
37
+
items:
38
+
- description: display controller reset
39
+
40
+
reset-names:
41
+
items:
42
+
- const: dc
43
+
44
+
power-domains:
45
+
maxItems: 1
46
+
47
+
iommus:
48
+
maxItems: 1
49
+
50
+
interconnects:
51
+
description: Description of the interconnect paths for the
52
+
display controller; see ../interconnect/interconnect.txt
53
+
for details.
54
+
55
+
interconnect-names:
56
+
items:
57
+
- const: dma-mem # read-0
58
+
- const: read-1
59
+
60
+
nvidia,outputs:
61
+
description: A list of phandles of outputs that this display
62
+
controller can drive.
63
+
$ref: "/schemas/types.yaml#/definitions/phandle-array"
64
+
65
+
nvidia,head:
66
+
description: The number of the display controller head. This
67
+
is used to setup the various types of output to receive
68
+
video data from the given head.
69
+
$ref: "/schemas/types.yaml#/definitions/uint32"
70
+
71
+
additionalProperties: false
72
+
73
+
required:
74
+
- compatible
75
+
- reg
76
+
- interrupts
77
+
- clocks
78
+
- clock-names
79
+
- resets
80
+
- reset-names
81
+
- power-domains
82
+
- nvidia,outputs
83
+
- nvidia,head
84
+
85
+
# see nvidia,tegra186-display.yaml for examples
+310
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
+310
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra186 (and later) Display Hub
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^display-hub@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra186-display
20
+
- nvidia,tegra194-display
21
+
22
+
'#address-cells':
23
+
const: 1
24
+
25
+
'#size-cells':
26
+
const: 1
27
+
28
+
reg:
29
+
maxItems: 1
30
+
31
+
interrupts:
32
+
maxItems: 1
33
+
34
+
clocks:
35
+
minItems: 2
36
+
maxItems: 3
37
+
38
+
clock-names:
39
+
minItems: 2
40
+
maxItems: 3
41
+
42
+
resets:
43
+
items:
44
+
- description: display hub reset
45
+
- description: window group 0 reset
46
+
- description: window group 1 reset
47
+
- description: window group 2 reset
48
+
- description: window group 3 reset
49
+
- description: window group 4 reset
50
+
- description: window group 5 reset
51
+
52
+
reset-names:
53
+
items:
54
+
- const: misc
55
+
- const: wgrp0
56
+
- const: wgrp1
57
+
- const: wgrp2
58
+
- const: wgrp3
59
+
- const: wgrp4
60
+
- const: wgrp5
61
+
62
+
power-domains:
63
+
maxItems: 1
64
+
65
+
ranges:
66
+
maxItems: 1
67
+
68
+
patternProperties:
69
+
"^display@[0-9a-f]+$":
70
+
type: object
71
+
72
+
allOf:
73
+
- if:
74
+
properties:
75
+
compatible:
76
+
contains:
77
+
const: nvidia,tegra186-display
78
+
then:
79
+
properties:
80
+
clocks:
81
+
items:
82
+
- description: display core clock
83
+
- description: display stream compression clock
84
+
- description: display hub clock
85
+
86
+
clock-names:
87
+
items:
88
+
- const: disp
89
+
- const: dsc
90
+
- const: hub
91
+
else:
92
+
properties:
93
+
clocks:
94
+
items:
95
+
- description: display core clock
96
+
- description: display hub clock
97
+
98
+
clock-names:
99
+
items:
100
+
- const: disp
101
+
- const: hub
102
+
103
+
additionalProperties: false
104
+
105
+
required:
106
+
- compatible
107
+
- reg
108
+
- clocks
109
+
- clock-names
110
+
- resets
111
+
- reset-names
112
+
- power-domains
113
+
- "#address-cells"
114
+
- "#size-cells"
115
+
- ranges
116
+
117
+
examples:
118
+
- |
119
+
#include <dt-bindings/clock/tegra186-clock.h>
120
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
121
+
#include <dt-bindings/memory/tegra186-mc.h>
122
+
#include <dt-bindings/power/tegra186-powergate.h>
123
+
#include <dt-bindings/reset/tegra186-reset.h>
124
+
125
+
display-hub@15200000 {
126
+
compatible = "nvidia,tegra186-display";
127
+
reg = <0x15200000 0x00040000>;
128
+
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
129
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
130
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
131
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
132
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
133
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
134
+
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
135
+
reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
136
+
"wgrp3", "wgrp4", "wgrp5";
137
+
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
138
+
<&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
139
+
<&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
140
+
clock-names = "disp", "dsc", "hub";
141
+
status = "disabled";
142
+
143
+
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
144
+
145
+
#address-cells = <1>;
146
+
#size-cells = <1>;
147
+
148
+
ranges = <0x15200000 0x15200000 0x40000>;
149
+
150
+
display@15200000 {
151
+
compatible = "nvidia,tegra186-dc";
152
+
reg = <0x15200000 0x10000>;
153
+
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
154
+
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
155
+
clock-names = "dc";
156
+
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
157
+
reset-names = "dc";
158
+
159
+
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
160
+
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
161
+
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
162
+
interconnect-names = "dma-mem", "read-1";
163
+
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
164
+
165
+
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
166
+
nvidia,head = <0>;
167
+
};
168
+
169
+
display@15210000 {
170
+
compatible = "nvidia,tegra186-dc";
171
+
reg = <0x15210000 0x10000>;
172
+
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
173
+
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
174
+
clock-names = "dc";
175
+
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
176
+
reset-names = "dc";
177
+
178
+
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
179
+
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
180
+
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
181
+
interconnect-names = "dma-mem", "read-1";
182
+
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
183
+
184
+
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
185
+
nvidia,head = <1>;
186
+
};
187
+
188
+
display@15220000 {
189
+
compatible = "nvidia,tegra186-dc";
190
+
reg = <0x15220000 0x10000>;
191
+
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
192
+
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
193
+
clock-names = "dc";
194
+
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
195
+
reset-names = "dc";
196
+
197
+
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
198
+
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
199
+
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
200
+
interconnect-names = "dma-mem", "read-1";
201
+
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
202
+
203
+
nvidia,outputs = <&sor0 &sor1>;
204
+
nvidia,head = <2>;
205
+
};
206
+
};
207
+
208
+
- |
209
+
#include <dt-bindings/clock/tegra194-clock.h>
210
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
211
+
#include <dt-bindings/memory/tegra194-mc.h>
212
+
#include <dt-bindings/power/tegra194-powergate.h>
213
+
#include <dt-bindings/reset/tegra194-reset.h>
214
+
215
+
display-hub@15200000 {
216
+
compatible = "nvidia,tegra194-display";
217
+
reg = <0x15200000 0x00040000>;
218
+
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
219
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
220
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
221
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
222
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
223
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
224
+
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
225
+
reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
226
+
"wgrp3", "wgrp4", "wgrp5";
227
+
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
228
+
<&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
229
+
clock-names = "disp", "hub";
230
+
status = "disabled";
231
+
232
+
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
233
+
234
+
#address-cells = <1>;
235
+
#size-cells = <1>;
236
+
237
+
ranges = <0x15200000 0x15200000 0x40000>;
238
+
239
+
display@15200000 {
240
+
compatible = "nvidia,tegra194-dc";
241
+
reg = <0x15200000 0x10000>;
242
+
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
243
+
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
244
+
clock-names = "dc";
245
+
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
246
+
reset-names = "dc";
247
+
248
+
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
249
+
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
250
+
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
251
+
interconnect-names = "dma-mem", "read-1";
252
+
253
+
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
254
+
nvidia,head = <0>;
255
+
};
256
+
257
+
display@15210000 {
258
+
compatible = "nvidia,tegra194-dc";
259
+
reg = <0x15210000 0x10000>;
260
+
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
261
+
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
262
+
clock-names = "dc";
263
+
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
264
+
reset-names = "dc";
265
+
266
+
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
267
+
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
268
+
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
269
+
interconnect-names = "dma-mem", "read-1";
270
+
271
+
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
272
+
nvidia,head = <1>;
273
+
};
274
+
275
+
display@15220000 {
276
+
compatible = "nvidia,tegra194-dc";
277
+
reg = <0x15220000 0x10000>;
278
+
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
279
+
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
280
+
clock-names = "dc";
281
+
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
282
+
reset-names = "dc";
283
+
284
+
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
285
+
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
286
+
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
287
+
interconnect-names = "dma-mem", "read-1";
288
+
289
+
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
290
+
nvidia,head = <2>;
291
+
};
292
+
293
+
display@15230000 {
294
+
compatible = "nvidia,tegra194-dc";
295
+
reg = <0x15230000 0x10000>;
296
+
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
297
+
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
298
+
clock-names = "dc";
299
+
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
300
+
reset-names = "dc";
301
+
302
+
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
303
+
interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
304
+
<&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
305
+
interconnect-names = "dma-mem", "read-1";
306
+
307
+
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
308
+
nvidia,head = <3>;
309
+
};
310
+
};
+45
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
+45
Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dsi-padctl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra MIPI DSI pad controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^padctl@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
const: nvidia,tegra186-dsi-padctl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
resets:
24
+
items:
25
+
- description: module reset
26
+
27
+
reset-names:
28
+
items:
29
+
- const: dsi
30
+
31
+
allOf:
32
+
- $ref: "/schemas/reset/reset.yaml"
33
+
34
+
additionalProperties: false
35
+
36
+
examples:
37
+
- |
38
+
#include <dt-bindings/reset/tegra186-reset.h>
39
+
40
+
padctl@15880000 {
41
+
compatible = "nvidia,tegra186-dsi-padctl";
42
+
reg = <0x15880000 0x10000>;
43
+
resets = <&bpmp TEGRA186_RESET_DSI>;
44
+
reset-names = "dsi";
45
+
};
+183
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
+183
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Display Controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^dc@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
oneOf:
19
+
- enum:
20
+
- nvidia,tegra20-dc
21
+
- nvidia,tegra30-dc
22
+
- nvidia,tegra114-dc
23
+
- nvidia,tegra124-dc
24
+
- nvidia,tegra210-dc
25
+
26
+
- items:
27
+
- const: nvidia,tegra124-dc
28
+
- const: nvidia,tegra132-dc
29
+
30
+
reg:
31
+
maxItems: 1
32
+
33
+
interrupts:
34
+
maxItems: 1
35
+
36
+
clocks:
37
+
minItems: 1
38
+
items:
39
+
- description: display controller pixel clock
40
+
- description: parent clock # optional
41
+
42
+
clock-names:
43
+
minItems: 1
44
+
items:
45
+
- const: dc
46
+
- const: parent # optional
47
+
48
+
resets:
49
+
items:
50
+
- description: module reset
51
+
52
+
reset-names:
53
+
items:
54
+
- const: dc
55
+
56
+
interconnect-names: true
57
+
interconnects: true
58
+
59
+
iommus:
60
+
maxItems: 1
61
+
62
+
operating-points-v2:
63
+
$ref: "/schemas/types.yaml#/definitions/phandle"
64
+
65
+
power-domains:
66
+
items:
67
+
- description: phandle to the core power domain
68
+
69
+
memory-region: true
70
+
71
+
nvidia,head:
72
+
$ref: /schemas/types.yaml#/definitions/uint32
73
+
description: The number of the display controller head. This is used to setup the various
74
+
types of output to receive video data from the given head.
75
+
76
+
nvidia,outputs:
77
+
$ref: /schemas/types.yaml#/definitions/phandle-array
78
+
description: A list of phandles of outputs that this display controller can drive.
79
+
80
+
rgb:
81
+
type: object
82
+
83
+
allOf:
84
+
- if:
85
+
properties:
86
+
compatible:
87
+
contains:
88
+
enum:
89
+
- nvidia,tegra20-dc
90
+
- nvidia,tegra30-dc
91
+
- nvidia,tegra114-dc
92
+
then:
93
+
properties:
94
+
interconnects:
95
+
items:
96
+
- description: window A memory client
97
+
- description: window B memory client
98
+
- description: window B memory client (vertical filter)
99
+
- description: window C memory client
100
+
- description: cursor memory client
101
+
102
+
interconnect-names:
103
+
items:
104
+
- const: wina
105
+
- const: winb
106
+
- const: winb-vfilter
107
+
- const: winc
108
+
- const: cursor
109
+
110
+
rgb:
111
+
description: Each display controller node has a child node, named "rgb", that represents
112
+
the RGB output associated with the controller.
113
+
type: object
114
+
properties:
115
+
nvidia,ddc-i2c-bus:
116
+
$ref: /schemas/types.yaml#/definitions/phandle
117
+
description: phandle of an I2C controller used for DDC EDID probing
118
+
119
+
nvidia,hpd-gpio:
120
+
description: specifies a GPIO used for hotplug detection
121
+
maxItems: 1
122
+
123
+
nvidia,edid:
124
+
$ref: /schemas/types.yaml#/definitions/uint8-array
125
+
description: supplies a binary EDID blob
126
+
127
+
nvidia,panel:
128
+
$ref: /schemas/types.yaml#/definitions/phandle
129
+
description: phandle of a display panel
130
+
131
+
- if:
132
+
properties:
133
+
compatible:
134
+
contains:
135
+
enum:
136
+
- nvidia,tegra124-dc
137
+
then:
138
+
properties:
139
+
interconnects:
140
+
minItems: 4
141
+
items:
142
+
- description: window A memory client
143
+
- description: window B memory client
144
+
- description: window C memory client
145
+
- description: cursor memory client
146
+
- description: window D memory client
147
+
- description: window T memory client
148
+
149
+
interconnect-names:
150
+
minItems: 4
151
+
items:
152
+
- const: wina
153
+
- const: winb
154
+
- const: winc
155
+
- const: cursor
156
+
- const: wind
157
+
- const: wint
158
+
159
+
additionalProperties: false
160
+
161
+
required:
162
+
- compatible
163
+
- reg
164
+
- interrupts
165
+
- clocks
166
+
- clock-names
167
+
- resets
168
+
- reset-names
169
+
170
+
examples:
171
+
- |
172
+
#include <dt-bindings/clock/tegra20-car.h>
173
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
174
+
175
+
dc@54200000 {
176
+
compatible = "nvidia,tegra20-dc";
177
+
reg = <0x54200000 0x00040000>;
178
+
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
179
+
clocks = <&tegra_car TEGRA20_CLK_DISP1>;
180
+
clock-names = "dc";
181
+
resets = <&tegra_car 27>;
182
+
reset-names = "dc";
183
+
};
+159
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
+159
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Display Serial Interface
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
compatible:
15
+
oneOf:
16
+
- enum:
17
+
- nvidia,tegra20-dsi
18
+
- nvidia,tegra30-dsi
19
+
- nvidia,tegra114-dsi
20
+
- nvidia,tegra124-dsi
21
+
- nvidia,tegra210-dsi
22
+
- nvidia,tegra186-dsi
23
+
24
+
- items:
25
+
- const: nvidia,tegra132-dsi
26
+
- const: nvidia,tegra124-dsi
27
+
28
+
reg:
29
+
maxItems: 1
30
+
31
+
interrupts:
32
+
maxItems: 1
33
+
34
+
clocks:
35
+
minItems: 2
36
+
maxItems: 3
37
+
38
+
clock-names:
39
+
minItems: 2
40
+
maxItems: 3
41
+
42
+
resets:
43
+
items:
44
+
- description: module reset
45
+
46
+
reset-names:
47
+
items:
48
+
- const: dsi
49
+
50
+
operating-points-v2:
51
+
$ref: "/schemas/types.yaml#/definitions/phandle"
52
+
53
+
power-domains:
54
+
maxItems: 1
55
+
56
+
avdd-dsi-csi-supply:
57
+
description: phandle of a supply that powers the DSI controller
58
+
59
+
nvidia,mipi-calibrate:
60
+
description: Should contain a phandle and a specifier specifying
61
+
which pads are used by this DSI output and need to be
62
+
calibrated. See nvidia,tegra114-mipi.yaml for details.
63
+
$ref: "/schemas/types.yaml#/definitions/phandle-array"
64
+
65
+
nvidia,ddc-i2c-bus:
66
+
description: phandle of an I2C controller used for DDC EDID
67
+
probing
68
+
$ref: "/schemas/types.yaml#/definitions/phandle"
69
+
70
+
nvidia,hpd-gpio:
71
+
description: specifies a GPIO used for hotplug detection
72
+
maxItems: 1
73
+
74
+
nvidia,edid:
75
+
description: supplies a binary EDID blob
76
+
$ref: "/schemas/types.yaml#/definitions/uint8-array"
77
+
78
+
nvidia,panel:
79
+
description: phandle of a display panel
80
+
$ref: "/schemas/types.yaml#/definitions/phandle"
81
+
82
+
nvidia,ganged-mode:
83
+
description: contains a phandle to a second DSI controller to
84
+
gang up with in order to support up to 8 data lanes
85
+
$ref: "/schemas/types.yaml#/definitions/phandle"
86
+
87
+
allOf:
88
+
- $ref: "../dsi-controller.yaml#"
89
+
- if:
90
+
properties:
91
+
compatible:
92
+
contains:
93
+
enum:
94
+
- nvidia,tegra20-dsi
95
+
- nvidia,tegra30-dsi
96
+
then:
97
+
properties:
98
+
clocks:
99
+
items:
100
+
- description: DSI module clock
101
+
- description: input for the pixel clock
102
+
103
+
clock-names:
104
+
items:
105
+
- const: dsi
106
+
- const: parent
107
+
else:
108
+
properties:
109
+
clocks:
110
+
items:
111
+
- description: DSI module clock
112
+
- description: low-power module clock
113
+
- description: input for the pixel clock
114
+
115
+
clock-names:
116
+
items:
117
+
- const: dsi
118
+
- const: lp
119
+
- const: parent
120
+
121
+
- if:
122
+
properties:
123
+
compatible:
124
+
contains:
125
+
const: nvidia,tegra186-dsi
126
+
then:
127
+
required:
128
+
- interrupts
129
+
130
+
unevaluatedProperties: false
131
+
132
+
required:
133
+
- compatible
134
+
- reg
135
+
- clocks
136
+
- clock-names
137
+
- resets
138
+
- reset-names
139
+
140
+
examples:
141
+
- |
142
+
#include <dt-bindings/clock/tegra186-clock.h>
143
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
144
+
#include <dt-bindings/power/tegra186-powergate.h>
145
+
#include <dt-bindings/reset/tegra186-reset.h>
146
+
147
+
dsi@15300000 {
148
+
compatible = "nvidia,tegra186-dsi";
149
+
reg = <0x15300000 0x10000>;
150
+
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
151
+
clocks = <&bpmp TEGRA186_CLK_DSI>,
152
+
<&bpmp TEGRA186_CLK_DSIA_LP>,
153
+
<&bpmp TEGRA186_CLK_PLLD>;
154
+
clock-names = "dsi", "lp", "parent";
155
+
resets = <&bpmp TEGRA186_RESET_DSI>;
156
+
reset-names = "dsi";
157
+
158
+
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
159
+
};
+70
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
+70
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Encoder Pre-Processor
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^epp@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra20-epp
20
+
- nvidia,tegra30-epp
21
+
- nvidia,tegra114-epp
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
maxItems: 1
31
+
32
+
resets:
33
+
items:
34
+
- description: module reset
35
+
36
+
reset-names:
37
+
items:
38
+
- const: epp
39
+
40
+
iommus:
41
+
maxItems: 1
42
+
43
+
interconnects:
44
+
maxItems: 4
45
+
46
+
interconnect-names:
47
+
maxItems: 4
48
+
49
+
operating-points-v2:
50
+
$ref: "/schemas/types.yaml#/definitions/phandle"
51
+
52
+
power-domains:
53
+
items:
54
+
- description: phandle to the core power domain
55
+
56
+
additionalProperties: false
57
+
58
+
examples:
59
+
- |
60
+
#include <dt-bindings/clock/tegra20-car.h>
61
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
62
+
63
+
epp@540c0000 {
64
+
compatible = "nvidia,tegra20-epp";
65
+
reg = <0x540c0000 0x00040000>;
66
+
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
67
+
clocks = <&tegra_car TEGRA20_CLK_EPP>;
68
+
resets = <&tegra_car 19>;
69
+
reset-names = "epp";
70
+
};
+74
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
+74
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA 2D graphics engine
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^gr2d@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra20-gr2d
20
+
- nvidia,tegra30-gr2d
21
+
- nvidia,tegra114-gr2d
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
items:
31
+
- description: module clock
32
+
33
+
resets:
34
+
items:
35
+
- description: module reset
36
+
- description: memory client hotflush reset
37
+
38
+
reset-names:
39
+
items:
40
+
- const: 2d
41
+
- const: mc
42
+
43
+
iommus:
44
+
maxItems: 1
45
+
46
+
interconnects:
47
+
maxItems: 4
48
+
49
+
interconnect-names:
50
+
maxItems: 4
51
+
52
+
operating-points-v2:
53
+
$ref: "/schemas/types.yaml#/definitions/phandle"
54
+
55
+
power-domains:
56
+
items:
57
+
- description: phandle to the HEG or core power domain
58
+
59
+
additionalProperties: false
60
+
61
+
examples:
62
+
- |
63
+
#include <dt-bindings/clock/tegra20-car.h>
64
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
65
+
#include <dt-bindings/memory/tegra20-mc.h>
66
+
67
+
gr2d@54140000 {
68
+
compatible = "nvidia,tegra20-gr2d";
69
+
reg = <0x54140000 0x00040000>;
70
+
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
71
+
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
72
+
resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
73
+
reset-names = "2d", "mc";
74
+
};
+215
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
+215
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA 3D graphics engine
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^gr3d@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra20-gr3d
20
+
- nvidia,tegra30-gr3d
21
+
- nvidia,tegra114-gr3d
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
minItems: 1
28
+
maxItems: 2
29
+
30
+
clock-names:
31
+
minItems: 1
32
+
maxItems: 2
33
+
34
+
resets:
35
+
minItems: 2
36
+
maxItems: 4
37
+
38
+
reset-names:
39
+
minItems: 2
40
+
maxItems: 4
41
+
42
+
iommus:
43
+
minItems: 1
44
+
maxItems: 2
45
+
46
+
interconnects:
47
+
minItems: 4
48
+
maxItems: 10
49
+
50
+
interconnect-names:
51
+
minItems: 4
52
+
maxItems: 10
53
+
54
+
operating-points-v2:
55
+
$ref: "/schemas/types.yaml#/definitions/phandle"
56
+
57
+
power-domains:
58
+
minItems: 1
59
+
maxItems: 2
60
+
61
+
power-domain-names:
62
+
minItems: 2
63
+
maxItems: 2
64
+
65
+
allOf:
66
+
- if:
67
+
properties:
68
+
compatible:
69
+
contains:
70
+
const: nvidia,tegra20-gr2d
71
+
then:
72
+
properties:
73
+
clocks:
74
+
items:
75
+
- description: module clock
76
+
77
+
clock-names:
78
+
items:
79
+
- const: 3d
80
+
81
+
resets:
82
+
items:
83
+
- description: module reset
84
+
- description: memory client hotflush reset
85
+
86
+
reset-names:
87
+
items:
88
+
- const: 3d
89
+
- const: mc
90
+
91
+
iommus:
92
+
maxItems: 1
93
+
94
+
interconnects:
95
+
minItems: 4
96
+
maxItems: 4
97
+
98
+
interconnect-names:
99
+
minItems: 4
100
+
maxItems: 4
101
+
102
+
power-domains:
103
+
items:
104
+
- description: phandle to the TD power domain
105
+
106
+
- if:
107
+
properties:
108
+
compatible:
109
+
contains:
110
+
const: nvidia,tegra30-gr3d
111
+
then:
112
+
properties:
113
+
clocks:
114
+
items:
115
+
- description: primary module clock
116
+
- description: secondary module clock
117
+
118
+
clock-names:
119
+
items:
120
+
- const: 3d
121
+
- const: 3d2
122
+
123
+
resets:
124
+
items:
125
+
- description: primary module reset
126
+
- description: secondary module reset
127
+
- description: primary memory client hotflush reset
128
+
- description: secondary memory client hotflush reset
129
+
130
+
reset-names:
131
+
items:
132
+
- const: 3d
133
+
- const: 3d2
134
+
- const: mc
135
+
- const: mc2
136
+
137
+
iommus:
138
+
minItems: 2
139
+
maxItems: 2
140
+
141
+
interconnects:
142
+
minItems: 8
143
+
maxItems: 8
144
+
145
+
interconnect-names:
146
+
minItems: 8
147
+
maxItems: 8
148
+
149
+
power-domains:
150
+
items:
151
+
- description: phandle to the TD power domain
152
+
- description: phandle to the TD2 power domain
153
+
154
+
power-domain-names:
155
+
items:
156
+
- const: 3d0
157
+
- const: 3d1
158
+
159
+
dependencies:
160
+
power-domains: [ power-domain-names ]
161
+
162
+
- if:
163
+
properties:
164
+
compatible:
165
+
contains:
166
+
const: nvidia,tegra114-gr2d
167
+
then:
168
+
properties:
169
+
clocks:
170
+
items:
171
+
- description: module clock
172
+
173
+
clock-names:
174
+
items:
175
+
- const: 3d
176
+
177
+
resets:
178
+
items:
179
+
- description: module reset
180
+
- description: memory client hotflush reset
181
+
182
+
reset-names:
183
+
items:
184
+
- const: 3d
185
+
- const: mc
186
+
187
+
iommus:
188
+
maxItems: 1
189
+
190
+
interconnects:
191
+
minItems: 10
192
+
maxItems: 10
193
+
194
+
interconnect-names:
195
+
minItems: 10
196
+
maxItems: 10
197
+
198
+
power-domains:
199
+
items:
200
+
- description: phandle to the TD power domain
201
+
202
+
additionalProperties: false
203
+
204
+
examples:
205
+
- |
206
+
#include <dt-bindings/clock/tegra20-car.h>
207
+
#include <dt-bindings/memory/tegra20-mc.h>
208
+
209
+
gr3d@54180000 {
210
+
compatible = "nvidia,tegra20-gr3d";
211
+
reg = <0x54180000 0x00040000>;
212
+
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
213
+
resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
214
+
reset-names = "3d", "mc";
215
+
};
+126
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
+126
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra HDMI Output Encoder
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^hdmi@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
oneOf:
19
+
- enum:
20
+
- nvidia,tegra20-hdmi
21
+
- nvidia,tegra30-hdmi
22
+
- nvidia,tegra114-hdmi
23
+
- nvidia,tegra124-hdmi
24
+
25
+
- items:
26
+
- const: nvidia,tegra132-hdmi
27
+
- const: nvidia,tegra124-hdmi
28
+
29
+
reg:
30
+
maxItems: 1
31
+
32
+
interrupts:
33
+
maxItems: 1
34
+
35
+
clocks:
36
+
items:
37
+
- description: module clock
38
+
- description: parent clock
39
+
40
+
clock-names:
41
+
items:
42
+
- const: hdmi
43
+
- const: parent
44
+
45
+
resets:
46
+
items:
47
+
- description: module reset
48
+
49
+
reset-names:
50
+
items:
51
+
- const: hdmi
52
+
53
+
operating-points-v2:
54
+
$ref: "/schemas/types.yaml#/definitions/phandle"
55
+
56
+
power-domains:
57
+
items:
58
+
- description: phandle to the core power domain
59
+
60
+
hdmi-supply:
61
+
description: supply for the +5V HDMI connector pin
62
+
63
+
vdd-supply:
64
+
description: regulator for supply voltage
65
+
66
+
pll-supply:
67
+
description: regulator for PLL
68
+
69
+
nvidia,ddc-i2c-bus:
70
+
description: phandle of an I2C controller used for DDC EDID
71
+
probing
72
+
$ref: "/schemas/types.yaml#/definitions/phandle"
73
+
74
+
nvidia,hpd-gpio:
75
+
description: specifies a GPIO used for hotplug detection
76
+
maxItems: 1
77
+
78
+
nvidia,edid:
79
+
description: supplies a binary EDID blob
80
+
$ref: "/schemas/types.yaml#/definitions/uint8-array"
81
+
82
+
nvidia,panel:
83
+
description: phandle of a display panel
84
+
$ref: "/schemas/types.yaml#/definitions/phandle"
85
+
86
+
"#sound-dai-cells":
87
+
const: 0
88
+
89
+
additionalProperties: false
90
+
91
+
required:
92
+
- compatible
93
+
- reg
94
+
- interrupts
95
+
- clocks
96
+
- clock-names
97
+
- resets
98
+
- reset-names
99
+
- pll-supply
100
+
- vdd-supply
101
+
- nvidia,ddc-i2c-bus
102
+
- nvidia,hpd-gpio
103
+
104
+
examples:
105
+
- |
106
+
#include <dt-bindings/clock/tegra124-car.h>
107
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
108
+
#include <dt-bindings/gpio/tegra-gpio.h>
109
+
110
+
hdmi@54280000 {
111
+
compatible = "nvidia,tegra124-hdmi";
112
+
reg = <0x54280000 0x00040000>;
113
+
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
114
+
clocks = <&tegra_car TEGRA124_CLK_HDMI>,
115
+
<&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
116
+
clock-names = "hdmi", "parent";
117
+
resets = <&tegra_car 51>;
118
+
reset-names = "hdmi";
119
+
120
+
hdmi-supply = <&vdd_5v0_hdmi>;
121
+
pll-supply = <&vdd_hdmi_pll>;
122
+
vdd-supply = <&vdd_3v3_hdmi>;
123
+
124
+
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
125
+
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
126
+
};
-675
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
-675
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
···
1
-
NVIDIA Tegra host1x
2
-
3
-
Required properties:
4
-
- compatible: "nvidia,tegra<chip>-host1x"
5
-
- reg: Physical base address and length of the controller's registers.
6
-
For pre-Tegra186, one entry describing the whole register area.
7
-
For Tegra186, one entry for each entry in reg-names:
8
-
"vm" - VM region assigned to Linux
9
-
"hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10
-
- interrupts: The interrupt outputs from the controller.
11
-
- #address-cells: The number of cells used to represent physical base addresses
12
-
in the host1x address space. Should be 1.
13
-
- #size-cells: The number of cells used to represent the size of an address
14
-
range in the host1x address space. Should be 1.
15
-
- ranges: The mapping of the host1x address space to the CPU address space.
16
-
- clocks: Must contain one entry, for the module clock.
17
-
See ../clocks/clock-bindings.txt for details.
18
-
- resets: Must contain an entry for each entry in reset-names.
19
-
See ../reset/reset.txt for details.
20
-
- reset-names: Must include the following entries:
21
-
- host1x
22
-
- mc
23
-
24
-
Optional properties:
25
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
26
-
- power-domains: Phandle to HEG or core power domain.
27
-
28
-
For each opp entry in 'operating-points-v2' table of host1x and its modules:
29
-
- opp-supported-hw: One bitfield indicating:
30
-
On Tegra20: SoC process ID mask
31
-
On Tegra30+: SoC speedo ID mask
32
-
33
-
A bitwise AND is performed against the value and if any bit
34
-
matches, the OPP gets enabled.
35
-
36
-
Each host1x client module having to perform DMA through the Memory Controller
37
-
should have the interconnect endpoints set to the Memory Client and External
38
-
Memory respectively.
39
-
40
-
The host1x top-level node defines a number of children, each representing one
41
-
of the following host1x client modules:
42
-
43
-
- mpe: video encoder
44
-
45
-
Required properties:
46
-
- compatible: "nvidia,tegra<chip>-mpe"
47
-
- reg: Physical base address and length of the controller's registers.
48
-
- interrupts: The interrupt outputs from the controller.
49
-
- clocks: Must contain one entry, for the module clock.
50
-
See ../clocks/clock-bindings.txt for details.
51
-
- resets: Must contain an entry for each entry in reset-names.
52
-
See ../reset/reset.txt for details.
53
-
- reset-names: Must include the following entries:
54
-
- mpe
55
-
56
-
Optional properties:
57
-
- interconnects: Must contain entry for the MPE memory clients.
58
-
- interconnect-names: Must include name of the interconnect path for each
59
-
interconnect entry. Consult TRM documentation for information about
60
-
available memory clients, see MEMORY CONTROLLER section.
61
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
62
-
- power-domains: Phandle to MPE power domain.
63
-
64
-
- vi: video input
65
-
66
-
Required properties:
67
-
- compatible: "nvidia,tegra<chip>-vi"
68
-
- reg: Physical base address and length of the controller registers.
69
-
- interrupts: The interrupt outputs from the controller.
70
-
- clocks: clocks: Must contain one entry, for the module clock.
71
-
See ../clocks/clock-bindings.txt for details.
72
-
- Tegra20/Tegra30/Tegra114/Tegra124:
73
-
- resets: Must contain an entry for each entry in reset-names.
74
-
See ../reset/reset.txt for details.
75
-
- reset-names: Must include the following entries:
76
-
- vi
77
-
- Tegra210:
78
-
- power-domains: Must include venc powergate node as vi is in VE partition.
79
-
80
-
ports (optional node)
81
-
vi can have optional ports node and max 6 ports are supported. Each port
82
-
should have single 'endpoint' child node. All port nodes are grouped under
83
-
ports node. Please refer to the bindings defined in
84
-
Documentation/devicetree/bindings/media/video-interfaces.txt
85
-
86
-
csi (required node)
87
-
Tegra210 has CSI part of VI sharing same host interface and register space.
88
-
So, VI device node should have CSI child node.
89
-
90
-
- csi: mipi csi interface to vi
91
-
92
-
Required properties:
93
-
- compatible: "nvidia,tegra210-csi"
94
-
- reg: Physical base address offset to parent and length of the controller
95
-
registers.
96
-
- clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
97
-
See ../clocks/clock-bindings.txt for details.
98
-
- power-domains: Must include sor powergate node as csicil is in
99
-
SOR partition.
100
-
101
-
channel (optional nodes)
102
-
Maximum 6 channels are supported with each csi brick as either x4 or x2
103
-
based on hw connectivity to sensor.
104
-
105
-
Required properties:
106
-
- reg: csi port number. Valid port numbers are 0 through 5.
107
-
- nvidia,mipi-calibrate: Should contain a phandle and a specifier
108
-
specifying which pads are used by this CSI port and need to be
109
-
calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt.
110
-
111
-
Each channel node must contain 2 port nodes which can be grouped
112
-
under 'ports' node and each port should have a single child 'endpoint'
113
-
node.
114
-
115
-
ports node
116
-
Please refer to the bindings defined in
117
-
Documentation/devicetree/bindings/media/video-interfaces.txt
118
-
119
-
ports node must contain below 2 port nodes.
120
-
port@0 with single child 'endpoint' node always a sink.
121
-
port@1 with single child 'endpoint' node always a source.
122
-
123
-
port@0 (required node)
124
-
Required properties:
125
-
- reg: 0
126
-
127
-
endpoint (required node)
128
-
Required properties:
129
-
- data-lanes: an array of data lane from 1 to 8. Valid array
130
-
lengths are 1/2/4/8.
131
-
- remote-endpoint: phandle to sensor 'endpoint' node.
132
-
133
-
port@1 (required node)
134
-
Required properties:
135
-
- reg: 1
136
-
137
-
endpoint (required node)
138
-
Required properties:
139
-
- remote-endpoint: phandle to vi port 'endpoint' node.
140
-
141
-
Optional properties:
142
-
- interconnects: Must contain entry for the VI memory clients.
143
-
- interconnect-names: Must include name of the interconnect path for each
144
-
interconnect entry. Consult TRM documentation for information about
145
-
available memory clients, see MEMORY CONTROLLER section.
146
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
147
-
- power-domains: Phandle to VENC power domain.
148
-
149
-
- epp: encoder pre-processor
150
-
151
-
Required properties:
152
-
- compatible: "nvidia,tegra<chip>-epp"
153
-
- reg: Physical base address and length of the controller's registers.
154
-
- interrupts: The interrupt outputs from the controller.
155
-
- clocks: Must contain one entry, for the module clock.
156
-
See ../clocks/clock-bindings.txt for details.
157
-
- resets: Must contain an entry for each entry in reset-names.
158
-
See ../reset/reset.txt for details.
159
-
- reset-names: Must include the following entries:
160
-
- epp
161
-
162
-
Optional properties:
163
-
- interconnects: Must contain entry for the EPP memory clients.
164
-
- interconnect-names: Must include name of the interconnect path for each
165
-
interconnect entry. Consult TRM documentation for information about
166
-
available memory clients, see MEMORY CONTROLLER section.
167
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
168
-
- power-domains: Phandle to HEG or core power domain.
169
-
170
-
- isp: image signal processor
171
-
172
-
Required properties:
173
-
- compatible: "nvidia,tegra<chip>-isp"
174
-
- reg: Physical base address and length of the controller's registers.
175
-
- interrupts: The interrupt outputs from the controller.
176
-
- clocks: Must contain one entry, for the module clock.
177
-
See ../clocks/clock-bindings.txt for details.
178
-
- resets: Must contain an entry for each entry in reset-names.
179
-
See ../reset/reset.txt for details.
180
-
- reset-names: Must include the following entries:
181
-
- isp
182
-
183
-
Optional properties:
184
-
- interconnects: Must contain entry for the ISP memory clients.
185
-
- interconnect-names: Must include name of the interconnect path for each
186
-
interconnect entry. Consult TRM documentation for information about
187
-
available memory clients, see MEMORY CONTROLLER section.
188
-
- power-domains: Phandle to VENC or core power domain.
189
-
190
-
- gr2d: 2D graphics engine
191
-
192
-
Required properties:
193
-
- compatible: "nvidia,tegra<chip>-gr2d"
194
-
- reg: Physical base address and length of the controller's registers.
195
-
- interrupts: The interrupt outputs from the controller.
196
-
- clocks: Must contain one entry, for the module clock.
197
-
See ../clocks/clock-bindings.txt for details.
198
-
- resets: Must contain an entry for each entry in reset-names.
199
-
See ../reset/reset.txt for details.
200
-
- reset-names: Must include the following entries:
201
-
- 2d
202
-
- mc
203
-
204
-
Optional properties:
205
-
- interconnects: Must contain entry for the GR2D memory clients.
206
-
- interconnect-names: Must include name of the interconnect path for each
207
-
interconnect entry. Consult TRM documentation for information about
208
-
available memory clients, see MEMORY CONTROLLER section.
209
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
210
-
- power-domains: Phandle to HEG or core power domain.
211
-
212
-
- gr3d: 3D graphics engine
213
-
214
-
Required properties:
215
-
- compatible: "nvidia,tegra<chip>-gr3d"
216
-
- reg: Physical base address and length of the controller's registers.
217
-
- clocks: Must contain an entry for each entry in clock-names.
218
-
See ../clocks/clock-bindings.txt for details.
219
-
- clock-names: Must include the following entries:
220
-
(This property may be omitted if the only clock in the list is "3d")
221
-
- 3d
222
-
This MUST be the first entry.
223
-
- 3d2 (Only required on SoCs with two 3D clocks)
224
-
- resets: Must contain an entry for each entry in reset-names.
225
-
See ../reset/reset.txt for details.
226
-
- reset-names: Must include the following entries:
227
-
- 3d
228
-
- 3d2 (Only required on SoCs with two 3D clocks)
229
-
- mc
230
-
- mc2 (Only required on SoCs with two 3D clocks)
231
-
232
-
Optional properties:
233
-
- interconnects: Must contain entry for the GR3D memory clients.
234
-
- interconnect-names: Must include name of the interconnect path for each
235
-
interconnect entry. Consult TRM documentation for information about
236
-
available memory clients, see MEMORY CONTROLLER section.
237
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
238
-
- power-domains: Phandles to 3D or core power domain.
239
-
240
-
- dc: display controller
241
-
242
-
Required properties:
243
-
- compatible: "nvidia,tegra<chip>-dc"
244
-
- reg: Physical base address and length of the controller's registers.
245
-
- interrupts: The interrupt outputs from the controller.
246
-
- clocks: Must contain an entry for each entry in clock-names.
247
-
See ../clocks/clock-bindings.txt for details.
248
-
- clock-names: Must include the following entries:
249
-
- dc
250
-
This MUST be the first entry.
251
-
- parent
252
-
- resets: Must contain an entry for each entry in reset-names.
253
-
See ../reset/reset.txt for details.
254
-
- reset-names: Must include the following entries:
255
-
- dc
256
-
- nvidia,head: The number of the display controller head. This is used to
257
-
setup the various types of output to receive video data from the given
258
-
head.
259
-
260
-
Each display controller node has a child node, named "rgb", that represents
261
-
the RGB output associated with the controller. It can take the following
262
-
optional properties:
263
-
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
264
-
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
265
-
- nvidia,edid: supplies a binary EDID blob
266
-
- nvidia,panel: phandle of a display panel
267
-
- interconnects: Must contain entry for the DC memory clients.
268
-
- interconnect-names: Must include name of the interconnect path for each
269
-
interconnect entry. Consult TRM documentation for information about
270
-
available memory clients, see MEMORY CONTROLLER section.
271
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
272
-
- power-domains: Phandle to core power domain.
273
-
274
-
- hdmi: High Definition Multimedia Interface
275
-
276
-
Required properties:
277
-
- compatible: "nvidia,tegra<chip>-hdmi"
278
-
- reg: Physical base address and length of the controller's registers.
279
-
- interrupts: The interrupt outputs from the controller.
280
-
- hdmi-supply: supply for the +5V HDMI connector pin
281
-
- vdd-supply: regulator for supply voltage
282
-
- pll-supply: regulator for PLL
283
-
- clocks: Must contain an entry for each entry in clock-names.
284
-
See ../clocks/clock-bindings.txt for details.
285
-
- clock-names: Must include the following entries:
286
-
- hdmi
287
-
This MUST be the first entry.
288
-
- parent
289
-
- resets: Must contain an entry for each entry in reset-names.
290
-
See ../reset/reset.txt for details.
291
-
- reset-names: Must include the following entries:
292
-
- hdmi
293
-
294
-
Optional properties:
295
-
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
296
-
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
297
-
- nvidia,edid: supplies a binary EDID blob
298
-
- nvidia,panel: phandle of a display panel
299
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
300
-
301
-
- tvo: TV encoder output
302
-
303
-
Required properties:
304
-
- compatible: "nvidia,tegra<chip>-tvo"
305
-
- reg: Physical base address and length of the controller's registers.
306
-
- interrupts: The interrupt outputs from the controller.
307
-
- clocks: Must contain one entry, for the module clock.
308
-
See ../clocks/clock-bindings.txt for details.
309
-
310
-
Optional properties:
311
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
312
-
- power-domains: Phandle to core power domain.
313
-
314
-
- dsi: display serial interface
315
-
316
-
Required properties:
317
-
- compatible: "nvidia,tegra<chip>-dsi"
318
-
- reg: Physical base address and length of the controller's registers.
319
-
- clocks: Must contain an entry for each entry in clock-names.
320
-
See ../clocks/clock-bindings.txt for details.
321
-
- clock-names: Must include the following entries:
322
-
- dsi
323
-
This MUST be the first entry.
324
-
- lp
325
-
- parent
326
-
- resets: Must contain an entry for each entry in reset-names.
327
-
See ../reset/reset.txt for details.
328
-
- reset-names: Must include the following entries:
329
-
- dsi
330
-
- avdd-dsi-supply: phandle of a supply that powers the DSI controller
331
-
- nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
332
-
which pads are used by this DSI output and need to be calibrated. See also
333
-
../display/tegra/nvidia,tegra114-mipi.txt.
334
-
335
-
Optional properties:
336
-
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
337
-
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
338
-
- nvidia,edid: supplies a binary EDID blob
339
-
- nvidia,panel: phandle of a display panel
340
-
- nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
341
-
up with in order to support up to 8 data lanes
342
-
- operating-points-v2: See ../bindings/opp/opp.txt for details.
343
-
344
-
- sor: serial output resource
345
-
346
-
Required properties:
347
-
- compatible: Should be:
348
-
- "nvidia,tegra124-sor": for Tegra124 and Tegra132
349
-
- "nvidia,tegra132-sor": for Tegra132
350
-
- "nvidia,tegra210-sor": for Tegra210
351
-
- "nvidia,tegra210-sor1": for Tegra210
352
-
- "nvidia,tegra186-sor": for Tegra186
353
-
- "nvidia,tegra186-sor1": for Tegra186
354
-
- reg: Physical base address and length of the controller's registers.
355
-
- interrupts: The interrupt outputs from the controller.
356
-
- clocks: Must contain an entry for each entry in clock-names.
357
-
See ../clocks/clock-bindings.txt for details.
358
-
- clock-names: Must include the following entries:
359
-
- sor: clock input for the SOR hardware
360
-
- out: SOR output clock
361
-
- parent: input for the pixel clock
362
-
- dp: reference clock for the SOR clock
363
-
- safe: safe reference for the SOR clock during power up
364
-
365
-
For Tegra186 and later:
366
-
- pad: SOR pad output clock (on Tegra186 and later)
367
-
368
-
Obsolete:
369
-
- source: source clock for the SOR clock (obsolete, use "out" instead)
370
-
371
-
- resets: Must contain an entry for each entry in reset-names.
372
-
See ../reset/reset.txt for details.
373
-
- reset-names: Must include the following entries:
374
-
- sor
375
-
376
-
Required properties on Tegra186 and later:
377
-
- nvidia,interface: index of the SOR interface
378
-
379
-
Optional properties:
380
-
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
381
-
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
382
-
- nvidia,edid: supplies a binary EDID blob
383
-
- nvidia,panel: phandle of a display panel
384
-
- nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
385
-
of the SOR, identified by the cell's index, is mapped via the crossbar to
386
-
the pad specified by the cell's value.
387
-
388
-
Optional properties when driving an eDP output:
389
-
- nvidia,dpaux: phandle to a DispayPort AUX interface
390
-
391
-
- dpaux: DisplayPort AUX interface
392
-
- compatible : Should contain one of the following:
393
-
- "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
394
-
- "nvidia,tegra210-dpaux": for Tegra210
395
-
- reg: Physical base address and length of the controller's registers.
396
-
- interrupts: The interrupt outputs from the controller.
397
-
- clocks: Must contain an entry for each entry in clock-names.
398
-
See ../clocks/clock-bindings.txt for details.
399
-
- clock-names: Must include the following entries:
400
-
- dpaux: clock input for the DPAUX hardware
401
-
- parent: reference clock
402
-
- resets: Must contain an entry for each entry in reset-names.
403
-
See ../reset/reset.txt for details.
404
-
- reset-names: Must include the following entries:
405
-
- dpaux
406
-
- vdd-supply: phandle of a supply that powers the DisplayPort link
407
-
- i2c-bus: Subnode where I2C slave devices are listed. This subnode
408
-
must be always present. If there are no I2C slave devices, an empty
409
-
node should be added. See ../../i2c/i2c.txt for more information.
410
-
411
-
See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
412
-
regarding the DPAUX pad controller bindings.
413
-
414
-
- vic: Video Image Compositor
415
-
- compatible : "nvidia,tegra<chip>-vic"
416
-
- reg: Physical base address and length of the controller's registers.
417
-
- interrupts: The interrupt outputs from the controller.
418
-
- clocks: Must contain an entry for each entry in clock-names.
419
-
See ../clocks/clock-bindings.txt for details.
420
-
- clock-names: Must include the following entries:
421
-
- vic: clock input for the VIC hardware
422
-
- resets: Must contain an entry for each entry in reset-names.
423
-
See ../reset/reset.txt for details.
424
-
- reset-names: Must include the following entries:
425
-
- vic
426
-
427
-
Optional properties:
428
-
- interconnects: Must contain entry for the VIC memory clients.
429
-
- interconnect-names: Must include name of the interconnect path for each
430
-
interconnect entry. Consult TRM documentation for information about
431
-
available memory clients, see MEMORY CONTROLLER section.
432
-
433
-
Example:
434
-
435
-
/ {
436
-
...
437
-
438
-
host1x {
439
-
compatible = "nvidia,tegra20-host1x", "simple-bus";
440
-
reg = <0x50000000 0x00024000>;
441
-
interrupts = <0 65 0x04 /* mpcore syncpt */
442
-
0 67 0x04>; /* mpcore general */
443
-
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
444
-
resets = <&tegra_car 28>;
445
-
reset-names = "host1x";
446
-
operating-points-v2 = <&dvfs_opp_table>;
447
-
power-domains = <&domain>;
448
-
449
-
#address-cells = <1>;
450
-
#size-cells = <1>;
451
-
452
-
ranges = <0x54000000 0x54000000 0x04000000>;
453
-
454
-
mpe {
455
-
compatible = "nvidia,tegra20-mpe";
456
-
reg = <0x54040000 0x00040000>;
457
-
interrupts = <0 68 0x04>;
458
-
clocks = <&tegra_car TEGRA20_CLK_MPE>;
459
-
resets = <&tegra_car 60>;
460
-
reset-names = "mpe";
461
-
operating-points-v2 = <&dvfs_opp_table>;
462
-
power-domains = <&domain>;
463
-
};
464
-
465
-
vi@54080000 {
466
-
compatible = "nvidia,tegra210-vi";
467
-
reg = <0x0 0x54080000 0x0 0x700>;
468
-
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
469
-
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
470
-
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
471
-
operating-points-v2 = <&dvfs_opp_table>;
472
-
473
-
clocks = <&tegra_car TEGRA210_CLK_VI>;
474
-
power-domains = <&pd_venc>;
475
-
476
-
#address-cells = <1>;
477
-
#size-cells = <1>;
478
-
479
-
ranges = <0x0 0x0 0x54080000 0x2000>;
480
-
481
-
ports {
482
-
#address-cells = <1>;
483
-
#size-cells = <0>;
484
-
485
-
port@0 {
486
-
reg = <0>;
487
-
imx219_vi_in0: endpoint {
488
-
remote-endpoint = <&imx219_csi_out0>;
489
-
};
490
-
};
491
-
};
492
-
493
-
csi@838 {
494
-
compatible = "nvidia,tegra210-csi";
495
-
reg = <0x838 0x1300>;
496
-
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
497
-
<&tegra_car TEGRA210_CLK_CILCD>,
498
-
<&tegra_car TEGRA210_CLK_CILE>,
499
-
<&tegra_car TEGRA210_CLK_CSI_TPG>;
500
-
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
501
-
<&tegra_car TEGRA210_CLK_PLL_P>,
502
-
<&tegra_car TEGRA210_CLK_PLL_P>;
503
-
assigned-clock-rates = <102000000>,
504
-
<102000000>,
505
-
<102000000>,
506
-
<972000000>;
507
-
508
-
clocks = <&tegra_car TEGRA210_CLK_CSI>,
509
-
<&tegra_car TEGRA210_CLK_CILAB>,
510
-
<&tegra_car TEGRA210_CLK_CILCD>,
511
-
<&tegra_car TEGRA210_CLK_CILE>,
512
-
<&tegra_car TEGRA210_CLK_CSI_TPG>;
513
-
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
514
-
power-domains = <&pd_sor>;
515
-
516
-
#address-cells = <1>;
517
-
#size-cells = <0>;
518
-
519
-
channel@0 {
520
-
reg = <0>;
521
-
nvidia,mipi-calibrate = <&mipi 0x001>;
522
-
523
-
ports {
524
-
#address-cells = <1>;
525
-
#size-cells = <0>;
526
-
527
-
port@0 {
528
-
reg = <0>;
529
-
imx219_csi_in0: endpoint {
530
-
data-lanes = <1 2>;
531
-
remote-endpoint = <&imx219_out0>;
532
-
};
533
-
};
534
-
535
-
port@1 {
536
-
reg = <1>;
537
-
imx219_csi_out0: endpoint {
538
-
remote-endpoint = <&imx219_vi_in0>;
539
-
};
540
-
};
541
-
};
542
-
};
543
-
};
544
-
};
545
-
546
-
epp {
547
-
compatible = "nvidia,tegra20-epp";
548
-
reg = <0x540c0000 0x00040000>;
549
-
interrupts = <0 70 0x04>;
550
-
clocks = <&tegra_car TEGRA20_CLK_EPP>;
551
-
resets = <&tegra_car 19>;
552
-
reset-names = "epp";
553
-
operating-points-v2 = <&dvfs_opp_table>;
554
-
power-domains = <&domain>;
555
-
};
556
-
557
-
isp {
558
-
compatible = "nvidia,tegra20-isp";
559
-
reg = <0x54100000 0x00040000>;
560
-
interrupts = <0 71 0x04>;
561
-
clocks = <&tegra_car TEGRA20_CLK_ISP>;
562
-
resets = <&tegra_car 23>;
563
-
reset-names = "isp";
564
-
};
565
-
566
-
gr2d {
567
-
compatible = "nvidia,tegra20-gr2d";
568
-
reg = <0x54140000 0x00040000>;
569
-
interrupts = <0 72 0x04>;
570
-
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
571
-
resets = <&tegra_car 21>;
572
-
reset-names = "2d";
573
-
operating-points-v2 = <&dvfs_opp_table>;
574
-
power-domains = <&domain>;
575
-
};
576
-
577
-
gr3d {
578
-
compatible = "nvidia,tegra20-gr3d";
579
-
reg = <0x54180000 0x00040000>;
580
-
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
581
-
resets = <&tegra_car 24>;
582
-
reset-names = "3d";
583
-
operating-points-v2 = <&dvfs_opp_table>;
584
-
power-domains = <&domain>;
585
-
};
586
-
587
-
dc@54200000 {
588
-
compatible = "nvidia,tegra20-dc";
589
-
reg = <0x54200000 0x00040000>;
590
-
interrupts = <0 73 0x04>;
591
-
clocks = <&tegra_car TEGRA20_CLK_DISP1>,
592
-
<&tegra_car TEGRA20_CLK_PLL_P>;
593
-
clock-names = "dc", "parent";
594
-
resets = <&tegra_car 27>;
595
-
reset-names = "dc";
596
-
operating-points-v2 = <&dvfs_opp_table>;
597
-
power-domains = <&domain>;
598
-
599
-
interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
600
-
<&mc TEGRA20_MC_DISPLAY0B &emc>,
601
-
<&mc TEGRA20_MC_DISPLAY0C &emc>,
602
-
<&mc TEGRA20_MC_DISPLAYHC &emc>;
603
-
interconnect-names = "wina",
604
-
"winb",
605
-
"winc",
606
-
"cursor";
607
-
608
-
rgb {
609
-
status = "disabled";
610
-
};
611
-
};
612
-
613
-
dc@54240000 {
614
-
compatible = "nvidia,tegra20-dc";
615
-
reg = <0x54240000 0x00040000>;
616
-
interrupts = <0 74 0x04>;
617
-
clocks = <&tegra_car TEGRA20_CLK_DISP2>,
618
-
<&tegra_car TEGRA20_CLK_PLL_P>;
619
-
clock-names = "dc", "parent";
620
-
resets = <&tegra_car 26>;
621
-
reset-names = "dc";
622
-
operating-points-v2 = <&dvfs_opp_table>;
623
-
power-domains = <&domain>;
624
-
625
-
interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
626
-
<&mc TEGRA20_MC_DISPLAY0BB &emc>,
627
-
<&mc TEGRA20_MC_DISPLAY0CB &emc>,
628
-
<&mc TEGRA20_MC_DISPLAYHCB &emc>;
629
-
interconnect-names = "wina",
630
-
"winb",
631
-
"winc",
632
-
"cursor";
633
-
634
-
rgb {
635
-
status = "disabled";
636
-
};
637
-
};
638
-
639
-
hdmi {
640
-
compatible = "nvidia,tegra20-hdmi";
641
-
reg = <0x54280000 0x00040000>;
642
-
interrupts = <0 75 0x04>;
643
-
clocks = <&tegra_car TEGRA20_CLK_HDMI>,
644
-
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
645
-
clock-names = "hdmi", "parent";
646
-
resets = <&tegra_car 51>;
647
-
reset-names = "hdmi";
648
-
status = "disabled";
649
-
operating-points-v2 = <&dvfs_opp_table>;
650
-
};
651
-
652
-
tvo {
653
-
compatible = "nvidia,tegra20-tvo";
654
-
reg = <0x542c0000 0x00040000>;
655
-
interrupts = <0 76 0x04>;
656
-
clocks = <&tegra_car TEGRA20_CLK_TVO>;
657
-
status = "disabled";
658
-
operating-points-v2 = <&dvfs_opp_table>;
659
-
};
660
-
661
-
dsi {
662
-
compatible = "nvidia,tegra20-dsi";
663
-
reg = <0x54300000 0x00040000>;
664
-
clocks = <&tegra_car TEGRA20_CLK_DSI>,
665
-
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
666
-
clock-names = "dsi", "parent";
667
-
resets = <&tegra_car 48>;
668
-
reset-names = "dsi";
669
-
status = "disabled";
670
-
operating-points-v2 = <&dvfs_opp_table>;
671
-
};
672
-
};
673
-
674
-
...
675
-
};
+431
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
+431
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra host1x controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description: The host1x top-level node defines a number of children, each
14
+
representing one of the host1x client modules defined in this binding.
15
+
16
+
properties:
17
+
compatible:
18
+
oneOf:
19
+
- enum:
20
+
- nvidia,tegra20-host1x
21
+
- nvidia,tegra30-host1x
22
+
- nvidia,tegra114-host1x
23
+
- nvidia,tegra124-host1x
24
+
- nvidia,tegra210-host1x
25
+
- nvidia,tegra186-host1x
26
+
- nvidia,tegra194-host1x
27
+
- nvidia,tegra234-host1x
28
+
29
+
- items:
30
+
- const: nvidia,tegra132-host1x
31
+
- const: nvidia,tegra124-host1x
32
+
33
+
reg:
34
+
minItems: 1
35
+
maxItems: 3
36
+
37
+
reg-names:
38
+
minItems: 1
39
+
maxItems: 3
40
+
41
+
interrupts:
42
+
minItems: 1
43
+
maxItems: 9
44
+
45
+
interrupt-names:
46
+
minItems: 1
47
+
maxItems: 9
48
+
49
+
'#address-cells':
50
+
description: The number of cells used to represent physical base addresses
51
+
in the host1x address space.
52
+
enum: [1, 2]
53
+
54
+
'#size-cells':
55
+
description: The number of cells used to represent the size of an address
56
+
range in the host1x address space.
57
+
enum: [1, 2]
58
+
59
+
ranges:
60
+
maxItems: 1
61
+
62
+
clocks:
63
+
description: Must contain one entry, for the module clock. See
64
+
../clocks/clock-bindings.txt for details.
65
+
66
+
clock-names:
67
+
items:
68
+
- const: host1x
69
+
70
+
resets:
71
+
minItems: 1 # MC reset is optional on Tegra186 and later
72
+
items:
73
+
- description: module reset
74
+
- description: memory client hotflush reset
75
+
76
+
reset-names:
77
+
minItems: 1 # MC reset is optional on Tegra186 and later
78
+
items:
79
+
- const: host1x
80
+
- const: mc
81
+
82
+
iommus:
83
+
maxItems: 1
84
+
85
+
interconnects:
86
+
items:
87
+
- description: memory read client for host1x
88
+
89
+
interconnect-names:
90
+
items:
91
+
- const: dma-mem # read
92
+
93
+
operating-points-v2:
94
+
$ref: "/schemas/types.yaml#/definitions/phandle"
95
+
96
+
power-domains:
97
+
items:
98
+
- description: phandle to the HEG or core power domain
99
+
100
+
required:
101
+
- compatible
102
+
- interrupts
103
+
- interrupt-names
104
+
- '#address-cells'
105
+
- '#size-cells'
106
+
- ranges
107
+
- reg
108
+
- clocks
109
+
- clock-names
110
+
111
+
unevaluatedProperties:
112
+
type: object
113
+
114
+
allOf:
115
+
- if:
116
+
properties:
117
+
compatible:
118
+
contains:
119
+
enum:
120
+
- nvidia,tegra20-host1x
121
+
- nvidia,tegra30-host1x
122
+
- nvidia,tegra114-host1x
123
+
- nvidia,tegra124-host1x
124
+
- nvidia,tegra210-host1x
125
+
then:
126
+
properties:
127
+
interrupts:
128
+
items:
129
+
- description: host1x syncpoint interrupt
130
+
- description: host1x general interrupt
131
+
132
+
interrupt-names:
133
+
items:
134
+
- const: syncpt
135
+
- const: host1x
136
+
required:
137
+
- resets
138
+
- reset-names
139
+
- if:
140
+
properties:
141
+
compatible:
142
+
contains:
143
+
enum:
144
+
- nvidia,tegra186-host1x
145
+
- nvidia,tegra194-host1x
146
+
then:
147
+
properties:
148
+
reg-names:
149
+
items:
150
+
- const: hypervisor
151
+
- const: vm
152
+
153
+
reg:
154
+
items:
155
+
- description: region used by the hypervisor
156
+
- description: region assigned to the virtual machine
157
+
158
+
resets:
159
+
maxItems: 1
160
+
161
+
reset-names:
162
+
maxItems: 1
163
+
164
+
interrupts:
165
+
items:
166
+
- description: host1x syncpoint interrupt
167
+
- description: host1x general interrupt
168
+
169
+
interrupt-names:
170
+
items:
171
+
- const: syncpt
172
+
- const: host1x
173
+
174
+
iommu-map:
175
+
description: Specification of stream IDs available for memory context device
176
+
use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
177
+
usable stream IDs.
178
+
179
+
required:
180
+
- reg-names
181
+
- if:
182
+
properties:
183
+
compatible:
184
+
contains:
185
+
enum:
186
+
- nvidia,tegra234-host1x
187
+
then:
188
+
properties:
189
+
reg-names:
190
+
items:
191
+
- const: common
192
+
- const: hypervisor
193
+
- const: vm
194
+
195
+
reg:
196
+
items:
197
+
- description: region used by host1x server
198
+
- description: region used by the hypervisor
199
+
- description: region assigned to the virtual machine
200
+
201
+
interrupts:
202
+
items:
203
+
- description: host1x syncpoint interrupt 0
204
+
- description: host1x syncpoint interrupt 1
205
+
- description: host1x syncpoint interrupt 2
206
+
- description: host1x syncpoint interrupt 3
207
+
- description: host1x syncpoint interrupt 4
208
+
- description: host1x syncpoint interrupt 5
209
+
- description: host1x syncpoint interrupt 6
210
+
- description: host1x syncpoint interrupt 7
211
+
- description: host1x general interrupt
212
+
213
+
interrupt-names:
214
+
items:
215
+
- const: syncpt0
216
+
- const: syncpt1
217
+
- const: syncpt2
218
+
- const: syncpt3
219
+
- const: syncpt4
220
+
- const: syncpt5
221
+
- const: syncpt6
222
+
- const: syncpt7
223
+
- const: host1x
224
+
225
+
iommu-map:
226
+
description: Specification of stream IDs available for memory context device
227
+
use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
228
+
usable stream IDs.
229
+
230
+
required:
231
+
- reg-names
232
+
233
+
examples:
234
+
- |
235
+
#include <dt-bindings/clock/tegra20-car.h>
236
+
#include <dt-bindings/gpio/tegra-gpio.h>
237
+
#include <dt-bindings/memory/tegra20-mc.h>
238
+
239
+
host1x@50000000 {
240
+
compatible = "nvidia,tegra20-host1x";
241
+
reg = <0x50000000 0x00024000>;
242
+
interrupts = <0 65 0x04>, /* mpcore syncpt */
243
+
<0 67 0x04>; /* mpcore general */
244
+
interrupt-names = "syncpt", "host1x";
245
+
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
246
+
clock-names = "host1x";
247
+
resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
248
+
reset-names = "host1x", "mc";
249
+
250
+
#address-cells = <1>;
251
+
#size-cells = <1>;
252
+
253
+
ranges = <0x54000000 0x54000000 0x04000000>;
254
+
255
+
mpe@54040000 {
256
+
compatible = "nvidia,tegra20-mpe";
257
+
reg = <0x54040000 0x00040000>;
258
+
interrupts = <0 68 0x04>;
259
+
clocks = <&tegra_car TEGRA20_CLK_MPE>;
260
+
resets = <&tegra_car 60>;
261
+
reset-names = "mpe";
262
+
};
263
+
264
+
vi@54080000 {
265
+
compatible = "nvidia,tegra20-vi";
266
+
reg = <0x54080000 0x00040000>;
267
+
interrupts = <0 69 0x04>;
268
+
clocks = <&tegra_car TEGRA20_CLK_VI>;
269
+
resets = <&tegra_car 100>;
270
+
reset-names = "vi";
271
+
};
272
+
273
+
epp@540c0000 {
274
+
compatible = "nvidia,tegra20-epp";
275
+
reg = <0x540c0000 0x00040000>;
276
+
interrupts = <0 70 0x04>;
277
+
clocks = <&tegra_car TEGRA20_CLK_EPP>;
278
+
resets = <&tegra_car 19>;
279
+
reset-names = "epp";
280
+
};
281
+
282
+
isp@54100000 {
283
+
compatible = "nvidia,tegra20-isp";
284
+
reg = <0x54100000 0x00040000>;
285
+
interrupts = <0 71 0x04>;
286
+
clocks = <&tegra_car TEGRA20_CLK_ISP>;
287
+
resets = <&tegra_car 23>;
288
+
reset-names = "isp";
289
+
};
290
+
291
+
gr2d@54140000 {
292
+
compatible = "nvidia,tegra20-gr2d";
293
+
reg = <0x54140000 0x00040000>;
294
+
interrupts = <0 72 0x04>;
295
+
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
296
+
resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
297
+
reset-names = "2d", "mc";
298
+
};
299
+
300
+
gr3d@54180000 {
301
+
compatible = "nvidia,tegra20-gr3d";
302
+
reg = <0x54180000 0x00040000>;
303
+
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
304
+
resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
305
+
reset-names = "3d", "mc";
306
+
};
307
+
308
+
dc@54200000 {
309
+
compatible = "nvidia,tegra20-dc";
310
+
reg = <0x54200000 0x00040000>;
311
+
interrupts = <0 73 0x04>;
312
+
clocks = <&tegra_car TEGRA20_CLK_DISP1>;
313
+
clock-names = "dc";
314
+
resets = <&tegra_car 27>;
315
+
reset-names = "dc";
316
+
317
+
rgb {
318
+
};
319
+
};
320
+
321
+
dc@54240000 {
322
+
compatible = "nvidia,tegra20-dc";
323
+
reg = <0x54240000 0x00040000>;
324
+
interrupts = <0 74 0x04>;
325
+
clocks = <&tegra_car TEGRA20_CLK_DISP2>;
326
+
clock-names = "dc";
327
+
resets = <&tegra_car 26>;
328
+
reset-names = "dc";
329
+
330
+
rgb {
331
+
};
332
+
};
333
+
334
+
hdmi@54280000 {
335
+
compatible = "nvidia,tegra20-hdmi";
336
+
reg = <0x54280000 0x00040000>;
337
+
interrupts = <0 75 0x04>;
338
+
clocks = <&tegra_car TEGRA20_CLK_HDMI>,
339
+
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
340
+
clock-names = "hdmi", "parent";
341
+
resets = <&tegra_car 51>;
342
+
reset-names = "hdmi";
343
+
344
+
hdmi-supply = <&vdd_5v0_hdmi>;
345
+
pll-supply = <&vdd_hdmi_pll>;
346
+
vdd-supply = <&vdd_3v3_hdmi>;
347
+
348
+
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
349
+
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
350
+
};
351
+
352
+
tvo@542c0000 {
353
+
compatible = "nvidia,tegra20-tvo";
354
+
reg = <0x542c0000 0x00040000>;
355
+
interrupts = <0 76 0x04>;
356
+
clocks = <&tegra_car TEGRA20_CLK_TVO>;
357
+
};
358
+
359
+
dsi@54300000 {
360
+
compatible = "nvidia,tegra20-dsi";
361
+
reg = <0x54300000 0x00040000>;
362
+
clocks = <&tegra_car TEGRA20_CLK_DSI>,
363
+
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
364
+
clock-names = "dsi", "parent";
365
+
resets = <&tegra_car 48>;
366
+
reset-names = "dsi";
367
+
};
368
+
};
369
+
370
+
- |
371
+
#include <dt-bindings/clock/tegra210-car.h>
372
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
373
+
#include <dt-bindings/memory/tegra210-mc.h>
374
+
375
+
host1x@50000000 {
376
+
compatible = "nvidia,tegra210-host1x";
377
+
reg = <0x50000000 0x00024000>;
378
+
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
379
+
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
380
+
interrupt-names = "syncpt", "host1x";
381
+
clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
382
+
clock-names = "host1x";
383
+
resets = <&tegra_car 28>;
384
+
reset-names = "host1x";
385
+
386
+
#address-cells = <1>;
387
+
#size-cells = <1>;
388
+
389
+
ranges = <0x54000000 0x54000000 0x01000000>;
390
+
iommus = <&mc TEGRA_SWGROUP_HC>;
391
+
392
+
vi@54080000 {
393
+
compatible = "nvidia,tegra210-vi";
394
+
reg = <0x54080000 0x00000700>;
395
+
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
396
+
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
397
+
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
398
+
399
+
clocks = <&tegra_car TEGRA210_CLK_VI>;
400
+
power-domains = <&pd_venc>;
401
+
402
+
#address-cells = <1>;
403
+
#size-cells = <1>;
404
+
405
+
ranges = <0x0 0x54080000 0x2000>;
406
+
407
+
csi@838 {
408
+
compatible = "nvidia,tegra210-csi";
409
+
reg = <0x838 0x1300>;
410
+
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
411
+
<&tegra_car TEGRA210_CLK_CILCD>,
412
+
<&tegra_car TEGRA210_CLK_CILE>,
413
+
<&tegra_car TEGRA210_CLK_CSI_TPG>;
414
+
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
415
+
<&tegra_car TEGRA210_CLK_PLL_P>,
416
+
<&tegra_car TEGRA210_CLK_PLL_P>;
417
+
assigned-clock-rates = <102000000>,
418
+
<102000000>,
419
+
<102000000>,
420
+
<972000000>;
421
+
422
+
clocks = <&tegra_car TEGRA210_CLK_CSI>,
423
+
<&tegra_car TEGRA210_CLK_CILAB>,
424
+
<&tegra_car TEGRA210_CLK_CILCD>,
425
+
<&tegra_car TEGRA210_CLK_CILE>,
426
+
<&tegra_car TEGRA210_CLK_CSI_TPG>;
427
+
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
428
+
power-domains = <&pd_sor>;
429
+
};
430
+
};
431
+
};
+67
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
+67
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra ISP processor
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- nvidia,tegra20-isp
17
+
- nvidia,tegra30-isp
18
+
- nvidia,tegra210-isp
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: module clock
29
+
30
+
resets:
31
+
items:
32
+
- description: module reset
33
+
34
+
reset-names:
35
+
items:
36
+
- const: isp
37
+
38
+
iommus:
39
+
maxItems: 1
40
+
41
+
interconnects:
42
+
items:
43
+
- description: memory write client
44
+
45
+
interconnect-names:
46
+
items:
47
+
- const: dma-mem # write
48
+
49
+
power-domains:
50
+
items:
51
+
- description: phandle to the VENC or core power domain
52
+
53
+
additionalProperties: false
54
+
55
+
examples:
56
+
- |
57
+
#include <dt-bindings/clock/tegra20-car.h>
58
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
59
+
60
+
isp@54100000 {
61
+
compatible = "nvidia,tegra20-isp";
62
+
reg = <0x54100000 0x00040000>;
63
+
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
64
+
clocks = <&tegra_car TEGRA20_CLK_ISP>;
65
+
resets = <&tegra_car 23>;
66
+
reset-names = "isp";
67
+
};
+73
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
+73
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Video Encoder
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^mpe@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra20-mpe
20
+
- nvidia,tegra30-mpe
21
+
- nvidia,tegra114-mpe
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
items:
31
+
- description: module clock
32
+
33
+
resets:
34
+
items:
35
+
- description: module reset
36
+
37
+
reset-names:
38
+
items:
39
+
- const: mpe
40
+
41
+
iommus:
42
+
maxItems: 1
43
+
44
+
interconnects:
45
+
minItems: 6
46
+
maxItems: 6
47
+
48
+
interconnect-names:
49
+
minItems: 6
50
+
maxItems: 6
51
+
52
+
operating-points-v2:
53
+
$ref: "/schemas/types.yaml#/definitions/phandle"
54
+
55
+
power-domains:
56
+
items:
57
+
- description: phandle to the MPE power domain
58
+
59
+
additionalProperties: false
60
+
61
+
examples:
62
+
- |
63
+
#include <dt-bindings/clock/tegra20-car.h>
64
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
65
+
66
+
mpe@54040000 {
67
+
compatible = "nvidia,tegra20-mpe";
68
+
reg = <0x54040000 0x00040000>;
69
+
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
70
+
clocks = <&tegra_car TEGRA20_CLK_MPE>;
71
+
resets = <&tegra_car 60>;
72
+
reset-names = "mpe";
73
+
};
+58
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
+58
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra TV Encoder Output
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^tvo@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra20-tvo
20
+
- nvidia,tegra30-tvo
21
+
- nvidia,tegra114-tvo
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
items:
31
+
- description: module clock
32
+
33
+
operating-points-v2:
34
+
$ref: "/schemas/types.yaml#/definitions/phandle"
35
+
36
+
power-domains:
37
+
items:
38
+
- description: phandle to the core power domain
39
+
40
+
additionalProperties: false
41
+
42
+
required:
43
+
- compatible
44
+
- reg
45
+
- interrupts
46
+
- clocks
47
+
48
+
examples:
49
+
- |
50
+
#include <dt-bindings/clock/tegra20-car.h>
51
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
52
+
53
+
tvo@542c0000 {
54
+
compatible = "nvidia,tegra20-tvo";
55
+
reg = <0x542c0000 0x00040000>;
56
+
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
57
+
clocks = <&tegra_car TEGRA20_CLK_TVO>;
58
+
};
+163
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
+163
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Video Input controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^vi@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
oneOf:
19
+
- const: nvidia,tegra20-vi
20
+
- const: nvidia,tegra30-vi
21
+
- const: nvidia,tegra114-vi
22
+
- const: nvidia,tegra124-vi
23
+
- items:
24
+
- const: nvidia,tegra132-vi
25
+
- const: nvidia,tegra124-vi
26
+
- const: nvidia,tegra210-vi
27
+
- const: nvidia,tegra186-vi
28
+
- const: nvidia,tegra194-vi
29
+
30
+
reg:
31
+
maxItems: 1
32
+
33
+
interrupts:
34
+
maxItems: 1
35
+
36
+
clocks:
37
+
maxItems: 1
38
+
39
+
resets:
40
+
items:
41
+
- description: module reset
42
+
43
+
reset-names:
44
+
items:
45
+
- const: vi
46
+
47
+
iommus:
48
+
maxItems: 1
49
+
50
+
interconnects:
51
+
minItems: 4
52
+
maxItems: 5
53
+
54
+
interconnect-names:
55
+
minItems: 4
56
+
maxItems: 5
57
+
58
+
operating-points-v2:
59
+
$ref: "/schemas/types.yaml#/definitions/phandle"
60
+
61
+
power-domains:
62
+
items:
63
+
- description: phandle to the VENC power domain
64
+
65
+
"#address-cells":
66
+
const: 1
67
+
68
+
"#size-cells":
69
+
const: 1
70
+
71
+
ranges:
72
+
maxItems: 1
73
+
74
+
avdd-dsi-csi-supply:
75
+
description: DSI/CSI power supply. Must supply 1.2 V.
76
+
77
+
patternProperties:
78
+
"^csi@[0-9a-f]+$":
79
+
type: object
80
+
81
+
additionalProperties: false
82
+
83
+
required:
84
+
- compatible
85
+
- reg
86
+
- interrupts
87
+
- clocks
88
+
89
+
allOf:
90
+
- if:
91
+
properties:
92
+
compatible:
93
+
contains:
94
+
enum:
95
+
- nvidia,tegra20-vi
96
+
- nvidia,tegra30-vi
97
+
- nvidia,tegra114-vi
98
+
- nvidia,tegra124-vi
99
+
then:
100
+
required:
101
+
- resets
102
+
- reset-names
103
+
else:
104
+
required:
105
+
- power-domains
106
+
107
+
examples:
108
+
- |
109
+
#include <dt-bindings/clock/tegra20-car.h>
110
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
111
+
112
+
vi@54080000 {
113
+
compatible = "nvidia,tegra20-vi";
114
+
reg = <0x54080000 0x00040000>;
115
+
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
116
+
clocks = <&tegra_car TEGRA20_CLK_VI>;
117
+
resets = <&tegra_car 100>;
118
+
reset-names = "vi";
119
+
};
120
+
121
+
- |
122
+
#include <dt-bindings/clock/tegra210-car.h>
123
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
124
+
125
+
vi@54080000 {
126
+
compatible = "nvidia,tegra210-vi";
127
+
reg = <0x54080000 0x00000700>;
128
+
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
129
+
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
130
+
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
131
+
132
+
clocks = <&tegra_car TEGRA210_CLK_VI>;
133
+
power-domains = <&pd_venc>;
134
+
135
+
#address-cells = <1>;
136
+
#size-cells = <1>;
137
+
138
+
ranges = <0x0 0x54080000 0x2000>;
139
+
140
+
csi@838 {
141
+
compatible = "nvidia,tegra210-csi";
142
+
reg = <0x838 0x1300>;
143
+
assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
144
+
<&tegra_car TEGRA210_CLK_CILCD>,
145
+
<&tegra_car TEGRA210_CLK_CILE>,
146
+
<&tegra_car TEGRA210_CLK_CSI_TPG>;
147
+
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
148
+
<&tegra_car TEGRA210_CLK_PLL_P>,
149
+
<&tegra_car TEGRA210_CLK_PLL_P>;
150
+
assigned-clock-rates = <102000000>,
151
+
<102000000>,
152
+
<102000000>,
153
+
<972000000>;
154
+
155
+
clocks = <&tegra_car TEGRA210_CLK_CSI>,
156
+
<&tegra_car TEGRA210_CLK_CILAB>,
157
+
<&tegra_car TEGRA210_CLK_CILCD>,
158
+
<&tegra_car TEGRA210_CLK_CILE>,
159
+
<&tegra_car TEGRA210_CLK_CSI_TPG>;
160
+
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
161
+
power-domains = <&pd_sor>;
162
+
};
163
+
};
+52
Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
+52
Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra CSI controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
$nodename:
15
+
pattern: "^csi@[0-9a-f]+$"
16
+
17
+
compatible:
18
+
enum:
19
+
- nvidia,tegra210-csi
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
clocks:
25
+
items:
26
+
- description: module clock
27
+
- description: A/B lanes clock
28
+
- description: C/D lanes clock
29
+
- description: E lane clock
30
+
- description: test pattern generator clock
31
+
32
+
clock-names:
33
+
items:
34
+
- const: csi
35
+
- const: cilab
36
+
- const: cilcd
37
+
- const: cile
38
+
- const: csi_tpg
39
+
40
+
power-domains:
41
+
maxItems: 1
42
+
43
+
additionalProperties: false
44
+
45
+
required:
46
+
- compatible
47
+
- reg
48
+
- clocks
49
+
- clock-names
50
+
- power-domains
51
+
52
+
# see nvidia,tegra20-vi.yaml for an example
-59
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
-59
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
···
1
-
Device tree binding for NVIDIA Tegra DPAUX pad controller
2
-
========================================================
3
-
4
-
The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins
5
-
which can be assigned to either the DPAUX channel or to an I2C
6
-
controller.
7
-
8
-
This document defines the device-specific binding for the DPAUX pad
9
-
controller. Refer to pinctrl-bindings.txt in this directory for generic
10
-
information about pin controller device tree bindings. Please refer to
11
-
the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more
12
-
details on the DPAUX binding.
13
-
14
-
Pin muxing:
15
-
-----------
16
-
17
-
Child nodes contain the pinmux configurations following the conventions
18
-
from the pinctrl-bindings.txt document.
19
-
20
-
Since only three configurations are possible, only three child nodes are
21
-
needed to describe the pin mux'ing options for the DPAUX pads.
22
-
Furthermore, given that the pad functions are only applicable to a
23
-
single set of pads, the child nodes only need to describe the pad group
24
-
the functions are being applied to rather than the individual pads.
25
-
26
-
Required properties:
27
-
- groups: Must be "dpaux-io"
28
-
- function: Must be either "aux", "i2c" or "off".
29
-
30
-
Example:
31
-
--------
32
-
33
-
dpaux@545c0000 {
34
-
...
35
-
36
-
state_dpaux_aux: pinmux-aux {
37
-
groups = "dpaux-io";
38
-
function = "aux";
39
-
};
40
-
41
-
state_dpaux_i2c: pinmux-i2c {
42
-
groups = "dpaux-io";
43
-
function = "i2c";
44
-
};
45
-
46
-
state_dpaux_off: pinmux-off {
47
-
groups = "dpaux-io";
48
-
function = "off";
49
-
};
50
-
};
51
-
52
-
...
53
-
54
-
i2c@7000d100 {
55
-
...
56
-
pinctrl-0 = <&state_dpaux_i2c>;
57
-
pinctrl-1 = <&state_dpaux_off>;
58
-
pinctrl-names = "default", "idle";
59
-
};
+2
-2
MAINTAINERS
+2
-2
MAINTAINERS
···
6748
6748
L: linux-tegra@vger.kernel.org
6749
6749
S: Supported
6750
6750
T: git git://anongit.freedesktop.org/tegra/linux.git
6751
-
F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
6751
+
F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
6752
6752
F: Documentation/devicetree/bindings/gpu/host1x/
6753
6753
F: drivers/gpu/drm/tegra/
6754
6754
F: drivers/gpu/host1x/
···
19682
19682
L: linux-media@vger.kernel.org
19683
19683
L: linux-tegra@vger.kernel.org
19684
19684
S: Maintained
19685
-
F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
19685
+
F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
19686
19686
F: drivers/staging/media/tegra-video/
19687
19687
19688
19688
TEGRA XUSB PADCTL DRIVER
+1
drivers/gpu/drm/tegra/dc.c
+1
drivers/gpu/drm/tegra/dc.c
+1
drivers/gpu/drm/tegra/drm.c
+1
drivers/gpu/drm/tegra/drm.c
+11
drivers/gpu/drm/tegra/drm.h
+11
drivers/gpu/drm/tegra/drm.h
···
80
80
81
81
/* Only used by new UAPI. */
82
82
struct xarray mappings;
83
+
struct host1x_memory_context *memory_context;
83
84
};
84
85
85
86
struct tegra_drm_client_ops {
···
92
91
int (*submit)(struct tegra_drm_context *context,
93
92
struct drm_tegra_submit *args, struct drm_device *drm,
94
93
struct drm_file *file);
94
+
int (*get_streamid_offset)(struct tegra_drm_client *client, u32 *offset);
95
+
int (*can_use_memory_ctx)(struct tegra_drm_client *client, bool *supported);
95
96
};
96
97
97
98
int tegra_drm_submit(struct tegra_drm_context *context,
98
99
struct drm_tegra_submit *args, struct drm_device *drm,
99
100
struct drm_file *file);
101
+
102
+
static inline int
103
+
tegra_drm_get_streamid_offset_thi(struct tegra_drm_client *client, u32 *offset)
104
+
{
105
+
*offset = 0x30;
106
+
107
+
return 0;
108
+
}
100
109
101
110
struct tegra_drm_client {
102
111
struct host1x_client base;
+8
drivers/gpu/drm/tegra/falcon.c
+8
drivers/gpu/drm/tegra/falcon.c
···
48
48
if (target == FALCON_MEMORY_IMEM)
49
49
cmd |= FALCON_DMATRFCMD_IMEM;
50
50
51
+
/*
52
+
* Use second DMA context (i.e. the one for firmware). Strictly
53
+
* speaking, at this point both DMA contexts point to the firmware
54
+
* stream ID, but this register's value will be reused by the firmware
55
+
* for later DMA transactions, so we need to use the correct value.
56
+
*/
57
+
cmd |= FALCON_DMATRFCMD_DMACTX(1);
58
+
51
59
falcon_writel(falcon, offset, FALCON_DMATRFMOFFS);
52
60
falcon_writel(falcon, base, FALCON_DMATRFFBOFFS);
53
61
falcon_writel(falcon, cmd, FALCON_DMATRFCMD);
+1
drivers/gpu/drm/tegra/falcon.h
+1
drivers/gpu/drm/tegra/falcon.h
+10
-1
drivers/gpu/drm/tegra/gem.c
+10
-1
drivers/gpu/drm/tegra/gem.c
···
704
704
{
705
705
struct drm_gem_object *gem = buf->priv;
706
706
struct tegra_bo *bo = to_tegra_bo(gem);
707
+
void *vaddr;
707
708
708
-
iosys_map_set_vaddr(map, bo->vaddr);
709
+
vaddr = tegra_bo_mmap(&bo->base);
710
+
if (IS_ERR(vaddr))
711
+
return PTR_ERR(vaddr);
712
+
713
+
iosys_map_set_vaddr(map, vaddr);
709
714
710
715
return 0;
711
716
}
712
717
713
718
static void tegra_gem_prime_vunmap(struct dma_buf *buf, struct iosys_map *map)
714
719
{
720
+
struct drm_gem_object *gem = buf->priv;
721
+
struct tegra_bo *bo = to_tegra_bo(gem);
722
+
723
+
tegra_bo_munmap(&bo->base, map->vaddr);
715
724
}
716
725
717
726
static const struct dma_buf_ops tegra_gem_prime_dmabuf_ops = {
+1
drivers/gpu/drm/tegra/hub.c
+1
drivers/gpu/drm/tegra/hub.c
+13
-1
drivers/gpu/drm/tegra/nvdec.c
+13
-1
drivers/gpu/drm/tegra/nvdec.c
···
5
5
6
6
#include <linux/clk.h>
7
7
#include <linux/delay.h>
8
+
#include <linux/dma-mapping.h>
8
9
#include <linux/host1x.h>
9
10
#include <linux/iommu.h>
10
11
#include <linux/module.h>
···
21
20
#include "drm.h"
22
21
#include "falcon.h"
23
22
#include "vic.h"
23
+
24
+
#define NVDEC_TFBIF_TRANSCFG 0x2c44
24
25
25
26
struct nvdec_config {
26
27
const char *firmware;
···
66
63
u32 value;
67
64
68
65
value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | TRANSCFG_ATT(0, TRANSCFG_SID_HW);
69
-
nvdec_writel(nvdec, value, VIC_TFBIF_TRANSCFG);
66
+
nvdec_writel(nvdec, value, NVDEC_TFBIF_TRANSCFG);
70
67
71
68
if (spec->num_ids > 0) {
72
69
value = spec->ids[0] & 0xffff;
···
307
304
host1x_channel_put(context->channel);
308
305
}
309
306
307
+
static int nvdec_can_use_memory_ctx(struct tegra_drm_client *client, bool *supported)
308
+
{
309
+
*supported = true;
310
+
311
+
return 0;
312
+
}
313
+
310
314
static const struct tegra_drm_client_ops nvdec_ops = {
311
315
.open_channel = nvdec_open_channel,
312
316
.close_channel = nvdec_close_channel,
313
317
.submit = tegra_drm_submit,
318
+
.get_streamid_offset = tegra_drm_get_streamid_offset_thi,
319
+
.can_use_memory_ctx = nvdec_can_use_memory_ctx,
314
320
};
315
321
316
322
#define NVIDIA_TEGRA_210_NVDEC_FIRMWARE "nvidia/tegra210/nvdec.bin"
+1
drivers/gpu/drm/tegra/plane.c
+1
drivers/gpu/drm/tegra/plane.c
+47
-1
drivers/gpu/drm/tegra/submit.c
+47
-1
drivers/gpu/drm/tegra/submit.c
···
498
498
struct tegra_drm_submit_data *job_data = job->user_data;
499
499
u32 i;
500
500
501
+
if (job->memory_context)
502
+
host1x_memory_context_put(job->memory_context);
503
+
501
504
for (i = 0; i < job_data->num_used_mappings; i++)
502
505
tegra_drm_mapping_put(job_data->used_mappings[i].mapping);
503
506
···
591
588
goto put_job;
592
589
}
593
590
591
+
if (context->client->ops->get_streamid_offset) {
592
+
err = context->client->ops->get_streamid_offset(
593
+
context->client, &job->engine_streamid_offset);
594
+
if (err) {
595
+
SUBMIT_ERR(context, "failed to get streamid offset: %d", err);
596
+
goto unpin_job;
597
+
}
598
+
}
599
+
600
+
if (context->memory_context && context->client->ops->can_use_memory_ctx) {
601
+
bool supported;
602
+
603
+
err = context->client->ops->can_use_memory_ctx(context->client, &supported);
604
+
if (err) {
605
+
SUBMIT_ERR(context, "failed to detect if engine can use memory context: %d", err);
606
+
goto unpin_job;
607
+
}
608
+
609
+
if (supported) {
610
+
job->memory_context = context->memory_context;
611
+
host1x_memory_context_get(job->memory_context);
612
+
}
613
+
} else if (context->client->ops->get_streamid_offset) {
614
+
#ifdef CONFIG_IOMMU_API
615
+
struct iommu_fwspec *spec;
616
+
617
+
/*
618
+
* Job submission will need to temporarily change stream ID,
619
+
* so need to tell it what to change it back to.
620
+
*/
621
+
spec = dev_iommu_fwspec_get(context->client->base.dev);
622
+
if (spec && spec->num_ids > 0)
623
+
job->engine_fallback_streamid = spec->ids[0] & 0xffff;
624
+
else
625
+
job->engine_fallback_streamid = 0x7f;
626
+
#else
627
+
job->engine_fallback_streamid = 0x7f;
628
+
#endif
629
+
}
630
+
594
631
/* Boot engine. */
595
632
err = pm_runtime_resume_and_get(context->client->base.dev);
596
633
if (err < 0) {
597
634
SUBMIT_ERR(context, "could not power up engine: %d", err);
598
-
goto unpin_job;
635
+
goto put_memory_context;
599
636
}
600
637
601
638
job->user_data = job_data;
···
670
627
671
628
goto put_job;
672
629
630
+
put_memory_context:
631
+
if (job->memory_context)
632
+
host1x_memory_context_put(job->memory_context);
673
633
unpin_job:
674
634
host1x_job_unpin(job);
675
635
put_job:
+41
-2
drivers/gpu/drm/tegra/uapi.c
+41
-2
drivers/gpu/drm/tegra/uapi.c
···
33
33
struct tegra_drm_mapping *mapping;
34
34
unsigned long id;
35
35
36
+
if (context->memory_context)
37
+
host1x_memory_context_put(context->memory_context);
38
+
36
39
xa_for_each(&context->mappings, id, mapping)
37
40
tegra_drm_mapping_put(mapping);
38
41
···
75
72
76
73
int tegra_drm_ioctl_channel_open(struct drm_device *drm, void *data, struct drm_file *file)
77
74
{
75
+
struct host1x *host = tegra_drm_to_host1x(drm->dev_private);
78
76
struct tegra_drm_file *fpriv = file->driver_priv;
79
77
struct tegra_drm *tegra = drm->dev_private;
80
78
struct drm_tegra_channel_open *args = data;
···
106
102
}
107
103
}
108
104
105
+
/* Only allocate context if the engine supports context isolation. */
106
+
if (device_iommu_mapped(client->base.dev) && client->ops->can_use_memory_ctx) {
107
+
bool supported;
108
+
109
+
err = client->ops->can_use_memory_ctx(client, &supported);
110
+
if (err)
111
+
goto put_channel;
112
+
113
+
if (supported)
114
+
context->memory_context = host1x_memory_context_alloc(
115
+
host, get_task_pid(current, PIDTYPE_TGID));
116
+
117
+
if (IS_ERR(context->memory_context)) {
118
+
if (PTR_ERR(context->memory_context) != -EOPNOTSUPP) {
119
+
err = PTR_ERR(context->memory_context);
120
+
goto put_channel;
121
+
} else {
122
+
/*
123
+
* OK, HW does not support contexts or contexts
124
+
* are disabled.
125
+
*/
126
+
context->memory_context = NULL;
127
+
}
128
+
}
129
+
}
130
+
109
131
err = xa_alloc(&fpriv->contexts, &args->context, context, XA_LIMIT(1, U32_MAX),
110
132
GFP_KERNEL);
111
133
if (err < 0)
112
-
goto put_channel;
134
+
goto put_memctx;
113
135
114
136
context->client = client;
115
137
xa_init_flags(&context->mappings, XA_FLAGS_ALLOC1);
···
148
118
149
119
return 0;
150
120
121
+
put_memctx:
122
+
if (context->memory_context)
123
+
host1x_memory_context_put(context->memory_context);
151
124
put_channel:
152
125
host1x_channel_put(context->channel);
153
126
free:
···
189
156
struct tegra_drm_mapping *mapping;
190
157
struct tegra_drm_context *context;
191
158
enum dma_data_direction direction;
159
+
struct device *mapping_dev;
192
160
int err = 0;
193
161
194
162
if (args->flags & ~DRM_TEGRA_CHANNEL_MAP_READ_WRITE)
···
210
176
}
211
177
212
178
kref_init(&mapping->ref);
179
+
180
+
if (context->memory_context)
181
+
mapping_dev = &context->memory_context->dev;
182
+
else
183
+
mapping_dev = context->client->base.dev;
213
184
214
185
mapping->bo = tegra_gem_lookup(file, args->handle);
215
186
if (!mapping->bo) {
···
240
201
goto put_gem;
241
202
}
242
203
243
-
mapping->map = host1x_bo_pin(context->client->base.dev, mapping->bo, direction, NULL);
204
+
mapping->map = host1x_bo_pin(mapping_dev, mapping->bo, direction, NULL);
244
205
if (IS_ERR(mapping->map)) {
245
206
err = PTR_ERR(mapping->map);
246
207
goto put_gem;
+74
-18
drivers/gpu/drm/tegra/vic.c
+74
-18
drivers/gpu/drm/tegra/vic.c
···
38
38
struct clk *clk;
39
39
struct reset_control *rst;
40
40
41
+
bool can_use_context;
42
+
41
43
/* Platform configuration */
42
44
const struct vic_config *config;
43
45
};
···
231
229
{
232
230
struct host1x_client *client = &vic->client.base;
233
231
struct tegra_drm *tegra = vic->client.drm;
232
+
static DEFINE_MUTEX(lock);
233
+
u32 fce_bin_data_offset;
234
234
dma_addr_t iova;
235
235
size_t size;
236
236
void *virt;
237
237
int err;
238
238
239
-
if (vic->falcon.firmware.virt)
240
-
return 0;
239
+
mutex_lock(&lock);
240
+
241
+
if (vic->falcon.firmware.virt) {
242
+
err = 0;
243
+
goto unlock;
244
+
}
241
245
242
246
err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
243
247
if (err < 0)
244
-
return err;
248
+
goto unlock;
245
249
246
250
size = vic->falcon.firmware.size;
247
251
248
252
if (!client->group) {
249
253
virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL);
250
-
if (!virt)
251
-
return -ENOMEM;
254
+
if (!virt) {
255
+
err = -ENOMEM;
256
+
goto unlock;
257
+
}
252
258
} else {
253
259
virt = tegra_drm_alloc(tegra, size, &iova);
254
-
if (IS_ERR(virt))
255
-
return PTR_ERR(virt);
260
+
if (IS_ERR(virt)) {
261
+
err = PTR_ERR(virt);
262
+
goto unlock;
263
+
}
256
264
}
257
265
258
266
vic->falcon.firmware.virt = virt;
···
289
277
vic->falcon.firmware.phys = phys;
290
278
}
291
279
292
-
return 0;
280
+
/*
281
+
* Check if firmware is new enough to not require mapping firmware
282
+
* to data buffer domains.
283
+
*/
284
+
fce_bin_data_offset = *(u32 *)(virt + VIC_UCODE_FCE_DATA_OFFSET);
285
+
286
+
if (!vic->config->supports_sid) {
287
+
vic->can_use_context = false;
288
+
} else if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) {
289
+
/*
290
+
* Firmware will access FCE through STREAMID0, so context
291
+
* isolation cannot be used.
292
+
*/
293
+
vic->can_use_context = false;
294
+
dev_warn_once(vic->dev, "context isolation disabled due to old firmware\n");
295
+
} else {
296
+
vic->can_use_context = true;
297
+
}
298
+
299
+
unlock:
300
+
mutex_unlock(&lock);
301
+
return err;
293
302
294
303
cleanup:
295
304
if (!client->group)
···
318
285
else
319
286
tegra_drm_free(tegra, size, virt, iova);
320
287
288
+
mutex_unlock(&lock);
321
289
return err;
322
290
}
323
291
324
292
325
-
static int vic_runtime_resume(struct device *dev)
293
+
static int __maybe_unused vic_runtime_resume(struct device *dev)
326
294
{
327
295
struct vic *vic = dev_get_drvdata(dev);
328
296
int err;
···
357
323
return err;
358
324
}
359
325
360
-
static int vic_runtime_suspend(struct device *dev)
326
+
static int __maybe_unused vic_runtime_suspend(struct device *dev)
361
327
{
362
328
struct vic *vic = dev_get_drvdata(dev);
363
329
int err;
···
392
358
host1x_channel_put(context->channel);
393
359
}
394
360
361
+
static int vic_can_use_memory_ctx(struct tegra_drm_client *client, bool *supported)
362
+
{
363
+
struct vic *vic = to_vic(client);
364
+
int err;
365
+
366
+
/* This doesn't access HW so it's safe to call without powering up. */
367
+
err = vic_load_firmware(vic);
368
+
if (err < 0)
369
+
return err;
370
+
371
+
*supported = vic->can_use_context;
372
+
373
+
return 0;
374
+
}
375
+
395
376
static const struct tegra_drm_client_ops vic_ops = {
396
377
.open_channel = vic_open_channel,
397
378
.close_channel = vic_close_channel,
398
379
.submit = tegra_drm_submit,
380
+
.get_streamid_offset = tegra_drm_get_streamid_offset_thi,
381
+
.can_use_memory_ctx = vic_can_use_memory_ctx,
399
382
};
400
383
401
384
#define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
···
447
396
.supports_sid = true,
448
397
};
449
398
399
+
#define NVIDIA_TEGRA_234_VIC_FIRMWARE "nvidia/tegra234/vic.bin"
400
+
401
+
static const struct vic_config vic_t234_config = {
402
+
.firmware = NVIDIA_TEGRA_234_VIC_FIRMWARE,
403
+
.version = 0x23,
404
+
.supports_sid = true,
405
+
};
406
+
450
407
static const struct of_device_id tegra_vic_of_match[] = {
451
408
{ .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
452
409
{ .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
453
410
{ .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
454
411
{ .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
412
+
{ .compatible = "nvidia,tegra234-vic", .data = &vic_t234_config },
455
413
{ },
456
414
};
457
415
MODULE_DEVICE_TABLE(of, tegra_vic_of_match);
···
469
409
{
470
410
struct device *dev = &pdev->dev;
471
411
struct host1x_syncpt **syncpts;
472
-
struct resource *regs;
473
412
struct vic *vic;
474
413
int err;
475
414
···
489
430
if (!syncpts)
490
431
return -ENOMEM;
491
432
492
-
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
493
-
if (!regs) {
494
-
dev_err(&pdev->dev, "failed to get registers\n");
495
-
return -ENXIO;
496
-
}
497
-
498
-
vic->regs = devm_ioremap_resource(dev, regs);
433
+
vic->regs = devm_platform_ioremap_resource(pdev, 0);
499
434
if (IS_ERR(vic->regs))
500
435
return PTR_ERR(vic->regs);
501
436
···
591
538
#endif
592
539
#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
593
540
MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE);
541
+
#endif
542
+
#if IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
543
+
MODULE_FIRMWARE(NVIDIA_TEGRA_234_VIC_FIRMWARE);
594
544
#endif
+5
-1
drivers/gpu/host1x/Makefile
+5
-1
drivers/gpu/host1x/Makefile
+26
-17
drivers/gpu/host1x/cdma.c
+26
-17
drivers/gpu/host1x/cdma.c
···
457
457
* to offset 0xbad. This does nothing but
458
458
* has a easily detected signature in debug
459
459
* traces.
460
+
*
461
+
* On systems with MLOCK enforcement enabled,
462
+
* the above 0 word writes would fall foul of
463
+
* the enforcement. As such, in the first slot
464
+
* put a RESTART_W opcode to the beginning
465
+
* of the next job. We don't use this for older
466
+
* chips since those only support the RESTART
467
+
* opcode with inconvenient alignment requirements.
460
468
*/
461
-
mapped[2*slot+0] = 0x1bad0000;
462
-
mapped[2*slot+1] = 0x1bad0000;
469
+
if (i == 0 && host1x->info->has_wide_gather) {
470
+
unsigned int next_job = (job->first_get/8 + job->num_slots)
471
+
% HOST1X_PUSHBUFFER_SLOTS;
472
+
mapped[2*slot+0] = (0xd << 28) | (next_job * 2);
473
+
mapped[2*slot+1] = 0x0;
474
+
} else {
475
+
mapped[2*slot+0] = 0x1bad0000;
476
+
mapped[2*slot+1] = 0x1bad0000;
477
+
}
463
478
}
464
479
465
480
job->cancelled = true;
···
615
600
struct host1x_channel *channel = cdma_to_channel(cdma);
616
601
struct host1x *host1x = cdma_to_host1x(cdma);
617
602
struct push_buffer *pb = &cdma->push_buffer;
618
-
unsigned int needed = 2, extra = 0, i;
619
603
unsigned int space = cdma->slots_free;
604
+
unsigned int needed = 2, extra = 0;
620
605
621
606
if (host1x_debug_trace_cmdbuf)
622
607
trace_host1x_cdma_push_wide(dev_name(channel->dev), op1, op2,
···
634
619
cdma->slots_free = space - needed;
635
620
cdma->slots_used += needed;
636
621
637
-
/*
638
-
* Note that we rely on the fact that this is only used to submit wide
639
-
* gather opcodes, which consist of 3 words, and they are padded with
640
-
* a NOP to avoid having to deal with fractional slots (a slot always
641
-
* represents 2 words). The fourth opcode passed to this function will
642
-
* therefore always be a NOP.
643
-
*
644
-
* This works around a slight ambiguity when it comes to opcodes. For
645
-
* all current host1x incarnations the NOP opcode uses the exact same
646
-
* encoding (0x20000000), so we could hard-code the value here, but a
647
-
* new incarnation may change it and break that assumption.
648
-
*/
649
-
for (i = 0; i < extra; i++)
650
-
host1x_pushbuffer_push(pb, op4, op4);
622
+
if (extra > 0) {
623
+
/*
624
+
* If there isn't enough space at the tail of the pushbuffer,
625
+
* insert a RESTART(0) here to go back to the beginning.
626
+
* The code above adjusted the indexes appropriately.
627
+
*/
628
+
host1x_pushbuffer_push(pb, (0x5 << 28), 0xdead0000);
629
+
}
651
630
652
631
host1x_pushbuffer_push(pb, op1, op2);
653
632
host1x_pushbuffer_push(pb, op3, op4);
+2
-6
drivers/gpu/host1x/channel.c
+2
-6
drivers/gpu/host1x/channel.c
···
21
21
if (!chlist->channels)
22
22
return -ENOMEM;
23
23
24
-
chlist->allocated_channels =
25
-
kcalloc(BITS_TO_LONGS(num_channels), sizeof(unsigned long),
26
-
GFP_KERNEL);
24
+
chlist->allocated_channels = bitmap_zalloc(num_channels, GFP_KERNEL);
27
25
if (!chlist->allocated_channels) {
28
26
kfree(chlist->channels);
29
27
return -ENOMEM;
30
28
}
31
-
32
-
bitmap_zero(chlist->allocated_channels, num_channels);
33
29
34
30
return 0;
35
31
}
36
32
37
33
void host1x_channel_list_free(struct host1x_channel_list *chlist)
38
34
{
39
-
kfree(chlist->allocated_channels);
35
+
bitmap_free(chlist->allocated_channels);
40
36
kfree(chlist->channels);
41
37
}
42
38
+160
drivers/gpu/host1x/context.c
+160
drivers/gpu/host1x/context.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2021, NVIDIA Corporation.
4
+
*/
5
+
6
+
#include <linux/device.h>
7
+
#include <linux/kref.h>
8
+
#include <linux/of.h>
9
+
#include <linux/of_platform.h>
10
+
#include <linux/pid.h>
11
+
#include <linux/slab.h>
12
+
13
+
#include "context.h"
14
+
#include "dev.h"
15
+
16
+
int host1x_memory_context_list_init(struct host1x *host1x)
17
+
{
18
+
struct host1x_memory_context_list *cdl = &host1x->context_list;
19
+
struct device_node *node = host1x->dev->of_node;
20
+
struct host1x_memory_context *ctx;
21
+
unsigned int i;
22
+
int err;
23
+
24
+
cdl->devs = NULL;
25
+
cdl->len = 0;
26
+
mutex_init(&cdl->lock);
27
+
28
+
err = of_property_count_u32_elems(node, "iommu-map");
29
+
if (err < 0)
30
+
return 0;
31
+
32
+
cdl->devs = kcalloc(err, sizeof(*cdl->devs), GFP_KERNEL);
33
+
if (!cdl->devs)
34
+
return -ENOMEM;
35
+
cdl->len = err / 4;
36
+
37
+
for (i = 0; i < cdl->len; i++) {
38
+
struct iommu_fwspec *fwspec;
39
+
40
+
ctx = &cdl->devs[i];
41
+
42
+
ctx->host = host1x;
43
+
44
+
device_initialize(&ctx->dev);
45
+
46
+
/*
47
+
* Due to an issue with T194 NVENC, only 38 bits can be used.
48
+
* Anyway, 256GiB of IOVA ought to be enough for anyone.
49
+
*/
50
+
ctx->dma_mask = DMA_BIT_MASK(38);
51
+
ctx->dev.dma_mask = &ctx->dma_mask;
52
+
ctx->dev.coherent_dma_mask = ctx->dma_mask;
53
+
dev_set_name(&ctx->dev, "host1x-ctx.%d", i);
54
+
ctx->dev.bus = &host1x_context_device_bus_type;
55
+
ctx->dev.parent = host1x->dev;
56
+
57
+
dma_set_max_seg_size(&ctx->dev, UINT_MAX);
58
+
59
+
err = device_add(&ctx->dev);
60
+
if (err) {
61
+
dev_err(host1x->dev, "could not add context device %d: %d\n", i, err);
62
+
goto del_devices;
63
+
}
64
+
65
+
err = of_dma_configure_id(&ctx->dev, node, true, &i);
66
+
if (err) {
67
+
dev_err(host1x->dev, "IOMMU configuration failed for context device %d: %d\n",
68
+
i, err);
69
+
device_del(&ctx->dev);
70
+
goto del_devices;
71
+
}
72
+
73
+
fwspec = dev_iommu_fwspec_get(&ctx->dev);
74
+
if (!fwspec || !device_iommu_mapped(&ctx->dev)) {
75
+
dev_err(host1x->dev, "Context device %d has no IOMMU!\n", i);
76
+
device_del(&ctx->dev);
77
+
goto del_devices;
78
+
}
79
+
80
+
ctx->stream_id = fwspec->ids[0] & 0xffff;
81
+
}
82
+
83
+
return 0;
84
+
85
+
del_devices:
86
+
while (i--)
87
+
device_del(&cdl->devs[i].dev);
88
+
89
+
kfree(cdl->devs);
90
+
cdl->len = 0;
91
+
92
+
return err;
93
+
}
94
+
95
+
void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl)
96
+
{
97
+
unsigned int i;
98
+
99
+
for (i = 0; i < cdl->len; i++)
100
+
device_del(&cdl->devs[i].dev);
101
+
102
+
kfree(cdl->devs);
103
+
cdl->len = 0;
104
+
}
105
+
106
+
struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
107
+
struct pid *pid)
108
+
{
109
+
struct host1x_memory_context_list *cdl = &host1x->context_list;
110
+
struct host1x_memory_context *free = NULL;
111
+
int i;
112
+
113
+
if (!cdl->len)
114
+
return ERR_PTR(-EOPNOTSUPP);
115
+
116
+
mutex_lock(&cdl->lock);
117
+
118
+
for (i = 0; i < cdl->len; i++) {
119
+
struct host1x_memory_context *cd = &cdl->devs[i];
120
+
121
+
if (cd->owner == pid) {
122
+
refcount_inc(&cd->ref);
123
+
mutex_unlock(&cdl->lock);
124
+
return cd;
125
+
} else if (!cd->owner && !free) {
126
+
free = cd;
127
+
}
128
+
}
129
+
130
+
if (!free) {
131
+
mutex_unlock(&cdl->lock);
132
+
return ERR_PTR(-EBUSY);
133
+
}
134
+
135
+
refcount_set(&free->ref, 1);
136
+
free->owner = get_pid(pid);
137
+
138
+
mutex_unlock(&cdl->lock);
139
+
140
+
return free;
141
+
}
142
+
EXPORT_SYMBOL_GPL(host1x_memory_context_alloc);
143
+
144
+
void host1x_memory_context_get(struct host1x_memory_context *cd)
145
+
{
146
+
refcount_inc(&cd->ref);
147
+
}
148
+
EXPORT_SYMBOL_GPL(host1x_memory_context_get);
149
+
150
+
void host1x_memory_context_put(struct host1x_memory_context *cd)
151
+
{
152
+
struct host1x_memory_context_list *cdl = &cd->host->context_list;
153
+
154
+
if (refcount_dec_and_mutex_lock(&cd->ref, &cdl->lock)) {
155
+
put_pid(cd->owner);
156
+
cd->owner = NULL;
157
+
mutex_unlock(&cdl->lock);
158
+
}
159
+
}
160
+
EXPORT_SYMBOL_GPL(host1x_memory_context_put);
+38
drivers/gpu/host1x/context.h
+38
drivers/gpu/host1x/context.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Host1x context devices
4
+
*
5
+
* Copyright (c) 2020, NVIDIA Corporation.
6
+
*/
7
+
8
+
#ifndef __HOST1X_CONTEXT_H
9
+
#define __HOST1X_CONTEXT_H
10
+
11
+
#include <linux/mutex.h>
12
+
#include <linux/refcount.h>
13
+
14
+
struct host1x;
15
+
16
+
extern struct bus_type host1x_context_device_bus_type;
17
+
18
+
struct host1x_memory_context_list {
19
+
struct mutex lock;
20
+
struct host1x_memory_context *devs;
21
+
unsigned int len;
22
+
};
23
+
24
+
#ifdef CONFIG_IOMMU_API
25
+
int host1x_memory_context_list_init(struct host1x *host1x);
26
+
void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl);
27
+
#else
28
+
static inline int host1x_memory_context_list_init(struct host1x *host1x)
29
+
{
30
+
return 0;
31
+
}
32
+
33
+
static inline void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl)
34
+
{
35
+
}
36
+
#endif
37
+
38
+
#endif
-5
drivers/gpu/host1x/context_bus.c
-5
drivers/gpu/host1x/context_bus.c
···
15
15
{
16
16
int err;
17
17
18
-
if (!of_machine_is_compatible("nvidia,tegra186") &&
19
-
!of_machine_is_compatible("nvidia,tegra194") &&
20
-
!of_machine_is_compatible("nvidia,tegra234"))
21
-
return 0;
22
-
23
18
err = bus_register(&host1x_context_device_bus_type);
24
19
if (err < 0) {
25
20
pr_err("bus type registration failed: %d\n", err);
+90
-34
drivers/gpu/host1x/dev.c
+90
-34
drivers/gpu/host1x/dev.c
···
28
28
29
29
#include "bus.h"
30
30
#include "channel.h"
31
+
#include "context.h"
31
32
#include "debug.h"
32
33
#include "dev.h"
33
34
#include "intr.h"
···
39
38
#include "hw/host1x05.h"
40
39
#include "hw/host1x06.h"
41
40
#include "hw/host1x07.h"
41
+
#include "hw/host1x08.h"
42
+
43
+
void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)
44
+
{
45
+
writel(v, host1x->common_regs + r);
46
+
}
42
47
43
48
void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
44
49
{
···
206
199
.reserve_vblank_syncpts = false,
207
200
};
208
201
202
+
/*
203
+
* Tegra234 has two stream ID protection tables, one for setting stream IDs
204
+
* through the channel path via SETSTREAMID, and one for setting them via
205
+
* MMIO. We program each engine's data stream ID in the channel path table
206
+
* and firmware stream ID in the MMIO path table.
207
+
*/
208
+
static const struct host1x_sid_entry tegra234_sid_table[] = {
209
+
{
210
+
/* VIC channel */
211
+
.base = 0x17b8,
212
+
.offset = 0x30,
213
+
.limit = 0x30
214
+
},
215
+
{
216
+
/* VIC MMIO */
217
+
.base = 0x1688,
218
+
.offset = 0x34,
219
+
.limit = 0x34
220
+
},
221
+
};
222
+
223
+
static const struct host1x_info host1x08_info = {
224
+
.nb_channels = 63,
225
+
.nb_pts = 1024,
226
+
.nb_mlocks = 24,
227
+
.nb_bases = 0,
228
+
.init = host1x08_init,
229
+
.sync_offset = 0x0,
230
+
.dma_mask = DMA_BIT_MASK(40),
231
+
.has_wide_gather = true,
232
+
.has_hypervisor = true,
233
+
.has_common = true,
234
+
.num_sid_entries = ARRAY_SIZE(tegra234_sid_table),
235
+
.sid_table = tegra234_sid_table,
236
+
.streamid_vm_table = { 0x1004, 128 },
237
+
.classid_vm_table = { 0x1404, 25 },
238
+
.mmio_vm_table = { 0x1504, 25 },
239
+
.reserve_vblank_syncpts = false,
240
+
};
241
+
209
242
static const struct of_device_id host1x_of_match[] = {
243
+
{ .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, },
210
244
{ .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
211
245
{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
212
246
{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
···
259
211
};
260
212
MODULE_DEVICE_TABLE(of, host1x_of_match);
261
213
262
-
static void host1x_setup_sid_table(struct host1x *host)
214
+
static void host1x_setup_virtualization_tables(struct host1x *host)
263
215
{
264
216
const struct host1x_info *info = host->info;
265
217
unsigned int i;
···
272
224
273
225
host1x_hypervisor_writel(host, entry->offset, entry->base);
274
226
host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
227
+
}
228
+
229
+
for (i = 0; i < info->streamid_vm_table.count; i++) {
230
+
/* Allow access to all stream IDs to all VMs. */
231
+
host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i);
232
+
}
233
+
234
+
for (i = 0; i < info->classid_vm_table.count; i++) {
235
+
/* Allow access to all classes to all VMs. */
236
+
host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i);
237
+
}
238
+
239
+
for (i = 0; i < info->mmio_vm_table.count; i++) {
240
+
/* Use VM1 (that's us) as originator VMID for engine MMIO accesses. */
241
+
host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i);
275
242
}
276
243
}
277
244
···
465
402
return err;
466
403
}
467
404
468
-
if (WARN_ON(!host->resets[1].rstc))
469
-
return -ENOENT;
470
-
471
405
return 0;
472
406
}
473
407
474
408
static int host1x_probe(struct platform_device *pdev)
475
409
{
476
410
struct host1x *host;
477
-
struct resource *regs, *hv_regs = NULL;
478
411
int syncpt_irq;
479
412
int err;
480
413
···
481
422
host->info = of_device_get_match_data(&pdev->dev);
482
423
483
424
if (host->info->has_hypervisor) {
484
-
regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");
485
-
if (!regs) {
486
-
dev_err(&pdev->dev, "failed to get vm registers\n");
487
-
return -ENXIO;
488
-
}
425
+
host->regs = devm_platform_ioremap_resource_byname(pdev, "vm");
426
+
if (IS_ERR(host->regs))
427
+
return PTR_ERR(host->regs);
489
428
490
-
hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
491
-
"hypervisor");
492
-
if (!hv_regs) {
493
-
dev_err(&pdev->dev,
494
-
"failed to get hypervisor registers\n");
495
-
return -ENXIO;
429
+
host->hv_regs = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
430
+
if (IS_ERR(host->hv_regs))
431
+
return PTR_ERR(host->hv_regs);
432
+
433
+
if (host->info->has_common) {
434
+
host->common_regs = devm_platform_ioremap_resource_byname(pdev, "common");
435
+
if (IS_ERR(host->common_regs))
436
+
return PTR_ERR(host->common_regs);
496
437
}
497
438
} else {
498
-
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
499
-
if (!regs) {
500
-
dev_err(&pdev->dev, "failed to get registers\n");
501
-
return -ENXIO;
502
-
}
439
+
host->regs = devm_platform_ioremap_resource(pdev, 0);
440
+
if (IS_ERR(host->regs))
441
+
return PTR_ERR(host->regs);
503
442
}
504
443
505
444
syncpt_irq = platform_get_irq(pdev, 0);
···
511
454
512
455
/* set common host1x device data */
513
456
platform_set_drvdata(pdev, host);
514
-
515
-
host->regs = devm_ioremap_resource(&pdev->dev, regs);
516
-
if (IS_ERR(host->regs))
517
-
return PTR_ERR(host->regs);
518
-
519
-
if (host->info->has_hypervisor) {
520
-
host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);
521
-
if (IS_ERR(host->hv_regs))
522
-
return PTR_ERR(host->hv_regs);
523
-
}
524
457
525
458
host->dev->dma_parms = &host->dma_parms;
526
459
dma_set_max_seg_size(host->dev, UINT_MAX);
···
550
503
goto iommu_exit;
551
504
}
552
505
506
+
err = host1x_memory_context_list_init(host);
507
+
if (err) {
508
+
dev_err(&pdev->dev, "failed to initialize context list\n");
509
+
goto free_channels;
510
+
}
511
+
553
512
err = host1x_syncpt_init(host);
554
513
if (err) {
555
514
dev_err(&pdev->dev, "failed to initialize syncpts\n");
556
-
goto free_channels;
515
+
goto free_contexts;
557
516
}
558
517
559
518
err = host1x_intr_init(host, syncpt_irq);
···
603
550
host1x_intr_deinit(host);
604
551
deinit_syncpt:
605
552
host1x_syncpt_deinit(host);
553
+
free_contexts:
554
+
host1x_memory_context_list_free(&host->context_list);
606
555
free_channels:
607
556
host1x_channel_list_free(&host->channel_list);
608
557
iommu_exit:
···
626
571
627
572
host1x_intr_deinit(host);
628
573
host1x_syncpt_deinit(host);
574
+
host1x_memory_context_list_free(&host->context_list);
629
575
host1x_channel_list_free(&host->channel_list);
630
576
host1x_iommu_exit(host);
631
577
host1x_bo_cache_destroy(&host->cache);
···
656
600
return 0;
657
601
658
602
resume_host1x:
659
-
host1x_setup_sid_table(host);
603
+
host1x_setup_virtualization_tables(host);
660
604
host1x_syncpt_restore(host);
661
605
host1x_intr_start(host);
662
606
···
686
630
goto disable_clk;
687
631
}
688
632
689
-
host1x_setup_sid_table(host);
633
+
host1x_setup_virtualization_tables(host);
690
634
host1x_syncpt_restore(host);
691
635
host1x_intr_start(host);
692
636
+13
drivers/gpu/host1x/dev.h
+13
drivers/gpu/host1x/dev.h
···
14
14
15
15
#include "cdma.h"
16
16
#include "channel.h"
17
+
#include "context.h"
17
18
#include "intr.h"
18
19
#include "job.h"
19
20
#include "syncpt.h"
···
90
89
unsigned int limit;
91
90
};
92
91
92
+
struct host1x_table_desc {
93
+
unsigned int base;
94
+
unsigned int count;
95
+
};
96
+
93
97
struct host1x_info {
94
98
unsigned int nb_channels; /* host1x: number of channels supported */
95
99
unsigned int nb_pts; /* host1x: number of syncpoints supported */
···
105
99
u64 dma_mask; /* mask of addressable memory */
106
100
bool has_wide_gather; /* supports GATHER_W opcode */
107
101
bool has_hypervisor; /* has hypervisor registers */
102
+
bool has_common; /* has common registers separate from hypervisor */
108
103
unsigned int num_sid_entries;
109
104
const struct host1x_sid_entry *sid_table;
105
+
struct host1x_table_desc streamid_vm_table;
106
+
struct host1x_table_desc classid_vm_table;
107
+
struct host1x_table_desc mmio_vm_table;
110
108
/*
111
109
* On T20-T148, the boot chain may setup DC to increment syncpoints
112
110
* 26/27 on VBLANK. As such we cannot use these syncpoints until
···
124
114
125
115
void __iomem *regs;
126
116
void __iomem *hv_regs; /* hypervisor region */
117
+
void __iomem *common_regs;
127
118
struct host1x_syncpt *syncpt;
128
119
struct host1x_syncpt_base *bases;
129
120
struct device *dev;
···
152
141
struct mutex syncpt_mutex;
153
142
154
143
struct host1x_channel_list channel_list;
144
+
struct host1x_memory_context_list context_list;
155
145
156
146
struct dentry *debugfs;
157
147
···
166
154
struct host1x_bo_cache cache;
167
155
};
168
156
157
+
void host1x_common_writel(struct host1x *host1x, u32 v, u32 r);
169
158
void host1x_hypervisor_writel(struct host1x *host1x, u32 r, u32 v);
170
159
u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r);
171
160
void host1x_sync_writel(struct host1x *host1x, u32 r, u32 v);
+34
drivers/gpu/host1x/hw/cdma_hw.c
+34
drivers/gpu/host1x/hw/cdma_hw.c
···
238
238
cdma_timeout_restart(cdma, getptr);
239
239
}
240
240
241
+
static void timeout_release_mlock(struct host1x_cdma *cdma)
242
+
{
243
+
#if HOST1X_HW >= 8
244
+
/* Tegra186 and Tegra194 require a more complicated MLOCK release
245
+
* sequence. Furthermore, those chips by default don't enforce MLOCKs,
246
+
* so it turns out that if we don't /actually/ need MLOCKs, we can just
247
+
* ignore them.
248
+
*
249
+
* As such, for now just implement this on Tegra234 where things are
250
+
* stricter but also easy to implement.
251
+
*/
252
+
struct host1x_channel *ch = cdma_to_channel(cdma);
253
+
struct host1x *host1x = cdma_to_host1x(cdma);
254
+
u32 offset;
255
+
256
+
switch (ch->client->class) {
257
+
case HOST1X_CLASS_VIC:
258
+
offset = HOST1X_COMMON_VIC_MLOCK;
259
+
break;
260
+
case HOST1X_CLASS_NVDEC:
261
+
offset = HOST1X_COMMON_NVDEC_MLOCK;
262
+
break;
263
+
default:
264
+
WARN(1, "%s was not updated for class %u", __func__, ch->client->class);
265
+
return;
266
+
}
267
+
268
+
host1x_common_writel(host1x, 0x0, offset);
269
+
#endif
270
+
}
271
+
241
272
/*
242
273
* If this timeout fires, it indicates the current sync_queue entry has
243
274
* exceeded its TTL and the userctx should be timed out and remaining
···
318
287
319
288
/* stop HW, resetting channel/module */
320
289
host1x_hw_cdma_freeze(host1x, cdma);
290
+
291
+
/* release any held MLOCK */
292
+
timeout_release_mlock(cdma);
321
293
322
294
host1x_cdma_update_sync_queue(cdma, ch->dev);
323
295
mutex_unlock(&cdma->lock);
+104
-33
drivers/gpu/host1x/hw/channel_hw.c
+104
-33
drivers/gpu/host1x/hw/channel_hw.c
···
47
47
}
48
48
}
49
49
50
-
static void submit_wait(struct host1x_cdma *cdma, u32 id, u32 threshold,
50
+
static void submit_wait(struct host1x_job *job, u32 id, u32 threshold,
51
51
u32 next_class)
52
52
{
53
-
#if HOST1X_HW >= 2
53
+
struct host1x_cdma *cdma = &job->channel->cdma;
54
+
55
+
#if HOST1X_HW >= 6
56
+
u32 stream_id;
57
+
58
+
/*
59
+
* If a memory context has been set, use it. Otherwise
60
+
* (if context isolation is disabled) use the engine's
61
+
* firmware stream ID.
62
+
*/
63
+
if (job->memory_context)
64
+
stream_id = job->memory_context->stream_id;
65
+
else
66
+
stream_id = job->engine_fallback_streamid;
67
+
68
+
host1x_cdma_push_wide(cdma,
69
+
host1x_opcode_setclass(
70
+
HOST1X_CLASS_HOST1X,
71
+
HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32,
72
+
/* WAIT_SYNCPT_32 is at SYNCPT_PAYLOAD_32+2 */
73
+
BIT(0) | BIT(2)
74
+
),
75
+
threshold,
76
+
id,
77
+
HOST1X_OPCODE_NOP
78
+
);
79
+
host1x_cdma_push_wide(&job->channel->cdma,
80
+
host1x_opcode_setclass(job->class, 0, 0),
81
+
host1x_opcode_setpayload(stream_id),
82
+
host1x_opcode_setstreamid(job->engine_streamid_offset / 4),
83
+
HOST1X_OPCODE_NOP);
84
+
#elif HOST1X_HW >= 2
54
85
host1x_cdma_push_wide(cdma,
55
86
host1x_opcode_setclass(
56
87
HOST1X_CLASS_HOST1X,
···
128
97
else
129
98
threshold = cmd->wait.threshold;
130
99
131
-
submit_wait(cdma, cmd->wait.id, threshold, cmd->wait.next_class);
100
+
submit_wait(job, cmd->wait.id, threshold, cmd->wait.next_class);
132
101
} else {
133
102
struct host1x_job_gather *g = &cmd->gather;
134
103
···
211
180
#endif
212
181
}
213
182
183
+
static void channel_program_cdma(struct host1x_job *job)
184
+
{
185
+
struct host1x_cdma *cdma = &job->channel->cdma;
186
+
struct host1x_syncpt *sp = job->syncpt;
187
+
188
+
#if HOST1X_HW >= 6
189
+
u32 fence;
190
+
191
+
/* Enter engine class with invalid stream ID. */
192
+
host1x_cdma_push_wide(cdma,
193
+
host1x_opcode_acquire_mlock(job->class),
194
+
host1x_opcode_setclass(job->class, 0, 0),
195
+
host1x_opcode_setpayload(0),
196
+
host1x_opcode_setstreamid(job->engine_streamid_offset / 4));
197
+
198
+
/* Before switching stream ID to real stream ID, ensure engine is idle. */
199
+
fence = host1x_syncpt_incr_max(sp, 1);
200
+
host1x_cdma_push(&job->channel->cdma,
201
+
host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1),
202
+
HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) |
203
+
HOST1X_UCLASS_INCR_SYNCPT_COND_F(4));
204
+
submit_wait(job, job->syncpt->id, fence, job->class);
205
+
206
+
/* Submit work. */
207
+
job->syncpt_end = host1x_syncpt_incr_max(sp, job->syncpt_incrs);
208
+
submit_gathers(job, job->syncpt_end - job->syncpt_incrs);
209
+
210
+
/* Before releasing MLOCK, ensure engine is idle again. */
211
+
fence = host1x_syncpt_incr_max(sp, 1);
212
+
host1x_cdma_push(&job->channel->cdma,
213
+
host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1),
214
+
HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) |
215
+
HOST1X_UCLASS_INCR_SYNCPT_COND_F(4));
216
+
submit_wait(job, job->syncpt->id, fence, job->class);
217
+
218
+
/* Release MLOCK. */
219
+
host1x_cdma_push(cdma,
220
+
HOST1X_OPCODE_NOP, host1x_opcode_release_mlock(job->class));
221
+
#else
222
+
if (job->serialize) {
223
+
/*
224
+
* Force serialization by inserting a host wait for the
225
+
* previous job to finish before this one can commence.
226
+
*/
227
+
host1x_cdma_push(cdma,
228
+
host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
229
+
host1x_uclass_wait_syncpt_r(), 1),
230
+
host1x_class_host_wait_syncpt(job->syncpt->id,
231
+
host1x_syncpt_read_max(sp)));
232
+
}
233
+
234
+
/* Synchronize base register to allow using it for relative waiting */
235
+
if (sp->base)
236
+
synchronize_syncpt_base(job);
237
+
238
+
/* add a setclass for modules that require it */
239
+
if (job->class)
240
+
host1x_cdma_push(cdma,
241
+
host1x_opcode_setclass(job->class, 0, 0),
242
+
HOST1X_OPCODE_NOP);
243
+
244
+
job->syncpt_end = host1x_syncpt_incr_max(sp, job->syncpt_incrs);
245
+
246
+
submit_gathers(job, job->syncpt_end - job->syncpt_incrs);
247
+
#endif
248
+
}
249
+
214
250
static int channel_submit(struct host1x_job *job)
215
251
{
216
252
struct host1x_channel *ch = job->channel;
217
253
struct host1x_syncpt *sp = job->syncpt;
218
-
u32 user_syncpt_incrs = job->syncpt_incrs;
219
254
u32 prev_max = 0;
220
255
u32 syncval;
221
256
int err;
···
309
212
310
213
host1x_channel_set_streamid(ch);
311
214
host1x_enable_gather_filter(ch);
215
+
host1x_hw_syncpt_assign_to_channel(host, sp, ch);
312
216
313
217
/* begin a CDMA submit */
314
218
err = host1x_cdma_begin(&ch->cdma, job);
···
318
220
goto error;
319
221
}
320
222
321
-
if (job->serialize) {
322
-
/*
323
-
* Force serialization by inserting a host wait for the
324
-
* previous job to finish before this one can commence.
325
-
*/
326
-
host1x_cdma_push(&ch->cdma,
327
-
host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
328
-
host1x_uclass_wait_syncpt_r(), 1),
329
-
host1x_class_host_wait_syncpt(job->syncpt->id,
330
-
host1x_syncpt_read_max(sp)));
331
-
}
332
-
333
-
/* Synchronize base register to allow using it for relative waiting */
334
-
if (sp->base)
335
-
synchronize_syncpt_base(job);
336
-
337
-
syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
338
-
339
-
host1x_hw_syncpt_assign_to_channel(host, sp, ch);
340
-
341
-
job->syncpt_end = syncval;
342
-
343
-
/* add a setclass for modules that require it */
344
-
if (job->class)
345
-
host1x_cdma_push(&ch->cdma,
346
-
host1x_opcode_setclass(job->class, 0, 0),
347
-
HOST1X_OPCODE_NOP);
348
-
349
-
submit_gathers(job, syncval - user_syncpt_incrs);
223
+
channel_program_cdma(job);
224
+
syncval = host1x_syncpt_read_max(sp);
350
225
351
226
/* end CDMA submit & stash pinned hMems into sync queue */
352
227
host1x_cdma_end(&ch->cdma, job);
+1
-113
drivers/gpu/host1x/hw/host1x01_hardware.h
+1
-113
drivers/gpu/host1x/hw/host1x01_hardware.h
···
15
15
#include "hw_host1x01_sync.h"
16
16
#include "hw_host1x01_uclass.h"
17
17
18
-
static inline u32 host1x_class_host_wait_syncpt(
19
-
unsigned indx, unsigned threshold)
20
-
{
21
-
return host1x_uclass_wait_syncpt_indx_f(indx)
22
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
23
-
}
24
-
25
-
static inline u32 host1x_class_host_load_syncpt_base(
26
-
unsigned indx, unsigned threshold)
27
-
{
28
-
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
29
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
30
-
}
31
-
32
-
static inline u32 host1x_class_host_wait_syncpt_base(
33
-
unsigned indx, unsigned base_indx, unsigned offset)
34
-
{
35
-
return host1x_uclass_wait_syncpt_base_indx_f(indx)
36
-
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
37
-
| host1x_uclass_wait_syncpt_base_offset_f(offset);
38
-
}
39
-
40
-
static inline u32 host1x_class_host_incr_syncpt_base(
41
-
unsigned base_indx, unsigned offset)
42
-
{
43
-
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
44
-
| host1x_uclass_incr_syncpt_base_offset_f(offset);
45
-
}
46
-
47
-
static inline u32 host1x_class_host_incr_syncpt(
48
-
unsigned cond, unsigned indx)
49
-
{
50
-
return host1x_uclass_incr_syncpt_cond_f(cond)
51
-
| host1x_uclass_incr_syncpt_indx_f(indx);
52
-
}
53
-
54
-
static inline u32 host1x_class_host_indoff_reg_write(
55
-
unsigned mod_id, unsigned offset, bool auto_inc)
56
-
{
57
-
u32 v = host1x_uclass_indoff_indbe_f(0xf)
58
-
| host1x_uclass_indoff_indmodid_f(mod_id)
59
-
| host1x_uclass_indoff_indroffset_f(offset);
60
-
if (auto_inc)
61
-
v |= host1x_uclass_indoff_autoinc_f(1);
62
-
return v;
63
-
}
64
-
65
-
static inline u32 host1x_class_host_indoff_reg_read(
66
-
unsigned mod_id, unsigned offset, bool auto_inc)
67
-
{
68
-
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
69
-
| host1x_uclass_indoff_indroffset_f(offset)
70
-
| host1x_uclass_indoff_rwn_read_v();
71
-
if (auto_inc)
72
-
v |= host1x_uclass_indoff_autoinc_f(1);
73
-
return v;
74
-
}
75
-
76
-
77
-
/* cdma opcodes */
78
-
static inline u32 host1x_opcode_setclass(
79
-
unsigned class_id, unsigned offset, unsigned mask)
80
-
{
81
-
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
82
-
}
83
-
84
-
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
85
-
{
86
-
return (1 << 28) | (offset << 16) | count;
87
-
}
88
-
89
-
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
90
-
{
91
-
return (2 << 28) | (offset << 16) | count;
92
-
}
93
-
94
-
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
95
-
{
96
-
return (3 << 28) | (offset << 16) | mask;
97
-
}
98
-
99
-
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
100
-
{
101
-
return (4 << 28) | (offset << 16) | value;
102
-
}
103
-
104
-
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
105
-
{
106
-
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
107
-
host1x_class_host_incr_syncpt(cond, indx));
108
-
}
109
-
110
-
static inline u32 host1x_opcode_restart(unsigned address)
111
-
{
112
-
return (5 << 28) | (address >> 4);
113
-
}
114
-
115
-
static inline u32 host1x_opcode_gather(unsigned count)
116
-
{
117
-
return (6 << 28) | count;
118
-
}
119
-
120
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
121
-
{
122
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
123
-
}
124
-
125
-
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
126
-
{
127
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
128
-
}
129
-
130
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
18
+
#include "opcodes.h"
131
19
132
20
#endif
+1
-112
drivers/gpu/host1x/hw/host1x02_hardware.h
+1
-112
drivers/gpu/host1x/hw/host1x02_hardware.h
···
15
15
#include "hw_host1x02_sync.h"
16
16
#include "hw_host1x02_uclass.h"
17
17
18
-
static inline u32 host1x_class_host_wait_syncpt(
19
-
unsigned indx, unsigned threshold)
20
-
{
21
-
return host1x_uclass_wait_syncpt_indx_f(indx)
22
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
23
-
}
24
-
25
-
static inline u32 host1x_class_host_load_syncpt_base(
26
-
unsigned indx, unsigned threshold)
27
-
{
28
-
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
29
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
30
-
}
31
-
32
-
static inline u32 host1x_class_host_wait_syncpt_base(
33
-
unsigned indx, unsigned base_indx, unsigned offset)
34
-
{
35
-
return host1x_uclass_wait_syncpt_base_indx_f(indx)
36
-
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
37
-
| host1x_uclass_wait_syncpt_base_offset_f(offset);
38
-
}
39
-
40
-
static inline u32 host1x_class_host_incr_syncpt_base(
41
-
unsigned base_indx, unsigned offset)
42
-
{
43
-
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
44
-
| host1x_uclass_incr_syncpt_base_offset_f(offset);
45
-
}
46
-
47
-
static inline u32 host1x_class_host_incr_syncpt(
48
-
unsigned cond, unsigned indx)
49
-
{
50
-
return host1x_uclass_incr_syncpt_cond_f(cond)
51
-
| host1x_uclass_incr_syncpt_indx_f(indx);
52
-
}
53
-
54
-
static inline u32 host1x_class_host_indoff_reg_write(
55
-
unsigned mod_id, unsigned offset, bool auto_inc)
56
-
{
57
-
u32 v = host1x_uclass_indoff_indbe_f(0xf)
58
-
| host1x_uclass_indoff_indmodid_f(mod_id)
59
-
| host1x_uclass_indoff_indroffset_f(offset);
60
-
if (auto_inc)
61
-
v |= host1x_uclass_indoff_autoinc_f(1);
62
-
return v;
63
-
}
64
-
65
-
static inline u32 host1x_class_host_indoff_reg_read(
66
-
unsigned mod_id, unsigned offset, bool auto_inc)
67
-
{
68
-
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
69
-
| host1x_uclass_indoff_indroffset_f(offset)
70
-
| host1x_uclass_indoff_rwn_read_v();
71
-
if (auto_inc)
72
-
v |= host1x_uclass_indoff_autoinc_f(1);
73
-
return v;
74
-
}
75
-
76
-
/* cdma opcodes */
77
-
static inline u32 host1x_opcode_setclass(
78
-
unsigned class_id, unsigned offset, unsigned mask)
79
-
{
80
-
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
81
-
}
82
-
83
-
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
84
-
{
85
-
return (1 << 28) | (offset << 16) | count;
86
-
}
87
-
88
-
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
89
-
{
90
-
return (2 << 28) | (offset << 16) | count;
91
-
}
92
-
93
-
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
94
-
{
95
-
return (3 << 28) | (offset << 16) | mask;
96
-
}
97
-
98
-
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
99
-
{
100
-
return (4 << 28) | (offset << 16) | value;
101
-
}
102
-
103
-
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
104
-
{
105
-
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
106
-
host1x_class_host_incr_syncpt(cond, indx));
107
-
}
108
-
109
-
static inline u32 host1x_opcode_restart(unsigned address)
110
-
{
111
-
return (5 << 28) | (address >> 4);
112
-
}
113
-
114
-
static inline u32 host1x_opcode_gather(unsigned count)
115
-
{
116
-
return (6 << 28) | count;
117
-
}
118
-
119
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
120
-
{
121
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
122
-
}
123
-
124
-
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
125
-
{
126
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
127
-
}
128
-
129
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
18
+
#include "opcodes.h"
130
19
131
20
#endif
+1
-112
drivers/gpu/host1x/hw/host1x04_hardware.h
+1
-112
drivers/gpu/host1x/hw/host1x04_hardware.h
···
15
15
#include "hw_host1x04_sync.h"
16
16
#include "hw_host1x04_uclass.h"
17
17
18
-
static inline u32 host1x_class_host_wait_syncpt(
19
-
unsigned indx, unsigned threshold)
20
-
{
21
-
return host1x_uclass_wait_syncpt_indx_f(indx)
22
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
23
-
}
24
-
25
-
static inline u32 host1x_class_host_load_syncpt_base(
26
-
unsigned indx, unsigned threshold)
27
-
{
28
-
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
29
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
30
-
}
31
-
32
-
static inline u32 host1x_class_host_wait_syncpt_base(
33
-
unsigned indx, unsigned base_indx, unsigned offset)
34
-
{
35
-
return host1x_uclass_wait_syncpt_base_indx_f(indx)
36
-
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
37
-
| host1x_uclass_wait_syncpt_base_offset_f(offset);
38
-
}
39
-
40
-
static inline u32 host1x_class_host_incr_syncpt_base(
41
-
unsigned base_indx, unsigned offset)
42
-
{
43
-
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
44
-
| host1x_uclass_incr_syncpt_base_offset_f(offset);
45
-
}
46
-
47
-
static inline u32 host1x_class_host_incr_syncpt(
48
-
unsigned cond, unsigned indx)
49
-
{
50
-
return host1x_uclass_incr_syncpt_cond_f(cond)
51
-
| host1x_uclass_incr_syncpt_indx_f(indx);
52
-
}
53
-
54
-
static inline u32 host1x_class_host_indoff_reg_write(
55
-
unsigned mod_id, unsigned offset, bool auto_inc)
56
-
{
57
-
u32 v = host1x_uclass_indoff_indbe_f(0xf)
58
-
| host1x_uclass_indoff_indmodid_f(mod_id)
59
-
| host1x_uclass_indoff_indroffset_f(offset);
60
-
if (auto_inc)
61
-
v |= host1x_uclass_indoff_autoinc_f(1);
62
-
return v;
63
-
}
64
-
65
-
static inline u32 host1x_class_host_indoff_reg_read(
66
-
unsigned mod_id, unsigned offset, bool auto_inc)
67
-
{
68
-
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
69
-
| host1x_uclass_indoff_indroffset_f(offset)
70
-
| host1x_uclass_indoff_rwn_read_v();
71
-
if (auto_inc)
72
-
v |= host1x_uclass_indoff_autoinc_f(1);
73
-
return v;
74
-
}
75
-
76
-
/* cdma opcodes */
77
-
static inline u32 host1x_opcode_setclass(
78
-
unsigned class_id, unsigned offset, unsigned mask)
79
-
{
80
-
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
81
-
}
82
-
83
-
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
84
-
{
85
-
return (1 << 28) | (offset << 16) | count;
86
-
}
87
-
88
-
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
89
-
{
90
-
return (2 << 28) | (offset << 16) | count;
91
-
}
92
-
93
-
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
94
-
{
95
-
return (3 << 28) | (offset << 16) | mask;
96
-
}
97
-
98
-
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
99
-
{
100
-
return (4 << 28) | (offset << 16) | value;
101
-
}
102
-
103
-
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
104
-
{
105
-
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
106
-
host1x_class_host_incr_syncpt(cond, indx));
107
-
}
108
-
109
-
static inline u32 host1x_opcode_restart(unsigned address)
110
-
{
111
-
return (5 << 28) | (address >> 4);
112
-
}
113
-
114
-
static inline u32 host1x_opcode_gather(unsigned count)
115
-
{
116
-
return (6 << 28) | count;
117
-
}
118
-
119
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
120
-
{
121
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
122
-
}
123
-
124
-
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
125
-
{
126
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
127
-
}
128
-
129
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
18
+
#include "opcodes.h"
130
19
131
20
#endif
+1
-112
drivers/gpu/host1x/hw/host1x05_hardware.h
+1
-112
drivers/gpu/host1x/hw/host1x05_hardware.h
···
15
15
#include "hw_host1x05_sync.h"
16
16
#include "hw_host1x05_uclass.h"
17
17
18
-
static inline u32 host1x_class_host_wait_syncpt(
19
-
unsigned indx, unsigned threshold)
20
-
{
21
-
return host1x_uclass_wait_syncpt_indx_f(indx)
22
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
23
-
}
24
-
25
-
static inline u32 host1x_class_host_load_syncpt_base(
26
-
unsigned indx, unsigned threshold)
27
-
{
28
-
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
29
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
30
-
}
31
-
32
-
static inline u32 host1x_class_host_wait_syncpt_base(
33
-
unsigned indx, unsigned base_indx, unsigned offset)
34
-
{
35
-
return host1x_uclass_wait_syncpt_base_indx_f(indx)
36
-
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
37
-
| host1x_uclass_wait_syncpt_base_offset_f(offset);
38
-
}
39
-
40
-
static inline u32 host1x_class_host_incr_syncpt_base(
41
-
unsigned base_indx, unsigned offset)
42
-
{
43
-
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
44
-
| host1x_uclass_incr_syncpt_base_offset_f(offset);
45
-
}
46
-
47
-
static inline u32 host1x_class_host_incr_syncpt(
48
-
unsigned cond, unsigned indx)
49
-
{
50
-
return host1x_uclass_incr_syncpt_cond_f(cond)
51
-
| host1x_uclass_incr_syncpt_indx_f(indx);
52
-
}
53
-
54
-
static inline u32 host1x_class_host_indoff_reg_write(
55
-
unsigned mod_id, unsigned offset, bool auto_inc)
56
-
{
57
-
u32 v = host1x_uclass_indoff_indbe_f(0xf)
58
-
| host1x_uclass_indoff_indmodid_f(mod_id)
59
-
| host1x_uclass_indoff_indroffset_f(offset);
60
-
if (auto_inc)
61
-
v |= host1x_uclass_indoff_autoinc_f(1);
62
-
return v;
63
-
}
64
-
65
-
static inline u32 host1x_class_host_indoff_reg_read(
66
-
unsigned mod_id, unsigned offset, bool auto_inc)
67
-
{
68
-
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
69
-
| host1x_uclass_indoff_indroffset_f(offset)
70
-
| host1x_uclass_indoff_rwn_read_v();
71
-
if (auto_inc)
72
-
v |= host1x_uclass_indoff_autoinc_f(1);
73
-
return v;
74
-
}
75
-
76
-
/* cdma opcodes */
77
-
static inline u32 host1x_opcode_setclass(
78
-
unsigned class_id, unsigned offset, unsigned mask)
79
-
{
80
-
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
81
-
}
82
-
83
-
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
84
-
{
85
-
return (1 << 28) | (offset << 16) | count;
86
-
}
87
-
88
-
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
89
-
{
90
-
return (2 << 28) | (offset << 16) | count;
91
-
}
92
-
93
-
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
94
-
{
95
-
return (3 << 28) | (offset << 16) | mask;
96
-
}
97
-
98
-
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
99
-
{
100
-
return (4 << 28) | (offset << 16) | value;
101
-
}
102
-
103
-
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
104
-
{
105
-
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
106
-
host1x_class_host_incr_syncpt(cond, indx));
107
-
}
108
-
109
-
static inline u32 host1x_opcode_restart(unsigned address)
110
-
{
111
-
return (5 << 28) | (address >> 4);
112
-
}
113
-
114
-
static inline u32 host1x_opcode_gather(unsigned count)
115
-
{
116
-
return (6 << 28) | count;
117
-
}
118
-
119
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
120
-
{
121
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
122
-
}
123
-
124
-
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
125
-
{
126
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
127
-
}
128
-
129
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
18
+
#include "opcodes.h"
130
19
131
20
#endif
+1
-117
drivers/gpu/host1x/hw/host1x06_hardware.h
+1
-117
drivers/gpu/host1x/hw/host1x06_hardware.h
···
16
16
#include "hw_host1x06_vm.h"
17
17
#include "hw_host1x06_hypervisor.h"
18
18
19
-
static inline u32 host1x_class_host_wait_syncpt(
20
-
unsigned indx, unsigned threshold)
21
-
{
22
-
return host1x_uclass_wait_syncpt_indx_f(indx)
23
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
24
-
}
25
-
26
-
static inline u32 host1x_class_host_load_syncpt_base(
27
-
unsigned indx, unsigned threshold)
28
-
{
29
-
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
30
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
31
-
}
32
-
33
-
static inline u32 host1x_class_host_wait_syncpt_base(
34
-
unsigned indx, unsigned base_indx, unsigned offset)
35
-
{
36
-
return host1x_uclass_wait_syncpt_base_indx_f(indx)
37
-
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
38
-
| host1x_uclass_wait_syncpt_base_offset_f(offset);
39
-
}
40
-
41
-
static inline u32 host1x_class_host_incr_syncpt_base(
42
-
unsigned base_indx, unsigned offset)
43
-
{
44
-
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
45
-
| host1x_uclass_incr_syncpt_base_offset_f(offset);
46
-
}
47
-
48
-
static inline u32 host1x_class_host_incr_syncpt(
49
-
unsigned cond, unsigned indx)
50
-
{
51
-
return host1x_uclass_incr_syncpt_cond_f(cond)
52
-
| host1x_uclass_incr_syncpt_indx_f(indx);
53
-
}
54
-
55
-
static inline u32 host1x_class_host_indoff_reg_write(
56
-
unsigned mod_id, unsigned offset, bool auto_inc)
57
-
{
58
-
u32 v = host1x_uclass_indoff_indbe_f(0xf)
59
-
| host1x_uclass_indoff_indmodid_f(mod_id)
60
-
| host1x_uclass_indoff_indroffset_f(offset);
61
-
if (auto_inc)
62
-
v |= host1x_uclass_indoff_autoinc_f(1);
63
-
return v;
64
-
}
65
-
66
-
static inline u32 host1x_class_host_indoff_reg_read(
67
-
unsigned mod_id, unsigned offset, bool auto_inc)
68
-
{
69
-
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
70
-
| host1x_uclass_indoff_indroffset_f(offset)
71
-
| host1x_uclass_indoff_rwn_read_v();
72
-
if (auto_inc)
73
-
v |= host1x_uclass_indoff_autoinc_f(1);
74
-
return v;
75
-
}
76
-
77
-
/* cdma opcodes */
78
-
static inline u32 host1x_opcode_setclass(
79
-
unsigned class_id, unsigned offset, unsigned mask)
80
-
{
81
-
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
82
-
}
83
-
84
-
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
85
-
{
86
-
return (1 << 28) | (offset << 16) | count;
87
-
}
88
-
89
-
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
90
-
{
91
-
return (2 << 28) | (offset << 16) | count;
92
-
}
93
-
94
-
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
95
-
{
96
-
return (3 << 28) | (offset << 16) | mask;
97
-
}
98
-
99
-
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
100
-
{
101
-
return (4 << 28) | (offset << 16) | value;
102
-
}
103
-
104
-
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
105
-
{
106
-
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
107
-
host1x_class_host_incr_syncpt(cond, indx));
108
-
}
109
-
110
-
static inline u32 host1x_opcode_restart(unsigned address)
111
-
{
112
-
return (5 << 28) | (address >> 4);
113
-
}
114
-
115
-
static inline u32 host1x_opcode_gather(unsigned count)
116
-
{
117
-
return (6 << 28) | count;
118
-
}
119
-
120
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
121
-
{
122
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
123
-
}
124
-
125
-
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
126
-
{
127
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
128
-
}
129
-
130
-
static inline u32 host1x_opcode_gather_wide(unsigned count)
131
-
{
132
-
return (12 << 28) | count;
133
-
}
134
-
135
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
19
+
#include "opcodes.h"
136
20
137
21
#endif
+1
-117
drivers/gpu/host1x/hw/host1x07_hardware.h
+1
-117
drivers/gpu/host1x/hw/host1x07_hardware.h
···
16
16
#include "hw_host1x07_vm.h"
17
17
#include "hw_host1x07_hypervisor.h"
18
18
19
-
static inline u32 host1x_class_host_wait_syncpt(
20
-
unsigned indx, unsigned threshold)
21
-
{
22
-
return host1x_uclass_wait_syncpt_indx_f(indx)
23
-
| host1x_uclass_wait_syncpt_thresh_f(threshold);
24
-
}
25
-
26
-
static inline u32 host1x_class_host_load_syncpt_base(
27
-
unsigned indx, unsigned threshold)
28
-
{
29
-
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
30
-
| host1x_uclass_load_syncpt_base_value_f(threshold);
31
-
}
32
-
33
-
static inline u32 host1x_class_host_wait_syncpt_base(
34
-
unsigned indx, unsigned base_indx, unsigned offset)
35
-
{
36
-
return host1x_uclass_wait_syncpt_base_indx_f(indx)
37
-
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
38
-
| host1x_uclass_wait_syncpt_base_offset_f(offset);
39
-
}
40
-
41
-
static inline u32 host1x_class_host_incr_syncpt_base(
42
-
unsigned base_indx, unsigned offset)
43
-
{
44
-
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
45
-
| host1x_uclass_incr_syncpt_base_offset_f(offset);
46
-
}
47
-
48
-
static inline u32 host1x_class_host_incr_syncpt(
49
-
unsigned cond, unsigned indx)
50
-
{
51
-
return host1x_uclass_incr_syncpt_cond_f(cond)
52
-
| host1x_uclass_incr_syncpt_indx_f(indx);
53
-
}
54
-
55
-
static inline u32 host1x_class_host_indoff_reg_write(
56
-
unsigned mod_id, unsigned offset, bool auto_inc)
57
-
{
58
-
u32 v = host1x_uclass_indoff_indbe_f(0xf)
59
-
| host1x_uclass_indoff_indmodid_f(mod_id)
60
-
| host1x_uclass_indoff_indroffset_f(offset);
61
-
if (auto_inc)
62
-
v |= host1x_uclass_indoff_autoinc_f(1);
63
-
return v;
64
-
}
65
-
66
-
static inline u32 host1x_class_host_indoff_reg_read(
67
-
unsigned mod_id, unsigned offset, bool auto_inc)
68
-
{
69
-
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
70
-
| host1x_uclass_indoff_indroffset_f(offset)
71
-
| host1x_uclass_indoff_rwn_read_v();
72
-
if (auto_inc)
73
-
v |= host1x_uclass_indoff_autoinc_f(1);
74
-
return v;
75
-
}
76
-
77
-
/* cdma opcodes */
78
-
static inline u32 host1x_opcode_setclass(
79
-
unsigned class_id, unsigned offset, unsigned mask)
80
-
{
81
-
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
82
-
}
83
-
84
-
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
85
-
{
86
-
return (1 << 28) | (offset << 16) | count;
87
-
}
88
-
89
-
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
90
-
{
91
-
return (2 << 28) | (offset << 16) | count;
92
-
}
93
-
94
-
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
95
-
{
96
-
return (3 << 28) | (offset << 16) | mask;
97
-
}
98
-
99
-
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
100
-
{
101
-
return (4 << 28) | (offset << 16) | value;
102
-
}
103
-
104
-
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
105
-
{
106
-
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
107
-
host1x_class_host_incr_syncpt(cond, indx));
108
-
}
109
-
110
-
static inline u32 host1x_opcode_restart(unsigned address)
111
-
{
112
-
return (5 << 28) | (address >> 4);
113
-
}
114
-
115
-
static inline u32 host1x_opcode_gather(unsigned count)
116
-
{
117
-
return (6 << 28) | count;
118
-
}
119
-
120
-
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
121
-
{
122
-
return (6 << 28) | (offset << 16) | BIT(15) | count;
123
-
}
124
-
125
-
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
126
-
{
127
-
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
128
-
}
129
-
130
-
static inline u32 host1x_opcode_gather_wide(unsigned count)
131
-
{
132
-
return (12 << 28) | count;
133
-
}
134
-
135
-
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
19
+
#include "opcodes.h"
136
20
137
21
#endif
+33
drivers/gpu/host1x/hw/host1x08.c
+33
drivers/gpu/host1x/hw/host1x08.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Host1x init for Tegra234 SoCs
4
+
*
5
+
* Copyright (c) 2022 NVIDIA Corporation.
6
+
*/
7
+
8
+
/* include hw specification */
9
+
#include "host1x08.h"
10
+
#include "host1x08_hardware.h"
11
+
12
+
/* include code */
13
+
#define HOST1X_HW 8
14
+
15
+
#include "cdma_hw.c"
16
+
#include "channel_hw.c"
17
+
#include "debug_hw.c"
18
+
#include "intr_hw.c"
19
+
#include "syncpt_hw.c"
20
+
21
+
#include "../dev.h"
22
+
23
+
int host1x08_init(struct host1x *host)
24
+
{
25
+
host->channel_op = &host1x_channel_ops;
26
+
host->cdma_op = &host1x_cdma_ops;
27
+
host->cdma_pb_op = &host1x_pushbuffer_ops;
28
+
host->syncpt_op = &host1x_syncpt_ops;
29
+
host->intr_op = &host1x_intr_ops;
30
+
host->debug_op = &host1x_debug_ops;
31
+
32
+
return 0;
33
+
}
+15
drivers/gpu/host1x/hw/host1x08.h
+15
drivers/gpu/host1x/hw/host1x08.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Host1x init for Tegra234 SoCs
4
+
*
5
+
* Copyright (c) 2018 NVIDIA Corporation.
6
+
*/
7
+
8
+
#ifndef HOST1X_HOST1X08_H
9
+
#define HOST1X_HOST1X08_H
10
+
11
+
struct host1x;
12
+
13
+
int host1x08_init(struct host1x *host);
14
+
15
+
#endif
+21
drivers/gpu/host1x/hw/host1x08_hardware.h
+21
drivers/gpu/host1x/hw/host1x08_hardware.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Tegra host1x Register Offsets for Tegra234
4
+
*
5
+
* Copyright (c) 2022 NVIDIA Corporation.
6
+
*/
7
+
8
+
#ifndef __HOST1X_HOST1X08_HARDWARE_H
9
+
#define __HOST1X_HOST1X08_HARDWARE_H
10
+
11
+
#include <linux/types.h>
12
+
#include <linux/bitops.h>
13
+
14
+
#include "hw_host1x08_uclass.h"
15
+
#include "hw_host1x08_vm.h"
16
+
#include "hw_host1x08_hypervisor.h"
17
+
#include "hw_host1x08_common.h"
18
+
19
+
#include "opcodes.h"
20
+
21
+
#endif
+11
drivers/gpu/host1x/hw/hw_host1x08_channel.h
+11
drivers/gpu/host1x/hw/hw_host1x08_channel.h
+11
drivers/gpu/host1x/hw/hw_host1x08_common.h
+11
drivers/gpu/host1x/hw/hw_host1x08_common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2022 NVIDIA Corporation.
4
+
*/
5
+
6
+
#define HOST1X_COMMON_OFA_MLOCK 0x4050
7
+
#define HOST1X_COMMON_NVJPG1_MLOCK 0x4070
8
+
#define HOST1X_COMMON_VIC_MLOCK 0x4078
9
+
#define HOST1X_COMMON_NVENC_MLOCK 0x407c
10
+
#define HOST1X_COMMON_NVDEC_MLOCK 0x4080
11
+
#define HOST1X_COMMON_NVJPG_MLOCK 0x4084
+9
drivers/gpu/host1x/hw/hw_host1x08_hypervisor.h
+9
drivers/gpu/host1x/hw/hw_host1x08_hypervisor.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2022 NVIDIA Corporation.
4
+
*/
5
+
6
+
#define HOST1X_HV_SYNCPT_PROT_EN 0x1724
7
+
#define HOST1X_HV_SYNCPT_PROT_EN_CH_EN BIT(1)
8
+
#define HOST1X_HV_CH_MLOCK_EN(x) (0x1700 + (x * 4))
9
+
#define HOST1X_HV_CH_KERNEL_FILTER_GBUFFER(x) (0x1710 + (x * 4))
+181
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
+181
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2018 NVIDIA Corporation.
4
+
*/
5
+
6
+
/*
7
+
* Function naming determines intended use:
8
+
*
9
+
* <x>_r(void) : Returns the offset for register <x>.
10
+
*
11
+
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
12
+
*
13
+
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
14
+
*
15
+
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
16
+
* and masked to place it at field <y> of register <x>. This value
17
+
* can be |'d with others to produce a full register value for
18
+
* register <x>.
19
+
*
20
+
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
21
+
* value can be ~'d and then &'d to clear the value of field <y> for
22
+
* register <x>.
23
+
*
24
+
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
25
+
* to place it at field <y> of register <x>. This value can be |'d
26
+
* with others to produce a full register value for <x>.
27
+
*
28
+
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
29
+
* <x> value 'r' after being shifted to place its LSB at bit 0.
30
+
* This value is suitable for direct comparison with other unshifted
31
+
* values appropriate for use in field <y> of register <x>.
32
+
*
33
+
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
34
+
* field <y> of register <x>. This value is suitable for direct
35
+
* comparison with unshifted values appropriate for use in field <y>
36
+
* of register <x>.
37
+
*/
38
+
39
+
#ifndef HOST1X_HW_HOST1X08_UCLASS_H
40
+
#define HOST1X_HW_HOST1X08_UCLASS_H
41
+
42
+
static inline u32 host1x_uclass_incr_syncpt_r(void)
43
+
{
44
+
return 0x0;
45
+
}
46
+
#define HOST1X_UCLASS_INCR_SYNCPT \
47
+
host1x_uclass_incr_syncpt_r()
48
+
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
49
+
{
50
+
return (v & 0xff) << 10;
51
+
}
52
+
#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
53
+
host1x_uclass_incr_syncpt_cond_f(v)
54
+
static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
55
+
{
56
+
return (v & 0xff) << 0;
57
+
}
58
+
#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
59
+
host1x_uclass_incr_syncpt_indx_f(v)
60
+
static inline u32 host1x_uclass_wait_syncpt_r(void)
61
+
{
62
+
return 0x8;
63
+
}
64
+
#define HOST1X_UCLASS_WAIT_SYNCPT \
65
+
host1x_uclass_wait_syncpt_r()
66
+
static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
67
+
{
68
+
return (v & 0xff) << 24;
69
+
}
70
+
#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
71
+
host1x_uclass_wait_syncpt_indx_f(v)
72
+
static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
73
+
{
74
+
return (v & 0xffffff) << 0;
75
+
}
76
+
#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
77
+
host1x_uclass_wait_syncpt_thresh_f(v)
78
+
static inline u32 host1x_uclass_wait_syncpt_base_r(void)
79
+
{
80
+
return 0x9;
81
+
}
82
+
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
83
+
host1x_uclass_wait_syncpt_base_r()
84
+
static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
85
+
{
86
+
return (v & 0xff) << 24;
87
+
}
88
+
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
89
+
host1x_uclass_wait_syncpt_base_indx_f(v)
90
+
static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
91
+
{
92
+
return (v & 0xff) << 16;
93
+
}
94
+
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
95
+
host1x_uclass_wait_syncpt_base_base_indx_f(v)
96
+
static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
97
+
{
98
+
return (v & 0xffff) << 0;
99
+
}
100
+
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
101
+
host1x_uclass_wait_syncpt_base_offset_f(v)
102
+
static inline u32 host1x_uclass_load_syncpt_base_r(void)
103
+
{
104
+
return 0xb;
105
+
}
106
+
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
107
+
host1x_uclass_load_syncpt_base_r()
108
+
static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
109
+
{
110
+
return (v & 0xff) << 24;
111
+
}
112
+
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
113
+
host1x_uclass_load_syncpt_base_base_indx_f(v)
114
+
static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
115
+
{
116
+
return (v & 0xffffff) << 0;
117
+
}
118
+
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
119
+
host1x_uclass_load_syncpt_base_value_f(v)
120
+
static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
121
+
{
122
+
return (v & 0xff) << 24;
123
+
}
124
+
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
125
+
host1x_uclass_incr_syncpt_base_base_indx_f(v)
126
+
static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
127
+
{
128
+
return (v & 0xffffff) << 0;
129
+
}
130
+
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
131
+
host1x_uclass_incr_syncpt_base_offset_f(v)
132
+
static inline u32 host1x_uclass_indoff_r(void)
133
+
{
134
+
return 0x2d;
135
+
}
136
+
#define HOST1X_UCLASS_INDOFF \
137
+
host1x_uclass_indoff_r()
138
+
static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
139
+
{
140
+
return (v & 0xf) << 28;
141
+
}
142
+
#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
143
+
host1x_uclass_indoff_indbe_f(v)
144
+
static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
145
+
{
146
+
return (v & 0x1) << 27;
147
+
}
148
+
#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
149
+
host1x_uclass_indoff_autoinc_f(v)
150
+
static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
151
+
{
152
+
return (v & 0xff) << 18;
153
+
}
154
+
#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
155
+
host1x_uclass_indoff_indmodid_f(v)
156
+
static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
157
+
{
158
+
return (v & 0xffff) << 2;
159
+
}
160
+
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
161
+
host1x_uclass_indoff_indroffset_f(v)
162
+
static inline u32 host1x_uclass_indoff_rwn_read_v(void)
163
+
{
164
+
return 1;
165
+
}
166
+
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
167
+
host1x_uclass_indoff_indroffset_f(v)
168
+
static inline u32 host1x_uclass_load_syncpt_payload_32_r(void)
169
+
{
170
+
return 0x4e;
171
+
}
172
+
#define HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32 \
173
+
host1x_uclass_load_syncpt_payload_32_r()
174
+
static inline u32 host1x_uclass_wait_syncpt_32_r(void)
175
+
{
176
+
return 0x50;
177
+
}
178
+
#define HOST1X_UCLASS_WAIT_SYNCPT_32 \
179
+
host1x_uclass_wait_syncpt_32_r()
180
+
181
+
#endif
+36
drivers/gpu/host1x/hw/hw_host1x08_vm.h
+36
drivers/gpu/host1x/hw/hw_host1x08_vm.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2022 NVIDIA Corporation.
4
+
*/
5
+
6
+
#define HOST1X_CHANNEL_DMASTART 0x0000
7
+
#define HOST1X_CHANNEL_DMASTART_HI 0x0004
8
+
#define HOST1X_CHANNEL_DMAPUT 0x0008
9
+
#define HOST1X_CHANNEL_DMAPUT_HI 0x000c
10
+
#define HOST1X_CHANNEL_DMAGET 0x0010
11
+
#define HOST1X_CHANNEL_DMAGET_HI 0x0014
12
+
#define HOST1X_CHANNEL_DMAEND 0x0018
13
+
#define HOST1X_CHANNEL_DMAEND_HI 0x001c
14
+
#define HOST1X_CHANNEL_DMACTRL 0x0020
15
+
#define HOST1X_CHANNEL_DMACTRL_DMASTOP BIT(0)
16
+
#define HOST1X_CHANNEL_DMACTRL_DMAGETRST BIT(1)
17
+
#define HOST1X_CHANNEL_DMACTRL_DMAINITGET BIT(2)
18
+
#define HOST1X_CHANNEL_CMDFIFO_STAT 0x0024
19
+
#define HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY BIT(13)
20
+
#define HOST1X_CHANNEL_CMDFIFO_RDATA 0x0028
21
+
#define HOST1X_CHANNEL_CMDP_OFFSET 0x0030
22
+
#define HOST1X_CHANNEL_CMDP_CLASS 0x0034
23
+
#define HOST1X_CHANNEL_CHANNELSTAT 0x0038
24
+
#define HOST1X_CHANNEL_CMDPROC_STOP 0x0048
25
+
#define HOST1X_CHANNEL_TEARDOWN 0x004c
26
+
#define HOST1X_CHANNEL_SMMU_STREAMID 0x0084
27
+
28
+
#define HOST1X_SYNC_SYNCPT_CPU_INCR(x) (0x6400 + 4 * (x))
29
+
#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(x) (0x6600 + 4 * (x))
30
+
#define HOST1X_SYNC_SYNCPT_INTR_DEST(x) (0x6684 + 4 * (x))
31
+
#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(x) (0x770c + 4 * (x))
32
+
#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(x) (0x7790 + 4 * (x))
33
+
#define HOST1X_SYNC_SYNCPT(x) (0x8080 + 4 * (x))
34
+
#define HOST1X_SYNC_SYNCPT_INT_THRESH(x) (0xa088 + 4 * (x))
35
+
#define HOST1X_SYNC_SYNCPT_CH_APP(x) (0xb090 + 4 * (x))
36
+
#define HOST1X_SYNC_SYNCPT_CH_APP_CH(v) (((v) & 0x3f) << 8)
+11
drivers/gpu/host1x/hw/intr_hw.c
+11
drivers/gpu/host1x/hw/intr_hw.c
···
76
76
/* update host clocks per usec */
77
77
host1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK);
78
78
#endif
79
+
#if HOST1X_HW >= 8
80
+
u32 id;
81
+
82
+
/*
83
+
* Program threshold interrupt destination among 8 lines per VM,
84
+
* per syncpoint. For now, just direct all to the first interrupt
85
+
* line.
86
+
*/
87
+
for (id = 0; id < host->info->nb_pts; id++)
88
+
host1x_sync_writel(host, 0, HOST1X_SYNC_SYNCPT_INTR_DEST(id));
89
+
#endif
79
90
}
80
91
81
92
static int
+150
drivers/gpu/host1x/hw/opcodes.h
+150
drivers/gpu/host1x/hw/opcodes.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Tegra host1x opcodes
4
+
*
5
+
* Copyright (c) 2022 NVIDIA Corporation.
6
+
*/
7
+
8
+
#ifndef __HOST1X_OPCODES_H
9
+
#define __HOST1X_OPCODES_H
10
+
11
+
#include <linux/types.h>
12
+
13
+
static inline u32 host1x_class_host_wait_syncpt(
14
+
unsigned indx, unsigned threshold)
15
+
{
16
+
return host1x_uclass_wait_syncpt_indx_f(indx)
17
+
| host1x_uclass_wait_syncpt_thresh_f(threshold);
18
+
}
19
+
20
+
static inline u32 host1x_class_host_load_syncpt_base(
21
+
unsigned indx, unsigned threshold)
22
+
{
23
+
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
24
+
| host1x_uclass_load_syncpt_base_value_f(threshold);
25
+
}
26
+
27
+
static inline u32 host1x_class_host_wait_syncpt_base(
28
+
unsigned indx, unsigned base_indx, unsigned offset)
29
+
{
30
+
return host1x_uclass_wait_syncpt_base_indx_f(indx)
31
+
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
32
+
| host1x_uclass_wait_syncpt_base_offset_f(offset);
33
+
}
34
+
35
+
static inline u32 host1x_class_host_incr_syncpt_base(
36
+
unsigned base_indx, unsigned offset)
37
+
{
38
+
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
39
+
| host1x_uclass_incr_syncpt_base_offset_f(offset);
40
+
}
41
+
42
+
static inline u32 host1x_class_host_incr_syncpt(
43
+
unsigned cond, unsigned indx)
44
+
{
45
+
return host1x_uclass_incr_syncpt_cond_f(cond)
46
+
| host1x_uclass_incr_syncpt_indx_f(indx);
47
+
}
48
+
49
+
static inline u32 host1x_class_host_indoff_reg_write(
50
+
unsigned mod_id, unsigned offset, bool auto_inc)
51
+
{
52
+
u32 v = host1x_uclass_indoff_indbe_f(0xf)
53
+
| host1x_uclass_indoff_indmodid_f(mod_id)
54
+
| host1x_uclass_indoff_indroffset_f(offset);
55
+
if (auto_inc)
56
+
v |= host1x_uclass_indoff_autoinc_f(1);
57
+
return v;
58
+
}
59
+
60
+
static inline u32 host1x_class_host_indoff_reg_read(
61
+
unsigned mod_id, unsigned offset, bool auto_inc)
62
+
{
63
+
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
64
+
| host1x_uclass_indoff_indroffset_f(offset)
65
+
| host1x_uclass_indoff_rwn_read_v();
66
+
if (auto_inc)
67
+
v |= host1x_uclass_indoff_autoinc_f(1);
68
+
return v;
69
+
}
70
+
71
+
static inline u32 host1x_opcode_setclass(
72
+
unsigned class_id, unsigned offset, unsigned mask)
73
+
{
74
+
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
75
+
}
76
+
77
+
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
78
+
{
79
+
return (1 << 28) | (offset << 16) | count;
80
+
}
81
+
82
+
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
83
+
{
84
+
return (2 << 28) | (offset << 16) | count;
85
+
}
86
+
87
+
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
88
+
{
89
+
return (3 << 28) | (offset << 16) | mask;
90
+
}
91
+
92
+
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
93
+
{
94
+
return (4 << 28) | (offset << 16) | value;
95
+
}
96
+
97
+
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
98
+
{
99
+
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
100
+
host1x_class_host_incr_syncpt(cond, indx));
101
+
}
102
+
103
+
static inline u32 host1x_opcode_restart(unsigned address)
104
+
{
105
+
return (5 << 28) | (address >> 4);
106
+
}
107
+
108
+
static inline u32 host1x_opcode_gather(unsigned count)
109
+
{
110
+
return (6 << 28) | count;
111
+
}
112
+
113
+
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
114
+
{
115
+
return (6 << 28) | (offset << 16) | BIT(15) | count;
116
+
}
117
+
118
+
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
119
+
{
120
+
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
121
+
}
122
+
123
+
static inline u32 host1x_opcode_setstreamid(unsigned streamid)
124
+
{
125
+
return (7 << 28) | streamid;
126
+
}
127
+
128
+
static inline u32 host1x_opcode_setpayload(unsigned payload)
129
+
{
130
+
return (9 << 28) | payload;
131
+
}
132
+
133
+
static inline u32 host1x_opcode_gather_wide(unsigned count)
134
+
{
135
+
return (12 << 28) | count;
136
+
}
137
+
138
+
static inline u32 host1x_opcode_acquire_mlock(unsigned mlock)
139
+
{
140
+
return (14 << 28) | (0 << 24) | mlock;
141
+
}
142
+
143
+
static inline u32 host1x_opcode_release_mlock(unsigned mlock)
144
+
{
145
+
return (14 << 28) | (1 << 24) | mlock;
146
+
}
147
+
148
+
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
149
+
150
+
#endif
+42
include/linux/host1x.h
+42
include/linux/host1x.h
···
327
327
328
328
/* Whether host1x-side firewall should be ran for this job or not */
329
329
bool enable_firewall;
330
+
331
+
/* Options for configuring engine data stream ID */
332
+
/* Context device to use for job */
333
+
struct host1x_memory_context *memory_context;
334
+
/* Stream ID to use if context isolation is disabled (!memory_context) */
335
+
u32 engine_fallback_streamid;
336
+
/* Engine offset to program stream ID to */
337
+
u32 engine_streamid_offset;
330
338
};
331
339
332
340
struct host1x_job *host1x_job_alloc(struct host1x_channel *ch,
···
453
445
int tegra_mipi_disable(struct tegra_mipi_device *device);
454
446
int tegra_mipi_start_calibration(struct tegra_mipi_device *device);
455
447
int tegra_mipi_finish_calibration(struct tegra_mipi_device *device);
448
+
449
+
/* host1x memory contexts */
450
+
451
+
struct host1x_memory_context {
452
+
struct host1x *host;
453
+
454
+
refcount_t ref;
455
+
struct pid *owner;
456
+
457
+
struct device dev;
458
+
u64 dma_mask;
459
+
u32 stream_id;
460
+
};
461
+
462
+
#ifdef CONFIG_IOMMU_API
463
+
struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
464
+
struct pid *pid);
465
+
void host1x_memory_context_get(struct host1x_memory_context *cd);
466
+
void host1x_memory_context_put(struct host1x_memory_context *cd);
467
+
#else
468
+
static inline struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
469
+
struct pid *pid)
470
+
{
471
+
return NULL;
472
+
}
473
+
474
+
static inline void host1x_memory_context_get(struct host1x_memory_context *cd)
475
+
{
476
+
}
477
+
478
+
static inline void host1x_memory_context_put(struct host1x_memory_context *cd)
479
+
{
480
+
}
481
+
#endif
456
482
457
483
#endif