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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: sun4i-usb: Replace types with explicit quirk flags
So far we were assigning some crude "type" (SoC name, really) to each
Allwinner USB PHY model, then guarding certain quirks based on this.
This does not only look weird, but gets more or more cumbersome to
maintain.
Remove the bogus type names altogether, instead introduce flags for each
quirk, and explicitly check for them.
This improves readability, and simplifies future extensions.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230109012223.4079299-4-andre.przywara@arm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Andre Przywara
and committed by
Vinod Koul
8dd256ba
50bd67ab
+15
-36
+15
-36
drivers/phy/allwinner/phy-sun4i-usb.c
+15
-36
drivers/phy/allwinner/phy-sun4i-usb.c
···
99
99
#define DEBOUNCE_TIME msecs_to_jiffies(50)
100
100
#define POLL_TIME msecs_to_jiffies(250)
101
101
102
-
enum sun4i_usb_phy_type {
103
-
sun4i_a10_phy,
104
-
sun6i_a31_phy,
105
-
sun8i_a33_phy,
106
-
sun8i_a83t_phy,
107
-
sun8i_h3_phy,
108
-
sun8i_r40_phy,
109
-
sun8i_v3s_phy,
110
-
sun50i_a64_phy,
111
-
sun50i_h6_phy,
112
-
};
113
-
114
102
struct sun4i_usb_phy_cfg {
115
103
int num_phys;
116
104
int hsic_index;
117
-
enum sun4i_usb_phy_type type;
118
105
u32 disc_thresh;
119
106
u32 hci_phy_ctl_clear;
120
107
u8 phyctl_offset;
121
108
bool dedicated_clocks;
122
109
bool phy0_dual_route;
123
110
bool needs_phy2_siddq;
111
+
bool siddq_in_base;
112
+
bool poll_vbusen;
124
113
int missing_phys;
125
114
};
126
115
···
241
252
SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
242
253
243
254
/* A83T USB2 is HSIC */
244
-
if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2)
255
+
if (phy_data->cfg->hsic_index &&
256
+
phy->index == phy_data->cfg->hsic_index)
245
257
bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
246
258
SUNXI_HSIC;
247
259
···
330
340
writel(val, phy->pmu + REG_HCI_PHY_CTL);
331
341
}
332
342
333
-
if (data->cfg->type == sun8i_a83t_phy ||
334
-
data->cfg->type == sun50i_h6_phy) {
343
+
if (data->cfg->siddq_in_base) {
335
344
if (phy->index == 0) {
336
345
val = readl(data->base + data->cfg->phyctl_offset);
337
346
val |= PHY_CTL_VBUSVLDEXT;
···
374
385
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
375
386
376
387
if (phy->index == 0) {
377
-
if (data->cfg->type == sun8i_a83t_phy ||
378
-
data->cfg->type == sun50i_h6_phy) {
388
+
if (data->cfg->siddq_in_base) {
379
389
void __iomem *phyctl = data->base +
380
390
data->cfg->phyctl_offset;
381
391
···
454
466
* vbus using the N_VBUSEN pin on the pmic, so we must poll
455
467
* when using the pmic for vbus-det _and_ we're driving vbus.
456
468
*/
457
-
if ((data->cfg->type == sun6i_a31_phy ||
458
-
data->cfg->type == sun8i_a33_phy) &&
459
-
data->vbus_power_supply && data->phys[0].regulator_on)
469
+
if (data->cfg->poll_vbusen && data->vbus_power_supply &&
470
+
data->phys[0].regulator_on)
460
471
return true;
461
472
462
473
return false;
···
907
920
908
921
static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
909
922
.num_phys = 1,
910
-
.type = sun4i_a10_phy,
911
923
.disc_thresh = 3,
912
924
.phyctl_offset = REG_PHYCTL_A10,
913
925
.dedicated_clocks = true,
···
914
928
915
929
static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
916
930
.num_phys = 3,
917
-
.type = sun4i_a10_phy,
918
931
.disc_thresh = 3,
919
932
.phyctl_offset = REG_PHYCTL_A10,
920
933
.dedicated_clocks = false,
···
921
936
922
937
static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
923
938
.num_phys = 2,
924
-
.type = sun4i_a10_phy,
925
939
.disc_thresh = 2,
926
940
.phyctl_offset = REG_PHYCTL_A10,
927
941
.dedicated_clocks = false,
···
928
944
929
945
static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
930
946
.num_phys = 3,
931
-
.type = sun6i_a31_phy,
932
947
.disc_thresh = 3,
933
948
.phyctl_offset = REG_PHYCTL_A10,
934
949
.dedicated_clocks = true,
950
+
.poll_vbusen = true,
935
951
};
936
952
937
953
static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
938
954
.num_phys = 3,
939
-
.type = sun4i_a10_phy,
940
955
.disc_thresh = 2,
941
956
.phyctl_offset = REG_PHYCTL_A10,
942
957
.dedicated_clocks = false,
···
943
960
944
961
static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
945
962
.num_phys = 2,
946
-
.type = sun6i_a31_phy,
947
963
.disc_thresh = 3,
948
964
.phyctl_offset = REG_PHYCTL_A10,
949
965
.dedicated_clocks = true,
966
+
.poll_vbusen = true,
950
967
};
951
968
952
969
static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
953
970
.num_phys = 2,
954
-
.type = sun8i_a33_phy,
955
971
.disc_thresh = 3,
956
972
.phyctl_offset = REG_PHYCTL_A33,
957
973
.dedicated_clocks = true,
974
+
.poll_vbusen = true,
958
975
};
959
976
960
977
static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
961
978
.num_phys = 3,
962
979
.hsic_index = 2,
963
-
.type = sun8i_a83t_phy,
964
980
.phyctl_offset = REG_PHYCTL_A33,
965
981
.dedicated_clocks = true,
982
+
.siddq_in_base = true,
966
983
};
967
984
968
985
static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
969
986
.num_phys = 4,
970
-
.type = sun8i_h3_phy,
971
987
.disc_thresh = 3,
972
988
.phyctl_offset = REG_PHYCTL_A33,
973
989
.dedicated_clocks = true,
···
976
994
977
995
static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
978
996
.num_phys = 3,
979
-
.type = sun8i_r40_phy,
980
997
.disc_thresh = 3,
981
998
.phyctl_offset = REG_PHYCTL_A33,
982
999
.dedicated_clocks = true,
···
985
1004
986
1005
static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
987
1006
.num_phys = 1,
988
-
.type = sun8i_v3s_phy,
989
1007
.disc_thresh = 3,
990
1008
.phyctl_offset = REG_PHYCTL_A33,
991
1009
.dedicated_clocks = true,
···
994
1014
995
1015
static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
996
1016
.num_phys = 2,
997
-
.type = sun50i_h6_phy,
998
1017
.phyctl_offset = REG_PHYCTL_A33,
999
1018
.dedicated_clocks = true,
1000
1019
.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
1001
1020
.phy0_dual_route = true,
1021
+
.siddq_in_base = true,
1002
1022
};
1003
1023
1004
1024
static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
1005
1025
.num_phys = 2,
1006
-
.type = sun50i_a64_phy,
1007
1026
.disc_thresh = 3,
1008
1027
.phyctl_offset = REG_PHYCTL_A33,
1009
1028
.dedicated_clocks = true,
···
1012
1033
1013
1034
static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
1014
1035
.num_phys = 4,
1015
-
.type = sun50i_h6_phy,
1016
1036
.phyctl_offset = REG_PHYCTL_A33,
1017
1037
.dedicated_clocks = true,
1018
1038
.phy0_dual_route = true,
1019
1039
.missing_phys = BIT(1) | BIT(2),
1040
+
.siddq_in_base = true,
1020
1041
};
1021
1042
1022
1043
static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
1023
1044
.num_phys = 4,
1024
-
.type = sun50i_h6_phy,
1025
1045
.disc_thresh = 3,
1026
1046
.phyctl_offset = REG_PHYCTL_A33,
1027
1047
.dedicated_clocks = true,
1028
1048
.phy0_dual_route = true,
1029
1049
.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
1030
1050
.needs_phy2_siddq = true,
1051
+
.siddq_in_base = true,
1031
1052
};
1032
1053
1033
1054
static const struct of_device_id sun4i_usb_phy_of_match[] = {