+4 -1

Documentation/devicetree/bindings/mfd/cros-ec.txt

reviewed

··· 3 3 Google's ChromeOS EC is a Cortex-M device which talks to the AP and 4 4 implements various function such as keyboard and battery charging. 5 5 6 6 - The EC can be connect through various means (I2C, SPI, LPC) and the 6 6 + The EC can be connect through various means (I2C, SPI, LPC, RPMSG) and the 7 7 compatible string used depends on the interface. Each connection method has 8 8 its own driver which connects to the top level interface-agnostic EC driver. 9 9 Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to ··· 16 16 Required properties (SPI): 17 17 - compatible: "google,cros-ec-spi" 18 18 - reg: SPI chip select 19 19 + 20 20 + Required properties (RPMSG): 21 21 + - compatible: "google,cros-ec-rpmsg" 19 22 20 23 Optional properties (SPI): 21 24 - google,cros-ec-spi-pre-delay: Some implementations of the EC need a little

+36

Documentation/devicetree/bindings/mfd/lp87565.txt

reviewed

··· 41 41 }; 42 42 }; 43 43 }; 44 44 + 45 45 + TI LP87561 PMIC: 46 46 + 47 47 + This is a single output 4-phase regulator configuration 48 48 + 49 49 + Required properties: 50 50 + - compatible: "ti,lp87561-q1" 51 51 + - reg: I2C slave address. 52 52 + - gpio-controller: Marks the device node as a GPIO Controller. 53 53 + - #gpio-cells: Should be two. The first cell is the pin number and 54 54 + the second cell is used to specify flags. 55 55 + See ../gpio/gpio.txt for more information. 56 56 + - xxx-in-supply: Phandle to parent supply node of each regulator 57 57 + populated under regulators node. xxx should match 58 58 + the supply_name populated in driver. 59 59 + Example: 60 60 + 61 61 + lp87561_pmic: pmic@62 { 62 62 + compatible = "ti,lp87561-q1"; 63 63 + reg = <0x62>; 64 64 + gpio-controller; 65 65 + #gpio-cells = <2>; 66 66 + 67 67 + buck3210-in-supply = <&vsys_3v3>; 68 68 + 69 69 + regulators: regulators { 70 70 + buck3210_reg: buck3210 { 71 71 + /* VDD_CORE */ 72 72 + regulator-name = "buck3210"; 73 73 + regulator-min-microvolt = <800000>; 74 74 + regulator-max-microvolt = <800000>; 75 75 + regulator-always-on; 76 76 + regulator-boot-on; 77 77 + }; 78 78 + }; 79 79 + };

+6 -2

Documentation/devicetree/bindings/mfd/madera.txt

reviewed

··· 11 11 Required properties: 12 12 13 13 - compatible : One of the following chip-specific strings: 14 14 + "cirrus,cs47l15" 14 15 "cirrus,cs47l35" 15 16 "cirrus,cs47l85" 16 17 "cirrus,cs47l90" 17 18 "cirrus,cs47l91" 19 19 + "cirrus,cs42l92" 20 20 + "cirrus,cs47l92" 21 21 + "cirrus,cs47l93" 18 22 "cirrus,wm1840" 19 23 20 24 - reg : I2C slave address when connected using I2C, chip select number when ··· 26 22 27 23 - DCVDD-supply : Power supply for the device as defined in 28 24 bindings/regulator/regulator.txt 29 29 - Mandatory on CS47L35, CS47L90, CS47L91 25 25 + Mandatory on CS47L15, CS47L35, CS47L90, CS47L91, CS42L92, CS47L92, CS47L93 30 26 Optional on CS47L85, WM1840 31 27 32 28 - AVDD-supply, DBVDD1-supply, DBVDD2-supply, CPVDD1-supply, CPVDD2-supply : ··· 39 35 (CS47L85, WM1840) 40 36 41 37 - SPKVDD-supply : Power supply for the device 42 42 - (CS47L35) 38 38 + (CS47L15, CS47L35) 43 39 44 40 - interrupt-controller : Indicates that this device is an interrupt controller 45 41

+44

Documentation/devicetree/bindings/mfd/rk808.txt

reviewed

··· 3 3 The rk8xx family current members: 4 4 rk805 5 5 rk808 6 6 + rk809 7 7 + rk817 6 8 rk818 7 9 8 10 Required properties: 9 11 - compatible: "rockchip,rk805" 10 12 - compatible: "rockchip,rk808" 13 13 + - compatible: "rockchip,rk809" 14 14 + - compatible: "rockchip,rk817" 11 15 - compatible: "rockchip,rk818" 12 16 - reg: I2C slave address 13 17 - interrupts: the interrupt outputs of the controller. ··· 48 44 for 2 host gpio's used for dvs. The format of the gpio specifier depends in 49 45 the gpio controller. If DVS GPIOs aren't present, voltage changes will happen 50 46 very quickly with no slow ramp time. 47 47 + 48 48 + Optional shared RK809 and RK817 properties: 49 49 + - vcc1-supply: The input supply for DCDC_REG1 50 50 + - vcc2-supply: The input supply for DCDC_REG2 51 51 + - vcc3-supply: The input supply for DCDC_REG3 52 52 + - vcc4-supply: The input supply for DCDC_REG4 53 53 + - vcc5-supply: The input supply for LDO_REG1, LDO_REG2, LDO_REG3 54 54 + - vcc6-supply: The input supply for LDO_REG4, LDO_REG5, LDO_REG6 55 55 + - vcc7-supply: The input supply for LDO_REG7, LDO_REG8, LDO_REG9 56 56 + 57 57 + Optional RK809 properties: 58 58 + - vcc8-supply: The input supply for SWITCH_REG1 59 59 + - vcc9-supply: The input supply for DCDC_REG5, SWITCH_REG2 60 60 + 61 61 + Optional RK817 properties: 62 62 + - vcc8-supply: The input supply for BOOST 63 63 + - vcc9-supply: The input supply for OTG_SWITCH 51 64 52 65 Optional RK818 properties: 53 66 - vcc1-supply: The input supply for DCDC_REG1 ··· 107 86 - SWITCH_REGn 108 87 - valid values for n are 1 to 2 109 88 89 89 + Following regulators of the RK809 and RK817 PMIC blocks are supported. Note that 90 90 + the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO 91 91 + number as described in RK809 and RK817 datasheets. 92 92 + 93 93 + - DCDC_REGn 94 94 + - valid values for n are 1 to 5 for RK809. 95 95 + - valid values for n are 1 to 4 for RK817. 96 96 + - LDO_REGn 97 97 + - valid values for n are 1 to 9 for RK809. 98 98 + - valid values for n are 1 to 9 for RK817. 99 99 + - SWITCH_REGn 100 100 + - valid values for n are 1 to 2 for RK809. 101 101 + - BOOST for RK817 102 102 + - OTG_SWITCH for RK817 103 103 + 110 104 Following regulators of the RK818 PMIC block are supported. Note that 111 105 the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO 112 106 number as described in RK818 datasheet. ··· 133 97 - SWITCH_REG 134 98 - HDMI_SWITCH 135 99 - OTG_SWITCH 100 100 + 101 101 + It is necessary to configure three pins for both the RK809 and RK817, the three 102 102 + pins are "gpio_ts" "gpio_gt" "gpio_slp". 103 103 + The gpio_gt and gpio_ts pins support the gpio function. 104 104 + The gpio_slp pin is for controlling the pmic states, as below: 105 105 + - reset 106 106 + - power down 107 107 + - sleep 136 108 137 109 Standard regulator bindings are used inside regulator subnodes. Check 138 110 Documentation/devicetree/bindings/regulator/regulator.txt

+102

Documentation/devicetree/bindings/mfd/rohm,bd70528-pmic.txt

reviewed

··· 1 1 + * ROHM BD70528 Power Management Integrated Circuit bindings 2 2 + 3 3 + BD70528MWV is an ultra-low quiescent current general purpose, single-chip, 4 4 + power management IC for battery-powered portable devices. The IC 5 5 + integrates 3 ultra-low current consumption buck converters, 3 LDOs and 2 6 6 + LED Drivers. Also included are 4 GPIOs, a real-time clock (RTC), a 32kHz 7 7 + clock gate, high-accuracy VREF for use with an external ADC, flexible 8 8 + dual-input power path, 10 bit SAR ADC for battery temperature monitor and 9 9 + 1S battery charger with scalable charge currents. 10 10 + 11 11 + Required properties: 12 12 + - compatible : Should be "rohm,bd70528" 13 13 + - reg : I2C slave address. 14 14 + - interrupts : The interrupt line the device is connected to. 15 15 + - interrupt-controller : To indicate BD70528 acts as an interrupt controller. 16 16 + - #interrupt-cells : Should be 2. Usage is compliant to the 2 cells 17 17 + variant of ../interrupt-controller/interrupts.txt 18 18 + - gpio-controller : To indicate BD70528 acts as a GPIO controller. 19 19 + - #gpio-cells : Should be 2. The first cell is the pin number and 20 20 + the second cell is used to specify flags. See 21 21 + ../gpio/gpio.txt for more information. 22 22 + - #clock-cells : Should be 0. 23 23 + - regulators: : List of child nodes that specify the regulators. 24 24 + Please see ../regulator/rohm,bd70528-regulator.txt 25 25 + 26 26 + Optional properties: 27 27 + - clock-output-names : Should contain name for output clock. 28 28 + 29 29 + Example: 30 30 + /* External oscillator */ 31 31 + osc: oscillator { 32 32 + compatible = "fixed-clock"; 33 33 + #clock-cells = <1>; 34 34 + clock-frequency = <32768>; 35 35 + clock-output-names = "osc"; 36 36 + }; 37 37 + 38 38 + pmic: pmic@4b { 39 39 + compatible = "rohm,bd70528"; 40 40 + reg = <0x4b>; 41 41 + interrupt-parent = <&gpio1>; 42 42 + interrupts = <29 GPIO_ACTIVE_LOW>; 43 43 + clocks = <&osc 0>; 44 44 + #clock-cells = <0>; 45 45 + clock-output-names = "bd70528-32k-out"; 46 46 + #gpio-cells = <2>; 47 47 + gpio-controller; 48 48 + interrupt-controller; 49 49 + #interrupt-cells = <2>; 50 50 + 51 51 + regulators { 52 52 + buck1: BUCK1 { 53 53 + regulator-name = "buck1"; 54 54 + regulator-min-microvolt = <1200000>; 55 55 + regulator-max-microvolt = <3400000>; 56 56 + regulator-boot-on; 57 57 + regulator-ramp-delay = <125>; 58 58 + }; 59 59 + buck2: BUCK2 { 60 60 + regulator-name = "buck2"; 61 61 + regulator-min-microvolt = <1200000>; 62 62 + regulator-max-microvolt = <3300000>; 63 63 + regulator-boot-on; 64 64 + regulator-ramp-delay = <125>; 65 65 + }; 66 66 + buck3: BUCK3 { 67 67 + regulator-name = "buck3"; 68 68 + regulator-min-microvolt = <800000>; 69 69 + regulator-max-microvolt = <1800000>; 70 70 + regulator-boot-on; 71 71 + regulator-ramp-delay = <250>; 72 72 + }; 73 73 + ldo1: LDO1 { 74 74 + regulator-name = "ldo1"; 75 75 + regulator-min-microvolt = <1650000>; 76 76 + regulator-max-microvolt = <3300000>; 77 77 + regulator-boot-on; 78 78 + }; 79 79 + ldo2: LDO2 { 80 80 + regulator-name = "ldo2"; 81 81 + regulator-min-microvolt = <1650000>; 82 82 + regulator-max-microvolt = <3300000>; 83 83 + regulator-boot-on; 84 84 + }; 85 85 + 86 86 + ldo3: LDO3 { 87 87 + regulator-name = "ldo3"; 88 88 + regulator-min-microvolt = <1650000>; 89 89 + regulator-max-microvolt = <3300000>; 90 90 + }; 91 91 + led_ldo1: LED_LDO1 { 92 92 + regulator-name = "led_ldo1"; 93 93 + regulator-min-microvolt = <200000>; 94 94 + regulator-max-microvolt = <300000>; 95 95 + }; 96 96 + led_ldo2: LED_LDO2 { 97 97 + regulator-name = "led_ldo2"; 98 98 + regulator-min-microvolt = <200000>; 99 99 + regulator-max-microvolt = <300000>; 100 100 + }; 101 101 + }; 102 102 + };

+10

Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.txt

reviewed

··· 8 8 9 9 Datasheet for BD71837 is available at: 10 10 https://www.rohm.com/datasheet/BD71837MWV/bd71837mwv-e 11 11 + Datasheet for BD71847 is available at: 12 12 + https://www.rohm.com/datasheet/BD71847AMWV/bd71847amwv-e 11 13 12 14 Required properties: 13 15 - compatible : Should be "rohm,bd71837" for bd71837 ··· 39 37 target state is set to READY by default. If SNVS state is used the boot 40 38 crucial regulators must have the regulator-always-on and regulator-boot-on 41 39 properties set in regulator node. 40 40 + 41 41 + - rohm,short-press-ms : Short press duration in milliseconds 42 42 + - rohm,long-press-ms : Long press duration in milliseconds 43 43 + 44 44 + Configure the "short press" and "long press" timers for the power button. 45 45 + Values are rounded to what hardware supports (500ms multiple for short and 46 46 + 1000ms multiple for long). If these properties are not present the existing 47 47 + configuration (from bootloader or OTP) is not touched. 42 48 43 49 Example: 44 50

+1 -1

MAINTAINERS

reviewed

··· 8222 8222 F: drivers/gpio/gpio-*cove.c 8223 8223 F: drivers/gpio/gpio-msic.c 8224 8224 8225 8225 - INTEL MULTIFUNCTION PMIC DEVICE DRIVERS 8225 8225 + INTEL PMIC MULTIFUNCTION DEVICE DRIVERS 8226 8226 R: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8227 8227 S: Maintained 8228 8228 F: drivers/mfd/intel_msic.c

+7 -8

drivers/clk/Kconfig

reviewed

··· 53 53 This driver supports Maxim 9485 Programmable Audio Clock Generator 54 54 55 55 config COMMON_CLK_RK808 56 56 - tristate "Clock driver for RK805/RK808/RK818" 56 56 + tristate "Clock driver for RK805/RK808/RK809/RK817/RK818" 57 57 depends on MFD_RK808 58 58 ---help--- 59 59 - This driver supports RK805, RK808 and RK818 crystal oscillator clock. These 60 60 - multi-function devices have two fixed-rate oscillators, 61 61 - clocked at 32KHz each. Clkout1 is always on, Clkout2 can off 62 62 - by control register. 59 59 + This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock. 60 60 + These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. 61 61 + Clkout1 is always on, Clkout2 can off by control register. 63 62 64 63 config COMMON_CLK_HI655X 65 64 tristate "Clock driver for Hi655x" if EXPERT ··· 292 293 293 294 config COMMON_CLK_BD718XX 294 295 tristate "Clock driver for ROHM BD718x7 PMIC" 295 295 - depends on MFD_ROHM_BD718XX 296 296 + depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 296 297 help 297 297 - This driver supports ROHM BD71837 and ROHM BD71847 298 298 - PMICs clock gates. 298 298 + This driver supports ROHM BD71837, ROHM BD71847 and 299 299 + ROHM BD70528 PMICs clock gates. 299 300 300 301 config COMMON_CLK_FIXED_MMIO 301 302 bool "Clock driver for Memory Mapped Fixed values"

+18 -6

drivers/clk/clk-bd718x7.c

reviewed

··· 8 8 #include <linux/platform_device.h> 9 9 #include <linux/slab.h> 10 10 #include <linux/mfd/rohm-bd718x7.h> 11 11 + #include <linux/mfd/rohm-bd70528.h> 11 12 #include <linux/clk-provider.h> 12 13 #include <linux/clkdev.h> 13 14 #include <linux/regmap.h> ··· 18 17 u8 reg; 19 18 u8 mask; 20 19 struct platform_device *pdev; 21 21 - struct bd718xx *mfd; 20 20 + struct rohm_regmap_dev *mfd; 22 21 }; 23 22 24 23 static int bd71837_clk_set(struct clk_hw *hw, int status) ··· 69 68 int rval = -ENOMEM; 70 69 const char *parent_clk; 71 70 struct device *parent = pdev->dev.parent; 72 72 - struct bd718xx *mfd = dev_get_drvdata(parent); 71 71 + struct rohm_regmap_dev *mfd = dev_get_drvdata(parent); 73 72 struct clk_init_data init = { 74 73 .name = "bd718xx-32k-out", 75 74 .ops = &bd71837_clk_ops, ··· 87 86 dev_err(&pdev->dev, "No parent clk found\n"); 88 87 return -EINVAL; 89 88 } 90 90 - 91 91 - c->reg = BD718XX_REG_OUT32K; 92 92 - c->mask = BD718XX_OUT32K_EN; 89 89 + switch (mfd->chip_type) { 90 90 + case ROHM_CHIP_TYPE_BD71837: 91 91 + case ROHM_CHIP_TYPE_BD71847: 92 92 + c->reg = BD718XX_REG_OUT32K; 93 93 + c->mask = BD718XX_OUT32K_EN; 94 94 + break; 95 95 + case ROHM_CHIP_TYPE_BD70528: 96 96 + c->reg = BD70528_REG_CLK_OUT; 97 97 + c->mask = BD70528_CLK_OUT_EN_MASK; 98 98 + break; 99 99 + default: 100 100 + dev_err(&pdev->dev, "Unknown clk chip\n"); 101 101 + return -EINVAL; 102 102 + } 93 103 c->mfd = mfd; 94 104 c->pdev = pdev; 95 105 c->hw.init = &init; ··· 131 119 module_platform_driver(bd71837_clk); 132 120 133 121 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 134 134 - MODULE_DESCRIPTION("BD71837 chip clk driver"); 122 122 + MODULE_DESCRIPTION("BD71837/BD71847/BD70528 chip clk driver"); 135 123 MODULE_LICENSE("GPL");

+63 -1

drivers/clk/clk-rk808.c

reviewed

··· 88 88 return idx ? &rk808_clkout->clkout2_hw : &rk808_clkout->clkout1_hw; 89 89 } 90 90 91 91 + static int rk817_clkout2_enable(struct clk_hw *hw, bool enable) 92 92 + { 93 93 + struct rk808_clkout *rk808_clkout = container_of(hw, 94 94 + struct rk808_clkout, 95 95 + clkout2_hw); 96 96 + struct rk808 *rk808 = rk808_clkout->rk808; 97 97 + 98 98 + return regmap_update_bits(rk808->regmap, RK817_SYS_CFG(1), 99 99 + RK817_CLK32KOUT2_EN, 100 100 + enable ? RK817_CLK32KOUT2_EN : 0); 101 101 + } 102 102 + 103 103 + static int rk817_clkout2_prepare(struct clk_hw *hw) 104 104 + { 105 105 + return rk817_clkout2_enable(hw, true); 106 106 + } 107 107 + 108 108 + static void rk817_clkout2_unprepare(struct clk_hw *hw) 109 109 + { 110 110 + rk817_clkout2_enable(hw, false); 111 111 + } 112 112 + 113 113 + static int rk817_clkout2_is_prepared(struct clk_hw *hw) 114 114 + { 115 115 + struct rk808_clkout *rk808_clkout = container_of(hw, 116 116 + struct rk808_clkout, 117 117 + clkout2_hw); 118 118 + struct rk808 *rk808 = rk808_clkout->rk808; 119 119 + unsigned int val; 120 120 + 121 121 + int ret = regmap_read(rk808->regmap, RK817_SYS_CFG(1), &val); 122 122 + 123 123 + if (ret < 0) 124 124 + return 0; 125 125 + 126 126 + return (val & RK817_CLK32KOUT2_EN) ? 1 : 0; 127 127 + } 128 128 + 129 129 + static const struct clk_ops rk817_clkout2_ops = { 130 130 + .prepare = rk817_clkout2_prepare, 131 131 + .unprepare = rk817_clkout2_unprepare, 132 132 + .is_prepared = rk817_clkout2_is_prepared, 133 133 + .recalc_rate = rk808_clkout_recalc_rate, 134 134 + }; 135 135 + 136 136 + static const struct clk_ops *rkpmic_get_ops(long variant) 137 137 + { 138 138 + switch (variant) { 139 139 + case RK809_ID: 140 140 + case RK817_ID: 141 141 + return &rk817_clkout2_ops; 142 142 + /* 143 143 + * For the default case, it match the following PMIC type. 144 144 + * RK805_ID 145 145 + * RK808_ID 146 146 + * RK818_ID 147 147 + */ 148 148 + default: 149 149 + return &rk808_clkout2_ops; 150 150 + } 151 151 + } 152 152 + 91 153 static int rk808_clkout_probe(struct platform_device *pdev) 92 154 { 93 155 struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent); ··· 181 119 return ret; 182 120 183 121 init.name = "rk808-clkout2"; 184 184 - init.ops = &rk808_clkout2_ops; 122 122 + init.ops = rkpmic_get_ops(rk808->variant); 185 123 rk808_clkout->clkout2_hw.init = &init; 186 124 187 125 /* optional override of the clockname */

+11

drivers/gpio/Kconfig

reviewed

··· 975 975 help 976 976 Support for GPIOs on Wolfson Arizona class devices. 977 977 978 978 + config GPIO_BD70528 979 979 + tristate "ROHM BD70528 GPIO support" 980 980 + depends on MFD_ROHM_BD70528 981 981 + help 982 982 + Support for GPIOs on ROHM BD70528 PMIC. There are four GPIOs 983 983 + available on the ROHM PMIC in total. The GPIOs can also 984 984 + generate interrupts. 985 985 + 986 986 + This driver can also be built as a module. If so, the module 987 987 + will be called gpio-bd70528. 988 988 + 978 989 config GPIO_BD9571MWV 979 990 tristate "ROHM BD9571 GPIO support" 980 991 depends on MFD_BD9571MWV

+1

drivers/gpio/Makefile

reviewed

··· 34 34 obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o 35 35 obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o 36 36 obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o 37 37 + obj-$(CONFIG_GPIO_BD70528) += gpio-bd70528.o 37 38 obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o 38 39 obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o 39 40 obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o

+232

drivers/gpio/gpio-bd70528.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + // Copyright (C) 2018 ROHM Semiconductors 3 3 + // gpio-bd70528.c ROHM BD70528MWV gpio driver 4 4 + 5 5 + #include <linux/gpio/driver.h> 6 6 + #include <linux/mfd/rohm-bd70528.h> 7 7 + #include <linux/module.h> 8 8 + #include <linux/platform_device.h> 9 9 + #include <linux/regmap.h> 10 10 + 11 11 + #define GPIO_IN_REG(offset) (BD70528_REG_GPIO1_IN + (offset) * 2) 12 12 + #define GPIO_OUT_REG(offset) (BD70528_REG_GPIO1_OUT + (offset) * 2) 13 13 + 14 14 + struct bd70528_gpio { 15 15 + struct rohm_regmap_dev chip; 16 16 + struct gpio_chip gpio; 17 17 + }; 18 18 + 19 19 + static int bd70528_set_debounce(struct bd70528_gpio *bdgpio, 20 20 + unsigned int offset, unsigned int debounce) 21 21 + { 22 22 + u8 val; 23 23 + 24 24 + switch (debounce) { 25 25 + case 0: 26 26 + val = BD70528_DEBOUNCE_DISABLE; 27 27 + break; 28 28 + case 1 ... 15: 29 29 + val = BD70528_DEBOUNCE_15MS; 30 30 + break; 31 31 + case 16 ... 30: 32 32 + val = BD70528_DEBOUNCE_30MS; 33 33 + break; 34 34 + case 31 ... 50: 35 35 + val = BD70528_DEBOUNCE_50MS; 36 36 + break; 37 37 + default: 38 38 + dev_err(bdgpio->chip.dev, 39 39 + "Invalid debouce value %u\n", debounce); 40 40 + return -EINVAL; 41 41 + } 42 42 + return regmap_update_bits(bdgpio->chip.regmap, GPIO_IN_REG(offset), 43 43 + BD70528_DEBOUNCE_MASK, val); 44 44 + } 45 45 + 46 46 + static int bd70528_get_direction(struct gpio_chip *chip, unsigned int offset) 47 47 + { 48 48 + struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); 49 49 + int val, ret; 50 50 + 51 51 + /* Do we need to do something to IRQs here? */ 52 52 + ret = regmap_read(bdgpio->chip.regmap, GPIO_OUT_REG(offset), &val); 53 53 + if (ret) { 54 54 + dev_err(bdgpio->chip.dev, "Could not read gpio direction\n"); 55 55 + return ret; 56 56 + } 57 57 + 58 58 + return !(val & BD70528_GPIO_OUT_EN_MASK); 59 59 + } 60 60 + 61 61 + static int bd70528_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 62 62 + unsigned long config) 63 63 + { 64 64 + struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); 65 65 + 66 66 + switch (pinconf_to_config_param(config)) { 67 67 + case PIN_CONFIG_DRIVE_OPEN_DRAIN: 68 68 + return regmap_update_bits(bdgpio->chip.regmap, 69 69 + GPIO_OUT_REG(offset), 70 70 + BD70528_GPIO_DRIVE_MASK, 71 71 + BD70528_GPIO_OPEN_DRAIN); 72 72 + break; 73 73 + case PIN_CONFIG_DRIVE_PUSH_PULL: 74 74 + return regmap_update_bits(bdgpio->chip.regmap, 75 75 + GPIO_OUT_REG(offset), 76 76 + BD70528_GPIO_DRIVE_MASK, 77 77 + BD70528_GPIO_PUSH_PULL); 78 78 + break; 79 79 + case PIN_CONFIG_INPUT_DEBOUNCE: 80 80 + return bd70528_set_debounce(bdgpio, offset, 81 81 + pinconf_to_config_argument(config)); 82 82 + break; 83 83 + default: 84 84 + break; 85 85 + } 86 86 + return -ENOTSUPP; 87 87 + } 88 88 + 89 89 + static int bd70528_direction_input(struct gpio_chip *chip, unsigned int offset) 90 90 + { 91 91 + struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); 92 92 + 93 93 + /* Do we need to do something to IRQs here? */ 94 94 + return regmap_update_bits(bdgpio->chip.regmap, GPIO_OUT_REG(offset), 95 95 + BD70528_GPIO_OUT_EN_MASK, 96 96 + BD70528_GPIO_OUT_DISABLE); 97 97 + } 98 98 + 99 99 + static void bd70528_gpio_set(struct gpio_chip *chip, unsigned int offset, 100 100 + int value) 101 101 + { 102 102 + int ret; 103 103 + struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); 104 104 + u8 val = (value) ? BD70528_GPIO_OUT_HI : BD70528_GPIO_OUT_LO; 105 105 + 106 106 + ret = regmap_update_bits(bdgpio->chip.regmap, GPIO_OUT_REG(offset), 107 107 + BD70528_GPIO_OUT_MASK, val); 108 108 + if (ret) 109 109 + dev_err(bdgpio->chip.dev, "Could not set gpio to %d\n", value); 110 110 + } 111 111 + 112 112 + static int bd70528_direction_output(struct gpio_chip *chip, unsigned int offset, 113 113 + int value) 114 114 + { 115 115 + struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); 116 116 + 117 117 + bd70528_gpio_set(chip, offset, value); 118 118 + return regmap_update_bits(bdgpio->chip.regmap, GPIO_OUT_REG(offset), 119 119 + BD70528_GPIO_OUT_EN_MASK, 120 120 + BD70528_GPIO_OUT_ENABLE); 121 121 + } 122 122 + 123 123 + #define GPIO_IN_STATE_MASK(offset) (BD70528_GPIO_IN_STATE_BASE << (offset)) 124 124 + 125 125 + static int bd70528_gpio_get_o(struct bd70528_gpio *bdgpio, unsigned int offset) 126 126 + { 127 127 + int ret; 128 128 + unsigned int val; 129 129 + 130 130 + ret = regmap_read(bdgpio->chip.regmap, GPIO_OUT_REG(offset), &val); 131 131 + if (!ret) 132 132 + ret = !!(val & BD70528_GPIO_OUT_MASK); 133 133 + else 134 134 + dev_err(bdgpio->chip.dev, "GPIO (out) state read failed\n"); 135 135 + 136 136 + return ret; 137 137 + } 138 138 + 139 139 + static int bd70528_gpio_get_i(struct bd70528_gpio *bdgpio, unsigned int offset) 140 140 + { 141 141 + unsigned int val; 142 142 + int ret; 143 143 + 144 144 + ret = regmap_read(bdgpio->chip.regmap, BD70528_REG_GPIO_STATE, &val); 145 145 + 146 146 + if (!ret) 147 147 + ret = !(val & GPIO_IN_STATE_MASK(offset)); 148 148 + else 149 149 + dev_err(bdgpio->chip.dev, "GPIO (in) state read failed\n"); 150 150 + 151 151 + return ret; 152 152 + } 153 153 + 154 154 + static int bd70528_gpio_get(struct gpio_chip *chip, unsigned int offset) 155 155 + { 156 156 + int ret = -EINVAL; 157 157 + struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); 158 158 + 159 159 + /* 160 160 + * There is a race condition where someone might be changing the 161 161 + * GPIO direction after we get it but before we read the value. But 162 162 + * application design where GPIO direction may be changed just when 163 163 + * we read GPIO value would be pointless as reader could not know 164 164 + * whether the returned high/low state is caused by input or output. 165 165 + * Or then there must be other ways to mitigate the issue. Thus 166 166 + * locking would make no sense. 167 167 + */ 168 168 + ret = bd70528_get_direction(chip, offset); 169 169 + if (ret == 0) 170 170 + ret = bd70528_gpio_get_o(bdgpio, offset); 171 171 + else if (ret == 1) 172 172 + ret = bd70528_gpio_get_i(bdgpio, offset); 173 173 + else 174 174 + dev_err(bdgpio->chip.dev, "failed to read GPIO direction\n"); 175 175 + 176 176 + return ret; 177 177 + } 178 178 + 179 179 + static int bd70528_probe(struct platform_device *pdev) 180 180 + { 181 181 + struct bd70528_gpio *bdgpio; 182 182 + struct rohm_regmap_dev *bd70528; 183 183 + int ret; 184 184 + 185 185 + bd70528 = dev_get_drvdata(pdev->dev.parent); 186 186 + if (!bd70528) { 187 187 + dev_err(&pdev->dev, "No MFD driver data\n"); 188 188 + return -EINVAL; 189 189 + } 190 190 + 191 191 + bdgpio = devm_kzalloc(&pdev->dev, sizeof(*bdgpio), 192 192 + GFP_KERNEL); 193 193 + if (!bdgpio) 194 194 + return -ENOMEM; 195 195 + bdgpio->chip.dev = &pdev->dev; 196 196 + bdgpio->gpio.parent = pdev->dev.parent; 197 197 + bdgpio->gpio.label = "bd70528-gpio"; 198 198 + bdgpio->gpio.owner = THIS_MODULE; 199 199 + bdgpio->gpio.get_direction = bd70528_get_direction; 200 200 + bdgpio->gpio.direction_input = bd70528_direction_input; 201 201 + bdgpio->gpio.direction_output = bd70528_direction_output; 202 202 + bdgpio->gpio.set_config = bd70528_gpio_set_config; 203 203 + bdgpio->gpio.can_sleep = true; 204 204 + bdgpio->gpio.get = bd70528_gpio_get; 205 205 + bdgpio->gpio.set = bd70528_gpio_set; 206 206 + bdgpio->gpio.ngpio = 4; 207 207 + bdgpio->gpio.base = -1; 208 208 + #ifdef CONFIG_OF_GPIO 209 209 + bdgpio->gpio.of_node = pdev->dev.parent->of_node; 210 210 + #endif 211 211 + bdgpio->chip.regmap = bd70528->regmap; 212 212 + 213 213 + ret = devm_gpiochip_add_data(&pdev->dev, &bdgpio->gpio, 214 214 + bdgpio); 215 215 + if (ret) 216 216 + dev_err(&pdev->dev, "gpio_init: Failed to add bd70528-gpio\n"); 217 217 + 218 218 + return ret; 219 219 + } 220 220 + 221 221 + static struct platform_driver bd70528_gpio = { 222 222 + .driver = { 223 223 + .name = "bd70528-gpio" 224 224 + }, 225 225 + .probe = bd70528_probe, 226 226 + }; 227 227 + 228 228 + module_platform_driver(bd70528_gpio); 229 229 + 230 230 + MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 231 231 + MODULE_DESCRIPTION("BD70528 voltage regulator driver"); 232 232 + MODULE_LICENSE("GPL");

+34 -3

drivers/mfd/Kconfig

reviewed

··· 261 261 Support for the Cirrus Logic Madera platform audio SoC 262 262 core functionality controlled via SPI. 263 263 264 264 + config MFD_CS47L15 265 265 + bool "Cirrus Logic CS47L15" 266 266 + select PINCTRL_CS47L15 267 267 + depends on MFD_MADERA 268 268 + help 269 269 + Support for Cirrus Logic CS47L15 Smart Codec 270 270 + 264 271 config MFD_CS47L35 265 272 bool "Cirrus Logic CS47L35" 266 273 select PINCTRL_CS47L35 ··· 288 281 depends on MFD_MADERA 289 282 help 290 283 Support for Cirrus Logic CS47L90 and CS47L91 Smart Codecs 284 284 + 285 285 + config MFD_CS47L92 286 286 + bool "Cirrus Logic CS47L92/93" 287 287 + select PINCTRL_CS47L92 288 288 + depends on MFD_MADERA 289 289 + help 290 290 + Support for Cirrus Logic CS42L92, CS47L92 and CS47L93 Smart Codecs 291 291 292 292 config MFD_ASIC3 293 293 bool "Compaq ASIC3" ··· 1045 1031 different functionality of the device. 1046 1032 1047 1033 config MFD_RK808 1048 1048 - tristate "Rockchip RK805/RK808/RK818 Power Management Chip" 1034 1034 + tristate "Rockchip RK805/RK808/RK809/RK817/RK818 Power Management Chip" 1049 1035 depends on I2C && OF 1050 1036 select MFD_CORE 1051 1037 select REGMAP_I2C 1052 1038 select REGMAP_IRQ 1053 1039 help 1054 1054 - If you say yes here you get support for the RK805, RK808 and RK818 1055 1055 - Power Management chips. 1040 1040 + If you say yes here you get support for the RK805, RK808, RK809, 1041 1041 + RK817 and RK818 Power Management chips. 1056 1042 This driver provides common support for accessing the device 1057 1043 through I2C interface. The device supports multiple sub-devices 1058 1044 including interrupts, RTC, LDO & DCDC regulators, and onkey. ··· 1903 1889 Power Management ICs. BD71837 is designed to power processors like 1904 1890 NXP i.MX8. It contains 8 BUCK outputs and 7 LDOs, voltage monitoring 1905 1891 and emergency shut down as well as 32,768KHz clock output. 1892 1892 + 1893 1893 + config MFD_ROHM_BD70528 1894 1894 + tristate "ROHM BD70528 Power Management IC" 1895 1895 + depends on I2C=y 1896 1896 + depends on OF 1897 1897 + select REGMAP_I2C 1898 1898 + select REGMAP_IRQ 1899 1899 + select MFD_CORE 1900 1900 + help 1901 1901 + Select this option to get support for the ROHM BD70528 Power 1902 1902 + Management IC. BD71837 is general purpose single-chip power 1903 1903 + management IC for battery-powered portable devices. It contains 1904 1904 + 3 ultra-low current consumption buck converters, 3 LDOs and 2 LED 1905 1905 + drivers. Also included are 4 GPIOs, a real-time clock (RTC), a 32kHz 1906 1906 + crystal oscillator, high-accuracy VREF for use with an external ADC, 1907 1907 + 10 bits SAR ADC for battery temperature monitor and 1S battery 1908 1908 + charger. 1906 1909 1907 1910 config MFD_STM32_LPTIMER 1908 1911 tristate "Support for STM32 Low-Power Timer"

+8

drivers/mfd/Makefile

reviewed

··· 75 75 obj-$(CONFIG_MFD_WM97xx) += wm97xx-core.o 76 76 77 77 madera-objs := madera-core.o 78 78 + ifeq ($(CONFIG_MFD_CS47L15),y) 79 79 + madera-objs += cs47l15-tables.o 80 80 + endif 78 81 ifeq ($(CONFIG_MFD_CS47L35),y) 79 82 madera-objs += cs47l35-tables.o 80 83 endif ··· 86 83 endif 87 84 ifeq ($(CONFIG_MFD_CS47L90),y) 88 85 madera-objs += cs47l90-tables.o 86 86 + endif 87 87 + ifeq ($(CONFIG_MFD_CS47L92),y) 88 88 + madera-objs += cs47l92-tables.o 89 89 endif 90 90 obj-$(CONFIG_MFD_MADERA) += madera.o 91 91 obj-$(CONFIG_MFD_MADERA_I2C) += madera-i2c.o ··· 253 247 obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o 254 248 obj-$(CONFIG_MFD_SC27XX_PMIC) += sprd-sc27xx-spi.o 255 249 obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o 250 250 + obj-$(CONFIG_MFD_ROHM_BD70528) += rohm-bd70528.o 256 251 obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o 257 252 obj-$(CONFIG_MFD_STMFX) += stmfx.o 253 253 +

+1 -1

drivers/mfd/arizona-core.c

reviewed

··· 993 993 unsigned int reg, val; 994 994 int (*apply_patch)(struct arizona *) = NULL; 995 995 const struct mfd_cell *subdevs = NULL; 996 996 - int n_subdevs, ret, i; 996 996 + int n_subdevs = 0, ret, i; 997 997 998 998 dev_set_drvdata(arizona->dev, arizona); 999 999 mutex_init(&arizona->clk_lock);

+89 -3

drivers/mfd/cros_ec_dev.c

reviewed

··· 285 285 286 286 resp = (struct ec_response_motion_sense *)msg->data; 287 287 sensor_num = resp->dump.sensor_count; 288 288 - /* Allocate 1 extra sensors in FIFO are needed */ 289 289 - sensor_cells = kcalloc(sensor_num + 1, sizeof(struct mfd_cell), 288 288 + /* 289 289 + * Allocate 2 extra sensors if lid angle sensor and/or FIFO are needed. 290 290 + */ 291 291 + sensor_cells = kcalloc(sensor_num + 2, sizeof(struct mfd_cell), 290 292 GFP_KERNEL); 291 293 if (sensor_cells == NULL) 292 294 goto error; 293 295 294 294 - sensor_platforms = kcalloc(sensor_num + 1, 296 296 + sensor_platforms = kcalloc(sensor_num, 295 297 sizeof(struct cros_ec_sensor_platform), 296 298 GFP_KERNEL); 297 299 if (sensor_platforms == NULL) ··· 353 351 sensor_cells[id].name = "cros-ec-ring"; 354 352 id++; 355 353 } 354 354 + if (cros_ec_check_features(ec, 355 355 + EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS)) { 356 356 + sensor_cells[id].name = "cros-ec-lid-angle"; 357 357 + id++; 358 358 + } 356 359 357 360 ret = mfd_add_devices(ec->dev, 0, sensor_cells, id, 358 361 NULL, 0, NULL); ··· 369 362 kfree(sensor_cells); 370 363 error: 371 364 kfree(msg); 365 365 + } 366 366 + 367 367 + static struct cros_ec_sensor_platform sensor_platforms[] = { 368 368 + { .sensor_num = 0 }, 369 369 + { .sensor_num = 1 } 370 370 + }; 371 371 + 372 372 + static const struct mfd_cell cros_ec_accel_legacy_cells[] = { 373 373 + { 374 374 + .name = "cros-ec-accel-legacy", 375 375 + .platform_data = &sensor_platforms[0], 376 376 + .pdata_size = sizeof(struct cros_ec_sensor_platform), 377 377 + }, 378 378 + { 379 379 + .name = "cros-ec-accel-legacy", 380 380 + .platform_data = &sensor_platforms[1], 381 381 + .pdata_size = sizeof(struct cros_ec_sensor_platform), 382 382 + } 383 383 + }; 384 384 + 385 385 + static void cros_ec_accel_legacy_register(struct cros_ec_dev *ec) 386 386 + { 387 387 + struct cros_ec_device *ec_dev = ec->ec_dev; 388 388 + u8 status; 389 389 + int ret; 390 390 + 391 391 + /* 392 392 + * ECs that need legacy support are the main EC, directly connected to 393 393 + * the AP. 394 394 + */ 395 395 + if (ec->cmd_offset != 0) 396 396 + return; 397 397 + 398 398 + /* 399 399 + * Check if EC supports direct memory reads and if EC has 400 400 + * accelerometers. 401 401 + */ 402 402 + if (ec_dev->cmd_readmem) { 403 403 + ret = ec_dev->cmd_readmem(ec_dev, EC_MEMMAP_ACC_STATUS, 1, 404 404 + &status); 405 405 + if (ret < 0) { 406 406 + dev_warn(ec->dev, "EC direct read error.\n"); 407 407 + return; 408 408 + } 409 409 + 410 410 + /* Check if EC has accelerometers. */ 411 411 + if (!(status & EC_MEMMAP_ACC_STATUS_PRESENCE_BIT)) { 412 412 + dev_info(ec->dev, "EC does not have accelerometers.\n"); 413 413 + return; 414 414 + } 415 415 + } 416 416 + 417 417 + /* 418 418 + * The device may still support accelerometers: 419 419 + * it would be an older ARM based device that do not suppor the 420 420 + * EC_CMD_GET_FEATURES command. 421 421 + * 422 422 + * Register 2 accelerometers, we will fail in the IIO driver if there 423 423 + * are no sensors. 424 424 + */ 425 425 + ret = mfd_add_devices(ec->dev, PLATFORM_DEVID_AUTO, 426 426 + cros_ec_accel_legacy_cells, 427 427 + ARRAY_SIZE(cros_ec_accel_legacy_cells), 428 428 + NULL, 0, NULL); 429 429 + if (ret) 430 430 + dev_err(ec_dev->dev, "failed to add EC sensors\n"); 372 431 } 373 432 374 433 static const struct mfd_cell cros_ec_cec_cells[] = { ··· 513 440 ec_platform->ec_name = CROS_EC_DEV_TP_NAME; 514 441 } 515 442 443 443 + /* Check whether this is actually a SCP rather than an EC. */ 444 444 + if (cros_ec_check_features(ec, EC_FEATURE_SCP)) { 445 445 + dev_info(dev, "CrOS SCP MCU detected.\n"); 446 446 + /* 447 447 + * Help userspace differentiating ECs from SCP, 448 448 + * regardless of the probing order. 449 449 + */ 450 450 + ec_platform->ec_name = CROS_EC_DEV_SCP_NAME; 451 451 + } 452 452 + 516 453 /* 517 454 * Add the class device 518 455 * Link to the character device for creating the /dev entry ··· 542 459 /* check whether this EC is a sensor hub. */ 543 460 if (cros_ec_check_features(ec, EC_FEATURE_MOTION_SENSE)) 544 461 cros_ec_sensors_register(ec); 462 462 + else 463 463 + /* Workaroud for older EC firmware */ 464 464 + cros_ec_accel_legacy_register(ec); 545 465 546 466 /* Check whether this EC instance has CEC host command support */ 547 467 if (cros_ec_check_features(ec, EC_FEATURE_CEC)) {

+1299

drivers/mfd/cs47l15-tables.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Regmap tables for CS47L15 codec 4 4 + * 5 5 + * Copyright (C) 2016-2019 Cirrus Logic, Inc. and 6 6 + * Cirrus Logic International Semiconductor Ltd. 7 7 + */ 8 8 + 9 9 + #include <linux/device.h> 10 10 + #include <linux/module.h> 11 11 + #include <linux/regmap.h> 12 12 + 13 13 + #include <linux/mfd/madera/core.h> 14 14 + #include <linux/mfd/madera/registers.h> 15 15 + 16 16 + #include "madera.h" 17 17 + 18 18 + static const struct reg_sequence cs47l15_reva_16_patch[] = { 19 19 + { 0x8C, 0x5555 }, 20 20 + { 0x8C, 0xAAAA }, 21 21 + { 0x314, 0x0080 }, 22 22 + { 0x4A8, 0x6023 }, 23 23 + { 0x4A9, 0x6023 }, 24 24 + { 0x4D4, 0x0008 }, 25 25 + { 0x4CF, 0x0F00 }, 26 26 + { 0x4D7, 0x1B2B }, 27 27 + { 0x8C, 0xCCCC }, 28 28 + { 0x8C, 0x3333 }, 29 29 + }; 30 30 + 31 31 + int cs47l15_patch(struct madera *madera) 32 32 + { 33 33 + int ret; 34 34 + 35 35 + ret = regmap_register_patch(madera->regmap, 36 36 + cs47l15_reva_16_patch, 37 37 + ARRAY_SIZE(cs47l15_reva_16_patch)); 38 38 + if (ret < 0) { 39 39 + dev_err(madera->dev, 40 40 + "Error in applying 16-bit patch: %d\n", ret); 41 41 + return ret; 42 42 + } 43 43 + 44 44 + return 0; 45 45 + } 46 46 + EXPORT_SYMBOL_GPL(cs47l15_patch); 47 47 + 48 48 + static const struct reg_default cs47l15_reg_default[] = { 49 49 + { 0x00000020, 0x0000 }, /* R32 (0x20) - Tone Generator 1 */ 50 50 + { 0x00000021, 0x1000 }, /* R33 (0x21) - Tone Generator 2 */ 51 51 + { 0x00000022, 0x0000 }, /* R34 (0x22) - Tone Generator 3 */ 52 52 + { 0x00000023, 0x1000 }, /* R35 (0x23) - Tone Generator 4 */ 53 53 + { 0x00000024, 0x0000 }, /* R36 (0x24) - Tone Generator 5 */ 54 54 + { 0x00000030, 0x0000 }, /* R48 (0x30) - PWM Drive 1 */ 55 55 + { 0x00000031, 0x0100 }, /* R49 (0x31) - PWM Drive 2 */ 56 56 + { 0x00000032, 0x0100 }, /* R50 (0x32) - PWM Drive 3 */ 57 57 + { 0x00000061, 0x01ff }, /* R97 (0x61) - Sample Rate Sequence Select 1 */ 58 58 + { 0x00000062, 0x01ff }, /* R98 (0x62) - Sample Rate Sequence Select 2 */ 59 59 + { 0x00000063, 0x01ff }, /* R99 (0x63) - Sample Rate Sequence Select 3 */ 60 60 + { 0x00000064, 0x01ff }, /* R100 (0x64) - Sample Rate Sequence Select 4 */ 61 61 + { 0x00000066, 0x01ff }, /* R102 (0x66) - Always On Triggers Sequence Select 1 */ 62 62 + { 0x00000067, 0x01ff }, /* R103 (0x67) - Always On Triggers Sequence Select 2 */ 63 63 + { 0x00000090, 0x0000 }, /* R144 (0x90) - Haptics Control 1 */ 64 64 + { 0x00000091, 0x7fff }, /* R145 (0x91) - Haptics Control 2 */ 65 65 + { 0x00000092, 0x0000 }, /* R146 (0x92) - Haptics Phase 1 Intensity */ 66 66 + { 0x00000093, 0x0000 }, /* R147 (0x93) - Haptics Phase 1 Duration */ 67 67 + { 0x00000094, 0x0000 }, /* R148 (0x94) - Haptics Phase 2 Intensity */ 68 68 + { 0x00000095, 0x0000 }, /* R149 (0x95) - Haptics Phase 2 Duration */ 69 69 + { 0x00000096, 0x0000 }, /* R150 (0x96) - Haptics Phase 3 Intensity */ 70 70 + { 0x00000097, 0x0000 }, /* R151 (0x97) - Haptics Phase 3 Duration */ 71 71 + { 0x000000a0, 0x0000 }, /* R160 (0xA0) - Comfort Noise Generator */ 72 72 + { 0x00000100, 0x0002 }, /* R256 (0x100) - Clock 32K 1 */ 73 73 + { 0x00000101, 0x0404 }, /* R257 (0x101) - System Clock 1 */ 74 74 + { 0x00000102, 0x0011 }, /* R258 (0x102) - Sample Rate 1 */ 75 75 + { 0x00000103, 0x0011 }, /* R259 (0x103) - Sample Rate 2 */ 76 76 + { 0x00000104, 0x0011 }, /* R260 (0x104) - Sample Rate 3 */ 77 77 + { 0x00000120, 0x0304 }, /* R288 (0x120) - DSP Clock 1 */ 78 78 + { 0x00000122, 0x0000 }, /* R290 (0x122) - DSP Clock 2 */ 79 79 + { 0x00000149, 0x0000 }, /* R329 (0x149) - Output System Clock */ 80 80 + { 0x00000152, 0x0000 }, /* R338 (0x152) - Rate Estimator 1 */ 81 81 + { 0x00000153, 0x0000 }, /* R339 (0x153) - Rate Estimator 2 */ 82 82 + { 0x00000154, 0x0000 }, /* R340 (0x154) - Rate Estimator 3 */ 83 83 + { 0x00000155, 0x0000 }, /* R341 (0x155) - Rate Estimator 4 */ 84 84 + { 0x00000156, 0x0000 }, /* R342 (0x156) - Rate Estimator 5 */ 85 85 + { 0x00000171, 0x0002 }, /* R369 (0x171) - FLL1 Control 1 */ 86 86 + { 0x00000172, 0x0008 }, /* R370 (0x172) - FLL1 Control 2 */ 87 87 + { 0x00000173, 0x0018 }, /* R371 (0x173) - FLL1 Control 3 */ 88 88 + { 0x00000174, 0x007d }, /* R372 (0x174) - FLL1 Control 4 */ 89 89 + { 0x00000175, 0x0000 }, /* R373 (0x175) - FLL1 Control 5 */ 90 90 + { 0x00000176, 0x0000 }, /* R374 (0x176) - FLL1 Control 6 */ 91 91 + { 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 7 */ 92 92 + { 0x0000017a, 0x2906 }, /* R378 (0x17A) - FLL1 EFS 2 */ 93 93 + { 0x00000181, 0x0000 }, /* R385 (0x181) - FLL1 Synchroniser 1 */ 94 94 + { 0x00000182, 0x0000 }, /* R386 (0x182) - FLL1 Synchroniser 2 */ 95 95 + { 0x00000183, 0x0000 }, /* R387 (0x183) - FLL1 Synchroniser 3 */ 96 96 + { 0x00000184, 0x0000 }, /* R388 (0x184) - FLL1 Synchroniser 4 */ 97 97 + { 0x00000185, 0x0000 }, /* R389 (0x185) - FLL1 Synchroniser 5 */ 98 98 + { 0x00000186, 0x0000 }, /* R390 (0x186) - FLL1 Synchroniser 6 */ 99 99 + { 0x00000187, 0x0001 }, /* R391 (0x187) - FLL1 Synchroniser 7 */ 100 100 + { 0x00000189, 0x0000 }, /* R393 (0x189) - FLL1 Spread Spectrum */ 101 101 + { 0x0000018a, 0x0004 }, /* R394 (0x18A) - FLL1 GPIO Clock */ 102 102 + { 0x000001d1, 0x0004 }, /* R465 (0x1D1) - FLL AO Control 1 */ 103 103 + { 0x000001d2, 0x0004 }, /* R466 (0x1D2) - FLL AO Control 2 */ 104 104 + { 0x000001d3, 0x0000 }, /* R467 (0x1D3) - FLL AO Control 3 */ 105 105 + { 0x000001d4, 0x0000 }, /* R468 (0x1D4) - FLL AO Control 4 */ 106 106 + { 0x000001d5, 0x0001 }, /* R469 (0x1D5) - FLL AO Control 5 */ 107 107 + { 0x000001d6, 0x8004 }, /* R470 (0x1D6) - FLL AO Control 6 */ 108 108 + { 0x000001d8, 0x0000 }, /* R472 (0x1D8) - FLL AO Control 7 */ 109 109 + { 0x000001da, 0x0077 }, /* R474 (0x1DA) - FLL AO Control 8 */ 110 110 + { 0x000001db, 0x0000 }, /* R475 (0x1DB) - FLL AO Control 9 */ 111 111 + { 0x000001dc, 0x06da }, /* R476 (0x1DC) - FLL AO Control 10 */ 112 112 + { 0x000001dd, 0x0011 }, /* R477 (0x1DD) - FLL AO Control 11 */ 113 113 + { 0x00000218, 0x00e6 }, /* R536 (0x218) - Mic Bias Ctrl 1 */ 114 114 + { 0x0000021c, 0x0222 }, /* R540 (0x21C) - Mic Bias Ctrl 5 */ 115 115 + { 0x00000299, 0x0000 }, /* R665 (0x299) - Headphone Detect 0 */ 116 116 + { 0x0000029b, 0x0000 }, /* R667 (0x29B) - Headphone Detect 1 */ 117 117 + { 0x000002a2, 0x0010 }, /* R674 (0x2A2) - Mic Detect 1 Control 0 */ 118 118 + { 0x000002a3, 0x1102 }, /* R675 (0x2A3) - Mic Detect 1 Control 1 */ 119 119 + { 0x000002a4, 0x009f }, /* R676 (0x2A4) - Mic Detect 1 Control 2 */ 120 120 + { 0x000002a6, 0x3d3d }, /* R678 (0x2A6) - Mic Detect 1 Level 1 */ 121 121 + { 0x000002a7, 0x3d3d }, /* R679 (0x2A7) - Mic Detect 1 Level 2 */ 122 122 + { 0x000002a8, 0x333d }, /* R680 (0x2A8) - Mic Detect 1 Level 3 */ 123 123 + { 0x000002a9, 0x202d }, /* R681 (0x2A9) - Mic Detect 1 Level 4 */ 124 124 + { 0x000002c6, 0x0010 }, /* R710 (0x2C6) - Micd Clamp Control */ 125 125 + { 0x000002c8, 0x0000 }, /* R712 (0x2C8) - GP Switch 1 */ 126 126 + { 0x000002d3, 0x0000 }, /* R723 (0x2D3) - Jack Detect Analogue */ 127 127 + { 0x00000300, 0x0000 }, /* R768 (0x300) - Input Enables */ 128 128 + { 0x00000308, 0x0000 }, /* R776 (0x308) - Input Rate */ 129 129 + { 0x00000309, 0x0022 }, /* R777 (0x309) - Input Volume Ramp */ 130 130 + { 0x0000030c, 0x0002 }, /* R780 (0x30C) - HPF Control */ 131 131 + { 0x00000310, 0x0080 }, /* R784 (0x310) - IN1L Control */ 132 132 + { 0x00000311, 0x0180 }, /* R785 (0x311) - ADC Digital Volume 1L */ 133 133 + { 0x00000312, 0x0500 }, /* R786 (0x312) - DMIC1L Control */ 134 134 + { 0x00000313, 0x0000 }, /* R787 (0x313) - IN1L Rate Control */ 135 135 + { 0x00000314, 0x0080 }, /* R788 (0x314) - IN1R Control */ 136 136 + { 0x00000315, 0x0180 }, /* R789 (0x315) - ADC Digital Volume 1R */ 137 137 + { 0x00000316, 0x0000 }, /* R790 (0x316) - DMIC1R Control */ 138 138 + { 0x00000317, 0x0000 }, /* R791 (0x317) - IN1R Rate Control */ 139 139 + { 0x00000318, 0x0000 }, /* R792 (0x318) - IN2L Control */ 140 140 + { 0x00000319, 0x0180 }, /* R793 (0x319) - ADC Digital Volume 2L */ 141 141 + { 0x0000031a, 0x0500 }, /* R794 (0x31A) - DMIC2L Control */ 142 142 + { 0x0000031b, 0x0000 }, /* R795 (0x31B) - IN2L Rate Control */ 143 143 + { 0x0000031c, 0x0800 }, /* R796 (0x31C) - IN2R Control */ 144 144 + { 0x0000031d, 0x0180 }, /* R797 (0x31D) - ADC Digital Volume 2R */ 145 145 + { 0x0000031e, 0x0000 }, /* R798 (0x31E) - DMIC2R Control */ 146 146 + { 0x0000031f, 0x0000 }, /* R799 (0x31F) - IN2R Rate Control */ 147 147 + { 0x000003a8, 0x2000 }, /* R936 (0x3A8) - CS47L15 ADC Int Bias */ 148 148 + { 0x000003c4, 0x0000 }, /* R964 (0x3C4) - CS47L15 PGA Bias Sel */ 149 149 + { 0x00000400, 0x0000 }, /* R1024 (0x400) - Output Enables 1 */ 150 150 + { 0x00000408, 0x0000 }, /* R1032 (0x408) - Output Rate 1 */ 151 151 + { 0x00000409, 0x0022 }, /* R1033 (0x409) - Output Volume Ramp */ 152 152 + { 0x00000410, 0x0080 }, /* R1040 (0x410) - Output Path Config 1L */ 153 153 + { 0x00000411, 0x0180 }, /* R1041 (0x411) - DAC Digital Volume 1L */ 154 154 + { 0x00000412, 0x0000 }, /* R1042 (0x412) - Output Path Config 1 */ 155 155 + { 0x00000413, 0x0001 }, /* R1043 (0x413) - Noise Gate Select 1L */ 156 156 + { 0x00000414, 0x0080 }, /* R1044 (0x414) - Output Path Config 1R */ 157 157 + { 0x00000415, 0x0180 }, /* R1045 (0x415) - DAC Digital Volume 1R */ 158 158 + { 0x00000417, 0x0002 }, /* R1047 (0x417) - Noise Gate Select 1R */ 159 159 + { 0x0000041a, 0x0600 }, /* R1050 (0x41A) - Output Path Config 2 */ 160 160 + { 0x00000428, 0x0000 }, /* R1064 (0x428) - Output Path Config 4L */ 161 161 + { 0x00000429, 0x0180 }, /* R1065 (0x429) - DAC Digital Volume 4L */ 162 162 + { 0x0000042b, 0x0040 }, /* R1067 (0x42B) - Noise Gate Select 4L */ 163 163 + { 0x00000430, 0x0000 }, /* R1072 (0x430) - Output Path Config 5L */ 164 164 + { 0x00000431, 0x0180 }, /* R1073 (0x431) - DAC Digital Volume 5L */ 165 165 + { 0x00000433, 0x0100 }, /* R1075 (0x433) - Noise Gate Select 5L */ 166 166 + { 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */ 167 167 + { 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */ 168 168 + { 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */ 169 169 + { 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */ 170 170 + { 0x00000451, 0x0000 }, /* R1105 (0x451) - DAC AEC Control 2 */ 171 171 + { 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */ 172 172 + { 0x00000490, 0x0069 }, /* R1168 (0x490) - PDM SPK1 Ctrl 1 */ 173 173 + { 0x00000491, 0x0000 }, /* R1169 (0x491) - PDM SPK1 Ctrl 2 */ 174 174 + { 0x000004a0, 0x3080 }, /* R1184 (0x4A0) - HP1 Short Circuit Ctrl */ 175 175 + { 0x000004a8, 0x6023 }, /* R1192 (0x4A8) - HP Test Ctrl 5 */ 176 176 + { 0x000004a9, 0x6023 }, /* R1193 (0x4A9) - HP Test Ctrl 6 */ 177 177 + { 0x00000500, 0x000c }, /* R1280 (0x500) - AIF1 BCLK Ctrl */ 178 178 + { 0x00000501, 0x0000 }, /* R1281 (0x501) - AIF1 Tx Pin Ctrl */ 179 179 + { 0x00000502, 0x0000 }, /* R1282 (0x502) - AIF1 Rx Pin Ctrl */ 180 180 + { 0x00000503, 0x0000 }, /* R1283 (0x503) - AIF1 Rate Ctrl */ 181 181 + { 0x00000504, 0x0000 }, /* R1284 (0x504) - AIF1 Format */ 182 182 + { 0x00000506, 0x0040 }, /* R1286 (0x506) - AIF1 Rx BCLK Rate */ 183 183 + { 0x00000507, 0x1818 }, /* R1287 (0x507) - AIF1 Frame Ctrl 1 */ 184 184 + { 0x00000508, 0x1818 }, /* R1288 (0x508) - AIF1 Frame Ctrl 2 */ 185 185 + { 0x00000509, 0x0000 }, /* R1289 (0x509) - AIF1 Frame Ctrl 3 */ 186 186 + { 0x0000050a, 0x0001 }, /* R1290 (0x50A) - AIF1 Frame Ctrl 4 */ 187 187 + { 0x0000050b, 0x0002 }, /* R1291 (0x50B) - AIF1 Frame Ctrl 5 */ 188 188 + { 0x0000050c, 0x0003 }, /* R1292 (0x50C) - AIF1 Frame Ctrl 6 */ 189 189 + { 0x0000050d, 0x0004 }, /* R1293 (0x50D) - AIF1 Frame Ctrl 7 */ 190 190 + { 0x0000050e, 0x0005 }, /* R1294 (0x50E) - AIF1 Frame Ctrl 8 */ 191 191 + { 0x00000511, 0x0000 }, /* R1297 (0x511) - AIF1 Frame Ctrl 11 */ 192 192 + { 0x00000512, 0x0001 }, /* R1298 (0x512) - AIF1 Frame Ctrl 12 */ 193 193 + { 0x00000513, 0x0002 }, /* R1299 (0x513) - AIF1 Frame Ctrl 13 */ 194 194 + { 0x00000514, 0x0003 }, /* R1300 (0x514) - AIF1 Frame Ctrl 14 */ 195 195 + { 0x00000515, 0x0004 }, /* R1301 (0x515) - AIF1 Frame Ctrl 15 */ 196 196 + { 0x00000516, 0x0005 }, /* R1302 (0x516) - AIF1 Frame Ctrl 16 */ 197 197 + { 0x00000519, 0x0000 }, /* R1305 (0x519) - AIF1 Tx Enables */ 198 198 + { 0x0000051a, 0x0000 }, /* R1306 (0x51A) - AIF1 Rx Enables */ 199 199 + { 0x00000540, 0x000c }, /* R1344 (0x540) - AIF2 BCLK Ctrl */ 200 200 + { 0x00000541, 0x0000 }, /* R1345 (0x541) - AIF2 Tx Pin Ctrl */ 201 201 + { 0x00000542, 0x0000 }, /* R1346 (0x542) - AIF2 Rx Pin Ctrl */ 202 202 + { 0x00000543, 0x0000 }, /* R1347 (0x543) - AIF2 Rate Ctrl */ 203 203 + { 0x00000544, 0x0000 }, /* R1348 (0x544) - AIF2 Format */ 204 204 + { 0x00000546, 0x0040 }, /* R1350 (0x546) - AIF2 Rx BCLK Rate */ 205 205 + { 0x00000547, 0x1818 }, /* R1351 (0x547) - AIF2 Frame Ctrl 1 */ 206 206 + { 0x00000548, 0x1818 }, /* R1352 (0x548) - AIF2 Frame Ctrl 2 */ 207 207 + { 0x00000549, 0x0000 }, /* R1353 (0x549) - AIF2 Frame Ctrl 3 */ 208 208 + { 0x0000054a, 0x0001 }, /* R1354 (0x54A) - AIF2 Frame Ctrl 4 */ 209 209 + { 0x0000054b, 0x0002 }, /* R1355 (0x54B) - AIF2 Frame Ctrl 5 */ 210 210 + { 0x0000054c, 0x0003 }, /* R1356 (0x54C) - AIF2 Frame Ctrl 6 */ 211 211 + { 0x00000551, 0x0000 }, /* R1361 (0x551) - AIF2 Frame Ctrl 11 */ 212 212 + { 0x00000552, 0x0001 }, /* R1362 (0x552) - AIF2 Frame Ctrl 12 */ 213 213 + { 0x00000553, 0x0002 }, /* R1363 (0x553) - AIF2 Frame Ctrl 13 */ 214 214 + { 0x00000554, 0x0003 }, /* R1364 (0x554) - AIF2 Frame Ctrl 14 */ 215 215 + { 0x00000559, 0x0000 }, /* R1369 (0x559) - AIF2 Tx Enables */ 216 216 + { 0x0000055a, 0x0000 }, /* R1370 (0x55A) - AIF2 Rx Enables */ 217 217 + { 0x00000580, 0x000c }, /* R1408 (0x580) - AIF3 BCLK Ctrl */ 218 218 + { 0x00000581, 0x0000 }, /* R1409 (0x581) - AIF3 Tx Pin Ctrl */ 219 219 + { 0x00000582, 0x0000 }, /* R1410 (0x582) - AIF3 Rx Pin Ctrl */ 220 220 + { 0x00000583, 0x0000 }, /* R1411 (0x583) - AIF3 Rate Ctrl */ 221 221 + { 0x00000584, 0x0000 }, /* R1412 (0x584) - AIF3 Format */ 222 222 + { 0x00000586, 0x0040 }, /* R1414 (0x586) - AIF3 Rx BCLK Rate */ 223 223 + { 0x00000587, 0x1818 }, /* R1415 (0x587) - AIF3 Frame Ctrl 1 */ 224 224 + { 0x00000588, 0x1818 }, /* R1416 (0x588) - AIF3 Frame Ctrl 2 */ 225 225 + { 0x00000589, 0x0000 }, /* R1417 (0x589) - AIF3 Frame Ctrl 3 */ 226 226 + { 0x0000058a, 0x0001 }, /* R1418 (0x58A) - AIF3 Frame Ctrl 4 */ 227 227 + { 0x00000591, 0x0000 }, /* R1425 (0x591) - AIF3 Frame Ctrl 11 */ 228 228 + { 0x00000592, 0x0001 }, /* R1426 (0x592) - AIF3 Frame Ctrl 12 */ 229 229 + { 0x00000599, 0x0000 }, /* R1433 (0x599) - AIF3 Tx Enables */ 230 230 + { 0x0000059a, 0x0000 }, /* R1434 (0x59A) - AIF3 Rx Enables */ 231 231 + { 0x000005c2, 0x0000 }, /* R1474 (0x5C2) - SPD1 Tx Control */ 232 232 + { 0x00000640, 0x0000 }, /* R1600 (0x640) - PWM1MIX Input 1 Source */ 233 233 + { 0x00000641, 0x0080 }, /* R1601 (0x641) - PWM1MIX Input 1 Volume */ 234 234 + { 0x00000642, 0x0000 }, /* R1602 (0x642) - PWM1MIX Input 2 Source */ 235 235 + { 0x00000643, 0x0080 }, /* R1603 (0x643) - PWM1MIX Input 2 Volume */ 236 236 + { 0x00000644, 0x0000 }, /* R1604 (0x644) - PWM1MIX Input 3 Source */ 237 237 + { 0x00000645, 0x0080 }, /* R1605 (0x645) - PWM1MIX Input 3 Volume */ 238 238 + { 0x00000646, 0x0000 }, /* R1606 (0x646) - PWM1MIX Input 4 Source */ 239 239 + { 0x00000647, 0x0080 }, /* R1607 (0x647) - PWM1MIX Input 4 Volume */ 240 240 + { 0x00000648, 0x0000 }, /* R1608 (0x648) - PWM2MIX Input 1 Source */ 241 241 + { 0x00000649, 0x0080 }, /* R1609 (0x649) - PWM2MIX Input 1 Volume */ 242 242 + { 0x0000064a, 0x0000 }, /* R1610 (0x64A) - PWM2MIX Input 2 Source */ 243 243 + { 0x0000064b, 0x0080 }, /* R1611 (0x64B) - PWM2MIX Input 2 Volume */ 244 244 + { 0x0000064c, 0x0000 }, /* R1612 (0x64C) - PWM2MIX Input 3 Source */ 245 245 + { 0x0000064d, 0x0080 }, /* R1613 (0x64D) - PWM2MIX Input 3 Volume */ 246 246 + { 0x0000064e, 0x0000 }, /* R1614 (0x64E) - PWM2MIX Input 4 Source */ 247 247 + { 0x0000064f, 0x0080 }, /* R1615 (0x64F) - PWM2MIX Input 4 Volume */ 248 248 + { 0x00000680, 0x0000 }, /* R1664 (0x680) - OUT1LMIX Input 1 Source */ 249 249 + { 0x00000681, 0x0080 }, /* R1665 (0x681) - OUT1LMIX Input 1 Volume */ 250 250 + { 0x00000682, 0x0000 }, /* R1666 (0x682) - OUT1LMIX Input 2 Source */ 251 251 + { 0x00000683, 0x0080 }, /* R1667 (0x683) - OUT1LMIX Input 2 Volume */ 252 252 + { 0x00000684, 0x0000 }, /* R1668 (0x684) - OUT1LMIX Input 3 Source */ 253 253 + { 0x00000685, 0x0080 }, /* R1669 (0x685) - OUT1LMIX Input 3 Volume */ 254 254 + { 0x00000686, 0x0000 }, /* R1670 (0x686) - OUT1LMIX Input 4 Source */ 255 255 + { 0x00000687, 0x0080 }, /* R1671 (0x687) - OUT1LMIX Input 4 Volume */ 256 256 + { 0x00000688, 0x0000 }, /* R1672 (0x688) - OUT1RMIX Input 1 Source */ 257 257 + { 0x00000689, 0x0080 }, /* R1673 (0x689) - OUT1RMIX Input 1 Volume */ 258 258 + { 0x0000068a, 0x0000 }, /* R1674 (0x68A) - OUT1RMIX Input 2 Source */ 259 259 + { 0x0000068b, 0x0080 }, /* R1675 (0x68B) - OUT1RMIX Input 2 Volume */ 260 260 + { 0x0000068c, 0x0000 }, /* R1676 (0x68C) - OUT1RMIX Input 3 Source */ 261 261 + { 0x0000068d, 0x0080 }, /* R1677 (0x68D) - OUT1RMIX Input 3 Volume */ 262 262 + { 0x0000068e, 0x0000 }, /* R1678 (0x68E) - OUT1RMIX Input 4 Source */ 263 263 + { 0x0000068f, 0x0080 }, /* R1679 (0x68F) - OUT1RMIX Input 4 Volume */ 264 264 + { 0x000006b0, 0x0000 }, /* R1712 (0x6B0) - OUT4LMIX Input 1 Source */ 265 265 + { 0x000006b1, 0x0080 }, /* R1713 (0x6B1) - OUT4LMIX Input 1 Volume */ 266 266 + { 0x000006b2, 0x0000 }, /* R1714 (0x6B2) - OUT4LMIX Input 2 Source */ 267 267 + { 0x000006b3, 0x0080 }, /* R1715 (0x6B3) - OUT4LMIX Input 2 Volume */ 268 268 + { 0x000006b4, 0x0000 }, /* R1716 (0x6B4) - OUT4LMIX Input 3 Source */ 269 269 + { 0x000006b5, 0x0080 }, /* R1717 (0x6B5) - OUT4LMIX Input 3 Volume */ 270 270 + { 0x000006b6, 0x0000 }, /* R1718 (0x6B6) - OUT4LMIX Input 4 Source */ 271 271 + { 0x000006b7, 0x0080 }, /* R1719 (0x6B7) - OUT4LMIX Input 4 Volume */ 272 272 + { 0x000006c0, 0x0000 }, /* R1728 (0x6C0) - OUT5LMIX Input 1 Source */ 273 273 + { 0x000006c1, 0x0080 }, /* R1729 (0x6C1) - OUT5LMIX Input 1 Volume */ 274 274 + { 0x000006c2, 0x0000 }, /* R1730 (0x6C2) - OUT5LMIX Input 2 Source */ 275 275 + { 0x000006c3, 0x0080 }, /* R1731 (0x6C3) - OUT5LMIX Input 2 Volume */ 276 276 + { 0x000006c4, 0x0000 }, /* R1732 (0x6C4) - OUT5LMIX Input 3 Source */ 277 277 + { 0x000006c5, 0x0080 }, /* R1733 (0x6C5) - OUT5LMIX Input 3 Volume */ 278 278 + { 0x000006c6, 0x0000 }, /* R1734 (0x6C6) - OUT5LMIX Input 4 Source */ 279 279 + { 0x000006c7, 0x0080 }, /* R1735 (0x6C7) - OUT5LMIX Input 4 Volume */ 280 280 + { 0x000006c8, 0x0000 }, /* R1736 (0x6C8) - OUT5RMIX Input 1 Source */ 281 281 + { 0x000006c9, 0x0080 }, /* R1737 (0x6C9) - OUT5RMIX Input 1 Volume */ 282 282 + { 0x000006ca, 0x0000 }, /* R1738 (0x6CA) - OUT5RMIX Input 2 Source */ 283 283 + { 0x000006cb, 0x0080 }, /* R1739 (0x6CB) - OUT5RMIX Input 2 Volume */ 284 284 + { 0x000006cc, 0x0000 }, /* R1740 (0x6CC) - OUT5RMIX Input 3 Source */ 285 285 + { 0x000006cd, 0x0080 }, /* R1741 (0x6CD) - OUT5RMIX Input 3 Volume */ 286 286 + { 0x000006ce, 0x0000 }, /* R1742 (0x6CE) - OUT5RMIX Input 4 Source */ 287 287 + { 0x000006cf, 0x0080 }, /* R1743 (0x6CF) - OUT5RMIX Input 4 Volume */ 288 288 + { 0x00000700, 0x0000 }, /* R1792 (0x700) - AIF1TX1MIX Input 1 Source */ 289 289 + { 0x00000701, 0x0080 }, /* R1793 (0x701) - AIF1TX1MIX Input 1 Volume */ 290 290 + { 0x00000702, 0x0000 }, /* R1794 (0x702) - AIF1TX1MIX Input 2 Source */ 291 291 + { 0x00000703, 0x0080 }, /* R1795 (0x703) - AIF1TX1MIX Input 2 Volume */ 292 292 + { 0x00000704, 0x0000 }, /* R1796 (0x704) - AIF1TX1MIX Input 3 Source */ 293 293 + { 0x00000705, 0x0080 }, /* R1797 (0x705) - AIF1TX1MIX Input 3 Volume */ 294 294 + { 0x00000706, 0x0000 }, /* R1798 (0x706) - AIF1TX1MIX Input 4 Source */ 295 295 + { 0x00000707, 0x0080 }, /* R1799 (0x707) - AIF1TX1MIX Input 4 Volume */ 296 296 + { 0x00000708, 0x0000 }, /* R1800 (0x708) - AIF1TX2MIX Input 1 Source */ 297 297 + { 0x00000709, 0x0080 }, /* R1801 (0x709) - AIF1TX2MIX Input 1 Volume */ 298 298 + { 0x0000070a, 0x0000 }, /* R1802 (0x70A) - AIF1TX2MIX Input 2 Source */ 299 299 + { 0x0000070b, 0x0080 }, /* R1803 (0x70B) - AIF1TX2MIX Input 2 Volume */ 300 300 + { 0x0000070c, 0x0000 }, /* R1804 (0x70C) - AIF1TX2MIX Input 3 Source */ 301 301 + { 0x0000070d, 0x0080 }, /* R1805 (0x70D) - AIF1TX2MIX Input 3 Volume */ 302 302 + { 0x0000070e, 0x0000 }, /* R1806 (0x70E) - AIF1TX2MIX Input 4 Source */ 303 303 + { 0x0000070f, 0x0080 }, /* R1807 (0x70F) - AIF1TX2MIX Input 4 Volume */ 304 304 + { 0x00000710, 0x0000 }, /* R1808 (0x710) - AIF1TX3MIX Input 1 Source */ 305 305 + { 0x00000711, 0x0080 }, /* R1809 (0x711) - AIF1TX3MIX Input 1 Volume */ 306 306 + { 0x00000712, 0x0000 }, /* R1810 (0x712) - AIF1TX3MIX Input 2 Source */ 307 307 + { 0x00000713, 0x0080 }, /* R1811 (0x713) - AIF1TX3MIX Input 2 Volume */ 308 308 + { 0x00000714, 0x0000 }, /* R1812 (0x714) - AIF1TX3MIX Input 3 Source */ 309 309 + { 0x00000715, 0x0080 }, /* R1813 (0x715) - AIF1TX3MIX Input 3 Volume */ 310 310 + { 0x00000716, 0x0000 }, /* R1814 (0x716) - AIF1TX3MIX Input 4 Source */ 311 311 + { 0x00000717, 0x0080 }, /* R1815 (0x717) - AIF1TX3MIX Input 4 Volume */ 312 312 + { 0x00000718, 0x0000 }, /* R1816 (0x718) - AIF1TX4MIX Input 1 Source */ 313 313 + { 0x00000719, 0x0080 }, /* R1817 (0x719) - AIF1TX4MIX Input 1 Volume */ 314 314 + { 0x0000071a, 0x0000 }, /* R1818 (0x71A) - AIF1TX4MIX Input 2 Source */ 315 315 + { 0x0000071b, 0x0080 }, /* R1819 (0x71B) - AIF1TX4MIX Input 2 Volume */ 316 316 + { 0x0000071c, 0x0000 }, /* R1820 (0x71C) - AIF1TX4MIX Input 3 Source */ 317 317 + { 0x0000071d, 0x0080 }, /* R1821 (0x71D) - AIF1TX4MIX Input 3 Volume */ 318 318 + { 0x0000071e, 0x0000 }, /* R1822 (0x71E) - AIF1TX4MIX Input 4 Source */ 319 319 + { 0x0000071f, 0x0080 }, /* R1823 (0x71F) - AIF1TX4MIX Input 4 Volume */ 320 320 + { 0x00000720, 0x0000 }, /* R1824 (0x720) - AIF1TX5MIX Input 1 Source */ 321 321 + { 0x00000721, 0x0080 }, /* R1825 (0x721) - AIF1TX5MIX Input 1 Volume */ 322 322 + { 0x00000722, 0x0000 }, /* R1826 (0x722) - AIF1TX5MIX Input 2 Source */ 323 323 + { 0x00000723, 0x0080 }, /* R1827 (0x723) - AIF1TX5MIX Input 2 Volume */ 324 324 + { 0x00000724, 0x0000 }, /* R1828 (0x724) - AIF1TX5MIX Input 3 Source */ 325 325 + { 0x00000725, 0x0080 }, /* R1829 (0x725) - AIF1TX5MIX Input 3 Volume */ 326 326 + { 0x00000726, 0x0000 }, /* R1830 (0x726) - AIF1TX5MIX Input 4 Source */ 327 327 + { 0x00000727, 0x0080 }, /* R1831 (0x727) - AIF1TX5MIX Input 4 Volume */ 328 328 + { 0x00000728, 0x0000 }, /* R1832 (0x728) - AIF1TX6MIX Input 1 Source */ 329 329 + { 0x00000729, 0x0080 }, /* R1833 (0x729) - AIF1TX6MIX Input 1 Volume */ 330 330 + { 0x0000072a, 0x0000 }, /* R1834 (0x72A) - AIF1TX6MIX Input 2 Source */ 331 331 + { 0x0000072b, 0x0080 }, /* R1835 (0x72B) - AIF1TX6MIX Input 2 Volume */ 332 332 + { 0x0000072c, 0x0000 }, /* R1836 (0x72C) - AIF1TX6MIX Input 3 Source */ 333 333 + { 0x0000072d, 0x0080 }, /* R1837 (0x72D) - AIF1TX6MIX Input 3 Volume */ 334 334 + { 0x0000072e, 0x0000 }, /* R1838 (0x72E) - AIF1TX6MIX Input 4 Source */ 335 335 + { 0x0000072f, 0x0080 }, /* R1839 (0x72F) - AIF1TX6MIX Input 4 Volume */ 336 336 + { 0x00000740, 0x0000 }, /* R1856 (0x740) - AIF2TX1MIX Input 1 Source */ 337 337 + { 0x00000741, 0x0080 }, /* R1857 (0x741) - AIF2TX1MIX Input 1 Volume */ 338 338 + { 0x00000742, 0x0000 }, /* R1858 (0x742) - AIF2TX1MIX Input 2 Source */ 339 339 + { 0x00000743, 0x0080 }, /* R1859 (0x743) - AIF2TX1MIX Input 2 Volume */ 340 340 + { 0x00000744, 0x0000 }, /* R1860 (0x744) - AIF2TX1MIX Input 3 Source */ 341 341 + { 0x00000745, 0x0080 }, /* R1861 (0x745) - AIF2TX1MIX Input 3 Volume */ 342 342 + { 0x00000746, 0x0000 }, /* R1862 (0x746) - AIF2TX1MIX Input 4 Source */ 343 343 + { 0x00000747, 0x0080 }, /* R1863 (0x747) - AIF2TX1MIX Input 4 Volume */ 344 344 + { 0x00000748, 0x0000 }, /* R1864 (0x748) - AIF2TX2MIX Input 1 Source */ 345 345 + { 0x00000749, 0x0080 }, /* R1865 (0x749) - AIF2TX2MIX Input 1 Volume */ 346 346 + { 0x0000074a, 0x0000 }, /* R1866 (0x74A) - AIF2TX2MIX Input 2 Source */ 347 347 + { 0x0000074b, 0x0080 }, /* R1867 (0x74B) - AIF2TX2MIX Input 2 Volume */ 348 348 + { 0x0000074c, 0x0000 }, /* R1868 (0x74C) - AIF2TX2MIX Input 3 Source */ 349 349 + { 0x0000074d, 0x0080 }, /* R1869 (0x74D) - AIF2TX2MIX Input 3 Volume */ 350 350 + { 0x0000074e, 0x0000 }, /* R1870 (0x74E) - AIF2TX2MIX Input 4 Source */ 351 351 + { 0x0000074f, 0x0080 }, /* R1871 (0x74F) - AIF2TX2MIX Input 4 Volume */ 352 352 + { 0x00000750, 0x0000 }, /* R1872 (0x750) - AIF2TX3MIX Input 1 Source */ 353 353 + { 0x00000751, 0x0080 }, /* R1873 (0x751) - AIF2TX3MIX Input 1 Volume */ 354 354 + { 0x00000752, 0x0000 }, /* R1874 (0x752) - AIF2TX3MIX Input 2 Source */ 355 355 + { 0x00000753, 0x0080 }, /* R1875 (0x753) - AIF2TX3MIX Input 2 Volume */ 356 356 + { 0x00000754, 0x0000 }, /* R1876 (0x754) - AIF2TX3MIX Input 3 Source */ 357 357 + { 0x00000755, 0x0080 }, /* R1877 (0x755) - AIF2TX3MIX Input 3 Volume */ 358 358 + { 0x00000756, 0x0000 }, /* R1878 (0x756) - AIF2TX3MIX Input 4 Source */ 359 359 + { 0x00000757, 0x0080 }, /* R1879 (0x757) - AIF2TX3MIX Input 4 Volume */ 360 360 + { 0x00000758, 0x0000 }, /* R1880 (0x758) - AIF2TX4MIX Input 1 Source */ 361 361 + { 0x00000759, 0x0080 }, /* R1881 (0x759) - AIF2TX4MIX Input 1 Volume */ 362 362 + { 0x0000075a, 0x0000 }, /* R1882 (0x75A) - AIF2TX4MIX Input 2 Source */ 363 363 + { 0x0000075b, 0x0080 }, /* R1883 (0x75B) - AIF2TX4MIX Input 2 Volume */ 364 364 + { 0x0000075c, 0x0000 }, /* R1884 (0x75C) - AIF2TX4MIX Input 3 Source */ 365 365 + { 0x0000075d, 0x0080 }, /* R1885 (0x75D) - AIF2TX4MIX Input 3 Volume */ 366 366 + { 0x0000075e, 0x0000 }, /* R1886 (0x75E) - AIF2TX4MIX Input 4 Source */ 367 367 + { 0x0000075f, 0x0080 }, /* R1887 (0x75F) - AIF2TX4MIX Input 4 Volume */ 368 368 + { 0x00000780, 0x0000 }, /* R1920 (0x780) - AIF3TX1MIX Input 1 Source */ 369 369 + { 0x00000781, 0x0080 }, /* R1921 (0x781) - AIF3TX1MIX Input 1 Volume */ 370 370 + { 0x00000782, 0x0000 }, /* R1922 (0x782) - AIF3TX1MIX Input 2 Source */ 371 371 + { 0x00000783, 0x0080 }, /* R1923 (0x783) - AIF3TX1MIX Input 2 Volume */ 372 372 + { 0x00000784, 0x0000 }, /* R1924 (0x784) - AIF3TX1MIX Input 3 Source */ 373 373 + { 0x00000785, 0x0080 }, /* R1925 (0x785) - AIF3TX1MIX Input 3 Volume */ 374 374 + { 0x00000786, 0x0000 }, /* R1926 (0x786) - AIF3TX1MIX Input 4 Source */ 375 375 + { 0x00000787, 0x0080 }, /* R1927 (0x787) - AIF3TX1MIX Input 4 Volume */ 376 376 + { 0x00000788, 0x0000 }, /* R1928 (0x788) - AIF3TX2MIX Input 1 Source */ 377 377 + { 0x00000789, 0x0080 }, /* R1929 (0x789) - AIF3TX2MIX Input 1 Volume */ 378 378 + { 0x0000078a, 0x0000 }, /* R1930 (0x78A) - AIF3TX2MIX Input 2 Source */ 379 379 + { 0x0000078b, 0x0080 }, /* R1931 (0x78B) - AIF3TX2MIX Input 2 Volume */ 380 380 + { 0x0000078c, 0x0000 }, /* R1932 (0x78C) - AIF3TX2MIX Input 3 Source */ 381 381 + { 0x0000078d, 0x0080 }, /* R1933 (0x78D) - AIF3TX2MIX Input 3 Volume */ 382 382 + { 0x0000078e, 0x0000 }, /* R1934 (0x78E) - AIF3TX2MIX Input 4 Source */ 383 383 + { 0x0000078f, 0x0080 }, /* R1935 (0x78F) - AIF3TX2MIX Input 4 Volume */ 384 384 + { 0x00000800, 0x0000 }, /* R2048 (0x800) - SPDIF1TX1MIX Input 1 Source */ 385 385 + { 0x00000801, 0x0080 }, /* R2049 (0x801) - SPDIF1TX1MIX Input 1 Volume */ 386 386 + { 0x00000808, 0x0000 }, /* R2056 (0x808) - SPDIF1TX2MIX Input 1 Source */ 387 387 + { 0x00000809, 0x0080 }, /* R2057 (0x809) - SPDIF1TX2MIX Input 1 Volume */ 388 388 + { 0x00000880, 0x0000 }, /* R2176 (0x880) - EQ1MIX Input 1 Source */ 389 389 + { 0x00000881, 0x0080 }, /* R2177 (0x881) - EQ1MIX Input 1 Volume */ 390 390 + { 0x00000882, 0x0000 }, /* R2178 (0x882) - EQ1MIX Input 2 Source */ 391 391 + { 0x00000883, 0x0080 }, /* R2179 (0x883) - EQ1MIX Input 2 Volume */ 392 392 + { 0x00000884, 0x0000 }, /* R2180 (0x884) - EQ1MIX Input 3 Source */ 393 393 + { 0x00000885, 0x0080 }, /* R2181 (0x885) - EQ1MIX Input 3 Volume */ 394 394 + { 0x00000886, 0x0000 }, /* R2182 (0x886) - EQ1MIX Input 4 Source */ 395 395 + { 0x00000887, 0x0080 }, /* R2183 (0x887) - EQ1MIX Input 4 Volume */ 396 396 + { 0x00000888, 0x0000 }, /* R2184 (0x888) - EQ2MIX Input 1 Source */ 397 397 + { 0x00000889, 0x0080 }, /* R2185 (0x889) - EQ2MIX Input 1 Volume */ 398 398 + { 0x0000088a, 0x0000 }, /* R2186 (0x88A) - EQ2MIX Input 2 Source */ 399 399 + { 0x0000088b, 0x0080 }, /* R2187 (0x88B) - EQ2MIX Input 2 Volume */ 400 400 + { 0x0000088c, 0x0000 }, /* R2188 (0x88C) - EQ2MIX Input 3 Source */ 401 401 + { 0x0000088d, 0x0080 }, /* R2189 (0x88D) - EQ2MIX Input 3 Volume */ 402 402 + { 0x0000088e, 0x0000 }, /* R2190 (0x88E) - EQ2MIX Input 4 Source */ 403 403 + { 0x0000088f, 0x0080 }, /* R2191 (0x88F) - EQ2MIX Input 4 Volume */ 404 404 + { 0x00000890, 0x0000 }, /* R2192 (0x890) - EQ3MIX Input 1 Source */ 405 405 + { 0x00000891, 0x0080 }, /* R2193 (0x891) - EQ3MIX Input 1 Volume */ 406 406 + { 0x00000892, 0x0000 }, /* R2194 (0x892) - EQ3MIX Input 2 Source */ 407 407 + { 0x00000893, 0x0080 }, /* R2195 (0x893) - EQ3MIX Input 2 Volume */ 408 408 + { 0x00000894, 0x0000 }, /* R2196 (0x894) - EQ3MIX Input 3 Source */ 409 409 + { 0x00000895, 0x0080 }, /* R2197 (0x895) - EQ3MIX Input 3 Volume */ 410 410 + { 0x00000896, 0x0000 }, /* R2198 (0x896) - EQ3MIX Input 4 Source */ 411 411 + { 0x00000897, 0x0080 }, /* R2199 (0x897) - EQ3MIX Input 4 Volume */ 412 412 + { 0x00000898, 0x0000 }, /* R2200 (0x898) - EQ4MIX Input 1 Source */ 413 413 + { 0x00000899, 0x0080 }, /* R2201 (0x899) - EQ4MIX Input 1 Volume */ 414 414 + { 0x0000089a, 0x0000 }, /* R2202 (0x89A) - EQ4MIX Input 2 Source */ 415 415 + { 0x0000089b, 0x0080 }, /* R2203 (0x89B) - EQ4MIX Input 2 Volume */ 416 416 + { 0x0000089c, 0x0000 }, /* R2204 (0x89C) - EQ4MIX Input 3 Source */ 417 417 + { 0x0000089d, 0x0080 }, /* R2205 (0x89D) - EQ4MIX Input 3 Volume */ 418 418 + { 0x0000089e, 0x0000 }, /* R2206 (0x89E) - EQ4MIX Input 4 Source */ 419 419 + { 0x0000089f, 0x0080 }, /* R2207 (0x89F) - EQ4MIX Input 4 Volume */ 420 420 + { 0x000008c0, 0x0000 }, /* R2240 (0x8C0) - DRC1LMIX Input 1 Source */ 421 421 + { 0x000008c1, 0x0080 }, /* R2241 (0x8C1) - DRC1LMIX Input 1 Volume */ 422 422 + { 0x000008c2, 0x0000 }, /* R2242 (0x8C2) - DRC1LMIX Input 2 Source */ 423 423 + { 0x000008c3, 0x0080 }, /* R2243 (0x8C3) - DRC1LMIX Input 2 Volume */ 424 424 + { 0x000008c4, 0x0000 }, /* R2244 (0x8C4) - DRC1LMIX Input 3 Source */ 425 425 + { 0x000008c5, 0x0080 }, /* R2245 (0x8C5) - DRC1LMIX Input 3 Volume */ 426 426 + { 0x000008c6, 0x0000 }, /* R2246 (0x8C6) - DRC1LMIX Input 4 Source */ 427 427 + { 0x000008c7, 0x0080 }, /* R2247 (0x8C7) - DRC1LMIX Input 4 Volume */ 428 428 + { 0x000008c8, 0x0000 }, /* R2248 (0x8C8) - DRC1RMIX Input 1 Source */ 429 429 + { 0x000008c9, 0x0080 }, /* R2249 (0x8C9) - DRC1RMIX Input 1 Volume */ 430 430 + { 0x000008ca, 0x0000 }, /* R2250 (0x8CA) - DRC1RMIX Input 2 Source */ 431 431 + { 0x000008cb, 0x0080 }, /* R2251 (0x8CB) - DRC1RMIX Input 2 Volume */ 432 432 + { 0x000008cc, 0x0000 }, /* R2252 (0x8CC) - DRC1RMIX Input 3 Source */ 433 433 + { 0x000008cd, 0x0080 }, /* R2253 (0x8CD) - DRC1RMIX Input 3 Volume */ 434 434 + { 0x000008ce, 0x0000 }, /* R2254 (0x8CE) - DRC1RMIX Input 4 Source */ 435 435 + { 0x000008cf, 0x0080 }, /* R2255 (0x8CF) - DRC1RMIX Input 4 Volume */ 436 436 + { 0x000008d0, 0x0000 }, /* R2256 (0x8D0) - DRC2LMIX Input 1 Source */ 437 437 + { 0x000008d1, 0x0080 }, /* R2257 (0x8D1) - DRC2LMIX Input 1 Volume */ 438 438 + { 0x000008d2, 0x0000 }, /* R2258 (0x8D2) - DRC2LMIX Input 2 Source */ 439 439 + { 0x000008d3, 0x0080 }, /* R2259 (0x8D3) - DRC2LMIX Input 2 Volume */ 440 440 + { 0x000008d4, 0x0000 }, /* R2260 (0x8D4) - DRC2LMIX Input 3 Source */ 441 441 + { 0x000008d5, 0x0080 }, /* R2261 (0x8D5) - DRC2LMIX Input 3 Volume */ 442 442 + { 0x000008d6, 0x0000 }, /* R2262 (0x8D6) - DRC2LMIX Input 4 Source */ 443 443 + { 0x000008d7, 0x0080 }, /* R2263 (0x8D7) - DRC2LMIX Input 4 Volume */ 444 444 + { 0x000008d8, 0x0000 }, /* R2264 (0x8D8) - DRC2RMIX Input 1 Source */ 445 445 + { 0x000008d9, 0x0080 }, /* R2265 (0x8D9) - DRC2RMIX Input 1 Volume */ 446 446 + { 0x000008da, 0x0000 }, /* R2266 (0x8DA) - DRC2RMIX Input 2 Source */ 447 447 + { 0x000008db, 0x0080 }, /* R2267 (0x8DB) - DRC2RMIX Input 2 Volume */ 448 448 + { 0x000008dc, 0x0000 }, /* R2268 (0x8DC) - DRC2RMIX Input 3 Source */ 449 449 + { 0x000008dd, 0x0080 }, /* R2269 (0x8DD) - DRC2RMIX Input 3 Volume */ 450 450 + { 0x000008de, 0x0000 }, /* R2270 (0x8DE) - DRC2RMIX Input 4 Source */ 451 451 + { 0x000008df, 0x0080 }, /* R2271 (0x8DF) - DRC2RMIX Input 4 Volume */ 452 452 + { 0x00000900, 0x0000 }, /* R2304 (0x900) - HPLP1MIX Input 1 Source */ 453 453 + { 0x00000901, 0x0080 }, /* R2305 (0x901) - HPLP1MIX Input 1 Volume */ 454 454 + { 0x00000902, 0x0000 }, /* R2306 (0x902) - HPLP1MIX Input 2 Source */ 455 455 + { 0x00000903, 0x0080 }, /* R2307 (0x903) - HPLP1MIX Input 2 Volume */ 456 456 + { 0x00000904, 0x0000 }, /* R2308 (0x904) - HPLP1MIX Input 3 Source */ 457 457 + { 0x00000905, 0x0080 }, /* R2309 (0x905) - HPLP1MIX Input 3 Volume */ 458 458 + { 0x00000906, 0x0000 }, /* R2310 (0x906) - HPLP1MIX Input 4 Source */ 459 459 + { 0x00000907, 0x0080 }, /* R2311 (0x907) - HPLP1MIX Input 4 Volume */ 460 460 + { 0x00000908, 0x0000 }, /* R2312 (0x908) - HPLP2MIX Input 1 Source */ 461 461 + { 0x00000909, 0x0080 }, /* R2313 (0x909) - HPLP2MIX Input 1 Volume */ 462 462 + { 0x0000090a, 0x0000 }, /* R2314 (0x90A) - HPLP2MIX Input 2 Source */ 463 463 + { 0x0000090b, 0x0080 }, /* R2315 (0x90B) - HPLP2MIX Input 2 Volume */ 464 464 + { 0x0000090c, 0x0000 }, /* R2316 (0x90C) - HPLP2MIX Input 3 Source */ 465 465 + { 0x0000090d, 0x0080 }, /* R2317 (0x90D) - HPLP2MIX Input 3 Volume */ 466 466 + { 0x0000090e, 0x0000 }, /* R2318 (0x90E) - HPLP2MIX Input 4 Source */ 467 467 + { 0x0000090f, 0x0080 }, /* R2319 (0x90F) - HPLP2MIX Input 4 Volume */ 468 468 + { 0x00000910, 0x0000 }, /* R2320 (0x910) - HPLP3MIX Input 1 Source */ 469 469 + { 0x00000911, 0x0080 }, /* R2321 (0x911) - HPLP3MIX Input 1 Volume */ 470 470 + { 0x00000912, 0x0000 }, /* R2322 (0x912) - HPLP3MIX Input 2 Source */ 471 471 + { 0x00000913, 0x0080 }, /* R2323 (0x913) - HPLP3MIX Input 2 Volume */ 472 472 + { 0x00000914, 0x0000 }, /* R2324 (0x914) - HPLP3MIX Input 3 Source */ 473 473 + { 0x00000915, 0x0080 }, /* R2325 (0x915) - HPLP3MIX Input 3 Volume */ 474 474 + { 0x00000916, 0x0000 }, /* R2326 (0x916) - HPLP3MIX Input 4 Source */ 475 475 + { 0x00000917, 0x0080 }, /* R2327 (0x917) - HPLP3MIX Input 4 Volume */ 476 476 + { 0x00000918, 0x0000 }, /* R2328 (0x918) - HPLP4MIX Input 1 Source */ 477 477 + { 0x00000919, 0x0080 }, /* R2329 (0x919) - HPLP4MIX Input 1 Volume */ 478 478 + { 0x0000091a, 0x0000 }, /* R2330 (0x91A) - HPLP4MIX Input 2 Source */ 479 479 + { 0x0000091b, 0x0080 }, /* R2331 (0x91B) - HPLP4MIX Input 2 Volume */ 480 480 + { 0x0000091c, 0x0000 }, /* R2332 (0x91C) - HPLP4MIX Input 3 Source */ 481 481 + { 0x0000091d, 0x0080 }, /* R2333 (0x91D) - HPLP4MIX Input 3 Volume */ 482 482 + { 0x0000091e, 0x0000 }, /* R2334 (0x91E) - HPLP4MIX Input 4 Source */ 483 483 + { 0x0000091f, 0x0080 }, /* R2335 (0x91F) - HPLP4MIX Input 4 Volume */ 484 484 + { 0x00000940, 0x0000 }, /* R2368 (0x940) - DSP1LMIX Input 1 Source */ 485 485 + { 0x00000941, 0x0080 }, /* R2369 (0x941) - DSP1LMIX Input 1 Volume */ 486 486 + { 0x00000942, 0x0000 }, /* R2370 (0x942) - DSP1LMIX Input 2 Source */ 487 487 + { 0x00000943, 0x0080 }, /* R2371 (0x943) - DSP1LMIX Input 2 Volume */ 488 488 + { 0x00000944, 0x0000 }, /* R2372 (0x944) - DSP1LMIX Input 3 Source */ 489 489 + { 0x00000945, 0x0080 }, /* R2373 (0x945) - DSP1LMIX Input 3 Volume */ 490 490 + { 0x00000946, 0x0000 }, /* R2374 (0x946) - DSP1LMIX Input 4 Source */ 491 491 + { 0x00000947, 0x0080 }, /* R2375 (0x947) - DSP1LMIX Input 4 Volume */ 492 492 + { 0x00000948, 0x0000 }, /* R2376 (0x948) - DSP1RMIX Input 1 Source */ 493 493 + { 0x00000949, 0x0080 }, /* R2377 (0x949) - DSP1RMIX Input 1 Volume */ 494 494 + { 0x0000094a, 0x0000 }, /* R2378 (0x94A) - DSP1RMIX Input 2 Source */ 495 495 + { 0x0000094b, 0x0080 }, /* R2379 (0x94B) - DSP1RMIX Input 2 Volume */ 496 496 + { 0x0000094c, 0x0000 }, /* R2380 (0x94C) - DSP1RMIX Input 3 Source */ 497 497 + { 0x0000094d, 0x0080 }, /* R2381 (0x94D) - DSP1RMIX Input 3 Volume */ 498 498 + { 0x0000094e, 0x0000 }, /* R2382 (0x94E) - DSP1RMIX Input 4 Source */ 499 499 + { 0x0000094f, 0x0080 }, /* R2383 (0x94F) - DSP1RMIX Input 4 Volume */ 500 500 + { 0x00000950, 0x0000 }, /* R2384 (0x950) - DSP1AUX1MIX Input 1 Source */ 501 501 + { 0x00000958, 0x0000 }, /* R2392 (0x958) - DSP1AUX2MIX Input 1 Source */ 502 502 + { 0x00000960, 0x0000 }, /* R2400 (0x960) - DSP1AUX3MIX Input 1 Source */ 503 503 + { 0x00000968, 0x0000 }, /* R2408 (0x968) - DSP1AUX4MIX Input 1 Source */ 504 504 + { 0x00000970, 0x0000 }, /* R2416 (0x970) - DSP1AUX5MIX Input 1 Source */ 505 505 + { 0x00000978, 0x0000 }, /* R2424 (0x978) - DSP1AUX6MIX Input 1 Source */ 506 506 + { 0x00000b00, 0x0000 }, /* R2816 (0xB00) - ISRC1DEC1MIX Input 1 Source */ 507 507 + { 0x00000b08, 0x0000 }, /* R2824 (0xB08) - ISRC1DEC2MIX Input 1 Source */ 508 508 + { 0x00000b10, 0x0000 }, /* R2832 (0xB10) - ISRC1DEC3MIX Input 1 Source */ 509 509 + { 0x00000b18, 0x0000 }, /* R2840 (0xB18) - ISRC1DEC4MIX Input 1 Source */ 510 510 + { 0x00000b20, 0x0000 }, /* R2848 (0xB20) - ISRC1INT1MIX Input 1 Source */ 511 511 + { 0x00000b28, 0x0000 }, /* R2856 (0xB28) - ISRC1INT2MIX Input 1 Source */ 512 512 + { 0x00000b30, 0x0000 }, /* R2864 (0xB30) - ISRC1INT3MIX Input 1 Source */ 513 513 + { 0x00000b38, 0x0000 }, /* R2872 (0xB38) - ISRC1INT4MIX Input 1 Source */ 514 514 + { 0x00000b40, 0x0000 }, /* R2880 (0xB40) - ISRC2DEC1MIX Input 1 Source */ 515 515 + { 0x00000b48, 0x0000 }, /* R2888 (0xB48) - ISRC2DEC2MIX Input 1 Source */ 516 516 + { 0x00000b50, 0x0000 }, /* R2896 (0xB50) - ISRC2DEC3MIX Input 1 Source */ 517 517 + { 0x00000b58, 0x0000 }, /* R2904 (0xB58) - ISRC2DEC4MIX Input 1 Source */ 518 518 + { 0x00000b60, 0x0000 }, /* R2912 (0xB60) - ISRC2INT1MIX Input 1 Source */ 519 519 + { 0x00000b68, 0x0000 }, /* R2920 (0xB68) - ISRC2INT2MIX Input 1 Source */ 520 520 + { 0x00000b70, 0x0000 }, /* R2928 (0xB70) - ISRC2INT3MIX Input 1 Source */ 521 521 + { 0x00000b78, 0x0000 }, /* R2936 (0xB78) - ISRC2INT4MIX Input 1 Source */ 522 522 + { 0x00000e00, 0x0000 }, /* R3584 (0xE00) - FX Ctrl 1 */ 523 523 + { 0x00000e10, 0x6318 }, /* R3600 (0xE10) - EQ1 1 */ 524 524 + { 0x00000e11, 0x6300 }, /* R3601 (0xE11) - EQ1 2 */ 525 525 + { 0x00000e12, 0x0fc8 }, /* R3602 (0xE12) - EQ1 3 */ 526 526 + { 0x00000e13, 0x03fe }, /* R3603 (0xE13) - EQ1 4 */ 527 527 + { 0x00000e14, 0x00e0 }, /* R3604 (0xE14) - EQ1 5 */ 528 528 + { 0x00000e15, 0x1ec4 }, /* R3605 (0xE15) - EQ1 6 */ 529 529 + { 0x00000e16, 0xf136 }, /* R3606 (0xE16) - EQ1 7 */ 530 530 + { 0x00000e17, 0x0409 }, /* R3607 (0xE17) - EQ1 8 */ 531 531 + { 0x00000e18, 0x04cc }, /* R3608 (0xE18) - EQ1 9 */ 532 532 + { 0x00000e19, 0x1c9b }, /* R3609 (0xE19) - EQ1 10 */ 533 533 + { 0x00000e1a, 0xf337 }, /* R3610 (0xE1A) - EQ1 11 */ 534 534 + { 0x00000e1b, 0x040b }, /* R3611 (0xE1B) - EQ1 12 */ 535 535 + { 0x00000e1c, 0x0cbb }, /* R3612 (0xE1C) - EQ1 13 */ 536 536 + { 0x00000e1d, 0x16f8 }, /* R3613 (0xE1D) - EQ1 14 */ 537 537 + { 0x00000e1e, 0xf7d9 }, /* R3614 (0xE1E) - EQ1 15 */ 538 538 + { 0x00000e1f, 0x040a }, /* R3615 (0xE1F) - EQ1 16 */ 539 539 + { 0x00000e20, 0x1f14 }, /* R3616 (0xE20) - EQ1 17 */ 540 540 + { 0x00000e21, 0x058c }, /* R3617 (0xE21) - EQ1 18 */ 541 541 + { 0x00000e22, 0x0563 }, /* R3618 (0xE22) - EQ1 19 */ 542 542 + { 0x00000e23, 0x4000 }, /* R3619 (0xE23) - EQ1 20 */ 543 543 + { 0x00000e24, 0x0b75 }, /* R3620 (0xE24) - EQ1 21 */ 544 544 + { 0x00000e26, 0x6318 }, /* R3622 (0xE26) - EQ2 1 */ 545 545 + { 0x00000e27, 0x6300 }, /* R3623 (0xE27) - EQ2 2 */ 546 546 + { 0x00000e28, 0x0fc8 }, /* R3624 (0xE28) - EQ2 3 */ 547 547 + { 0x00000e29, 0x03fe }, /* R3625 (0xE29) - EQ2 4 */ 548 548 + { 0x00000e2a, 0x00e0 }, /* R3626 (0xE2A) - EQ2 5 */ 549 549 + { 0x00000e2b, 0x1ec4 }, /* R3627 (0xE2B) - EQ2 6 */ 550 550 + { 0x00000e2c, 0xf136 }, /* R3628 (0xE2C) - EQ2 7 */ 551 551 + { 0x00000e2d, 0x0409 }, /* R3629 (0xE2D) - EQ2 8 */ 552 552 + { 0x00000e2e, 0x04cc }, /* R3630 (0xE2E) - EQ2 9 */ 553 553 + { 0x00000e2f, 0x1c9b }, /* R3631 (0xE2F) - EQ2 10 */ 554 554 + { 0x00000e30, 0xf337 }, /* R3632 (0xE30) - EQ2 11 */ 555 555 + { 0x00000e31, 0x040b }, /* R3633 (0xE31) - EQ2 12 */ 556 556 + { 0x00000e32, 0x0cbb }, /* R3634 (0xE32) - EQ2 13 */ 557 557 + { 0x00000e33, 0x16f8 }, /* R3635 (0xE33) - EQ2 14 */ 558 558 + { 0x00000e34, 0xf7d9 }, /* R3636 (0xE34) - EQ2 15 */ 559 559 + { 0x00000e35, 0x040a }, /* R3637 (0xE35) - EQ2 16 */ 560 560 + { 0x00000e36, 0x1f14 }, /* R3638 (0xE36) - EQ2 17 */ 561 561 + { 0x00000e37, 0x058c }, /* R3639 (0xE37) - EQ2 18 */ 562 562 + { 0x00000e38, 0x0563 }, /* R3640 (0xE38) - EQ2 19 */ 563 563 + { 0x00000e39, 0x4000 }, /* R3641 (0xE39) - EQ2 20 */ 564 564 + { 0x00000e3a, 0x0b75 }, /* R3642 (0xE3A) - EQ2 21 */ 565 565 + { 0x00000e3c, 0x6318 }, /* R3644 (0xE3C) - EQ3 1 */ 566 566 + { 0x00000e3d, 0x6300 }, /* R3645 (0xE3D) - EQ3 2 */ 567 567 + { 0x00000e3e, 0x0fc8 }, /* R3646 (0xE3E) - EQ3 3 */ 568 568 + { 0x00000e3f, 0x03fe }, /* R3647 (0xE3F) - EQ3 4 */ 569 569 + { 0x00000e40, 0x00e0 }, /* R3648 (0xE40) - EQ3 5 */ 570 570 + { 0x00000e41, 0x1ec4 }, /* R3649 (0xE41) - EQ3 6 */ 571 571 + { 0x00000e42, 0xf136 }, /* R3650 (0xE42) - EQ3 7 */ 572 572 + { 0x00000e43, 0x0409 }, /* R3651 (0xE43) - EQ3 8 */ 573 573 + { 0x00000e44, 0x04cc }, /* R3652 (0xE44) - EQ3 9 */ 574 574 + { 0x00000e45, 0x1c9b }, /* R3653 (0xE45) - EQ3 10 */ 575 575 + { 0x00000e46, 0xf337 }, /* R3654 (0xE46) - EQ3 11 */ 576 576 + { 0x00000e47, 0x040b }, /* R3655 (0xE47) - EQ3 12 */ 577 577 + { 0x00000e48, 0x0cbb }, /* R3656 (0xE48) - EQ3 13 */ 578 578 + { 0x00000e49, 0x16f8 }, /* R3657 (0xE49) - EQ3 14 */ 579 579 + { 0x00000e4a, 0xf7d9 }, /* R3658 (0xE4A) - EQ3 15 */ 580 580 + { 0x00000e4b, 0x040a }, /* R3659 (0xE4B) - EQ3 16 */ 581 581 + { 0x00000e4c, 0x1f14 }, /* R3660 (0xE4C) - EQ3 17 */ 582 582 + { 0x00000e4d, 0x058c }, /* R3661 (0xE4D) - EQ3 18 */ 583 583 + { 0x00000e4e, 0x0563 }, /* R3662 (0xE4E) - EQ3 19 */ 584 584 + { 0x00000e4f, 0x4000 }, /* R3663 (0xE4F) - EQ3 20 */ 585 585 + { 0x00000e50, 0x0b75 }, /* R3664 (0xE50) - EQ3 21 */ 586 586 + { 0x00000e52, 0x6318 }, /* R3666 (0xE52) - EQ4 1 */ 587 587 + { 0x00000e53, 0x6300 }, /* R3667 (0xE53) - EQ4 2 */ 588 588 + { 0x00000e54, 0x0fc8 }, /* R3668 (0xE54) - EQ4 3 */ 589 589 + { 0x00000e55, 0x03fe }, /* R3669 (0xE55) - EQ4 4 */ 590 590 + { 0x00000e56, 0x00e0 }, /* R3670 (0xE56) - EQ4 5 */ 591 591 + { 0x00000e57, 0x1ec4 }, /* R3671 (0xE57) - EQ4 6 */ 592 592 + { 0x00000e58, 0xf136 }, /* R3672 (0xE58) - EQ4 7 */ 593 593 + { 0x00000e59, 0x0409 }, /* R3673 (0xE59) - EQ4 8 */ 594 594 + { 0x00000e5a, 0x04cc }, /* R3674 (0xE5A) - EQ4 9 */ 595 595 + { 0x00000e5b, 0x1c9b }, /* R3675 (0xE5B) - EQ4 10 */ 596 596 + { 0x00000e5c, 0xf337 }, /* R3676 (0xE5C) - EQ4 11 */ 597 597 + { 0x00000e5d, 0x040b }, /* R3677 (0xE5D) - EQ4 12 */ 598 598 + { 0x00000e5e, 0x0cbb }, /* R3678 (0xE5E) - EQ4 13 */ 599 599 + { 0x00000e5f, 0x16f8 }, /* R3679 (0xE5F) - EQ4 14 */ 600 600 + { 0x00000e60, 0xf7d9 }, /* R3680 (0xE60) - EQ4 15 */ 601 601 + { 0x00000e61, 0x040a }, /* R3681 (0xE61) - EQ4 16 */ 602 602 + { 0x00000e62, 0x1f14 }, /* R3682 (0xE62) - EQ4 17 */ 603 603 + { 0x00000e63, 0x058c }, /* R3683 (0xE63) - EQ4 18 */ 604 604 + { 0x00000e64, 0x0563 }, /* R3684 (0xE64) - EQ4 19 */ 605 605 + { 0x00000e65, 0x4000 }, /* R3685 (0xE65) - EQ4 20 */ 606 606 + { 0x00000e66, 0x0b75 }, /* R3686 (0xE66) - EQ4 21 */ 607 607 + { 0x00000e80, 0x0018 }, /* R3712 (0xE80) - DRC1 Ctrl 1 */ 608 608 + { 0x00000e81, 0x0933 }, /* R3713 (0xE81) - DRC1 Ctrl 2 */ 609 609 + { 0x00000e82, 0x0018 }, /* R3714 (0xE82) - DRC1 Ctrl 3 */ 610 610 + { 0x00000e83, 0x0000 }, /* R3715 (0xE83) - DRC1 Ctrl 4 */ 611 611 + { 0x00000e84, 0x0000 }, /* R3716 (0xE84) - DRC1 Ctrl 5 */ 612 612 + { 0x00000e88, 0x0018 }, /* R3720 (0xE88) - DRC2 Ctrl 1 */ 613 613 + { 0x00000e89, 0x0933 }, /* R3721 (0xE89) - DRC2 Ctrl 2 */ 614 614 + { 0x00000e8a, 0x0018 }, /* R3722 (0xE8A) - DRC2 Ctrl 3 */ 615 615 + { 0x00000e8b, 0x0000 }, /* R3723 (0xE8B) - DRC2 Ctrl 4 */ 616 616 + { 0x00000e8c, 0x0000 }, /* R3724 (0xE8C) - DRC2 Ctrl 5 */ 617 617 + { 0x00000ec0, 0x0000 }, /* R3776 (0xEC0) - HPLPF1 1 */ 618 618 + { 0x00000ec1, 0x0000 }, /* R3777 (0xEC1) - HPLPF1 2 */ 619 619 + { 0x00000ec4, 0x0000 }, /* R3780 (0xEC4) - HPLPF2 1 */ 620 620 + { 0x00000ec5, 0x0000 }, /* R3781 (0xEC5) - HPLPF2 2 */ 621 621 + { 0x00000ec8, 0x0000 }, /* R3784 (0xEC8) - HPLPF3 1 */ 622 622 + { 0x00000ec9, 0x0000 }, /* R3785 (0xEC9) - HPLPF3 2 */ 623 623 + { 0x00000ecc, 0x0000 }, /* R3788 (0xECC) - HPLPF4 1 */ 624 624 + { 0x00000ecd, 0x0000 }, /* R3789 (0xECD) - HPLPF4 2 */ 625 625 + { 0x00000ef0, 0x0000 }, /* R3824 (0xEF0) - ISRC1 Ctrl 1 */ 626 626 + { 0x00000ef1, 0x0001 }, /* R3825 (0xEF1) - ISRC1 Ctrl 2 */ 627 627 + { 0x00000ef2, 0x0000 }, /* R3826 (0xEF2) - ISRC1 Ctrl 3 */ 628 628 + { 0x00000ef3, 0x0000 }, /* R3827 (0xEF3) - ISRC2 Ctrl 1 */ 629 629 + { 0x00000ef4, 0x0001 }, /* R3828 (0xEF4) - ISRC2 Ctrl 2 */ 630 630 + { 0x00000ef5, 0x0000 }, /* R3829 (0xEF5) - ISRC2 Ctrl 3 */ 631 631 + { 0x00001700, 0x2801 }, /* R5888 (0x1700) - GPIO1 Ctrl 1 */ 632 632 + { 0x00001701, 0xe800 }, /* R5889 (0x1701) - GPIO1 Ctrl 2 */ 633 633 + { 0x00001702, 0x2801 }, /* R5890 (0x1702) - GPIO2 Ctrl 1 */ 634 634 + { 0x00001703, 0xe800 }, /* R5891 (0x1703) - GPIO2 Ctrl 2 */ 635 635 + { 0x00001704, 0x2801 }, /* R5892 (0x1704) - GPIO3 Ctrl 1 */ 636 636 + { 0x00001705, 0xe800 }, /* R5893 (0x1705) - GPIO3 Ctrl 2 */ 637 637 + { 0x00001706, 0x2801 }, /* R5894 (0x1706) - GPIO4 Ctrl 1 */ 638 638 + { 0x00001707, 0xe800 }, /* R5895 (0x1707) - GPIO4 Ctrl 2 */ 639 639 + { 0x00001708, 0x2801 }, /* R5896 (0x1708) - GPIO5 Ctrl 1 */ 640 640 + { 0x00001709, 0xe800 }, /* R5897 (0x1709) - GPIO5 Ctrl 2 */ 641 641 + { 0x0000170a, 0x2801 }, /* R5898 (0x170A) - GPIO6 Ctrl 1 */ 642 642 + { 0x0000170b, 0xe800 }, /* R5899 (0x170B) - GPIO6 Ctrl 2 */ 643 643 + { 0x0000170c, 0x2801 }, /* R5900 (0x170C) - GPIO7 Ctrl 1 */ 644 644 + { 0x0000170d, 0xe800 }, /* R5901 (0x170D) - GPIO7 Ctrl 2 */ 645 645 + { 0x0000170e, 0x2801 }, /* R5902 (0x170E) - GPIO8 Ctrl 1 */ 646 646 + { 0x0000170f, 0xe800 }, /* R5903 (0x170F) - GPIO8 Ctrl 2 */ 647 647 + { 0x00001710, 0x2801 }, /* R5904 (0x1710) - GPIO9 Ctrl 1 */ 648 648 + { 0x00001711, 0xe800 }, /* R5905 (0x1711) - GPIO9 Ctrl 2 */ 649 649 + { 0x00001712, 0x2801 }, /* R5906 (0x1712) - GPIO10 Ctrl 1 */ 650 650 + { 0x00001713, 0xe800 }, /* R5907 (0x1713) - GPIO10 Ctrl 2 */ 651 651 + { 0x00001714, 0x2801 }, /* R5908 (0x1714) - GPIO11 Ctrl 1 */ 652 652 + { 0x00001715, 0xe800 }, /* R5909 (0x1715) - GPIO11 Ctrl 2 */ 653 653 + { 0x00001716, 0x2801 }, /* R5910 (0x1716) - GPIO12 Ctrl 1 */ 654 654 + { 0x00001717, 0xe800 }, /* R5911 (0x1717) - GPIO12 Ctrl 2 */ 655 655 + { 0x00001718, 0x2801 }, /* R5912 (0x1718) - GPIO13 Ctrl 1 */ 656 656 + { 0x00001719, 0xe800 }, /* R5913 (0x1719) - GPIO13 Ctrl 2 */ 657 657 + { 0x0000171a, 0x2801 }, /* R5914 (0x171A) - GPIO14 Ctrl 1 */ 658 658 + { 0x0000171b, 0xe800 }, /* R5915 (0x171B) - GPIO14 Ctrl 2 */ 659 659 + { 0x0000171c, 0x2801 }, /* R5916 (0x171C) - GPIO15 Ctrl 1 */ 660 660 + { 0x0000171d, 0xe800 }, /* R5917 (0x171D) - GPIO15 Ctrl 2 */ 661 661 + { 0x00001840, 0xffff }, /* R6208 (0x1840) - IRQ1 Mask 1 */ 662 662 + { 0x00001841, 0xffff }, /* R6209 (0x1841) - IRQ1 Mask 2 */ 663 663 + { 0x00001842, 0xffff }, /* R6210 (0x1842) - IRQ1 Mask 3 */ 664 664 + { 0x00001843, 0xffff }, /* R6211 (0x1843) - IRQ1 Mask 4 */ 665 665 + { 0x00001844, 0xffff }, /* R6212 (0x1844) - IRQ1 Mask 5 */ 666 666 + { 0x00001845, 0xffff }, /* R6213 (0x1845) - IRQ1 Mask 6 */ 667 667 + { 0x00001846, 0xffff }, /* R6214 (0x1846) - IRQ1 Mask 7 */ 668 668 + { 0x00001847, 0xffff }, /* R6215 (0x1847) - IRQ1 Mask 8 */ 669 669 + { 0x00001848, 0xffff }, /* R6216 (0x1848) - IRQ1 Mask 9 */ 670 670 + { 0x00001849, 0xffff }, /* R6217 (0x1849) - IRQ1 Mask 10 */ 671 671 + { 0x0000184a, 0xffff }, /* R6218 (0x184A) - IRQ1 Mask 11 */ 672 672 + { 0x0000184b, 0xffff }, /* R6219 (0x184B) - IRQ1 Mask 12 */ 673 673 + { 0x0000184c, 0xffff }, /* R6220 (0x184C) - IRQ1 Mask 13 */ 674 674 + { 0x0000184d, 0xffff }, /* R6221 (0x184D) - IRQ1 Mask 14 */ 675 675 + { 0x0000184e, 0xffff }, /* R6222 (0x184E) - IRQ1 Mask 15 */ 676 676 + { 0x0000184f, 0xffff }, /* R6223 (0x184F) - IRQ1 Mask 16 */ 677 677 + { 0x00001850, 0xffff }, /* R6224 (0x1850) - IRQ1 Mask 17 */ 678 678 + { 0x00001851, 0xffff }, /* R6225 (0x1851) - IRQ1 Mask 18 */ 679 679 + { 0x00001852, 0xffff }, /* R6226 (0x1852) - IRQ1 Mask 19 */ 680 680 + { 0x00001853, 0xffff }, /* R6227 (0x1853) - IRQ1 Mask 20 */ 681 681 + { 0x00001854, 0xffff }, /* R6228 (0x1854) - IRQ1 Mask 21 */ 682 682 + { 0x00001855, 0xffff }, /* R6229 (0x1855) - IRQ1 Mask 22 */ 683 683 + { 0x00001856, 0xffff }, /* R6230 (0x1856) - IRQ1 Mask 23 */ 684 684 + { 0x00001857, 0xffff }, /* R6231 (0x1857) - IRQ1 Mask 24 */ 685 685 + { 0x00001858, 0xffff }, /* R6232 (0x1858) - IRQ1 Mask 25 */ 686 686 + { 0x00001859, 0xffff }, /* R6233 (0x1859) - IRQ1 Mask 26 */ 687 687 + { 0x0000185a, 0xffff }, /* R6234 (0x185A) - IRQ1 Mask 27 */ 688 688 + { 0x0000185b, 0xffff }, /* R6235 (0x185B) - IRQ1 Mask 28 */ 689 689 + { 0x0000185c, 0xffff }, /* R6236 (0x185C) - IRQ1 Mask 29 */ 690 690 + { 0x0000185d, 0xffff }, /* R6237 (0x185D) - IRQ1 Mask 30 */ 691 691 + { 0x0000185e, 0xffff }, /* R6238 (0x185E) - IRQ1 Mask 31 */ 692 692 + { 0x0000185f, 0xffff }, /* R6239 (0x185F) - IRQ1 Mask 32 */ 693 693 + { 0x00001860, 0xffff }, /* R6240 (0x1860) - IRQ1 Mask 33 */ 694 694 + { 0x00001a06, 0x0000 }, /* R6662 (0x1A06) - Interrupt Debounce 7 */ 695 695 + { 0x00001a80, 0x4400 }, /* R6784 (0x1A80) - IRQ1 Ctrl */ 696 696 + }; 697 697 + 698 698 + static bool cs47l15_is_adsp_memory(struct device *dev, unsigned int reg) 699 699 + { 700 700 + switch (reg) { 701 701 + case 0x080000 ... 0x088ffe: 702 702 + case 0x0a0000 ... 0x0a9ffe: 703 703 + case 0x0c0000 ... 0x0c1ffe: 704 704 + case 0x0e0000 ... 0x0e1ffe: 705 705 + return true; 706 706 + default: 707 707 + return false; 708 708 + } 709 709 + } 710 710 + 711 711 + static bool cs47l15_16bit_readable_register(struct device *dev, 712 712 + unsigned int reg) 713 713 + { 714 714 + switch (reg) { 715 715 + case MADERA_SOFTWARE_RESET: 716 716 + case MADERA_HARDWARE_REVISION: 717 717 + case MADERA_WRITE_SEQUENCER_CTRL_0 ... MADERA_WRITE_SEQUENCER_CTRL_2: 718 718 + case MADERA_TONE_GENERATOR_1 ... MADERA_TONE_GENERATOR_5: 719 719 + case MADERA_PWM_DRIVE_1 ... MADERA_PWM_DRIVE_3: 720 720 + case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_1: 721 721 + case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_2: 722 722 + case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_3: 723 723 + case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_4: 724 724 + case MADERA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1: 725 725 + case MADERA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2: 726 726 + case MADERA_HAPTICS_CONTROL_1 ... MADERA_HAPTICS_CONTROL_2: 727 727 + case MADERA_HAPTICS_PHASE_1_INTENSITY: 728 728 + case MADERA_HAPTICS_PHASE_1_DURATION: 729 729 + case MADERA_HAPTICS_PHASE_2_INTENSITY: 730 730 + case MADERA_HAPTICS_PHASE_2_DURATION: 731 731 + case MADERA_HAPTICS_PHASE_3_INTENSITY: 732 732 + case MADERA_HAPTICS_PHASE_3_DURATION: 733 733 + case MADERA_HAPTICS_STATUS: 734 734 + case MADERA_COMFORT_NOISE_GENERATOR: 735 735 + case MADERA_CLOCK_32K_1: 736 736 + case MADERA_SYSTEM_CLOCK_1: 737 737 + case MADERA_SAMPLE_RATE_1 ... MADERA_SAMPLE_RATE_3: 738 738 + case MADERA_SAMPLE_RATE_1_STATUS: 739 739 + case MADERA_SAMPLE_RATE_2_STATUS: 740 740 + case MADERA_SAMPLE_RATE_3_STATUS: 741 741 + case MADERA_DSP_CLOCK_1: 742 742 + case MADERA_DSP_CLOCK_2: 743 743 + case MADERA_OUTPUT_SYSTEM_CLOCK: 744 744 + case MADERA_RATE_ESTIMATOR_1 ... MADERA_RATE_ESTIMATOR_5: 745 745 + case MADERA_FLL1_CONTROL_1 ... MADERA_FLL1_CONTROL_6: 746 746 + case MADERA_FLL1_CONTROL_7: 747 747 + case MADERA_FLL1_EFS_2: 748 748 + case MADERA_FLL1_SYNCHRONISER_1 ... MADERA_FLL1_SYNCHRONISER_7: 749 749 + case MADERA_FLL1_SPREAD_SPECTRUM: 750 750 + case MADERA_FLL1_GPIO_CLOCK: 751 751 + case MADERA_FLLAO_CONTROL_1: 752 752 + case MADERA_FLLAO_CONTROL_2: 753 753 + case MADERA_FLLAO_CONTROL_3: 754 754 + case MADERA_FLLAO_CONTROL_4: 755 755 + case MADERA_FLLAO_CONTROL_5: 756 756 + case MADERA_FLLAO_CONTROL_6: 757 757 + case MADERA_FLLAO_CONTROL_7: 758 758 + case MADERA_FLLAO_CONTROL_8: 759 759 + case MADERA_FLLAO_CONTROL_9: 760 760 + case MADERA_FLLAO_CONTROL_10: 761 761 + case MADERA_FLLAO_CONTROL_11: 762 762 + case MADERA_MIC_BIAS_CTRL_1: 763 763 + case MADERA_MIC_BIAS_CTRL_5: 764 764 + case MADERA_HP_CTRL_1L: 765 765 + case MADERA_HP_CTRL_1R: 766 766 + case MADERA_ACCESSORY_DETECT_MODE_1: 767 767 + case MADERA_HEADPHONE_DETECT_0: 768 768 + case MADERA_HEADPHONE_DETECT_1: 769 769 + case MADERA_HEADPHONE_DETECT_2: 770 770 + case MADERA_HEADPHONE_DETECT_3: 771 771 + case MADERA_HEADPHONE_DETECT_5: 772 772 + case MADERA_MICD_CLAMP_CONTROL: 773 773 + case MADERA_MIC_DETECT_1_CONTROL_0: 774 774 + case MADERA_MIC_DETECT_1_CONTROL_1: 775 775 + case MADERA_MIC_DETECT_1_CONTROL_2: 776 776 + case MADERA_MIC_DETECT_1_CONTROL_3: 777 777 + case MADERA_MIC_DETECT_1_LEVEL_1 ... MADERA_MIC_DETECT_1_LEVEL_4: 778 778 + case MADERA_MIC_DETECT_1_CONTROL_4: 779 779 + case MADERA_GP_SWITCH_1: 780 780 + case MADERA_JACK_DETECT_ANALOGUE: 781 781 + case MADERA_INPUT_ENABLES: 782 782 + case MADERA_INPUT_ENABLES_STATUS: 783 783 + case MADERA_INPUT_RATE: 784 784 + case MADERA_INPUT_VOLUME_RAMP: 785 785 + case MADERA_HPF_CONTROL: 786 786 + case MADERA_IN1L_CONTROL: 787 787 + case MADERA_ADC_DIGITAL_VOLUME_1L: 788 788 + case MADERA_DMIC1L_CONTROL: 789 789 + case MADERA_IN1L_RATE_CONTROL: 790 790 + case MADERA_IN1R_CONTROL: 791 791 + case MADERA_ADC_DIGITAL_VOLUME_1R: 792 792 + case MADERA_DMIC1R_CONTROL: 793 793 + case MADERA_IN1R_RATE_CONTROL: 794 794 + case MADERA_IN2L_CONTROL: 795 795 + case MADERA_ADC_DIGITAL_VOLUME_2L: 796 796 + case MADERA_DMIC2L_CONTROL: 797 797 + case MADERA_IN2L_RATE_CONTROL: 798 798 + case MADERA_IN2R_CONTROL: 799 799 + case MADERA_ADC_DIGITAL_VOLUME_2R: 800 800 + case MADERA_DMIC2R_CONTROL: 801 801 + case MADERA_IN2R_RATE_CONTROL: 802 802 + case CS47L15_ADC_INT_BIAS: 803 803 + case CS47L15_PGA_BIAS_SEL: 804 804 + case MADERA_OUTPUT_ENABLES_1: 805 805 + case MADERA_OUTPUT_STATUS_1: 806 806 + case MADERA_RAW_OUTPUT_STATUS_1: 807 807 + case MADERA_OUTPUT_RATE_1: 808 808 + case MADERA_OUTPUT_VOLUME_RAMP: 809 809 + case MADERA_OUTPUT_PATH_CONFIG_1L: 810 810 + case MADERA_DAC_DIGITAL_VOLUME_1L: 811 811 + case MADERA_OUTPUT_PATH_CONFIG_1: 812 812 + case MADERA_NOISE_GATE_SELECT_1L: 813 813 + case MADERA_OUTPUT_PATH_CONFIG_1R: 814 814 + case MADERA_DAC_DIGITAL_VOLUME_1R: 815 815 + case MADERA_NOISE_GATE_SELECT_1R: 816 816 + case MADERA_OUTPUT_PATH_CONFIG_2: 817 817 + case MADERA_OUTPUT_PATH_CONFIG_4L: 818 818 + case MADERA_DAC_DIGITAL_VOLUME_4L: 819 819 + case MADERA_NOISE_GATE_SELECT_4L: 820 820 + case MADERA_OUTPUT_PATH_CONFIG_5L: 821 821 + case MADERA_DAC_DIGITAL_VOLUME_5L: 822 822 + case MADERA_NOISE_GATE_SELECT_5L: 823 823 + case MADERA_OUTPUT_PATH_CONFIG_5R: 824 824 + case MADERA_DAC_DIGITAL_VOLUME_5R: 825 825 + case MADERA_NOISE_GATE_SELECT_5R: 826 826 + case MADERA_DAC_AEC_CONTROL_1: 827 827 + case MADERA_DAC_AEC_CONTROL_2: 828 828 + case MADERA_NOISE_GATE_CONTROL: 829 829 + case MADERA_PDM_SPK1_CTRL_1 ... MADERA_PDM_SPK1_CTRL_2: 830 830 + case MADERA_HP1_SHORT_CIRCUIT_CTRL: 831 831 + case MADERA_HP_TEST_CTRL_5: 832 832 + case MADERA_HP_TEST_CTRL_6: 833 833 + case MADERA_AIF1_BCLK_CTRL: 834 834 + case MADERA_AIF1_TX_PIN_CTRL: 835 835 + case MADERA_AIF1_RX_PIN_CTRL: 836 836 + case MADERA_AIF1_RATE_CTRL: 837 837 + case MADERA_AIF1_FORMAT: 838 838 + case MADERA_AIF1_RX_BCLK_RATE: 839 839 + case MADERA_AIF1_FRAME_CTRL_1 ... MADERA_AIF1_FRAME_CTRL_8: 840 840 + case MADERA_AIF1_FRAME_CTRL_11 ... MADERA_AIF1_FRAME_CTRL_16: 841 841 + case MADERA_AIF1_TX_ENABLES: 842 842 + case MADERA_AIF1_RX_ENABLES: 843 843 + case MADERA_AIF2_BCLK_CTRL: 844 844 + case MADERA_AIF2_TX_PIN_CTRL: 845 845 + case MADERA_AIF2_RX_PIN_CTRL: 846 846 + case MADERA_AIF2_RATE_CTRL: 847 847 + case MADERA_AIF2_FORMAT: 848 848 + case MADERA_AIF2_RX_BCLK_RATE: 849 849 + case MADERA_AIF2_FRAME_CTRL_1 ... MADERA_AIF2_FRAME_CTRL_6: 850 850 + case MADERA_AIF2_FRAME_CTRL_11 ... MADERA_AIF2_FRAME_CTRL_14: 851 851 + case MADERA_AIF2_TX_ENABLES: 852 852 + case MADERA_AIF2_RX_ENABLES: 853 853 + case MADERA_AIF3_BCLK_CTRL: 854 854 + case MADERA_AIF3_TX_PIN_CTRL: 855 855 + case MADERA_AIF3_RX_PIN_CTRL: 856 856 + case MADERA_AIF3_RATE_CTRL: 857 857 + case MADERA_AIF3_FORMAT: 858 858 + case MADERA_AIF3_RX_BCLK_RATE: 859 859 + case MADERA_AIF3_FRAME_CTRL_1 ... MADERA_AIF3_FRAME_CTRL_4: 860 860 + case MADERA_AIF3_FRAME_CTRL_11 ... MADERA_AIF3_FRAME_CTRL_12: 861 861 + case MADERA_AIF3_TX_ENABLES: 862 862 + case MADERA_AIF3_RX_ENABLES: 863 863 + case MADERA_SPD1_TX_CONTROL: 864 864 + case MADERA_SPD1_TX_CHANNEL_STATUS_1: 865 865 + case MADERA_SPD1_TX_CHANNEL_STATUS_2: 866 866 + case MADERA_SPD1_TX_CHANNEL_STATUS_3: 867 867 + case MADERA_PWM1MIX_INPUT_1_SOURCE: 868 868 + case MADERA_PWM1MIX_INPUT_1_VOLUME: 869 869 + case MADERA_PWM1MIX_INPUT_2_SOURCE: 870 870 + case MADERA_PWM1MIX_INPUT_2_VOLUME: 871 871 + case MADERA_PWM1MIX_INPUT_3_SOURCE: 872 872 + case MADERA_PWM1MIX_INPUT_3_VOLUME: 873 873 + case MADERA_PWM1MIX_INPUT_4_SOURCE: 874 874 + case MADERA_PWM1MIX_INPUT_4_VOLUME: 875 875 + case MADERA_PWM2MIX_INPUT_1_SOURCE: 876 876 + case MADERA_PWM2MIX_INPUT_1_VOLUME: 877 877 + case MADERA_PWM2MIX_INPUT_2_SOURCE: 878 878 + case MADERA_PWM2MIX_INPUT_2_VOLUME: 879 879 + case MADERA_PWM2MIX_INPUT_3_SOURCE: 880 880 + case MADERA_PWM2MIX_INPUT_3_VOLUME: 881 881 + case MADERA_PWM2MIX_INPUT_4_SOURCE: 882 882 + case MADERA_PWM2MIX_INPUT_4_VOLUME: 883 883 + case MADERA_OUT1LMIX_INPUT_1_SOURCE: 884 884 + case MADERA_OUT1LMIX_INPUT_1_VOLUME: 885 885 + case MADERA_OUT1LMIX_INPUT_2_SOURCE: 886 886 + case MADERA_OUT1LMIX_INPUT_2_VOLUME: 887 887 + case MADERA_OUT1LMIX_INPUT_3_SOURCE: 888 888 + case MADERA_OUT1LMIX_INPUT_3_VOLUME: 889 889 + case MADERA_OUT1LMIX_INPUT_4_SOURCE: 890 890 + case MADERA_OUT1LMIX_INPUT_4_VOLUME: 891 891 + case MADERA_OUT1RMIX_INPUT_1_SOURCE: 892 892 + case MADERA_OUT1RMIX_INPUT_1_VOLUME: 893 893 + case MADERA_OUT1RMIX_INPUT_2_SOURCE: 894 894 + case MADERA_OUT1RMIX_INPUT_2_VOLUME: 895 895 + case MADERA_OUT1RMIX_INPUT_3_SOURCE: 896 896 + case MADERA_OUT1RMIX_INPUT_3_VOLUME: 897 897 + case MADERA_OUT1RMIX_INPUT_4_SOURCE: 898 898 + case MADERA_OUT1RMIX_INPUT_4_VOLUME: 899 899 + case MADERA_OUT4LMIX_INPUT_1_SOURCE: 900 900 + case MADERA_OUT4LMIX_INPUT_1_VOLUME: 901 901 + case MADERA_OUT4LMIX_INPUT_2_SOURCE: 902 902 + case MADERA_OUT4LMIX_INPUT_2_VOLUME: 903 903 + case MADERA_OUT4LMIX_INPUT_3_SOURCE: 904 904 + case MADERA_OUT4LMIX_INPUT_3_VOLUME: 905 905 + case MADERA_OUT4LMIX_INPUT_4_SOURCE: 906 906 + case MADERA_OUT4LMIX_INPUT_4_VOLUME: 907 907 + case MADERA_OUT5LMIX_INPUT_1_SOURCE: 908 908 + case MADERA_OUT5LMIX_INPUT_1_VOLUME: 909 909 + case MADERA_OUT5LMIX_INPUT_2_SOURCE: 910 910 + case MADERA_OUT5LMIX_INPUT_2_VOLUME: 911 911 + case MADERA_OUT5LMIX_INPUT_3_SOURCE: 912 912 + case MADERA_OUT5LMIX_INPUT_3_VOLUME: 913 913 + case MADERA_OUT5LMIX_INPUT_4_SOURCE: 914 914 + case MADERA_OUT5LMIX_INPUT_4_VOLUME: 915 915 + case MADERA_OUT5RMIX_INPUT_1_SOURCE: 916 916 + case MADERA_OUT5RMIX_INPUT_1_VOLUME: 917 917 + case MADERA_OUT5RMIX_INPUT_2_SOURCE: 918 918 + case MADERA_OUT5RMIX_INPUT_2_VOLUME: 919 919 + case MADERA_OUT5RMIX_INPUT_3_SOURCE: 920 920 + case MADERA_OUT5RMIX_INPUT_3_VOLUME: 921 921 + case MADERA_OUT5RMIX_INPUT_4_SOURCE: 922 922 + case MADERA_OUT5RMIX_INPUT_4_VOLUME: 923 923 + case MADERA_AIF1TX1MIX_INPUT_1_SOURCE: 924 924 + case MADERA_AIF1TX1MIX_INPUT_1_VOLUME: 925 925 + case MADERA_AIF1TX1MIX_INPUT_2_SOURCE: 926 926 + case MADERA_AIF1TX1MIX_INPUT_2_VOLUME: 927 927 + case MADERA_AIF1TX1MIX_INPUT_3_SOURCE: 928 928 + case MADERA_AIF1TX1MIX_INPUT_3_VOLUME: 929 929 + case MADERA_AIF1TX1MIX_INPUT_4_SOURCE: 930 930 + case MADERA_AIF1TX1MIX_INPUT_4_VOLUME: 931 931 + case MADERA_AIF1TX2MIX_INPUT_1_SOURCE: 932 932 + case MADERA_AIF1TX2MIX_INPUT_1_VOLUME: 933 933 + case MADERA_AIF1TX2MIX_INPUT_2_SOURCE: 934 934 + case MADERA_AIF1TX2MIX_INPUT_2_VOLUME: 935 935 + case MADERA_AIF1TX2MIX_INPUT_3_SOURCE: 936 936 + case MADERA_AIF1TX2MIX_INPUT_3_VOLUME: 937 937 + case MADERA_AIF1TX2MIX_INPUT_4_SOURCE: 938 938 + case MADERA_AIF1TX2MIX_INPUT_4_VOLUME: 939 939 + case MADERA_AIF1TX3MIX_INPUT_1_SOURCE: 940 940 + case MADERA_AIF1TX3MIX_INPUT_1_VOLUME: 941 941 + case MADERA_AIF1TX3MIX_INPUT_2_SOURCE: 942 942 + case MADERA_AIF1TX3MIX_INPUT_2_VOLUME: 943 943 + case MADERA_AIF1TX3MIX_INPUT_3_SOURCE: 944 944 + case MADERA_AIF1TX3MIX_INPUT_3_VOLUME: 945 945 + case MADERA_AIF1TX3MIX_INPUT_4_SOURCE: 946 946 + case MADERA_AIF1TX3MIX_INPUT_4_VOLUME: 947 947 + case MADERA_AIF1TX4MIX_INPUT_1_SOURCE: 948 948 + case MADERA_AIF1TX4MIX_INPUT_1_VOLUME: 949 949 + case MADERA_AIF1TX4MIX_INPUT_2_SOURCE: 950 950 + case MADERA_AIF1TX4MIX_INPUT_2_VOLUME: 951 951 + case MADERA_AIF1TX4MIX_INPUT_3_SOURCE: 952 952 + case MADERA_AIF1TX4MIX_INPUT_3_VOLUME: 953 953 + case MADERA_AIF1TX4MIX_INPUT_4_SOURCE: 954 954 + case MADERA_AIF1TX4MIX_INPUT_4_VOLUME: 955 955 + case MADERA_AIF1TX5MIX_INPUT_1_SOURCE: 956 956 + case MADERA_AIF1TX5MIX_INPUT_1_VOLUME: 957 957 + case MADERA_AIF1TX5MIX_INPUT_2_SOURCE: 958 958 + case MADERA_AIF1TX5MIX_INPUT_2_VOLUME: 959 959 + case MADERA_AIF1TX5MIX_INPUT_3_SOURCE: 960 960 + case MADERA_AIF1TX5MIX_INPUT_3_VOLUME: 961 961 + case MADERA_AIF1TX5MIX_INPUT_4_SOURCE: 962 962 + case MADERA_AIF1TX5MIX_INPUT_4_VOLUME: 963 963 + case MADERA_AIF1TX6MIX_INPUT_1_SOURCE: 964 964 + case MADERA_AIF1TX6MIX_INPUT_1_VOLUME: 965 965 + case MADERA_AIF1TX6MIX_INPUT_2_SOURCE: 966 966 + case MADERA_AIF1TX6MIX_INPUT_2_VOLUME: 967 967 + case MADERA_AIF1TX6MIX_INPUT_3_SOURCE: 968 968 + case MADERA_AIF1TX6MIX_INPUT_3_VOLUME: 969 969 + case MADERA_AIF1TX6MIX_INPUT_4_SOURCE: 970 970 + case MADERA_AIF1TX6MIX_INPUT_4_VOLUME: 971 971 + case MADERA_AIF2TX1MIX_INPUT_1_SOURCE: 972 972 + case MADERA_AIF2TX1MIX_INPUT_1_VOLUME: 973 973 + case MADERA_AIF2TX1MIX_INPUT_2_SOURCE: 974 974 + case MADERA_AIF2TX1MIX_INPUT_2_VOLUME: 975 975 + case MADERA_AIF2TX1MIX_INPUT_3_SOURCE: 976 976 + case MADERA_AIF2TX1MIX_INPUT_3_VOLUME: 977 977 + case MADERA_AIF2TX1MIX_INPUT_4_SOURCE: 978 978 + case MADERA_AIF2TX1MIX_INPUT_4_VOLUME: 979 979 + case MADERA_AIF2TX2MIX_INPUT_1_SOURCE: 980 980 + case MADERA_AIF2TX2MIX_INPUT_1_VOLUME: 981 981 + case MADERA_AIF2TX2MIX_INPUT_2_SOURCE: 982 982 + case MADERA_AIF2TX2MIX_INPUT_2_VOLUME: 983 983 + case MADERA_AIF2TX2MIX_INPUT_3_SOURCE: 984 984 + case MADERA_AIF2TX2MIX_INPUT_3_VOLUME: 985 985 + case MADERA_AIF2TX2MIX_INPUT_4_SOURCE: 986 986 + case MADERA_AIF2TX2MIX_INPUT_4_VOLUME: 987 987 + case MADERA_AIF2TX3MIX_INPUT_1_SOURCE: 988 988 + case MADERA_AIF2TX3MIX_INPUT_1_VOLUME: 989 989 + case MADERA_AIF2TX3MIX_INPUT_2_SOURCE: 990 990 + case MADERA_AIF2TX3MIX_INPUT_2_VOLUME: 991 991 + case MADERA_AIF2TX3MIX_INPUT_3_SOURCE: 992 992 + case MADERA_AIF2TX3MIX_INPUT_3_VOLUME: 993 993 + case MADERA_AIF2TX3MIX_INPUT_4_SOURCE: 994 994 + case MADERA_AIF2TX3MIX_INPUT_4_VOLUME: 995 995 + case MADERA_AIF2TX4MIX_INPUT_1_SOURCE: 996 996 + case MADERA_AIF2TX4MIX_INPUT_1_VOLUME: 997 997 + case MADERA_AIF2TX4MIX_INPUT_2_SOURCE: 998 998 + case MADERA_AIF2TX4MIX_INPUT_2_VOLUME: 999 999 + case MADERA_AIF2TX4MIX_INPUT_3_SOURCE: 1000 1000 + case MADERA_AIF2TX4MIX_INPUT_3_VOLUME: 1001 1001 + case MADERA_AIF2TX4MIX_INPUT_4_SOURCE: 1002 1002 + case MADERA_AIF2TX4MIX_INPUT_4_VOLUME: 1003 1003 + case MADERA_AIF3TX1MIX_INPUT_1_SOURCE: 1004 1004 + case MADERA_AIF3TX1MIX_INPUT_1_VOLUME: 1005 1005 + case MADERA_AIF3TX1MIX_INPUT_2_SOURCE: 1006 1006 + case MADERA_AIF3TX1MIX_INPUT_2_VOLUME: 1007 1007 + case MADERA_AIF3TX1MIX_INPUT_3_SOURCE: 1008 1008 + case MADERA_AIF3TX1MIX_INPUT_3_VOLUME: 1009 1009 + case MADERA_AIF3TX1MIX_INPUT_4_SOURCE: 1010 1010 + case MADERA_AIF3TX1MIX_INPUT_4_VOLUME: 1011 1011 + case MADERA_AIF3TX2MIX_INPUT_1_SOURCE: 1012 1012 + case MADERA_AIF3TX2MIX_INPUT_1_VOLUME: 1013 1013 + case MADERA_AIF3TX2MIX_INPUT_2_SOURCE: 1014 1014 + case MADERA_AIF3TX2MIX_INPUT_2_VOLUME: 1015 1015 + case MADERA_AIF3TX2MIX_INPUT_3_SOURCE: 1016 1016 + case MADERA_AIF3TX2MIX_INPUT_3_VOLUME: 1017 1017 + case MADERA_AIF3TX2MIX_INPUT_4_SOURCE: 1018 1018 + case MADERA_AIF3TX2MIX_INPUT_4_VOLUME: 1019 1019 + case MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE: 1020 1020 + case MADERA_SPDIF1TX1MIX_INPUT_1_VOLUME: 1021 1021 + case MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE: 1022 1022 + case MADERA_SPDIF1TX2MIX_INPUT_1_VOLUME: 1023 1023 + case MADERA_EQ1MIX_INPUT_1_SOURCE: 1024 1024 + case MADERA_EQ1MIX_INPUT_1_VOLUME: 1025 1025 + case MADERA_EQ1MIX_INPUT_2_SOURCE: 1026 1026 + case MADERA_EQ1MIX_INPUT_2_VOLUME: 1027 1027 + case MADERA_EQ1MIX_INPUT_3_SOURCE: 1028 1028 + case MADERA_EQ1MIX_INPUT_3_VOLUME: 1029 1029 + case MADERA_EQ1MIX_INPUT_4_SOURCE: 1030 1030 + case MADERA_EQ1MIX_INPUT_4_VOLUME: 1031 1031 + case MADERA_EQ2MIX_INPUT_1_SOURCE: 1032 1032 + case MADERA_EQ2MIX_INPUT_1_VOLUME: 1033 1033 + case MADERA_EQ2MIX_INPUT_2_SOURCE: 1034 1034 + case MADERA_EQ2MIX_INPUT_2_VOLUME: 1035 1035 + case MADERA_EQ2MIX_INPUT_3_SOURCE: 1036 1036 + case MADERA_EQ2MIX_INPUT_3_VOLUME: 1037 1037 + case MADERA_EQ2MIX_INPUT_4_SOURCE: 1038 1038 + case MADERA_EQ2MIX_INPUT_4_VOLUME: 1039 1039 + case MADERA_EQ3MIX_INPUT_1_SOURCE: 1040 1040 + case MADERA_EQ3MIX_INPUT_1_VOLUME: 1041 1041 + case MADERA_EQ3MIX_INPUT_2_SOURCE: 1042 1042 + case MADERA_EQ3MIX_INPUT_2_VOLUME: 1043 1043 + case MADERA_EQ3MIX_INPUT_3_SOURCE: 1044 1044 + case MADERA_EQ3MIX_INPUT_3_VOLUME: 1045 1045 + case MADERA_EQ3MIX_INPUT_4_SOURCE: 1046 1046 + case MADERA_EQ3MIX_INPUT_4_VOLUME: 1047 1047 + case MADERA_EQ4MIX_INPUT_1_SOURCE: 1048 1048 + case MADERA_EQ4MIX_INPUT_1_VOLUME: 1049 1049 + case MADERA_EQ4MIX_INPUT_2_SOURCE: 1050 1050 + case MADERA_EQ4MIX_INPUT_2_VOLUME: 1051 1051 + case MADERA_EQ4MIX_INPUT_3_SOURCE: 1052 1052 + case MADERA_EQ4MIX_INPUT_3_VOLUME: 1053 1053 + case MADERA_EQ4MIX_INPUT_4_SOURCE: 1054 1054 + case MADERA_EQ4MIX_INPUT_4_VOLUME: 1055 1055 + case MADERA_DRC1LMIX_INPUT_1_SOURCE: 1056 1056 + case MADERA_DRC1LMIX_INPUT_1_VOLUME: 1057 1057 + case MADERA_DRC1LMIX_INPUT_2_SOURCE: 1058 1058 + case MADERA_DRC1LMIX_INPUT_2_VOLUME: 1059 1059 + case MADERA_DRC1LMIX_INPUT_3_SOURCE: 1060 1060 + case MADERA_DRC1LMIX_INPUT_3_VOLUME: 1061 1061 + case MADERA_DRC1LMIX_INPUT_4_SOURCE: 1062 1062 + case MADERA_DRC1LMIX_INPUT_4_VOLUME: 1063 1063 + case MADERA_DRC1RMIX_INPUT_1_SOURCE: 1064 1064 + case MADERA_DRC1RMIX_INPUT_1_VOLUME: 1065 1065 + case MADERA_DRC1RMIX_INPUT_2_SOURCE: 1066 1066 + case MADERA_DRC1RMIX_INPUT_2_VOLUME: 1067 1067 + case MADERA_DRC1RMIX_INPUT_3_SOURCE: 1068 1068 + case MADERA_DRC1RMIX_INPUT_3_VOLUME: 1069 1069 + case MADERA_DRC1RMIX_INPUT_4_SOURCE: 1070 1070 + case MADERA_DRC1RMIX_INPUT_4_VOLUME: 1071 1071 + case MADERA_DRC2LMIX_INPUT_1_SOURCE: 1072 1072 + case MADERA_DRC2LMIX_INPUT_1_VOLUME: 1073 1073 + case MADERA_DRC2LMIX_INPUT_2_SOURCE: 1074 1074 + case MADERA_DRC2LMIX_INPUT_2_VOLUME: 1075 1075 + case MADERA_DRC2LMIX_INPUT_3_SOURCE: 1076 1076 + case MADERA_DRC2LMIX_INPUT_3_VOLUME: 1077 1077 + case MADERA_DRC2LMIX_INPUT_4_SOURCE: 1078 1078 + case MADERA_DRC2LMIX_INPUT_4_VOLUME: 1079 1079 + case MADERA_DRC2RMIX_INPUT_1_SOURCE: 1080 1080 + case MADERA_DRC2RMIX_INPUT_1_VOLUME: 1081 1081 + case MADERA_DRC2RMIX_INPUT_2_SOURCE: 1082 1082 + case MADERA_DRC2RMIX_INPUT_2_VOLUME: 1083 1083 + case MADERA_DRC2RMIX_INPUT_3_SOURCE: 1084 1084 + case MADERA_DRC2RMIX_INPUT_3_VOLUME: 1085 1085 + case MADERA_DRC2RMIX_INPUT_4_SOURCE: 1086 1086 + case MADERA_DRC2RMIX_INPUT_4_VOLUME: 1087 1087 + case MADERA_HPLP1MIX_INPUT_1_SOURCE: 1088 1088 + case MADERA_HPLP1MIX_INPUT_1_VOLUME: 1089 1089 + case MADERA_HPLP1MIX_INPUT_2_SOURCE: 1090 1090 + case MADERA_HPLP1MIX_INPUT_2_VOLUME: 1091 1091 + case MADERA_HPLP1MIX_INPUT_3_SOURCE: 1092 1092 + case MADERA_HPLP1MIX_INPUT_3_VOLUME: 1093 1093 + case MADERA_HPLP1MIX_INPUT_4_SOURCE: 1094 1094 + case MADERA_HPLP1MIX_INPUT_4_VOLUME: 1095 1095 + case MADERA_HPLP2MIX_INPUT_1_SOURCE: 1096 1096 + case MADERA_HPLP2MIX_INPUT_1_VOLUME: 1097 1097 + case MADERA_HPLP2MIX_INPUT_2_SOURCE: 1098 1098 + case MADERA_HPLP2MIX_INPUT_2_VOLUME: 1099 1099 + case MADERA_HPLP2MIX_INPUT_3_SOURCE: 1100 1100 + case MADERA_HPLP2MIX_INPUT_3_VOLUME: 1101 1101 + case MADERA_HPLP2MIX_INPUT_4_SOURCE: 1102 1102 + case MADERA_HPLP2MIX_INPUT_4_VOLUME: 1103 1103 + case MADERA_HPLP3MIX_INPUT_1_SOURCE: 1104 1104 + case MADERA_HPLP3MIX_INPUT_1_VOLUME: 1105 1105 + case MADERA_HPLP3MIX_INPUT_2_SOURCE: 1106 1106 + case MADERA_HPLP3MIX_INPUT_2_VOLUME: 1107 1107 + case MADERA_HPLP3MIX_INPUT_3_SOURCE: 1108 1108 + case MADERA_HPLP3MIX_INPUT_3_VOLUME: 1109 1109 + case MADERA_HPLP3MIX_INPUT_4_SOURCE: 1110 1110 + case MADERA_HPLP3MIX_INPUT_4_VOLUME: 1111 1111 + case MADERA_HPLP4MIX_INPUT_1_SOURCE: 1112 1112 + case MADERA_HPLP4MIX_INPUT_1_VOLUME: 1113 1113 + case MADERA_HPLP4MIX_INPUT_2_SOURCE: 1114 1114 + case MADERA_HPLP4MIX_INPUT_2_VOLUME: 1115 1115 + case MADERA_HPLP4MIX_INPUT_3_SOURCE: 1116 1116 + case MADERA_HPLP4MIX_INPUT_3_VOLUME: 1117 1117 + case MADERA_HPLP4MIX_INPUT_4_SOURCE: 1118 1118 + case MADERA_HPLP4MIX_INPUT_4_VOLUME: 1119 1119 + case MADERA_DSP1LMIX_INPUT_1_SOURCE: 1120 1120 + case MADERA_DSP1LMIX_INPUT_1_VOLUME: 1121 1121 + case MADERA_DSP1LMIX_INPUT_2_SOURCE: 1122 1122 + case MADERA_DSP1LMIX_INPUT_2_VOLUME: 1123 1123 + case MADERA_DSP1LMIX_INPUT_3_SOURCE: 1124 1124 + case MADERA_DSP1LMIX_INPUT_3_VOLUME: 1125 1125 + case MADERA_DSP1LMIX_INPUT_4_SOURCE: 1126 1126 + case MADERA_DSP1LMIX_INPUT_4_VOLUME: 1127 1127 + case MADERA_DSP1RMIX_INPUT_1_SOURCE: 1128 1128 + case MADERA_DSP1RMIX_INPUT_1_VOLUME: 1129 1129 + case MADERA_DSP1RMIX_INPUT_2_SOURCE: 1130 1130 + case MADERA_DSP1RMIX_INPUT_2_VOLUME: 1131 1131 + case MADERA_DSP1RMIX_INPUT_3_SOURCE: 1132 1132 + case MADERA_DSP1RMIX_INPUT_3_VOLUME: 1133 1133 + case MADERA_DSP1RMIX_INPUT_4_SOURCE: 1134 1134 + case MADERA_DSP1RMIX_INPUT_4_VOLUME: 1135 1135 + case MADERA_DSP1AUX1MIX_INPUT_1_SOURCE: 1136 1136 + case MADERA_DSP1AUX2MIX_INPUT_1_SOURCE: 1137 1137 + case MADERA_DSP1AUX3MIX_INPUT_1_SOURCE: 1138 1138 + case MADERA_DSP1AUX4MIX_INPUT_1_SOURCE: 1139 1139 + case MADERA_DSP1AUX5MIX_INPUT_1_SOURCE: 1140 1140 + case MADERA_DSP1AUX6MIX_INPUT_1_SOURCE: 1141 1141 + case MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE: 1142 1142 + case MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE: 1143 1143 + case MADERA_ISRC1DEC3MIX_INPUT_1_SOURCE: 1144 1144 + case MADERA_ISRC1DEC4MIX_INPUT_1_SOURCE: 1145 1145 + case MADERA_ISRC1INT1MIX_INPUT_1_SOURCE: 1146 1146 + case MADERA_ISRC1INT2MIX_INPUT_1_SOURCE: 1147 1147 + case MADERA_ISRC1INT3MIX_INPUT_1_SOURCE: 1148 1148 + case MADERA_ISRC1INT4MIX_INPUT_1_SOURCE: 1149 1149 + case MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE: 1150 1150 + case MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE: 1151 1151 + case MADERA_ISRC2DEC3MIX_INPUT_1_SOURCE: 1152 1152 + case MADERA_ISRC2DEC4MIX_INPUT_1_SOURCE: 1153 1153 + case MADERA_ISRC2INT1MIX_INPUT_1_SOURCE: 1154 1154 + case MADERA_ISRC2INT2MIX_INPUT_1_SOURCE: 1155 1155 + case MADERA_ISRC2INT3MIX_INPUT_1_SOURCE: 1156 1156 + case MADERA_ISRC2INT4MIX_INPUT_1_SOURCE: 1157 1157 + case MADERA_FX_CTRL1 ... MADERA_FX_CTRL2: 1158 1158 + case MADERA_EQ1_1 ... MADERA_EQ1_21: 1159 1159 + case MADERA_EQ2_1 ... MADERA_EQ2_21: 1160 1160 + case MADERA_EQ3_1 ... MADERA_EQ3_21: 1161 1161 + case MADERA_EQ4_1 ... MADERA_EQ4_21: 1162 1162 + case MADERA_DRC1_CTRL1 ... MADERA_DRC1_CTRL5: 1163 1163 + case MADERA_DRC2_CTRL1 ... MADERA_DRC2_CTRL5: 1164 1164 + case MADERA_HPLPF1_1 ... MADERA_HPLPF1_2: 1165 1165 + case MADERA_HPLPF2_1 ... MADERA_HPLPF2_2: 1166 1166 + case MADERA_HPLPF3_1 ... MADERA_HPLPF3_2: 1167 1167 + case MADERA_HPLPF4_1 ... MADERA_HPLPF4_2: 1168 1168 + case MADERA_ISRC_1_CTRL_1 ... MADERA_ISRC_1_CTRL_3: 1169 1169 + case MADERA_ISRC_2_CTRL_1 ... MADERA_ISRC_2_CTRL_3: 1170 1170 + case MADERA_GPIO1_CTRL_1 ... MADERA_GPIO15_CTRL_2: 1171 1171 + case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33: 1172 1172 + case MADERA_IRQ1_MASK_1 ... MADERA_IRQ1_MASK_33: 1173 1173 + case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33: 1174 1174 + case MADERA_INTERRUPT_DEBOUNCE_7: 1175 1175 + case MADERA_IRQ1_CTRL: 1176 1176 + return true; 1177 1177 + default: 1178 1178 + return false; 1179 1179 + } 1180 1180 + } 1181 1181 + 1182 1182 + static bool cs47l15_16bit_volatile_register(struct device *dev, 1183 1183 + unsigned int reg) 1184 1184 + { 1185 1185 + switch (reg) { 1186 1186 + case MADERA_SOFTWARE_RESET: 1187 1187 + case MADERA_HARDWARE_REVISION: 1188 1188 + case MADERA_WRITE_SEQUENCER_CTRL_0 ... MADERA_WRITE_SEQUENCER_CTRL_2: 1189 1189 + case MADERA_HAPTICS_STATUS: 1190 1190 + case MADERA_SAMPLE_RATE_1_STATUS: 1191 1191 + case MADERA_SAMPLE_RATE_2_STATUS: 1192 1192 + case MADERA_SAMPLE_RATE_3_STATUS: 1193 1193 + case MADERA_HP_CTRL_1L: 1194 1194 + case MADERA_HP_CTRL_1R: 1195 1195 + case MADERA_MIC_DETECT_1_CONTROL_3: 1196 1196 + case MADERA_MIC_DETECT_1_CONTROL_4: 1197 1197 + case MADERA_HEADPHONE_DETECT_2: 1198 1198 + case MADERA_HEADPHONE_DETECT_3: 1199 1199 + case MADERA_HEADPHONE_DETECT_5: 1200 1200 + case MADERA_INPUT_ENABLES_STATUS: 1201 1201 + case MADERA_OUTPUT_STATUS_1: 1202 1202 + case MADERA_RAW_OUTPUT_STATUS_1: 1203 1203 + case MADERA_SPD1_TX_CHANNEL_STATUS_1: 1204 1204 + case MADERA_SPD1_TX_CHANNEL_STATUS_2: 1205 1205 + case MADERA_SPD1_TX_CHANNEL_STATUS_3: 1206 1206 + case MADERA_FX_CTRL2: 1207 1207 + case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33: 1208 1208 + case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33: 1209 1209 + return true; 1210 1210 + default: 1211 1211 + return false; 1212 1212 + } 1213 1213 + } 1214 1214 + 1215 1215 + static bool cs47l15_32bit_readable_register(struct device *dev, 1216 1216 + unsigned int reg) 1217 1217 + { 1218 1218 + switch (reg) { 1219 1219 + case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_225: 1220 1220 + case MADERA_OTP_HPDET_CAL_1 ... MADERA_OTP_HPDET_CAL_2: 1221 1221 + case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR: 1222 1222 + return true; 1223 1223 + default: 1224 1224 + return cs47l15_is_adsp_memory(dev, reg); 1225 1225 + } 1226 1226 + } 1227 1227 + 1228 1228 + static bool cs47l15_32bit_volatile_register(struct device *dev, 1229 1229 + unsigned int reg) 1230 1230 + { 1231 1231 + switch (reg) { 1232 1232 + case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_225: 1233 1233 + case MADERA_OTP_HPDET_CAL_1 ... MADERA_OTP_HPDET_CAL_2: 1234 1234 + case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR: 1235 1235 + return true; 1236 1236 + default: 1237 1237 + return cs47l15_is_adsp_memory(dev, reg); 1238 1238 + } 1239 1239 + } 1240 1240 + 1241 1241 + const struct regmap_config cs47l15_16bit_spi_regmap = { 1242 1242 + .name = "cs47l15_16bit", 1243 1243 + .reg_bits = 32, 1244 1244 + .pad_bits = 16, 1245 1245 + .val_bits = 16, 1246 1246 + 1247 1247 + .max_register = MADERA_INTERRUPT_RAW_STATUS_1, 1248 1248 + .readable_reg = &cs47l15_16bit_readable_register, 1249 1249 + .volatile_reg = &cs47l15_16bit_volatile_register, 1250 1250 + 1251 1251 + .cache_type = REGCACHE_RBTREE, 1252 1252 + .reg_defaults = cs47l15_reg_default, 1253 1253 + .num_reg_defaults = ARRAY_SIZE(cs47l15_reg_default), 1254 1254 + }; 1255 1255 + EXPORT_SYMBOL_GPL(cs47l15_16bit_spi_regmap); 1256 1256 + 1257 1257 + const struct regmap_config cs47l15_16bit_i2c_regmap = { 1258 1258 + .name = "cs47l15_16bit", 1259 1259 + .reg_bits = 32, 1260 1260 + .val_bits = 16, 1261 1261 + 1262 1262 + .max_register = MADERA_INTERRUPT_RAW_STATUS_1, 1263 1263 + .readable_reg = &cs47l15_16bit_readable_register, 1264 1264 + .volatile_reg = &cs47l15_16bit_volatile_register, 1265 1265 + 1266 1266 + .cache_type = REGCACHE_RBTREE, 1267 1267 + .reg_defaults = cs47l15_reg_default, 1268 1268 + .num_reg_defaults = ARRAY_SIZE(cs47l15_reg_default), 1269 1269 + }; 1270 1270 + EXPORT_SYMBOL_GPL(cs47l15_16bit_i2c_regmap); 1271 1271 + 1272 1272 + const struct regmap_config cs47l15_32bit_spi_regmap = { 1273 1273 + .name = "cs47l15_32bit", 1274 1274 + .reg_bits = 32, 1275 1275 + .reg_stride = 2, 1276 1276 + .pad_bits = 16, 1277 1277 + .val_bits = 32, 1278 1278 + 1279 1279 + .max_register = MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR, 1280 1280 + .readable_reg = &cs47l15_32bit_readable_register, 1281 1281 + .volatile_reg = &cs47l15_32bit_volatile_register, 1282 1282 + 1283 1283 + .cache_type = REGCACHE_RBTREE, 1284 1284 + }; 1285 1285 + EXPORT_SYMBOL_GPL(cs47l15_32bit_spi_regmap); 1286 1286 + 1287 1287 + const struct regmap_config cs47l15_32bit_i2c_regmap = { 1288 1288 + .name = "cs47l15_32bit", 1289 1289 + .reg_bits = 32, 1290 1290 + .reg_stride = 2, 1291 1291 + .val_bits = 32, 1292 1292 + 1293 1293 + .max_register = MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR, 1294 1294 + .readable_reg = &cs47l15_32bit_readable_register, 1295 1295 + .volatile_reg = &cs47l15_32bit_volatile_register, 1296 1296 + 1297 1297 + .cache_type = REGCACHE_RBTREE, 1298 1298 + }; 1299 1299 + EXPORT_SYMBOL_GPL(cs47l15_32bit_i2c_regmap);

+2 -58

drivers/mfd/cs47l35-tables.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 3 * Regmap tables for CS47L35 codec 4 4 * 5 5 * Copyright (C) 2015-2017 Cirrus Logic 6 6 - * 7 7 - * This program is free software; you can redistribute it and/or modify 8 8 - * it under the terms of the GNU General Public License as published by the 9 9 - * Free Software Foundation; version 2. 10 6 */ 11 7 12 8 #include <linux/device.h> ··· 105 109 { 0x00000174, 0x007d }, /* R372 (0x174) - FLL1 Control 4 */ 106 110 { 0x00000175, 0x0000 }, /* R373 (0x175) - FLL1 Control 5 */ 107 111 { 0x00000176, 0x0000 }, /* R374 (0x176) - FLL1 Control 6 */ 108 108 - { 0x00000177, 0x0281 }, /* R375 (0x177) - FLL1 Loop Filter Test 1 */ 109 112 { 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 7 */ 110 110 - { 0x0000017a, 0x0b06 }, /* R378 (0x17a) - FLL1 EFS2 */ 113 113 + { 0x0000017a, 0x2906 }, /* R378 (0x17a) - FLL1 EFS2 */ 111 114 { 0x0000017f, 0x0000 }, /* R383 (0x17f) - FLL1 Synchroniser 1 */ 112 115 { 0x00000180, 0x0000 }, /* R384 (0x180) - FLL1 Synchroniser 2 */ 113 116 { 0x00000181, 0x0000 }, /* R385 (0x181) - FLL1 Synchroniser 3 */ ··· 169 174 { 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */ 170 175 { 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */ 171 176 { 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */ 172 172 - { 0x00000440, 0x0003 }, /* R1088 (0x440) - DRE Enable */ 173 173 - { 0x00000448, 0x0a83 }, /* R1096 (0x448) - eDRE Enable */ 174 174 - { 0x0000044a, 0x0000 }, /* R1098 (0x44a) - eDRE Manual */ 175 177 { 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */ 176 178 { 0x00000451, 0x0000 }, /* R1105 (0x451) - DAC AEC Control 2 */ 177 179 { 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */ ··· 712 720 { 0x00000ef3, 0x0000 }, /* R3827 (0xef3) - ISRC 2 CTRL 1 */ 713 721 { 0x00000ef4, 0x0001 }, /* R3828 (0xef4) - ISRC 2 CTRL 2 */ 714 722 { 0x00000ef5, 0x0000 }, /* R3829 (0xef5) - ISRC 2 CTRL 3 */ 715 715 - { 0x00001300, 0x0000 }, /* R4864 (0x1300) - DAC Comp 1 */ 716 716 - { 0x00001302, 0x0000 }, /* R4866 (0x1302) - DAC Comp 2 */ 717 717 - { 0x00001380, 0x0000 }, /* R4992 (0x1380) - FRF Coefficient 1L 1 */ 718 718 - { 0x00001381, 0x0000 }, /* R4993 (0x1381) - FRF Coefficient 1L 2 */ 719 719 - { 0x00001382, 0x0000 }, /* R4994 (0x1382) - FRF Coefficient 1L 3 */ 720 720 - { 0x00001383, 0x0000 }, /* R4995 (0x1383) - FRF Coefficient 1L 4 */ 721 721 - { 0x00001390, 0x0000 }, /* R5008 (0x1390) - FRF Coefficient 1R 1 */ 722 722 - { 0x00001391, 0x0000 }, /* R5009 (0x1391) - FRF Coefficient 1R 2 */ 723 723 - { 0x00001392, 0x0000 }, /* R5010 (0x1392) - FRF Coefficient 1R 3 */ 724 724 - { 0x00001393, 0x0000 }, /* R5011 (0x1393) - FRF Coefficient 1R 4 */ 725 725 - { 0x000013a0, 0x0000 }, /* R5024 (0x13a0) - FRF Coefficient 4L 1 */ 726 726 - { 0x000013a1, 0x0000 }, /* R5025 (0x13a1) - FRF Coefficient 4L 2 */ 727 727 - { 0x000013a2, 0x0000 }, /* R5026 (0x13a2) - FRF Coefficient 4L 3 */ 728 728 - { 0x000013a3, 0x0000 }, /* R5027 (0x13a3) - FRF Coefficient 4L 4 */ 729 729 - { 0x000013b0, 0x0000 }, /* R5040 (0x13b0) - FRF Coefficient 5L 1 */ 730 730 - { 0x000013b1, 0x0000 }, /* R5041 (0x13b1) - FRF Coefficient 5L 2 */ 731 731 - { 0x000013b2, 0x0000 }, /* R5042 (0x13b2) - FRF Coefficient 5L 3 */ 732 732 - { 0x000013b3, 0x0000 }, /* R5043 (0x13b3) - FRF Coefficient 5L 4 */ 733 733 - { 0x000013c0, 0x0000 }, /* R5040 (0x13c0) - FRF Coefficient 5R 1 */ 734 734 - { 0x000013c1, 0x0000 }, /* R5041 (0x13c1) - FRF Coefficient 5R 2 */ 735 735 - { 0x000013c2, 0x0000 }, /* R5042 (0x13c2) - FRF Coefficient 5R 3 */ 736 736 - { 0x000013c3, 0x0000 }, /* R5043 (0x13c3) - FRF Coefficient 5R 4 */ 737 723 { 0x00001700, 0x2001 }, /* R5888 (0x1700) - GPIO1 Control 1 */ 738 724 { 0x00001701, 0xf000 }, /* R5889 (0x1701) - GPIO1 Control 2 */ 739 725 { 0x00001702, 0x2001 }, /* R5890 (0x1702) - GPIO2 Control 1 */ ··· 862 892 case MADERA_FLL1_CONTROL_6: 863 893 case MADERA_FLL1_CONTROL_7: 864 894 case MADERA_FLL1_EFS_2: 865 865 - case MADERA_FLL1_LOOP_FILTER_TEST_1: 866 895 case CS47L35_FLL1_SYNCHRONISER_1: 867 896 case CS47L35_FLL1_SYNCHRONISER_2: 868 897 case CS47L35_FLL1_SYNCHRONISER_3: ··· 936 967 case MADERA_OUTPUT_PATH_CONFIG_5R: 937 968 case MADERA_DAC_DIGITAL_VOLUME_5R: 938 969 case MADERA_NOISE_GATE_SELECT_5R: 939 939 - case MADERA_DRE_ENABLE: 940 940 - case MADERA_EDRE_ENABLE: 941 941 - case MADERA_EDRE_MANUAL: 942 970 case MADERA_DAC_AEC_CONTROL_1: 943 971 case MADERA_DAC_AEC_CONTROL_2: 944 972 case MADERA_NOISE_GATE_CONTROL: ··· 1405 1439 case MADERA_ISRC_2_CTRL_1: 1406 1440 case MADERA_ISRC_2_CTRL_2: 1407 1441 case MADERA_ISRC_2_CTRL_3: 1408 1408 - case MADERA_DAC_COMP_1: 1409 1409 - case MADERA_DAC_COMP_2: 1410 1410 - case MADERA_FRF_COEFFICIENT_1L_1: 1411 1411 - case MADERA_FRF_COEFFICIENT_1L_2: 1412 1412 - case MADERA_FRF_COEFFICIENT_1L_3: 1413 1413 - case MADERA_FRF_COEFFICIENT_1L_4: 1414 1414 - case MADERA_FRF_COEFFICIENT_1R_1: 1415 1415 - case MADERA_FRF_COEFFICIENT_1R_2: 1416 1416 - case MADERA_FRF_COEFFICIENT_1R_3: 1417 1417 - case MADERA_FRF_COEFFICIENT_1R_4: 1418 1418 - case CS47L35_FRF_COEFFICIENT_4L_1: 1419 1419 - case CS47L35_FRF_COEFFICIENT_4L_2: 1420 1420 - case CS47L35_FRF_COEFFICIENT_4L_3: 1421 1421 - case CS47L35_FRF_COEFFICIENT_4L_4: 1422 1422 - case CS47L35_FRF_COEFFICIENT_5L_1: 1423 1423 - case CS47L35_FRF_COEFFICIENT_5L_2: 1424 1424 - case CS47L35_FRF_COEFFICIENT_5L_3: 1425 1425 - case CS47L35_FRF_COEFFICIENT_5L_4: 1426 1426 - case CS47L35_FRF_COEFFICIENT_5R_1: 1427 1427 - case CS47L35_FRF_COEFFICIENT_5R_2: 1428 1428 - case CS47L35_FRF_COEFFICIENT_5R_3: 1429 1429 - case CS47L35_FRF_COEFFICIENT_5R_4: 1430 1442 case MADERA_GPIO1_CTRL_1 ... MADERA_GPIO16_CTRL_2: 1431 1443 case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33: 1432 1444 case MADERA_IRQ1_MASK_1 ... MADERA_IRQ1_MASK_33:

+6 -122

drivers/mfd/cs47l85-tables.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 3 * Regmap tables for CS47L85 codec 4 4 * 5 5 * Copyright (C) 2015-2017 Cirrus Logic 6 6 - * 7 7 - * This program is free software; you can redistribute it and/or modify 8 8 - * it under the terms of the GNU General Public License as published by the 9 9 - * Free Software Foundation; version 2. 10 6 */ 11 7 12 8 #include <linux/device.h> ··· 398 402 { 0x00000174, 0x007d }, /* R372 (0x174) - FLL1 Control 4 */ 399 403 { 0x00000175, 0x0000 }, /* R373 (0x175) - FLL1 Control 5 */ 400 404 { 0x00000176, 0x0000 }, /* R374 (0x176) - FLL1 Control 6 */ 401 401 - { 0x00000177, 0x0281 }, /* R375 (0x177) - FLL1 Loop Filter Test 1 */ 402 405 { 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 7 */ 403 406 { 0x00000181, 0x0000 }, /* R385 (0x181) - FLL1 Synchroniser 1 */ 404 407 { 0x00000182, 0x0000 }, /* R386 (0x182) - FLL1 Synchroniser 2 */ ··· 414 419 { 0x00000194, 0x007d }, /* R404 (0x194) - FLL2 Control 4 */ 415 420 { 0x00000195, 0x0000 }, /* R405 (0x195) - FLL2 Control 5 */ 416 421 { 0x00000196, 0x0000 }, /* R406 (0x196) - FLL2 Control 6 */ 417 417 - { 0x00000197, 0x0281 }, /* R407 (0x197) - FLL2 Loop Filter Test 1 */ 418 422 { 0x00000199, 0x0000 }, /* R409 (0x199) - FLL2 Control 7 */ 419 423 { 0x000001a1, 0x0000 }, /* R417 (0x1a1) - FLL2 Synchroniser 1 */ 420 424 { 0x000001a2, 0x0000 }, /* R418 (0x1a2) - FLL2 Synchroniser 2 */ ··· 430 436 { 0x000001b4, 0x007d }, /* R436 (0x1b4) - FLL3 Control 4 */ 431 437 { 0x000001b5, 0x0000 }, /* R437 (0x1b5) - FLL3 Control 5 */ 432 438 { 0x000001b6, 0x0000 }, /* R438 (0x1b6) - FLL3 Control 6 */ 433 433 - { 0x000001b7, 0x0281 }, /* R439 (0x1b7) - FLL3 Loop Filter Test 1 */ 434 439 { 0x000001b9, 0x0000 }, /* R441 (0x1b9) - FLL3 Control 7 */ 435 440 { 0x000001c1, 0x0000 }, /* R449 (0x1c1) - FLL3 Synchroniser 1 */ 436 441 { 0x000001c2, 0x0000 }, /* R450 (0x1c2) - FLL3 Synchroniser 2 */ ··· 539 546 { 0x0000043c, 0x0000 }, /* R1084 (0x43c) - Output Path Config 6R */ 540 547 { 0x0000043d, 0x0180 }, /* R1085 (0x43d) - DAC Digital Volume 6R */ 541 548 { 0x0000043f, 0x0800 }, /* R1087 (0x43f) - Noise Gate Select 6R */ 542 542 - { 0x00000440, 0x003f }, /* R1088 (0x440) - DRE Enable */ 543 543 - { 0x00000448, 0x003f }, /* R1096 (0x448) - EDRE Enable */ 544 544 - { 0x0000044a, 0x0000 }, /* R1098 (0x44a) - EDRE Manual */ 545 549 { 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */ 546 550 { 0x00000451, 0x0000 }, /* R1105 (0x451) - DAC AEC Control 2 */ 547 551 { 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */ ··· 546 556 { 0x00000491, 0x0000 }, /* R1169 (0x491) - PDM SPK1 CTRL 2 */ 547 557 { 0x00000492, 0x0069 }, /* R1170 (0x492) - PDM SPK2 CTRL 1 */ 548 558 { 0x00000493, 0x0000 }, /* R1171 (0x493) - PDM SPK2 CTRL 2 */ 549 549 - { 0x000004a0, 0x3210 }, /* R1184 (0x4a0) - HP1 Short Circuit Ctrl */ 559 559 + { 0x000004a0, 0x3280 }, /* R1184 (0x4a0) - HP1 Short Circuit Ctrl */ 550 560 { 0x000004a1, 0x3200 }, /* R1185 (0x4a1) - HP2 Short Circuit Ctrl */ 551 561 { 0x000004a2, 0x3200 }, /* R1186 (0x4a2) - HP3 Short Circuit Ctrl */ 552 562 { 0x000004a8, 0x7020 }, /* R1192 (0x4a8) - HP Test Ctrl 5 */ ··· 1355 1365 { 0x00000e82, 0x0018 }, /* R3714 (0xe82) - DRC1 ctrl3 */ 1356 1366 { 0x00000e83, 0x0000 }, /* R3715 (0xe83) - DRC1 ctrl4 */ 1357 1367 { 0x00000e84, 0x0000 }, /* R3716 (0xe84) - DRC1 ctrl5 */ 1358 1358 - { 0x00000e88, 0x0933 }, /* R3720 (0xe88) - DRC2 ctrl1 */ 1359 1359 - { 0x00000e89, 0x0018 }, /* R3721 (0xe89) - DRC2 ctrl2 */ 1360 1360 - { 0x00000e8a, 0x0000 }, /* R3722 (0xe8a) - DRC2 ctrl3 */ 1368 1368 + { 0x00000e88, 0x0018 }, /* R3720 (0xe88) - DRC2 ctrl1 */ 1369 1369 + { 0x00000e89, 0x0933 }, /* R3721 (0xe89) - DRC2 ctrl2 */ 1370 1370 + { 0x00000e8a, 0x0018 }, /* R3722 (0xe8a) - DRC2 ctrl3 */ 1361 1371 { 0x00000e8b, 0x0000 }, /* R3723 (0xe8b) - DRC2 ctrl4 */ 1362 1362 - { 0x00000e8c, 0x0040 }, /* R3724 (0xe8c) - DRC2 ctrl5 */ 1372 1372 + { 0x00000e8c, 0x0000 }, /* R3724 (0xe8c) - DRC2 ctrl5 */ 1363 1373 { 0x00000ec0, 0x0000 }, /* R3776 (0xec0) - HPLPF1_1 */ 1364 1374 { 0x00000ec1, 0x0000 }, /* R3777 (0xec1) - HPLPF1_2 */ 1365 1375 { 0x00000ec4, 0x0000 }, /* R3780 (0xec4) - HPLPF2_1 */ ··· 1567 1577 { 0x00000fc3, 0x0000 }, /* R4035 (0xfc3) - ANC Coefficient */ 1568 1578 { 0x00000fc4, 0x0000 }, /* R4036 (0xfc4) - ANC Coefficient */ 1569 1579 { 0x00000fc5, 0x0000 }, /* R4037 (0xfc5) - ANC Coefficient */ 1570 1570 - { 0x00001300, 0x0000 }, /* R4864 (0x1300) - DAC Comp 1 */ 1571 1571 - { 0x00001302, 0x0000 }, /* R4866 (0x1302) - DAC Comp 2 */ 1572 1572 - { 0x00001380, 0x0000 }, /* R4992 (0x1380) - FRF Coefficient 1L 1 */ 1573 1573 - { 0x00001381, 0x0000 }, /* R4993 (0x1381) - FRF Coefficient 1L 2 */ 1574 1574 - { 0x00001382, 0x0000 }, /* R4994 (0x1382) - FRF Coefficient 1L 3 */ 1575 1575 - { 0x00001383, 0x0000 }, /* R4995 (0x1383) - FRF Coefficient 1L 4 */ 1576 1576 - { 0x00001390, 0x0000 }, /* R5008 (0x1390) - FRF Coefficient 1R 1 */ 1577 1577 - { 0x00001391, 0x0000 }, /* R5009 (0x1391) - FRF Coefficient 1R 2 */ 1578 1578 - { 0x00001392, 0x0000 }, /* R5010 (0x1392) - FRF Coefficient 1R 3 */ 1579 1579 - { 0x00001393, 0x0000 }, /* R5011 (0x1393) - FRF Coefficient 1R 4 */ 1580 1580 - { 0x000013a0, 0x0000 }, /* R5024 (0x13a0) - FRF Coefficient 2L 1 */ 1581 1581 - { 0x000013a1, 0x0000 }, /* R5025 (0x13a1) - FRF Coefficient 2L 2 */ 1582 1582 - { 0x000013a2, 0x0000 }, /* R5026 (0x13a2) - FRF Coefficient 2L 3 */ 1583 1583 - { 0x000013a3, 0x0000 }, /* R5027 (0x13a3) - FRF Coefficient 2L 4 */ 1584 1584 - { 0x000013b0, 0x0000 }, /* R5040 (0x13b0) - FRF Coefficient 2R 1 */ 1585 1585 - { 0x000013b1, 0x0000 }, /* R5041 (0x13b1) - FRF Coefficient 2R 2 */ 1586 1586 - { 0x000013b2, 0x0000 }, /* R5042 (0x13b2) - FRF Coefficient 2R 3 */ 1587 1587 - { 0x000013b3, 0x0000 }, /* R5043 (0x13b3) - FRF Coefficient 2R 4 */ 1588 1588 - { 0x000013c0, 0x0000 }, /* R5040 (0x13c0) - FRF Coefficient 3L 1 */ 1589 1589 - { 0x000013c1, 0x0000 }, /* R5041 (0x13c1) - FRF Coefficient 3L 2 */ 1590 1590 - { 0x000013c2, 0x0000 }, /* R5042 (0x13c2) - FRF Coefficient 3L 3 */ 1591 1591 - { 0x000013c3, 0x0000 }, /* R5043 (0x13c3) - FRF Coefficient 3L 4 */ 1592 1592 - { 0x000013d0, 0x0000 }, /* R5072 (0x13d0) - FRF Coefficient 3R 1 */ 1593 1593 - { 0x000013d1, 0x0000 }, /* R5073 (0x13d1) - FRF Coefficient 3R 2 */ 1594 1594 - { 0x000013d2, 0x0000 }, /* R5074 (0x13d2) - FRF Coefficient 3R 3 */ 1595 1595 - { 0x000013d3, 0x0000 }, /* R5075 (0x13d3) - FRF Coefficient 3R 4 */ 1596 1596 - { 0x000013e0, 0x0000 }, /* R5088 (0x13e0) - FRF Coefficient 4L 1 */ 1597 1597 - { 0x000013e1, 0x0000 }, /* R5089 (0x13e1) - FRF Coefficient 4L 2 */ 1598 1598 - { 0x000013e2, 0x0000 }, /* R5090 (0x13e2) - FRF Coefficient 4L 3 */ 1599 1599 - { 0x000013e3, 0x0000 }, /* R5091 (0x13e3) - FRF Coefficient 4L 4 */ 1600 1600 - { 0x000013f0, 0x0000 }, /* R5104 (0x13f0) - FRF Coefficient 4R 1 */ 1601 1601 - { 0x000013f1, 0x0000 }, /* R5105 (0x13f1) - FRF Coefficient 4R 2 */ 1602 1602 - { 0x000013f2, 0x0000 }, /* R5106 (0x13f2) - FRF Coefficient 4R 3 */ 1603 1603 - { 0x000013f3, 0x0000 }, /* R5107 (0x13f3) - FRF Coefficient 4R 4 */ 1604 1604 - { 0x00001400, 0x0000 }, /* R5120 (0x1400) - FRF Coefficient 5L 1 */ 1605 1605 - { 0x00001401, 0x0000 }, /* R5121 (0x1401) - FRF Coefficient 5L 2 */ 1606 1606 - { 0x00001402, 0x0000 }, /* R5122 (0x1402) - FRF Coefficient 5L 3 */ 1607 1607 - { 0x00001403, 0x0000 }, /* R5123 (0x1403) - FRF Coefficient 5L 4 */ 1608 1608 - { 0x00001410, 0x0000 }, /* R5136 (0x1410) - FRF Coefficient 5R 1 */ 1609 1609 - { 0x00001411, 0x0000 }, /* R5137 (0x1411) - FRF Coefficient 5R 2 */ 1610 1610 - { 0x00001412, 0x0000 }, /* R5138 (0x1412) - FRF Coefficient 5R 3 */ 1611 1611 - { 0x00001413, 0x0000 }, /* R5139 (0x1413) - FRF Coefficient 5R 4 */ 1612 1612 - { 0x00001420, 0x0000 }, /* R5152 (0x1420) - FRF Coefficient 6L 1 */ 1613 1613 - { 0x00001421, 0x0000 }, /* R5153 (0x1421) - FRF Coefficient 6L 2 */ 1614 1614 - { 0x00001422, 0x0000 }, /* R5154 (0x1422) - FRF Coefficient 6L 3 */ 1615 1615 - { 0x00001423, 0x0000 }, /* R5155 (0x1423) - FRF Coefficient 6L 4 */ 1616 1616 - { 0x00001430, 0x0000 }, /* R5168 (0x1430) - FRF Coefficient 6R 1 */ 1617 1617 - { 0x00001431, 0x0000 }, /* R5169 (0x1431) - FRF Coefficient 6R 2 */ 1618 1618 - { 0x00001432, 0x0000 }, /* R5170 (0x1432) - FRF Coefficient 6R 3 */ 1619 1619 - { 0x00001433, 0x0000 }, /* R5171 (0x1433) - FRF Coefficient 6R 4 */ 1620 1580 { 0x00001700, 0x2001 }, /* R5888 (0x1700) - GPIO1 Control 1 */ 1621 1581 { 0x00001701, 0xe000 }, /* R5889 (0x1701) - GPIO1 Control 2 */ 1622 1582 { 0x00001702, 0x2001 }, /* R5890 (0x1702) - GPIO2 Control 1 */ ··· 1785 1845 case MADERA_FLL1_CONTROL_5: 1786 1846 case MADERA_FLL1_CONTROL_6: 1787 1847 case MADERA_FLL1_CONTROL_7: 1788 1788 - case MADERA_FLL1_LOOP_FILTER_TEST_1: 1789 1848 case MADERA_FLL1_SYNCHRONISER_1: 1790 1849 case MADERA_FLL1_SYNCHRONISER_2: 1791 1850 case MADERA_FLL1_SYNCHRONISER_3: ··· 1801 1862 case MADERA_FLL2_CONTROL_5: 1802 1863 case MADERA_FLL2_CONTROL_6: 1803 1864 case MADERA_FLL2_CONTROL_7: 1804 1804 - case MADERA_FLL2_LOOP_FILTER_TEST_1: 1805 1865 case MADERA_FLL2_SYNCHRONISER_1: 1806 1866 case MADERA_FLL2_SYNCHRONISER_2: 1807 1867 case MADERA_FLL2_SYNCHRONISER_3: ··· 1817 1879 case MADERA_FLL3_CONTROL_5: 1818 1880 case MADERA_FLL3_CONTROL_6: 1819 1881 case MADERA_FLL3_CONTROL_7: 1820 1820 - case MADERA_FLL3_LOOP_FILTER_TEST_1: 1821 1882 case MADERA_FLL3_SYNCHRONISER_1: 1822 1883 case MADERA_FLL3_SYNCHRONISER_2: 1823 1884 case MADERA_FLL3_SYNCHRONISER_3: ··· 1941 2004 case MADERA_OUTPUT_PATH_CONFIG_6R: 1942 2005 case MADERA_DAC_DIGITAL_VOLUME_6R: 1943 2006 case MADERA_NOISE_GATE_SELECT_6R: 1944 1944 - case MADERA_DRE_ENABLE: 1945 1945 - case MADERA_EDRE_ENABLE: 1946 1946 - case MADERA_EDRE_MANUAL: 1947 2007 case MADERA_DAC_AEC_CONTROL_1: 1948 2008 case MADERA_DAC_AEC_CONTROL_2: 1949 2009 case MADERA_NOISE_GATE_CONTROL: ··· 2726 2792 case MADERA_FCR_FILTER_CONTROL: 2727 2793 case MADERA_FCR_ADC_REFORMATTER_CONTROL: 2728 2794 case MADERA_FCR_COEFF_START ... MADERA_FCR_COEFF_END: 2729 2729 - case MADERA_DAC_COMP_1: 2730 2730 - case MADERA_DAC_COMP_2: 2731 2731 - case MADERA_FRF_COEFFICIENT_1L_1: 2732 2732 - case MADERA_FRF_COEFFICIENT_1L_2: 2733 2733 - case MADERA_FRF_COEFFICIENT_1L_3: 2734 2734 - case MADERA_FRF_COEFFICIENT_1L_4: 2735 2735 - case MADERA_FRF_COEFFICIENT_1R_1: 2736 2736 - case MADERA_FRF_COEFFICIENT_1R_2: 2737 2737 - case MADERA_FRF_COEFFICIENT_1R_3: 2738 2738 - case MADERA_FRF_COEFFICIENT_1R_4: 2739 2739 - case MADERA_FRF_COEFFICIENT_2L_1: 2740 2740 - case MADERA_FRF_COEFFICIENT_2L_2: 2741 2741 - case MADERA_FRF_COEFFICIENT_2L_3: 2742 2742 - case MADERA_FRF_COEFFICIENT_2L_4: 2743 2743 - case MADERA_FRF_COEFFICIENT_2R_1: 2744 2744 - case MADERA_FRF_COEFFICIENT_2R_2: 2745 2745 - case MADERA_FRF_COEFFICIENT_2R_3: 2746 2746 - case MADERA_FRF_COEFFICIENT_2R_4: 2747 2747 - case MADERA_FRF_COEFFICIENT_3L_1: 2748 2748 - case MADERA_FRF_COEFFICIENT_3L_2: 2749 2749 - case MADERA_FRF_COEFFICIENT_3L_3: 2750 2750 - case MADERA_FRF_COEFFICIENT_3L_4: 2751 2751 - case MADERA_FRF_COEFFICIENT_3R_1: 2752 2752 - case MADERA_FRF_COEFFICIENT_3R_2: 2753 2753 - case MADERA_FRF_COEFFICIENT_3R_3: 2754 2754 - case MADERA_FRF_COEFFICIENT_3R_4: 2755 2755 - case MADERA_FRF_COEFFICIENT_4L_1: 2756 2756 - case MADERA_FRF_COEFFICIENT_4L_2: 2757 2757 - case MADERA_FRF_COEFFICIENT_4L_3: 2758 2758 - case MADERA_FRF_COEFFICIENT_4L_4: 2759 2759 - case MADERA_FRF_COEFFICIENT_4R_1: 2760 2760 - case MADERA_FRF_COEFFICIENT_4R_2: 2761 2761 - case MADERA_FRF_COEFFICIENT_4R_3: 2762 2762 - case MADERA_FRF_COEFFICIENT_4R_4: 2763 2763 - case MADERA_FRF_COEFFICIENT_5L_1: 2764 2764 - case MADERA_FRF_COEFFICIENT_5L_2: 2765 2765 - case MADERA_FRF_COEFFICIENT_5L_3: 2766 2766 - case MADERA_FRF_COEFFICIENT_5L_4: 2767 2767 - case MADERA_FRF_COEFFICIENT_5R_1: 2768 2768 - case MADERA_FRF_COEFFICIENT_5R_2: 2769 2769 - case MADERA_FRF_COEFFICIENT_5R_3: 2770 2770 - case MADERA_FRF_COEFFICIENT_5R_4: 2771 2771 - case MADERA_FRF_COEFFICIENT_6L_1: 2772 2772 - case MADERA_FRF_COEFFICIENT_6L_2: 2773 2773 - case MADERA_FRF_COEFFICIENT_6L_3: 2774 2774 - case MADERA_FRF_COEFFICIENT_6L_4: 2775 2775 - case MADERA_FRF_COEFFICIENT_6R_1: 2776 2776 - case MADERA_FRF_COEFFICIENT_6R_2: 2777 2777 - case MADERA_FRF_COEFFICIENT_6R_3: 2778 2778 - case MADERA_FRF_COEFFICIENT_6R_4: 2779 2795 case MADERA_GPIO1_CTRL_1 ... MADERA_GPIO40_CTRL_2: 2780 2796 case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33: 2781 2797 case MADERA_IRQ1_MASK_1 ... MADERA_IRQ1_MASK_33:

+1 -81

drivers/mfd/cs47l90-tables.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 3 * Regmap tables for CS47L90 codec 4 4 * 5 5 * Copyright (C) 2015-2017 Cirrus Logic 6 6 - * 7 7 - * This program is free software; you can redistribute it and/or modify 8 8 - * it under the terms of the GNU General Public License as published by the 9 9 - * Free Software Foundation; version 2. 10 6 */ 11 7 12 8 #include <linux/device.h> ··· 115 119 { 0x00000174, 0x007d }, /* R372 (0x174) - FLL1 Control 4 */ 116 120 { 0x00000175, 0x0000 }, /* R373 (0x175) - FLL1 Control 5 */ 117 121 { 0x00000176, 0x0000 }, /* R374 (0x176) - FLL1 Control 6 */ 118 118 - { 0x00000177, 0x0281 }, /* R375 (0x177) - FLL1 Loop Filter Test 1 */ 119 122 { 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 7 */ 120 123 { 0x0000017a, 0x2906 }, /* R377 (0x17a) - FLL1 Efs 2 */ 121 124 { 0x00000181, 0x0000 }, /* R385 (0x181) - FLL1 Synchroniser 1 */ ··· 132 137 { 0x00000194, 0x007d }, /* R404 (0x194) - FLL2 Control 4 */ 133 138 { 0x00000195, 0x0000 }, /* R405 (0x195) - FLL2 Control 5 */ 134 139 { 0x00000196, 0x0000 }, /* R406 (0x196) - FLL2 Control 6 */ 135 135 - { 0x00000197, 0x0281 }, /* R407 (0x197) - FLL2 Loop Filter Test 1 */ 136 140 { 0x00000199, 0x0000 }, /* R409 (0x199) - FLL2 Control 7 */ 137 141 { 0x0000019a, 0x2906 }, /* R410 (0x19a) - FLL2 Efs 2 */ 138 142 { 0x000001a1, 0x0000 }, /* R417 (0x1a1) - FLL2 Synchroniser 1 */ ··· 254 260 { 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */ 255 261 { 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */ 256 262 { 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */ 257 257 - { 0x00000440, 0x003f }, /* R1088 (0x440) - DRE Enable */ 258 258 - { 0x00000448, 0x003f }, /* R1096 (0x448) - eDRE Enable */ 259 263 { 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */ 260 264 { 0x00000451, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 2 */ 261 265 { 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */ ··· 1254 1262 { 0x00000fc3, 0x0000 }, /* R4035 (0xfc3) - ANC Coefficient */ 1255 1263 { 0x00000fc4, 0x0000 }, /* R4036 (0xfc4) - ANC Coefficient */ 1256 1264 { 0x00000fc5, 0x0000 }, /* R4037 (0xfc5) - ANC Coefficient */ 1257 1257 - { 0x00001300, 0x050E }, /* R4864 (0x1300) - DAC Comp 1 */ 1258 1258 - { 0x00001302, 0x0101 }, /* R4866 (0x1302) - DAC Comp 2 */ 1259 1259 - { 0x00001380, 0x0425 }, /* R4992 (0x1380) - FRF Coefficient 1L 1 */ 1260 1260 - { 0x00001381, 0xF6D8 }, /* R4993 (0x1381) - FRF Coefficient 1L 2 */ 1261 1261 - { 0x00001382, 0x0632 }, /* R4994 (0x1382) - FRF Coefficient 1L 3 */ 1262 1262 - { 0x00001383, 0xFEC8 }, /* R4995 (0x1383) - FRF Coefficient 1L 4 */ 1263 1263 - { 0x00001390, 0x042F }, /* R5008 (0x1390) - FRF Coefficient 1R 1 */ 1264 1264 - { 0x00001391, 0xF6CA }, /* R5009 (0x1391) - FRF Coefficient 1R 2 */ 1265 1265 - { 0x00001392, 0x0637 }, /* R5010 (0x1392) - FRF Coefficient 1R 3 */ 1266 1266 - { 0x00001393, 0xFEC8 }, /* R5011 (0x1393) - FRF Coefficient 1R 4 */ 1267 1267 - { 0x000013a0, 0x0000 }, /* R5024 (0x13a0) - FRF Coefficient 2L 1 */ 1268 1268 - { 0x000013a1, 0x0000 }, /* R5025 (0x13a1) - FRF Coefficient 2L 2 */ 1269 1269 - { 0x000013a2, 0x0000 }, /* R5026 (0x13a2) - FRF Coefficient 2L 3 */ 1270 1270 - { 0x000013a3, 0x0000 }, /* R5027 (0x13a3) - FRF Coefficient 2L 4 */ 1271 1271 - { 0x000013b0, 0x0000 }, /* R5040 (0x13b0) - FRF Coefficient 2R 1 */ 1272 1272 - { 0x000013b1, 0x0000 }, /* R5041 (0x13b1) - FRF Coefficient 2R 2 */ 1273 1273 - { 0x000013b2, 0x0000 }, /* R5042 (0x13b2) - FRF Coefficient 2R 3 */ 1274 1274 - { 0x000013b3, 0x0000 }, /* R5043 (0x13b3) - FRF Coefficient 2R 4 */ 1275 1275 - { 0x000013c0, 0x0000 }, /* R5040 (0x13c0) - FRF Coefficient 3L 1 */ 1276 1276 - { 0x000013c1, 0x0000 }, /* R5041 (0x13c1) - FRF Coefficient 3L 2 */ 1277 1277 - { 0x000013c2, 0x0000 }, /* R5042 (0x13c2) - FRF Coefficient 3L 3 */ 1278 1278 - { 0x000013c3, 0x0000 }, /* R5043 (0x13c3) - FRF Coefficient 3L 4 */ 1279 1279 - { 0x000013d0, 0x0000 }, /* R5072 (0x13d0) - FRF Coefficient 3R 1 */ 1280 1280 - { 0x000013d1, 0x0000 }, /* R5073 (0x13d1) - FRF Coefficient 3R 2 */ 1281 1281 - { 0x000013d2, 0x0000 }, /* R5074 (0x13d2) - FRF Coefficient 3R 3 */ 1282 1282 - { 0x000013d3, 0x0000 }, /* R5075 (0x13d3) - FRF Coefficient 3R 4 */ 1283 1283 - { 0x00001400, 0x0000 }, /* R5120 (0x1400) - FRF Coefficient 5L 1 */ 1284 1284 - { 0x00001401, 0x0000 }, /* R5121 (0x1401) - FRF Coefficient 5L 2 */ 1285 1285 - { 0x00001402, 0x0000 }, /* R5122 (0x1402) - FRF Coefficient 5L 3 */ 1286 1286 - { 0x00001403, 0x0000 }, /* R5123 (0x1403) - FRF Coefficient 5L 4 */ 1287 1287 - { 0x00001410, 0x0000 }, /* R5136 (0x1410) - FRF Coefficient 5R 1 */ 1288 1288 - { 0x00001411, 0x0000 }, /* R5137 (0x1411) - FRF Coefficient 5R 2 */ 1289 1289 - { 0x00001412, 0x0000 }, /* R5138 (0x1412) - FRF Coefficient 5R 3 */ 1290 1290 - { 0x00001413, 0x0000 }, /* R5139 (0x1413) - FRF Coefficient 5R 4 */ 1291 1265 { 0x00001480, 0x0000 }, /* R5248 (0x1480) - DFC1_CTRL */ 1292 1266 { 0x00001482, 0x1f00 }, /* R5250 (0x1482) - DFC1_RX */ 1293 1267 { 0x00001484, 0x1f00 }, /* R5252 (0x1486) - DFC1_TX */ ··· 1493 1535 case MADERA_FLL1_CONTROL_6: 1494 1536 case MADERA_FLL1_CONTROL_7: 1495 1537 case MADERA_FLL1_EFS_2: 1496 1496 - case MADERA_FLL1_LOOP_FILTER_TEST_1: 1497 1538 case MADERA_FLL1_SYNCHRONISER_1: 1498 1539 case MADERA_FLL1_SYNCHRONISER_2: 1499 1540 case MADERA_FLL1_SYNCHRONISER_3: ··· 1510 1553 case MADERA_FLL2_CONTROL_6: 1511 1554 case MADERA_FLL2_CONTROL_7: 1512 1555 case MADERA_FLL2_EFS_2: 1513 1513 - case MADERA_FLL2_LOOP_FILTER_TEST_1: 1514 1556 case MADERA_FLL2_SYNCHRONISER_1: 1515 1557 case MADERA_FLL2_SYNCHRONISER_2: 1516 1558 case MADERA_FLL2_SYNCHRONISER_3: ··· 1646 1690 case MADERA_OUTPUT_PATH_CONFIG_5R: 1647 1691 case MADERA_DAC_DIGITAL_VOLUME_5R: 1648 1692 case MADERA_NOISE_GATE_SELECT_5R: 1649 1649 - case MADERA_DRE_ENABLE: 1650 1650 - case MADERA_EDRE_ENABLE: 1651 1693 case MADERA_DAC_AEC_CONTROL_1: 1652 1694 case MADERA_DAC_AEC_CONTROL_2: 1653 1695 case MADERA_NOISE_GATE_CONTROL: ··· 2403 2449 case MADERA_FCR_FILTER_CONTROL: 2404 2450 case MADERA_FCR_ADC_REFORMATTER_CONTROL: 2405 2451 case MADERA_FCR_COEFF_START ... MADERA_FCR_COEFF_END: 2406 2406 - case MADERA_DAC_COMP_1: 2407 2407 - case MADERA_DAC_COMP_2: 2408 2408 - case MADERA_FRF_COEFFICIENT_1L_1: 2409 2409 - case MADERA_FRF_COEFFICIENT_1L_2: 2410 2410 - case MADERA_FRF_COEFFICIENT_1L_3: 2411 2411 - case MADERA_FRF_COEFFICIENT_1L_4: 2412 2412 - case MADERA_FRF_COEFFICIENT_1R_1: 2413 2413 - case MADERA_FRF_COEFFICIENT_1R_2: 2414 2414 - case MADERA_FRF_COEFFICIENT_1R_3: 2415 2415 - case MADERA_FRF_COEFFICIENT_1R_4: 2416 2416 - case MADERA_FRF_COEFFICIENT_2L_1: 2417 2417 - case MADERA_FRF_COEFFICIENT_2L_2: 2418 2418 - case MADERA_FRF_COEFFICIENT_2L_3: 2419 2419 - case MADERA_FRF_COEFFICIENT_2L_4: 2420 2420 - case MADERA_FRF_COEFFICIENT_2R_1: 2421 2421 - case MADERA_FRF_COEFFICIENT_2R_2: 2422 2422 - case MADERA_FRF_COEFFICIENT_2R_3: 2423 2423 - case MADERA_FRF_COEFFICIENT_2R_4: 2424 2424 - case MADERA_FRF_COEFFICIENT_3L_1: 2425 2425 - case MADERA_FRF_COEFFICIENT_3L_2: 2426 2426 - case MADERA_FRF_COEFFICIENT_3L_3: 2427 2427 - case MADERA_FRF_COEFFICIENT_3L_4: 2428 2428 - case MADERA_FRF_COEFFICIENT_3R_1: 2429 2429 - case MADERA_FRF_COEFFICIENT_3R_2: 2430 2430 - case MADERA_FRF_COEFFICIENT_3R_3: 2431 2431 - case MADERA_FRF_COEFFICIENT_3R_4: 2432 2432 - case MADERA_FRF_COEFFICIENT_5L_1: 2433 2433 - case MADERA_FRF_COEFFICIENT_5L_2: 2434 2434 - case MADERA_FRF_COEFFICIENT_5L_3: 2435 2435 - case MADERA_FRF_COEFFICIENT_5L_4: 2436 2436 - case MADERA_FRF_COEFFICIENT_5R_1: 2437 2437 - case MADERA_FRF_COEFFICIENT_5R_2: 2438 2438 - case MADERA_FRF_COEFFICIENT_5R_3: 2439 2439 - case MADERA_FRF_COEFFICIENT_5R_4: 2440 2452 case MADERA_DFC1_CTRL: 2441 2453 case MADERA_DFC1_RX: 2442 2454 case MADERA_DFC1_TX:

+1947

drivers/mfd/cs47l92-tables.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Regmap tables for CS47L92 codec 4 4 + * 5 5 + * Copyright (C) 2016-2019 Cirrus Logic, Inc. and 6 6 + * Cirrus Logic International Semiconductor Ltd. 7 7 + * 8 8 + * Author: Stuart Henderson <stuarth@opensource.cirrus.com> 9 9 + */ 10 10 + 11 11 + #include <linux/device.h> 12 12 + #include <linux/module.h> 13 13 + #include <linux/regmap.h> 14 14 + 15 15 + #include <linux/mfd/madera/core.h> 16 16 + #include <linux/mfd/madera/registers.h> 17 17 + 18 18 + #include "madera.h" 19 19 + 20 20 + static const struct reg_sequence cs47l92_reva_16_patch[] = { 21 21 + { 0x3A2, 0x2C29 }, 22 22 + { 0x3A3, 0x0E00 }, 23 23 + { 0x281, 0x0000 }, 24 24 + { 0x282, 0x0000 }, 25 25 + { 0x4EA, 0x0100 }, 26 26 + { 0x22B, 0x0000 }, 27 27 + { 0x4A0, 0x0080 }, 28 28 + { 0x4A1, 0x0000 }, 29 29 + { 0x4A2, 0x0000 }, 30 30 + { 0x180B, 0x033F }, 31 31 + { 0x190B, 0x033F }, 32 32 + { 0x442, 0x0304 }, 33 33 + { 0x34C, 0x0003 }, 34 34 + { 0x124, 0x0C49 }, 35 35 + { 0x120, 0x0345 }, 36 36 + { 0x120, 0x0305 }, 37 37 + { 0x4FA, 0x5064 }, 38 38 + { 0x1300, 0x050E }, 39 39 + { 0x1302, 0x0101 }, 40 40 + { 0x1380, 0x02E0 }, 41 41 + { 0x1381, 0xF942 }, 42 42 + { 0x1382, 0x04CE }, 43 43 + { 0x1383, 0xFF06 }, 44 44 + { 0x1390, 0x0304 }, 45 45 + { 0x1391, 0xF8FF }, 46 46 + { 0x1392, 0x04F3 }, 47 47 + { 0x1393, 0xFF00 }, 48 48 + { 0x13A0, 0x02E0 }, 49 49 + { 0x13A1, 0xF942 }, 50 50 + { 0x13A2, 0x04CE }, 51 51 + { 0x13A3, 0xFF06 }, 52 52 + { 0x13B0, 0x0304 }, 53 53 + { 0x13B1, 0xF8FF }, 54 54 + { 0x13B2, 0x04F3 }, 55 55 + { 0x13B3, 0xFF00 }, 56 56 + { 0x412, 0x0005 }, 57 57 + { 0x41A, 0x0005 }, 58 58 + { 0x422, 0x0005 }, 59 59 + }; 60 60 + 61 61 + static const struct reg_sequence cs47l92_reva_32_patch[] = { 62 62 + { 0x3030, 0x04A00C01 }, 63 63 + { 0x3032, 0x0225F501 }, 64 64 + { 0x3044, 0x04A00C00 }, 65 65 + { 0x3046, 0x0225FF01 }, 66 66 + { 0x3080, 0x04A00C01 }, 67 67 + { 0x3082, 0x0226F501 }, 68 68 + { 0x3094, 0x04A00C00 }, 69 69 + { 0x3096, 0x0226FF01 }, 70 70 + { 0x30D1, 0x04A10C01 }, 71 71 + { 0x30D2, 0x0227F501 }, 72 72 + { 0x30E4, 0x04A10C00 }, 73 73 + { 0x30E6, 0x0227FF01 }, 74 74 + { 0x3120, 0x04A10C01 }, 75 75 + { 0x3122, 0x0228F501 }, 76 76 + { 0x3134, 0x04A10C00 }, 77 77 + { 0x3136, 0x0228FF01 }, 78 78 + { 0x3170, 0x04A20C01 }, 79 79 + { 0x3172, 0x022B0101 }, 80 80 + { 0x3174, 0x0229F501 }, 81 81 + { 0x3184, 0x04A20C00 }, 82 82 + { 0x3186, 0x022B0100 }, 83 83 + { 0x3188, 0x0229FF01 }, 84 84 + { 0x31C0, 0x04A20C01 }, 85 85 + { 0x31C2, 0x022B0001 }, 86 86 + { 0x31C4, 0x022AF501 }, 87 87 + { 0x31D4, 0x04A20C00 }, 88 88 + { 0x31D6, 0x022B0000 }, 89 89 + { 0x31D8, 0x022AFF01 }, 90 90 + }; 91 91 + 92 92 + int cs47l92_patch(struct madera *madera) 93 93 + { 94 94 + int ret; 95 95 + 96 96 + ret = regmap_register_patch(madera->regmap, 97 97 + cs47l92_reva_16_patch, 98 98 + ARRAY_SIZE(cs47l92_reva_16_patch)); 99 99 + if (ret < 0) { 100 100 + dev_err(madera->dev, 101 101 + "Error in applying 16-bit patch: %d\n", ret); 102 102 + return ret; 103 103 + } 104 104 + 105 105 + ret = regmap_register_patch(madera->regmap_32bit, 106 106 + cs47l92_reva_32_patch, 107 107 + ARRAY_SIZE(cs47l92_reva_32_patch)); 108 108 + if (ret < 0) { 109 109 + dev_err(madera->dev, 110 110 + "Error in applying 32-bit patch: %d\n", ret); 111 111 + return ret; 112 112 + } 113 113 + 114 114 + return 0; 115 115 + } 116 116 + EXPORT_SYMBOL_GPL(cs47l92_patch); 117 117 + 118 118 + static const struct reg_default cs47l92_reg_default[] = { 119 119 + { 0x00000020, 0x0000 }, /* R32 (0x20) - Tone Generator 1 */ 120 120 + { 0x00000021, 0x1000 }, /* R33 (0x21) - Tone Generator 2 */ 121 121 + { 0x00000022, 0x0000 }, /* R34 (0x22) - Tone Generator 3 */ 122 122 + { 0x00000023, 0x1000 }, /* R35 (0x23) - Tone Generator 4 */ 123 123 + { 0x00000024, 0x0000 }, /* R36 (0x24) - Tone Generator 5 */ 124 124 + { 0x00000030, 0x0000 }, /* R48 (0x30) - PWM Drive 1 */ 125 125 + { 0x00000031, 0x0100 }, /* R49 (0x31) - PWM Drive 2 */ 126 126 + { 0x00000032, 0x0100 }, /* R50 (0x32) - PWM Drive 3 */ 127 127 + { 0x00000061, 0x01ff }, /* R97 (0x61) - Sample Rate Sequence Select 1 */ 128 128 + { 0x00000062, 0x01ff }, /* R98 (0x62) - Sample Rate Sequence Select 2 */ 129 129 + { 0x00000063, 0x01ff }, /* R99 (0x63) - Sample Rate Sequence Select 3 */ 130 130 + { 0x00000064, 0x01ff }, /* R100 (0x64) - Sample Rate Sequence Select 4 */ 131 131 + { 0x00000090, 0x0000 }, /* R144 (0x90) - Haptics Control 1 */ 132 132 + { 0x00000091, 0x7fff }, /* R145 (0x91) - Haptics Control 2 */ 133 133 + { 0x00000092, 0x0000 }, /* R146 (0x92) - Haptics Phase 1 Intensity */ 134 134 + { 0x00000093, 0x0000 }, /* R147 (0x93) - Haptics Phase 1 Duration */ 135 135 + { 0x00000094, 0x0000 }, /* R148 (0x94) - Haptics Phase 2 Intensity */ 136 136 + { 0x00000095, 0x0000 }, /* R149 (0x95) - Haptics Phase 2 Duration */ 137 137 + { 0x00000096, 0x0000 }, /* R150 (0x96) - Haptics Phase 3 Intensity */ 138 138 + { 0x00000097, 0x0000 }, /* R151 (0x97) - Haptics Phase 3 Duration */ 139 139 + { 0x000000a0, 0x0000 }, /* R160 (0xa0) - Comfort Noise Generator */ 140 140 + { 0x00000100, 0x0002 }, /* R256 (0x100) - Clock 32k 1 */ 141 141 + { 0x00000101, 0x0404 }, /* R257 (0x101) - System Clock 1 */ 142 142 + { 0x00000102, 0x0011 }, /* R258 (0x102) - Sample Rate 1 */ 143 143 + { 0x00000103, 0x0011 }, /* R259 (0x103) - Sample Rate 2 */ 144 144 + { 0x00000104, 0x0011 }, /* R260 (0x104) - Sample Rate 3 */ 145 145 + { 0x00000112, 0x0305 }, /* R274 (0x112) - Async Clock 1 */ 146 146 + { 0x00000113, 0x0011 }, /* R275 (0x113) - Async Sample Rate 1 */ 147 147 + { 0x00000114, 0x0011 }, /* R276 (0x114) - Async Sample Rate 2 */ 148 148 + { 0x00000120, 0x0305 }, /* R288 (0x120) - DSP Clock 1 */ 149 149 + { 0x00000122, 0x0000 }, /* R290 (0x122) - DSP Clock 2 */ 150 150 + { 0x00000149, 0x0000 }, /* R329 (0x149) - Output System Clock */ 151 151 + { 0x0000014a, 0x0000 }, /* R330 (0x14a) - Output Async Clock */ 152 152 + { 0x00000152, 0x0000 }, /* R338 (0x152) - Rate Estimator 1 */ 153 153 + { 0x00000153, 0x0000 }, /* R339 (0x153) - Rate Estimator 2 */ 154 154 + { 0x00000154, 0x0000 }, /* R340 (0x154) - Rate Estimator 3 */ 155 155 + { 0x00000155, 0x0000 }, /* R341 (0x155) - Rate Estimator 4 */ 156 156 + { 0x00000156, 0x0000 }, /* R342 (0x156) - Rate Estimator 5 */ 157 157 + { 0x00000171, 0x7004 }, /* R369 (0x171) - FLL1 Control 1 */ 158 158 + { 0x00000172, 0x0004 }, /* R370 (0x172) - FLL1 Control 2 */ 159 159 + { 0x00000173, 0x0000 }, /* R371 (0x173) - FLL1 Control 3 */ 160 160 + { 0x00000174, 0x0000 }, /* R372 (0x174) - FLL1 Control 4 */ 161 161 + { 0x00000175, 0x0001 }, /* R373 (0x175) - FLL1 Control 5 */ 162 162 + { 0x00000176, 0x8000 }, /* R374 (0x176) - FLL1 Control 6 */ 163 163 + { 0x00000177, 0x0680 }, /* R375 (0x177) - FLL1 Control 7 */ 164 164 + { 0x00000178, 0x21f0 }, /* R376 (0x178) - FLL1 Control 8 */ 165 165 + { 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 9 */ 166 166 + { 0x0000017a, 0x0000 }, /* R378 (0x17a) - FLL1 Control 10 */ 167 167 + { 0x0000017b, 0x0011 }, /* R379 (0x17b) - FLL1 Control 11 */ 168 168 + { 0x0000017d, 0x33e8 }, /* R381 (0x17d) - FLL1 Digital Test 1 */ 169 169 + { 0x00000181, 0x7000 }, /* R385 (0x181) - FLL1 Synchroniser 1 */ 170 170 + { 0x00000182, 0x0004 }, /* R386 (0x182) - FLL1 Synchroniser 2 */ 171 171 + { 0x00000183, 0x0000 }, /* R387 (0x183) - FLL1 Synchroniser 3 */ 172 172 + { 0x00000184, 0x0000 }, /* R388 (0x184) - FLL1 Synchroniser 4 */ 173 173 + { 0x00000185, 0x0001 }, /* R389 (0x185) - FLL1 Synchroniser 5 */ 174 174 + { 0x00000186, 0x0000 }, /* R390 (0x186) - FLL1 Synchroniser 6 */ 175 175 + { 0x0000018e, 0x0c04 }, /* R398 (0x18e) - FLL1 GPIO Clock */ 176 176 + { 0x00000191, 0x7000 }, /* R401 (0x191) - FLL2 Control 1 */ 177 177 + { 0x00000192, 0x0004 }, /* R402 (0x192) - FLL2 Control 2 */ 178 178 + { 0x00000193, 0x0000 }, /* R403 (0x193) - FLL2 Control 3 */ 179 179 + { 0x00000194, 0x0000 }, /* R404 (0x194) - FLL2 Control 4 */ 180 180 + { 0x00000195, 0x0001 }, /* R405 (0x195) - FLL2 Control 5 */ 181 181 + { 0x00000196, 0x8000 }, /* R406 (0x196) - FLL2 Control 6 */ 182 182 + { 0x00000197, 0x0680 }, /* R407 (0x197) - FLL2 Control 7 */ 183 183 + { 0x00000198, 0x21f0 }, /* R408 (0x198) - FLL2 Control 8 */ 184 184 + { 0x00000199, 0x0000 }, /* R409 (0x199) - FLL2 Control 9 */ 185 185 + { 0x0000019a, 0x0000 }, /* R410 (0x19a) - FLL2 Control 10 */ 186 186 + { 0x0000019b, 0x0011 }, /* R411 (0x19b) - FLL2 Control 11 */ 187 187 + { 0x0000019d, 0x33e8 }, /* R413 (0x19d) - FLL2 Digital Test 1 */ 188 188 + { 0x000001a1, 0x7000 }, /* R417 (0x1a1) - FLL2 Synchroniser 1 */ 189 189 + { 0x000001a2, 0x0004 }, /* R418 (0x1a2) - FLL2 Synchroniser 2 */ 190 190 + { 0x000001a3, 0x0000 }, /* R419 (0x1a3) - FLL2 Synchroniser 3 */ 191 191 + { 0x000001a4, 0x0000 }, /* R420 (0x1a4) - FLL2 Synchroniser 4 */ 192 192 + { 0x000001a5, 0x0001 }, /* R421 (0x1a5) - FLL2 Synchroniser 5 */ 193 193 + { 0x000001a6, 0x0000 }, /* R422 (0x1a6) - FLL2 Synchroniser 6 */ 194 194 + { 0x000001ae, 0x0c04 }, /* R430 (0x1ae) - FLL2 GPIO Clock */ 195 195 + { 0x00000200, 0x0006 }, /* R512 (0x200) - Mic Charge Pump 1 */ 196 196 + { 0x00000213, 0x03e4 }, /* R531 (0x213) - LDO2 Control 1 */ 197 197 + { 0x00000218, 0x00e6 }, /* R536 (0x218) - Mic Bias Ctrl 1 */ 198 198 + { 0x00000219, 0x00e6 }, /* R537 (0x219) - Mic Bias Ctrl 2 */ 199 199 + { 0x0000021c, 0x2222 }, /* R540 (0x21c) - Mic Bias Ctrl 5 */ 200 200 + { 0x0000021e, 0x0022 }, /* R542 (0x21e) - Mic Bias Ctrl 6 */ 201 201 + { 0x00000293, 0x0080 }, /* R659 (0x293) - Accessory Detect Mode 1 */ 202 202 + { 0x00000299, 0x0000 }, /* R665 (0x299) - Headphone Detect 0 */ 203 203 + { 0x0000029b, 0x0000 }, /* R667 (0x29b) - Headphone Detect 1 */ 204 204 + { 0x000002a2, 0x0010 }, /* R674 (0x2a2) - Mic Detect 1 Control 0 */ 205 205 + { 0x000002a3, 0x1102 }, /* R675 (0x2a3) - Mic Detect 1 Control 1 */ 206 206 + { 0x000002a4, 0x009f }, /* R676 (0x2a4) - Mic Detect 1 Control 2 */ 207 207 + { 0x000002a6, 0x3d3d }, /* R678 (0x2a6) - Mic Detect 1 Level 1 */ 208 208 + { 0x000002a7, 0x3d3d }, /* R679 (0x2a7) - Mic Detect 1 Level 2 */ 209 209 + { 0x000002a8, 0x333d }, /* R680 (0x2a8) - Mic Detect 1 Level 3 */ 210 210 + { 0x000002a9, 0x202d }, /* R681 (0x2a9) - Mic Detect 1 Level 4 */ 211 211 + { 0x000002b2, 0x0010 }, /* R690 (0x2b2) - Mic Detect 2 Control 0 */ 212 212 + { 0x000002b3, 0x1102 }, /* R691 (0x2b3) - Mic Detect 2 Control 1 */ 213 213 + { 0x000002b4, 0x009f }, /* R692 (0x2b4) - Mic Detect 2 Control 2 */ 214 214 + { 0x000002b6, 0x3d3d }, /* R694 (0x2b6) - Mic Detect 2 Level 1 */ 215 215 + { 0x000002b7, 0x3d3d }, /* R695 (0x2b7) - Mic Detect 2 Level 2 */ 216 216 + { 0x000002b8, 0x333d }, /* R696 (0x2b8) - Mic Detect 2 Level 3 */ 217 217 + { 0x000002b9, 0x202d }, /* R697 (0x2b9) - Mic Detect 2 Level 4 */ 218 218 + { 0x000002c6, 0x0210 }, /* R710 (0x2c6) - Micd Clamp control */ 219 219 + { 0x000002c8, 0x0000 }, /* R712 (0x2c8) - GP Switch 1 */ 220 220 + { 0x000002d3, 0x0000 }, /* R723 (0x2d3) - Jack Detect Analogue */ 221 221 + { 0x00000300, 0x0000 }, /* R768 (0x300) - Input Enables */ 222 222 + { 0x00000308, 0x0400 }, /* R776 (0x308) - Input Rate */ 223 223 + { 0x00000309, 0x0022 }, /* R777 (0x309) - Input Volume Ramp */ 224 224 + { 0x0000030c, 0x0002 }, /* R780 (0x30c) - HPF Control */ 225 225 + { 0x00000310, 0x0080 }, /* R784 (0x310) - IN1L Control */ 226 226 + { 0x00000311, 0x0180 }, /* R785 (0x311) - ADC Digital Volume 1L */ 227 227 + { 0x00000312, 0x0500 }, /* R786 (0x312) - DMIC1L Control */ 228 228 + { 0x00000313, 0x0000 }, /* R787 (0x313) - IN1L Rate Control */ 229 229 + { 0x00000314, 0x0080 }, /* R788 (0x314) - IN1R Control */ 230 230 + { 0x00000315, 0x0180 }, /* R789 (0x315) - ADC Digital Volume 1R */ 231 231 + { 0x00000316, 0x0000 }, /* R790 (0x316) - DMIC1R Control */ 232 232 + { 0x00000317, 0x0000 }, /* R791 (0x317) - IN1R Rate Control */ 233 233 + { 0x00000318, 0x0080 }, /* R792 (0x318) - IN2L Control */ 234 234 + { 0x00000319, 0x0180 }, /* R793 (0x319) - ADC Digital Volume 2L */ 235 235 + { 0x0000031a, 0x0500 }, /* R794 (0x31a) - DMIC2L Control */ 236 236 + { 0x0000031b, 0x0000 }, /* R795 (0x31b) - IN2L Rate Control */ 237 237 + { 0x0000031c, 0x0080 }, /* R796 (0x31c) - IN2R Control */ 238 238 + { 0x0000031d, 0x0180 }, /* R797 (0x31d) - ADC Digital Volume 2R */ 239 239 + { 0x0000031e, 0x0000 }, /* R798 (0x31e) - DMIC2R Control */ 240 240 + { 0x0000031f, 0x0000 }, /* R799 (0x31f) - IN2R Rate Control */ 241 241 + { 0x00000320, 0x0000 }, /* R800 (0x320) - IN3L Control */ 242 242 + { 0x00000321, 0x0180 }, /* R801 (0x321) - ADC Digital Volume 3L */ 243 243 + { 0x00000322, 0x0500 }, /* R802 (0x322) - DMIC3L Control */ 244 244 + { 0x00000323, 0x0000 }, /* R803 (0x323) - IN3L Rate Control */ 245 245 + { 0x00000324, 0x0000 }, /* R804 (0x324) - IN3R Control */ 246 246 + { 0x00000325, 0x0180 }, /* R805 (0x325) - ADC Digital Volume 3R */ 247 247 + { 0x00000326, 0x0000 }, /* R806 (0x326) - DMIC3R Control */ 248 248 + { 0x00000327, 0x0000 }, /* R807 (0x327) - IN3R Rate Control */ 249 249 + { 0x00000328, 0x0000 }, /* R808 (0x328) - IN4L Control */ 250 250 + { 0x00000329, 0x0180 }, /* R809 (0x329) - ADC Digital Volume 4L */ 251 251 + { 0x0000032a, 0x0500 }, /* R810 (0x32a) - DMIC4L Control */ 252 252 + { 0x0000032b, 0x0000 }, /* R811 (0x32b) - IN4L Rate Control */ 253 253 + { 0x0000032c, 0x0000 }, /* R812 (0x32c) - IN4R Control */ 254 254 + { 0x0000032d, 0x0180 }, /* R813 (0x32d) - ADC Digital Volume 4R */ 255 255 + { 0x0000032e, 0x0000 }, /* R814 (0x32e) - DMIC4R Control */ 256 256 + { 0x0000032f, 0x0000 }, /* R815 (0x32f) - IN4R Rate Control */ 257 257 + { 0x00000400, 0x0000 }, /* R1024 (0x400) - Output Enables 1 */ 258 258 + { 0x00000408, 0x0040 }, /* R1032 (0x408) - Output Rate 1 */ 259 259 + { 0x00000409, 0x0022 }, /* R1033 (0x409) - Output Volume Ramp */ 260 260 + { 0x00000410, 0x0080 }, /* R1040 (0x410) - Output Path Config 1L */ 261 261 + { 0x00000411, 0x0180 }, /* R1041 (0x411) - DAC Digital Volume 1L */ 262 262 + { 0x00000412, 0x0005 }, /* R1042 (0x412) - Output Path Config 1 */ 263 263 + { 0x00000413, 0x0001 }, /* R1043 (0x413) - Noise Gate Select 1L */ 264 264 + { 0x00000414, 0x0080 }, /* R1044 (0x414) - Output Path Config 1R */ 265 265 + { 0x00000415, 0x0180 }, /* R1045 (0x415) - DAC Digital Volume 1R */ 266 266 + { 0x00000417, 0x0002 }, /* R1047 (0x417) - Noise Gate Select 1R */ 267 267 + { 0x00000418, 0x0080 }, /* R1048 (0x418) - Output Path Config 2L */ 268 268 + { 0x00000419, 0x0180 }, /* R1049 (0x419) - DAC Digital Volume 2L */ 269 269 + { 0x0000041a, 0x0005 }, /* R1050 (0x41a) - Output Path Config 2 */ 270 270 + { 0x0000041b, 0x0004 }, /* R1051 (0x41b) - Noise Gate Select 2L */ 271 271 + { 0x0000041c, 0x0080 }, /* R1052 (0x41c) - Output Path Config 2R */ 272 272 + { 0x0000041d, 0x0180 }, /* R1053 (0x41d) - DAC Digital Volume 2R */ 273 273 + { 0x0000041f, 0x0008 }, /* R1055 (0x41f) - Noise Gate Select 2R */ 274 274 + { 0x00000420, 0x0080 }, /* R1056 (0x420) - Output Path Config 3L */ 275 275 + { 0x00000421, 0x0180 }, /* R1057 (0x421) - DAC Digital Volume 3L */ 276 276 + { 0x00000422, 0x0005 }, /* R1058 (0x422) - Output Path Config 3 */ 277 277 + { 0x00000423, 0x0010 }, /* R1059 (0x423) - Noise Gate Select 3L */ 278 278 + { 0x00000424, 0x0080 }, /* R1060 (0x424) - Output Path Config 3R */ 279 279 + { 0x00000425, 0x0180 }, /* R1061 (0x425) - DAC Digital Volume 3R */ 280 280 + { 0x00000427, 0x0020 }, /* R1063 (0x427) - Noise Gate Select 3R */ 281 281 + { 0x00000430, 0x0000 }, /* R1072 (0x430) - Output Path Config 5L */ 282 282 + { 0x00000431, 0x0180 }, /* R1073 (0x431) - DAC Digital Volume 5L */ 283 283 + { 0x00000433, 0x0100 }, /* R1075 (0x433) - Noise Gate Select 5L */ 284 284 + { 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */ 285 285 + { 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */ 286 286 + { 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */ 287 287 + { 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */ 288 288 + { 0x00000451, 0x0000 }, /* R1105 (0x451) - DAC AEC Control 2 */ 289 289 + { 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */ 290 290 + { 0x00000490, 0x0069 }, /* R1168 (0x490) - PDM SPK1 Ctrl 1 */ 291 291 + { 0x00000491, 0x0000 }, /* R1169 (0x491) - PDM SPK1 Ctrl 2 */ 292 292 + { 0x000004a0, 0x0080 }, /* R1184 (0x4a0) - HP1 Short Circuit Ctrl */ 293 293 + { 0x000004a1, 0x0000 }, /* R1185 (0x4a1) - HP2 Short Circuit Ctrl */ 294 294 + { 0x000004a2, 0x0000 }, /* R1186 (0x4a2) - HP3 Short Circuit Ctrl */ 295 295 + { 0x00000500, 0x000c }, /* R1280 (0x500) - AIF1 BCLK Ctrl */ 296 296 + { 0x00000501, 0x0000 }, /* R1281 (0x501) - AIF1 Tx Pin Ctrl */ 297 297 + { 0x00000502, 0x0000 }, /* R1282 (0x502) - AIF1 Rx Pin Ctrl */ 298 298 + { 0x00000503, 0x0000 }, /* R1283 (0x503) - AIF1 Rate Ctrl */ 299 299 + { 0x00000504, 0x0000 }, /* R1284 (0x504) - AIF1 Format */ 300 300 + { 0x00000506, 0x0040 }, /* R1286 (0x506) - AIF1 Rx BCLK Rate */ 301 301 + { 0x00000507, 0x1818 }, /* R1287 (0x507) - AIF1 Frame Ctrl 1 */ 302 302 + { 0x00000508, 0x1818 }, /* R1288 (0x508) - AIF1 Frame Ctrl 2 */ 303 303 + { 0x00000509, 0x0000 }, /* R1289 (0x509) - AIF1 Frame Ctrl 3 */ 304 304 + { 0x0000050a, 0x0001 }, /* R1290 (0x50a) - AIF1 Frame Ctrl 4 */ 305 305 + { 0x0000050b, 0x0002 }, /* R1291 (0x50b) - AIF1 Frame Ctrl 5 */ 306 306 + { 0x0000050c, 0x0003 }, /* R1292 (0x50c) - AIF1 Frame Ctrl 6 */ 307 307 + { 0x0000050d, 0x0004 }, /* R1293 (0x50d) - AIF1 Frame Ctrl 7 */ 308 308 + { 0x0000050e, 0x0005 }, /* R1294 (0x50e) - AIF1 Frame Ctrl 8 */ 309 309 + { 0x0000050f, 0x0006 }, /* R1295 (0x50f) - AIF1 Frame Ctrl 9 */ 310 310 + { 0x00000510, 0x0007 }, /* R1296 (0x510) - AIF1 Frame Ctrl 10 */ 311 311 + { 0x00000511, 0x0000 }, /* R1297 (0x511) - AIF1 Frame Ctrl 11 */ 312 312 + { 0x00000512, 0x0001 }, /* R1298 (0x512) - AIF1 Frame Ctrl 12 */ 313 313 + { 0x00000513, 0x0002 }, /* R1299 (0x513) - AIF1 Frame Ctrl 13 */ 314 314 + { 0x00000514, 0x0003 }, /* R1300 (0x514) - AIF1 Frame Ctrl 14 */ 315 315 + { 0x00000515, 0x0004 }, /* R1301 (0x515) - AIF1 Frame Ctrl 15 */ 316 316 + { 0x00000516, 0x0005 }, /* R1302 (0x516) - AIF1 Frame Ctrl 16 */ 317 317 + { 0x00000517, 0x0006 }, /* R1303 (0x517) - AIF1 Frame Ctrl 17 */ 318 318 + { 0x00000518, 0x0007 }, /* R1304 (0x518) - AIF1 Frame Ctrl 18 */ 319 319 + { 0x00000519, 0x0000 }, /* R1305 (0x519) - AIF1 Tx Enables */ 320 320 + { 0x0000051a, 0x0000 }, /* R1306 (0x51a) - AIF1 Rx Enables */ 321 321 + { 0x00000540, 0x000c }, /* R1344 (0x540) - AIF2 BCLK Ctrl */ 322 322 + { 0x00000541, 0x0000 }, /* R1345 (0x541) - AIF2 Tx Pin Ctrl */ 323 323 + { 0x00000542, 0x0000 }, /* R1346 (0x542) - AIF2 Rx Pin Ctrl */ 324 324 + { 0x00000543, 0x0000 }, /* R1347 (0x543) - AIF2 Rate Ctrl */ 325 325 + { 0x00000544, 0x0000 }, /* R1348 (0x544) - AIF2 Format */ 326 326 + { 0x00000546, 0x0040 }, /* R1350 (0x546) - AIF2 Rx BCLK Rate */ 327 327 + { 0x00000547, 0x1818 }, /* R1351 (0x547) - AIF2 Frame Ctrl 1 */ 328 328 + { 0x00000548, 0x1818 }, /* R1352 (0x548) - AIF2 Frame Ctrl 2 */ 329 329 + { 0x00000549, 0x0000 }, /* R1353 (0x549) - AIF2 Frame Ctrl 3 */ 330 330 + { 0x0000054a, 0x0001 }, /* R1354 (0x54a) - AIF2 Frame Ctrl 4 */ 331 331 + { 0x0000054b, 0x0002 }, /* R1355 (0x54b) - AIF2 Frame Ctrl 5 */ 332 332 + { 0x0000054c, 0x0003 }, /* R1356 (0x54c) - AIF2 Frame Ctrl 6 */ 333 333 + { 0x0000054d, 0x0004 }, /* R1357 (0x54d) - AIF2 Frame Ctrl 7 */ 334 334 + { 0x0000054e, 0x0005 }, /* R1358 (0x54e) - AIF2 Frame Ctrl 8 */ 335 335 + { 0x0000054f, 0x0006 }, /* R1359 (0x54f) - AIF2 Frame Ctrl 9 */ 336 336 + { 0x00000550, 0x0007 }, /* R1360 (0x550) - AIF2 Frame Ctrl 10 */ 337 337 + { 0x00000551, 0x0000 }, /* R1361 (0x551) - AIF2 Frame Ctrl 11 */ 338 338 + { 0x00000552, 0x0001 }, /* R1362 (0x552) - AIF2 Frame Ctrl 12 */ 339 339 + { 0x00000553, 0x0002 }, /* R1363 (0x553) - AIF2 Frame Ctrl 13 */ 340 340 + { 0x00000554, 0x0003 }, /* R1364 (0x554) - AIF2 Frame Ctrl 14 */ 341 341 + { 0x00000555, 0x0004 }, /* R1365 (0x555) - AIF2 Frame Ctrl 15 */ 342 342 + { 0x00000556, 0x0005 }, /* R1366 (0x556) - AIF2 Frame Ctrl 16 */ 343 343 + { 0x00000557, 0x0006 }, /* R1367 (0x557) - AIF2 Frame Ctrl 17 */ 344 344 + { 0x00000558, 0x0007 }, /* R1368 (0x558) - AIF2 Frame Ctrl 18 */ 345 345 + { 0x00000559, 0x0000 }, /* R1369 (0x559) - AIF2 Tx Enables */ 346 346 + { 0x0000055a, 0x0000 }, /* R1370 (0x55a) - AIF2 Rx Enables */ 347 347 + { 0x00000580, 0x000c }, /* R1408 (0x580) - AIF3 BCLK Ctrl */ 348 348 + { 0x00000581, 0x0000 }, /* R1409 (0x581) - AIF3 Tx Pin Ctrl */ 349 349 + { 0x00000582, 0x0000 }, /* R1410 (0x582) - AIF3 Rx Pin Ctrl */ 350 350 + { 0x00000583, 0x0000 }, /* R1411 (0x583) - AIF3 Rate Ctrl */ 351 351 + { 0x00000584, 0x0000 }, /* R1412 (0x584) - AIF3 Format */ 352 352 + { 0x00000586, 0x0040 }, /* R1414 (0x586) - AIF3 Rx BCLK Rate */ 353 353 + { 0x00000587, 0x1818 }, /* R1415 (0x587) - AIF3 Frame Ctrl 1 */ 354 354 + { 0x00000588, 0x1818 }, /* R1416 (0x588) - AIF3 Frame Ctrl 2 */ 355 355 + { 0x00000589, 0x0000 }, /* R1417 (0x589) - AIF3 Frame Ctrl 3 */ 356 356 + { 0x0000058a, 0x0001 }, /* R1418 (0x58a) - AIF3 Frame Ctrl 4 */ 357 357 + { 0x0000058b, 0x0002 }, /* R1419 (0x58b) - AIF3 Frame Ctrl 5 */ 358 358 + { 0x0000058c, 0x0003 }, /* R1420 (0x58c) - AIF3 Frame Ctrl 6 */ 359 359 + { 0x0000058d, 0x0004 }, /* R1421 (0x58d) - AIF3 Frame Ctrl 7 */ 360 360 + { 0x0000058e, 0x0005 }, /* R1422 (0x58e) - AIF3 Frame Ctrl 8 */ 361 361 + { 0x0000058f, 0x0006 }, /* R1423 (0x58f) - AIF3 Frame Ctrl 9 */ 362 362 + { 0x00000590, 0x0007 }, /* R1424 (0x590) - AIF3 Frame Ctrl 10 */ 363 363 + { 0x00000591, 0x0000 }, /* R1425 (0x591) - AIF3 Frame Ctrl 11 */ 364 364 + { 0x00000592, 0x0001 }, /* R1426 (0x592) - AIF3 Frame Ctrl 12 */ 365 365 + { 0x00000593, 0x0002 }, /* R1427 (0x593) - AIF3 Frame Ctrl 13 */ 366 366 + { 0x00000594, 0x0003 }, /* R1428 (0x594) - AIF3 Frame Ctrl 14 */ 367 367 + { 0x00000595, 0x0004 }, /* R1429 (0x595) - AIF3 Frame Ctrl 15 */ 368 368 + { 0x00000596, 0x0005 }, /* R1430 (0x596) - AIF3 Frame Ctrl 16 */ 369 369 + { 0x00000597, 0x0006 }, /* R1431 (0x597) - AIF3 Frame Ctrl 17 */ 370 370 + { 0x00000598, 0x0007 }, /* R1432 (0x598) - AIF3 Frame Ctrl 18 */ 371 371 + { 0x00000599, 0x0000 }, /* R1433 (0x599) - AIF3 Tx Enables */ 372 372 + { 0x0000059a, 0x0000 }, /* R1434 (0x59a) - AIF3 Rx Enables */ 373 373 + { 0x000005c2, 0x0000 }, /* R1474 (0x5c2) - SPD1 Tx Control */ 374 374 + { 0x000005e3, 0x0000 }, /* R1507 (0x5e3) - SLIMBus Framer Ref Gear */ 375 375 + { 0x000005e5, 0x0000 }, /* R1509 (0x5e5) - SLIMBus Rates 1 */ 376 376 + { 0x000005e6, 0x0000 }, /* R1510 (0x5e6) - SLIMBus Rates 2 */ 377 377 + { 0x000005e7, 0x0000 }, /* R1511 (0x5e7) - SLIMBus Rates 3 */ 378 378 + { 0x000005e8, 0x0000 }, /* R1512 (0x5e8) - SLIMBus Rates 4 */ 379 379 + { 0x000005e9, 0x0000 }, /* R1513 (0x5e9) - SLIMBus Rates 5 */ 380 380 + { 0x000005ea, 0x0000 }, /* R1514 (0x5ea) - SLIMBus Rates 6 */ 381 381 + { 0x000005eb, 0x0000 }, /* R1515 (0x5eb) - SLIMBus Rates 7 */ 382 382 + { 0x000005ec, 0x0000 }, /* R1516 (0x5ec) - SLIMBus Rates 8 */ 383 383 + { 0x000005f5, 0x0000 }, /* R1525 (0x5f5) - SLIMBus RX Channel Enable */ 384 384 + { 0x000005f6, 0x0000 }, /* R1526 (0x5f6) - SLIMBus TX Channel Enable */ 385 385 + { 0x00000640, 0x0000 }, /* R1600 (0x640) - PWM1MIX Input 1 Source */ 386 386 + { 0x00000641, 0x0080 }, /* R1601 (0x641) - PWM1MIX Input 1 Volume */ 387 387 + { 0x00000642, 0x0000 }, /* R1602 (0x642) - PWM1MIX Input 2 Source */ 388 388 + { 0x00000643, 0x0080 }, /* R1603 (0x643) - PWM1MIX Input 2 Volume */ 389 389 + { 0x00000644, 0x0000 }, /* R1604 (0x644) - PWM1MIX Input 3 Source */ 390 390 + { 0x00000645, 0x0080 }, /* R1605 (0x645) - PWM1MIX Input 3 Volume */ 391 391 + { 0x00000646, 0x0000 }, /* R1606 (0x646) - PWM1MIX Input 4 Source */ 392 392 + { 0x00000647, 0x0080 }, /* R1607 (0x647) - PWM1MIX Input 4 Volume */ 393 393 + { 0x00000648, 0x0000 }, /* R1608 (0x648) - PWM2MIX Input 1 Source */ 394 394 + { 0x00000649, 0x0080 }, /* R1609 (0x649) - PWM2MIX Input 1 Volume */ 395 395 + { 0x0000064a, 0x0000 }, /* R1610 (0x64a) - PWM2MIX Input 2 Source */ 396 396 + { 0x0000064b, 0x0080 }, /* R1611 (0x64b) - PWM2MIX Input 2 Volume */ 397 397 + { 0x0000064c, 0x0000 }, /* R1612 (0x64c) - PWM2MIX Input 3 Source */ 398 398 + { 0x0000064d, 0x0080 }, /* R1613 (0x64d) - PWM2MIX Input 3 Volume */ 399 399 + { 0x0000064e, 0x0000 }, /* R1614 (0x64e) - PWM2MIX Input 4 Source */ 400 400 + { 0x0000064f, 0x0080 }, /* R1615 (0x64f) - PWM2MIX Input 4 Volume */ 401 401 + { 0x00000680, 0x0000 }, /* R1664 (0x680) - OUT1LMIX Input 1 Source */ 402 402 + { 0x00000681, 0x0080 }, /* R1665 (0x681) - OUT1LMIX Input 1 Volume */ 403 403 + { 0x00000682, 0x0000 }, /* R1666 (0x682) - OUT1LMIX Input 2 Source */ 404 404 + { 0x00000683, 0x0080 }, /* R1667 (0x683) - OUT1LMIX Input 2 Volume */ 405 405 + { 0x00000684, 0x0000 }, /* R1668 (0x684) - OUT1LMIX Input 3 Source */ 406 406 + { 0x00000685, 0x0080 }, /* R1669 (0x685) - OUT1LMIX Input 3 Volume */ 407 407 + { 0x00000686, 0x0000 }, /* R1670 (0x686) - OUT1LMIX Input 4 Source */ 408 408 + { 0x00000687, 0x0080 }, /* R1671 (0x687) - OUT1LMIX Input 4 Volume */ 409 409 + { 0x00000688, 0x0000 }, /* R1672 (0x688) - OUT1RMIX Input 1 Source */ 410 410 + { 0x00000689, 0x0080 }, /* R1673 (0x689) - OUT1RMIX Input 1 Volume */ 411 411 + { 0x0000068a, 0x0000 }, /* R1674 (0x68a) - OUT1RMIX Input 2 Source */ 412 412 + { 0x0000068b, 0x0080 }, /* R1675 (0x68b) - OUT1RMIX Input 2 Volume */ 413 413 + { 0x0000068c, 0x0000 }, /* R1676 (0x68c) - OUT1RMIX Input 3 Source */ 414 414 + { 0x0000068d, 0x0080 }, /* R1677 (0x68d) - OUT1RMIX Input 3 Volume */ 415 415 + { 0x0000068e, 0x0000 }, /* R1678 (0x68e) - OUT1RMIX Input 4 Source */ 416 416 + { 0x0000068f, 0x0080 }, /* R1679 (0x68f) - OUT1RMIX Input 4 Volume */ 417 417 + { 0x00000690, 0x0000 }, /* R1680 (0x690) - OUT2LMIX Input 1 Source */ 418 418 + { 0x00000691, 0x0080 }, /* R1681 (0x691) - OUT2LMIX Input 1 Volume */ 419 419 + { 0x00000692, 0x0000 }, /* R1682 (0x692) - OUT2LMIX Input 2 Source */ 420 420 + { 0x00000693, 0x0080 }, /* R1683 (0x693) - OUT2LMIX Input 2 Volume */ 421 421 + { 0x00000694, 0x0000 }, /* R1684 (0x694) - OUT2LMIX Input 3 Source */ 422 422 + { 0x00000695, 0x0080 }, /* R1685 (0x695) - OUT2LMIX Input 3 Volume */ 423 423 + { 0x00000696, 0x0000 }, /* R1686 (0x696) - OUT2LMIX Input 4 Source */ 424 424 + { 0x00000697, 0x0080 }, /* R1687 (0x697) - OUT2LMIX Input 4 Volume */ 425 425 + { 0x00000698, 0x0000 }, /* R1688 (0x698) - OUT2RMIX Input 1 Source */ 426 426 + { 0x00000699, 0x0080 }, /* R1689 (0x699) - OUT2RMIX Input 1 Volume */ 427 427 + { 0x0000069a, 0x0000 }, /* R1690 (0x69a) - OUT2RMIX Input 2 Source */ 428 428 + { 0x0000069b, 0x0080 }, /* R1691 (0x69b) - OUT2RMIX Input 2 Volume */ 429 429 + { 0x0000069c, 0x0000 }, /* R1692 (0x69c) - OUT2RMIX Input 3 Source */ 430 430 + { 0x0000069d, 0x0080 }, /* R1693 (0x69d) - OUT2RMIX Input 3 Volume */ 431 431 + { 0x0000069e, 0x0000 }, /* R1694 (0x69e) - OUT2RMIX Input 4 Source */ 432 432 + { 0x0000069f, 0x0080 }, /* R1695 (0x69f) - OUT2RMIX Input 4 Volume */ 433 433 + { 0x000006a0, 0x0000 }, /* R1696 (0x6a0) - OUT3LMIX Input 1 Source */ 434 434 + { 0x000006a1, 0x0080 }, /* R1697 (0x6a1) - OUT3LMIX Input 1 Volume */ 435 435 + { 0x000006a2, 0x0000 }, /* R1698 (0x6a2) - OUT3LMIX Input 2 Source */ 436 436 + { 0x000006a3, 0x0080 }, /* R1699 (0x6a3) - OUT3LMIX Input 2 Volume */ 437 437 + { 0x000006a4, 0x0000 }, /* R1700 (0x6a4) - OUT3LMIX Input 3 Source */ 438 438 + { 0x000006a5, 0x0080 }, /* R1701 (0x6a5) - OUT3LMIX Input 3 Volume */ 439 439 + { 0x000006a6, 0x0000 }, /* R1702 (0x6a6) - OUT3LMIX Input 4 Source */ 440 440 + { 0x000006a7, 0x0080 }, /* R1703 (0x6a7) - OUT3LMIX Input 4 Volume */ 441 441 + { 0x000006a8, 0x0000 }, /* R1704 (0x6a8) - OUT3RMIX Input 1 Source */ 442 442 + { 0x000006a9, 0x0080 }, /* R1705 (0x6a9) - OUT3RMIX Input 1 Volume */ 443 443 + { 0x000006aa, 0x0000 }, /* R1706 (0x6aa) - OUT3RMIX Input 2 Source */ 444 444 + { 0x000006ab, 0x0080 }, /* R1707 (0x6ab) - OUT3RMIX Input 2 Volume */ 445 445 + { 0x000006ac, 0x0000 }, /* R1708 (0x6ac) - OUT3RMIX Input 3 Source */ 446 446 + { 0x000006ad, 0x0080 }, /* R1709 (0x6ad) - OUT3RMIX Input 3 Volume */ 447 447 + { 0x000006ae, 0x0000 }, /* R1710 (0x6ae) - OUT3RMIX Input 4 Source */ 448 448 + { 0x000006af, 0x0080 }, /* R1711 (0x6af) - OUT3RMIX Input 4 Volume */ 449 449 + { 0x000006c0, 0x0000 }, /* R1728 (0x6c0) - OUT5LMIX Input 1 Source */ 450 450 + { 0x000006c1, 0x0080 }, /* R1729 (0x6c1) - OUT5LMIX Input 1 Volume */ 451 451 + { 0x000006c2, 0x0000 }, /* R1730 (0x6c2) - OUT5LMIX Input 2 Source */ 452 452 + { 0x000006c3, 0x0080 }, /* R1731 (0x6c3) - OUT5LMIX Input 2 Volume */ 453 453 + { 0x000006c4, 0x0000 }, /* R1732 (0x6c4) - OUT5LMIX Input 3 Source */ 454 454 + { 0x000006c5, 0x0080 }, /* R1733 (0x6c5) - OUT5LMIX Input 3 Volume */ 455 455 + { 0x000006c6, 0x0000 }, /* R1734 (0x6c6) - OUT5LMIX Input 4 Source */ 456 456 + { 0x000006c7, 0x0080 }, /* R1735 (0x6c7) - OUT5LMIX Input 4 Volume */ 457 457 + { 0x000006c8, 0x0000 }, /* R1736 (0x6c8) - OUT5RMIX Input 1 Source */ 458 458 + { 0x000006c9, 0x0080 }, /* R1737 (0x6c9) - OUT5RMIX Input 1 Volume */ 459 459 + { 0x000006ca, 0x0000 }, /* R1738 (0x6ca) - OUT5RMIX Input 2 Source */ 460 460 + { 0x000006cb, 0x0080 }, /* R1739 (0x6cb) - OUT5RMIX Input 2 Volume */ 461 461 + { 0x000006cc, 0x0000 }, /* R1740 (0x6cc) - OUT5RMIX Input 3 Source */ 462 462 + { 0x000006cd, 0x0080 }, /* R1741 (0x6cd) - OUT5RMIX Input 3 Volume */ 463 463 + { 0x000006ce, 0x0000 }, /* R1742 (0x6ce) - OUT5RMIX Input 4 Source */ 464 464 + { 0x000006cf, 0x0080 }, /* R1743 (0x6cf) - OUT5RMIX Input 4 Volume */ 465 465 + { 0x00000700, 0x0000 }, /* R1792 (0x700) - AIF1TX1MIX Input 1 Source */ 466 466 + { 0x00000701, 0x0080 }, /* R1793 (0x701) - AIF1TX1MIX Input 1 Volume */ 467 467 + { 0x00000702, 0x0000 }, /* R1794 (0x702) - AIF1TX1MIX Input 2 Source */ 468 468 + { 0x00000703, 0x0080 }, /* R1795 (0x703) - AIF1TX1MIX Input 2 Volume */ 469 469 + { 0x00000704, 0x0000 }, /* R1796 (0x704) - AIF1TX1MIX Input 3 Source */ 470 470 + { 0x00000705, 0x0080 }, /* R1797 (0x705) - AIF1TX1MIX Input 3 Volume */ 471 471 + { 0x00000706, 0x0000 }, /* R1798 (0x706) - AIF1TX1MIX Input 4 Source */ 472 472 + { 0x00000707, 0x0080 }, /* R1799 (0x707) - AIF1TX1MIX Input 4 Volume */ 473 473 + { 0x00000708, 0x0000 }, /* R1800 (0x708) - AIF1TX2MIX Input 1 Source */ 474 474 + { 0x00000709, 0x0080 }, /* R1801 (0x709) - AIF1TX2MIX Input 1 Volume */ 475 475 + { 0x0000070a, 0x0000 }, /* R1802 (0x70a) - AIF1TX2MIX Input 2 Source */ 476 476 + { 0x0000070b, 0x0080 }, /* R1803 (0x70b) - AIF1TX2MIX Input 2 Volume */ 477 477 + { 0x0000070c, 0x0000 }, /* R1804 (0x70c) - AIF1TX2MIX Input 3 Source */ 478 478 + { 0x0000070d, 0x0080 }, /* R1805 (0x70d) - AIF1TX2MIX Input 3 Volume */ 479 479 + { 0x0000070e, 0x0000 }, /* R1806 (0x70e) - AIF1TX2MIX Input 4 Source */ 480 480 + { 0x0000070f, 0x0080 }, /* R1807 (0x70f) - AIF1TX2MIX Input 4 Volume */ 481 481 + { 0x00000710, 0x0000 }, /* R1808 (0x710) - AIF1TX3MIX Input 1 Source */ 482 482 + { 0x00000711, 0x0080 }, /* R1809 (0x711) - AIF1TX3MIX Input 1 Volume */ 483 483 + { 0x00000712, 0x0000 }, /* R1810 (0x712) - AIF1TX3MIX Input 2 Source */ 484 484 + { 0x00000713, 0x0080 }, /* R1811 (0x713) - AIF1TX3MIX Input 2 Volume */ 485 485 + { 0x00000714, 0x0000 }, /* R1812 (0x714) - AIF1TX3MIX Input 3 Source */ 486 486 + { 0x00000715, 0x0080 }, /* R1813 (0x715) - AIF1TX3MIX Input 3 Volume */ 487 487 + { 0x00000716, 0x0000 }, /* R1814 (0x716) - AIF1TX3MIX Input 4 Source */ 488 488 + { 0x00000717, 0x0080 }, /* R1815 (0x717) - AIF1TX3MIX Input 4 Volume */ 489 489 + { 0x00000718, 0x0000 }, /* R1816 (0x718) - AIF1TX4MIX Input 1 Source */ 490 490 + { 0x00000719, 0x0080 }, /* R1817 (0x719) - AIF1TX4MIX Input 1 Volume */ 491 491 + { 0x0000071a, 0x0000 }, /* R1818 (0x71a) - AIF1TX4MIX Input 2 Source */ 492 492 + { 0x0000071b, 0x0080 }, /* R1819 (0x71b) - AIF1TX4MIX Input 2 Volume */ 493 493 + { 0x0000071c, 0x0000 }, /* R1820 (0x71c) - AIF1TX4MIX Input 3 Source */ 494 494 + { 0x0000071d, 0x0080 }, /* R1821 (0x71d) - AIF1TX4MIX Input 3 Volume */ 495 495 + { 0x0000071e, 0x0000 }, /* R1822 (0x71e) - AIF1TX4MIX Input 4 Source */ 496 496 + { 0x0000071f, 0x0080 }, /* R1823 (0x71f) - AIF1TX4MIX Input 4 Volume */ 497 497 + { 0x00000720, 0x0000 }, /* R1824 (0x720) - AIF1TX5MIX Input 1 Source */ 498 498 + { 0x00000721, 0x0080 }, /* R1825 (0x721) - AIF1TX5MIX Input 1 Volume */ 499 499 + { 0x00000722, 0x0000 }, /* R1826 (0x722) - AIF1TX5MIX Input 2 Source */ 500 500 + { 0x00000723, 0x0080 }, /* R1827 (0x723) - AIF1TX5MIX Input 2 Volume */ 501 501 + { 0x00000724, 0x0000 }, /* R1828 (0x724) - AIF1TX5MIX Input 3 Source */ 502 502 + { 0x00000725, 0x0080 }, /* R1829 (0x725) - AIF1TX5MIX Input 3 Volume */ 503 503 + { 0x00000726, 0x0000 }, /* R1830 (0x726) - AIF1TX5MIX Input 4 Source */ 504 504 + { 0x00000727, 0x0080 }, /* R1831 (0x727) - AIF1TX5MIX Input 4 Volume */ 505 505 + { 0x00000728, 0x0000 }, /* R1832 (0x728) - AIF1TX6MIX Input 1 Source */ 506 506 + { 0x00000729, 0x0080 }, /* R1833 (0x729) - AIF1TX6MIX Input 1 Volume */ 507 507 + { 0x0000072a, 0x0000 }, /* R1834 (0x72a) - AIF1TX6MIX Input 2 Source */ 508 508 + { 0x0000072b, 0x0080 }, /* R1835 (0x72b) - AIF1TX6MIX Input 2 Volume */ 509 509 + { 0x0000072c, 0x0000 }, /* R1836 (0x72c) - AIF1TX6MIX Input 3 Source */ 510 510 + { 0x0000072d, 0x0080 }, /* R1837 (0x72d) - AIF1TX6MIX Input 3 Volume */ 511 511 + { 0x0000072e, 0x0000 }, /* R1838 (0x72e) - AIF1TX6MIX Input 4 Source */ 512 512 + { 0x0000072f, 0x0080 }, /* R1839 (0x72f) - AIF1TX6MIX Input 4 Volume */ 513 513 + { 0x00000730, 0x0000 }, /* R1840 (0x730) - AIF1TX7MIX Input 1 Source */ 514 514 + { 0x00000731, 0x0080 }, /* R1841 (0x731) - AIF1TX7MIX Input 1 Volume */ 515 515 + { 0x00000732, 0x0000 }, /* R1842 (0x732) - AIF1TX7MIX Input 2 Source */ 516 516 + { 0x00000733, 0x0080 }, /* R1843 (0x733) - AIF1TX7MIX Input 2 Volume */ 517 517 + { 0x00000734, 0x0000 }, /* R1844 (0x734) - AIF1TX7MIX Input 3 Source */ 518 518 + { 0x00000735, 0x0080 }, /* R1845 (0x735) - AIF1TX7MIX Input 3 Volume */ 519 519 + { 0x00000736, 0x0000 }, /* R1846 (0x736) - AIF1TX7MIX Input 4 Source */ 520 520 + { 0x00000737, 0x0080 }, /* R1847 (0x737) - AIF1TX7MIX Input 4 Volume */ 521 521 + { 0x00000738, 0x0000 }, /* R1848 (0x738) - AIF1TX8MIX Input 1 Source */ 522 522 + { 0x00000739, 0x0080 }, /* R1849 (0x739) - AIF1TX8MIX Input 1 Volume */ 523 523 + { 0x0000073a, 0x0000 }, /* R1850 (0x73a) - AIF1TX8MIX Input 2 Source */ 524 524 + { 0x0000073b, 0x0080 }, /* R1851 (0x73b) - AIF1TX8MIX Input 2 Volume */ 525 525 + { 0x0000073c, 0x0000 }, /* R1852 (0x73c) - AIF1TX8MIX Input 3 Source */ 526 526 + { 0x0000073d, 0x0080 }, /* R1853 (0x73d) - AIF1TX8MIX Input 3 Volume */ 527 527 + { 0x0000073e, 0x0000 }, /* R1854 (0x73e) - AIF1TX8MIX Input 4 Source */ 528 528 + { 0x0000073f, 0x0080 }, /* R1855 (0x73f) - AIF1TX8MIX Input 4 Volume */ 529 529 + { 0x00000740, 0x0000 }, /* R1856 (0x740) - AIF2TX1MIX Input 1 Source */ 530 530 + { 0x00000741, 0x0080 }, /* R1857 (0x741) - AIF2TX1MIX Input 1 Volume */ 531 531 + { 0x00000742, 0x0000 }, /* R1858 (0x742) - AIF2TX1MIX Input 2 Source */ 532 532 + { 0x00000743, 0x0080 }, /* R1859 (0x743) - AIF2TX1MIX Input 2 Volume */ 533 533 + { 0x00000744, 0x0000 }, /* R1860 (0x744) - AIF2TX1MIX Input 3 Source */ 534 534 + { 0x00000745, 0x0080 }, /* R1861 (0x745) - AIF2TX1MIX Input 3 Volume */ 535 535 + { 0x00000746, 0x0000 }, /* R1862 (0x746) - AIF2TX1MIX Input 4 Source */ 536 536 + { 0x00000747, 0x0080 }, /* R1863 (0x747) - AIF2TX1MIX Input 4 Volume */ 537 537 + { 0x00000748, 0x0000 }, /* R1864 (0x748) - AIF2TX2MIX Input 1 Source */ 538 538 + { 0x00000749, 0x0080 }, /* R1865 (0x749) - AIF2TX2MIX Input 1 Volume */ 539 539 + { 0x0000074a, 0x0000 }, /* R1866 (0x74a) - AIF2TX2MIX Input 2 Source */ 540 540 + { 0x0000074b, 0x0080 }, /* R1867 (0x74b) - AIF2TX2MIX Input 2 Volume */ 541 541 + { 0x0000074c, 0x0000 }, /* R1868 (0x74c) - AIF2TX2MIX Input 3 Source */ 542 542 + { 0x0000074d, 0x0080 }, /* R1869 (0x74d) - AIF2TX2MIX Input 3 Volume */ 543 543 + { 0x0000074e, 0x0000 }, /* R1870 (0x74e) - AIF2TX2MIX Input 4 Source */ 544 544 + { 0x0000074f, 0x0080 }, /* R1871 (0x74f) - AIF2TX2MIX Input 4 Volume */ 545 545 + { 0x00000750, 0x0000 }, /* R1872 (0x750) - AIF2TX3MIX Input 1 Source */ 546 546 + { 0x00000751, 0x0080 }, /* R1873 (0x751) - AIF2TX3MIX Input 1 Volume */ 547 547 + { 0x00000752, 0x0000 }, /* R1874 (0x752) - AIF2TX3MIX Input 2 Source */ 548 548 + { 0x00000753, 0x0080 }, /* R1875 (0x753) - AIF2TX3MIX Input 2 Volume */ 549 549 + { 0x00000754, 0x0000 }, /* R1876 (0x754) - AIF2TX3MIX Input 3 Source */ 550 550 + { 0x00000755, 0x0080 }, /* R1877 (0x755) - AIF2TX3MIX Input 3 Volume */ 551 551 + { 0x00000756, 0x0000 }, /* R1878 (0x756) - AIF2TX3MIX Input 4 Source */ 552 552 + { 0x00000757, 0x0080 }, /* R1879 (0x757) - AIF2TX3MIX Input 4 Volume */ 553 553 + { 0x00000758, 0x0000 }, /* R1880 (0x758) - AIF2TX4MIX Input 1 Source */ 554 554 + { 0x00000759, 0x0080 }, /* R1881 (0x759) - AIF2TX4MIX Input 1 Volume */ 555 555 + { 0x0000075a, 0x0000 }, /* R1882 (0x75a) - AIF2TX4MIX Input 2 Source */ 556 556 + { 0x0000075b, 0x0080 }, /* R1883 (0x75b) - AIF2TX4MIX Input 2 Volume */ 557 557 + { 0x0000075c, 0x0000 }, /* R1884 (0x75c) - AIF2TX4MIX Input 3 Source */ 558 558 + { 0x0000075d, 0x0080 }, /* R1885 (0x75d) - AIF2TX4MIX Input 3 Volume */ 559 559 + { 0x0000075e, 0x0000 }, /* R1886 (0x75e) - AIF2TX4MIX Input 4 Source */ 560 560 + { 0x0000075f, 0x0080 }, /* R1887 (0x75f) - AIF2TX4MIX Input 4 Volume */ 561 561 + { 0x00000760, 0x0000 }, /* R1888 (0x760) - AIF2TX5MIX Input 1 Source */ 562 562 + { 0x00000761, 0x0080 }, /* R1889 (0x761) - AIF2TX5MIX Input 1 Volume */ 563 563 + { 0x00000762, 0x0000 }, /* R1890 (0x762) - AIF2TX5MIX Input 2 Source */ 564 564 + { 0x00000763, 0x0080 }, /* R1891 (0x763) - AIF2TX5MIX Input 2 Volume */ 565 565 + { 0x00000764, 0x0000 }, /* R1892 (0x764) - AIF2TX5MIX Input 3 Source */ 566 566 + { 0x00000765, 0x0080 }, /* R1893 (0x765) - AIF2TX5MIX Input 3 Volume */ 567 567 + { 0x00000766, 0x0000 }, /* R1894 (0x766) - AIF2TX5MIX Input 4 Source */ 568 568 + { 0x00000767, 0x0080 }, /* R1895 (0x767) - AIF2TX5MIX Input 4 Volume */ 569 569 + { 0x00000768, 0x0000 }, /* R1896 (0x768) - AIF2TX6MIX Input 1 Source */ 570 570 + { 0x00000769, 0x0080 }, /* R1897 (0x769) - AIF2TX6MIX Input 1 Volume */ 571 571 + { 0x0000076a, 0x0000 }, /* R1898 (0x76a) - AIF2TX6MIX Input 2 Source */ 572 572 + { 0x0000076b, 0x0080 }, /* R1899 (0x76b) - AIF2TX6MIX Input 2 Volume */ 573 573 + { 0x0000076c, 0x0000 }, /* R1900 (0x76c) - AIF2TX6MIX Input 3 Source */ 574 574 + { 0x0000076d, 0x0080 }, /* R1901 (0x76d) - AIF2TX6MIX Input 3 Volume */ 575 575 + { 0x0000076e, 0x0000 }, /* R1902 (0x76e) - AIF2TX6MIX Input 4 Source */ 576 576 + { 0x0000076f, 0x0080 }, /* R1903 (0x76f) - AIF2TX6MIX Input 4 Volume */ 577 577 + { 0x00000770, 0x0000 }, /* R1904 (0x770) - AIF2TX7MIX Input 1 Source */ 578 578 + { 0x00000771, 0x0080 }, /* R1905 (0x771) - AIF2TX7MIX Input 1 Volume */ 579 579 + { 0x00000772, 0x0000 }, /* R1906 (0x772) - AIF2TX7MIX Input 2 Source */ 580 580 + { 0x00000773, 0x0080 }, /* R1907 (0x773) - AIF2TX7MIX Input 2 Volume */ 581 581 + { 0x00000774, 0x0000 }, /* R1908 (0x774) - AIF2TX7MIX Input 3 Source */ 582 582 + { 0x00000775, 0x0080 }, /* R1909 (0x775) - AIF2TX7MIX Input 3 Volume */ 583 583 + { 0x00000776, 0x0000 }, /* R1910 (0x776) - AIF2TX7MIX Input 4 Source */ 584 584 + { 0x00000777, 0x0080 }, /* R1911 (0x777) - AIF2TX7MIX Input 4 Volume */ 585 585 + { 0x00000778, 0x0000 }, /* R1912 (0x778) - AIF2TX8MIX Input 1 Source */ 586 586 + { 0x00000779, 0x0080 }, /* R1913 (0x779) - AIF2TX8MIX Input 1 Volume */ 587 587 + { 0x0000077a, 0x0000 }, /* R1914 (0x77a) - AIF2TX8MIX Input 2 Source */ 588 588 + { 0x0000077b, 0x0080 }, /* R1915 (0x77b) - AIF2TX8MIX Input 2 Volume */ 589 589 + { 0x0000077c, 0x0000 }, /* R1916 (0x77c) - AIF2TX8MIX Input 3 Source */ 590 590 + { 0x0000077d, 0x0080 }, /* R1917 (0x77d) - AIF2TX8MIX Input 3 Volume */ 591 591 + { 0x0000077e, 0x0000 }, /* R1918 (0x77e) - AIF2TX8MIX Input 4 Source */ 592 592 + { 0x0000077f, 0x0080 }, /* R1919 (0x77f) - AIF2TX8MIX Input 4 Volume */ 593 593 + { 0x00000780, 0x0000 }, /* R1920 (0x780) - AIF3TX1MIX Input 1 Source */ 594 594 + { 0x00000781, 0x0080 }, /* R1921 (0x781) - AIF3TX1MIX Input 1 Volume */ 595 595 + { 0x00000782, 0x0000 }, /* R1922 (0x782) - AIF3TX1MIX Input 2 Source */ 596 596 + { 0x00000783, 0x0080 }, /* R1923 (0x783) - AIF3TX1MIX Input 2 Volume */ 597 597 + { 0x00000784, 0x0000 }, /* R1924 (0x784) - AIF3TX1MIX Input 3 Source */ 598 598 + { 0x00000785, 0x0080 }, /* R1925 (0x785) - AIF3TX1MIX Input 3 Volume */ 599 599 + { 0x00000786, 0x0000 }, /* R1926 (0x786) - AIF3TX1MIX Input 4 Source */ 600 600 + { 0x00000787, 0x0080 }, /* R1927 (0x787) - AIF3TX1MIX Input 4 Volume */ 601 601 + { 0x00000788, 0x0000 }, /* R1928 (0x788) - AIF3TX2MIX Input 1 Source */ 602 602 + { 0x00000789, 0x0080 }, /* R1929 (0x789) - AIF3TX2MIX Input 1 Volume */ 603 603 + { 0x0000078a, 0x0000 }, /* R1930 (0x78a) - AIF3TX2MIX Input 2 Source */ 604 604 + { 0x0000078b, 0x0080 }, /* R1931 (0x78b) - AIF3TX2MIX Input 2 Volume */ 605 605 + { 0x0000078c, 0x0000 }, /* R1932 (0x78c) - AIF3TX2MIX Input 3 Source */ 606 606 + { 0x0000078d, 0x0080 }, /* R1933 (0x78d) - AIF3TX2MIX Input 3 Volume */ 607 607 + { 0x0000078e, 0x0000 }, /* R1934 (0x78e) - AIF3TX2MIX Input 4 Source */ 608 608 + { 0x0000078f, 0x0080 }, /* R1935 (0x78f) - AIF3TX2MIX Input 4 Volume */ 609 609 + { 0x00000790, 0x0000 }, /* R1936 (0x790) - AIF3TX3MIX Input 1 Source */ 610 610 + { 0x00000791, 0x0080 }, /* R1937 (0x791) - AIF3TX3MIX Input 1 Volume */ 611 611 + { 0x00000792, 0x0000 }, /* R1938 (0x792) - AIF3TX3MIX Input 2 Source */ 612 612 + { 0x00000793, 0x0080 }, /* R1939 (0x793) - AIF3TX3MIX Input 2 Volume */ 613 613 + { 0x00000794, 0x0000 }, /* R1940 (0x794) - AIF3TX3MIX Input 3 Source */ 614 614 + { 0x00000795, 0x0080 }, /* R1941 (0x795) - AIF3TX3MIX Input 3 Volume */ 615 615 + { 0x00000796, 0x0000 }, /* R1942 (0x796) - AIF3TX3MIX Input 4 Source */ 616 616 + { 0x00000797, 0x0080 }, /* R1943 (0x797) - AIF3TX3MIX Input 4 Volume */ 617 617 + { 0x00000798, 0x0000 }, /* R1944 (0x798) - AIF3TX4MIX Input 1 Source */ 618 618 + { 0x00000799, 0x0080 }, /* R1945 (0x799) - AIF3TX4MIX Input 1 Volume */ 619 619 + { 0x0000079a, 0x0000 }, /* R1946 (0x79a) - AIF3TX4MIX Input 2 Source */ 620 620 + { 0x0000079b, 0x0080 }, /* R1947 (0x79b) - AIF3TX4MIX Input 2 Volume */ 621 621 + { 0x0000079c, 0x0000 }, /* R1948 (0x79c) - AIF3TX4MIX Input 3 Source */ 622 622 + { 0x0000079d, 0x0080 }, /* R1949 (0x79d) - AIF3TX4MIX Input 3 Volume */ 623 623 + { 0x0000079e, 0x0000 }, /* R1950 (0x79e) - AIF3TX4MIX Input 4 Source */ 624 624 + { 0x0000079f, 0x0080 }, /* R1951 (0x79f) - AIF3TX4MIX Input 4 Volume */ 625 625 + { 0x000007a0, 0x0000 }, /* R1952 (0x7a0) - AIF3TX5MIX Input 1 Source */ 626 626 + { 0x000007a1, 0x0080 }, /* R1953 (0x7a1) - AIF3TX5MIX Input 1 Volume */ 627 627 + { 0x000007a2, 0x0000 }, /* R1954 (0x7a2) - AIF3TX5MIX Input 2 Source */ 628 628 + { 0x000007a3, 0x0080 }, /* R1955 (0x7a3) - AIF3TX5MIX Input 2 Volume */ 629 629 + { 0x000007a4, 0x0000 }, /* R1956 (0x7a4) - AIF3TX5MIX Input 3 Source */ 630 630 + { 0x000007a5, 0x0080 }, /* R1957 (0x7a5) - AIF3TX5MIX Input 3 Volume */ 631 631 + { 0x000007a6, 0x0000 }, /* R1958 (0x7a6) - AIF3TX5MIX Input 4 Source */ 632 632 + { 0x000007a7, 0x0080 }, /* R1959 (0x7a7) - AIF3TX5MIX Input 4 Volume */ 633 633 + { 0x000007a8, 0x0000 }, /* R1960 (0x7a8) - AIF3TX6MIX Input 1 Source */ 634 634 + { 0x000007a9, 0x0080 }, /* R1961 (0x7a9) - AIF3TX6MIX Input 1 Volume */ 635 635 + { 0x000007aa, 0x0000 }, /* R1962 (0x7aa) - AIF3TX6MIX Input 2 Source */ 636 636 + { 0x000007ab, 0x0080 }, /* R1963 (0x7ab) - AIF3TX6MIX Input 2 Volume */ 637 637 + { 0x000007ac, 0x0000 }, /* R1964 (0x7ac) - AIF3TX6MIX Input 3 Source */ 638 638 + { 0x000007ad, 0x0080 }, /* R1965 (0x7ad) - AIF3TX6MIX Input 3 Volume */ 639 639 + { 0x000007ae, 0x0000 }, /* R1966 (0x7ae) - AIF3TX6MIX Input 4 Source */ 640 640 + { 0x000007af, 0x0080 }, /* R1967 (0x7af) - AIF3TX6MIX Input 4 Volume */ 641 641 + { 0x000007b0, 0x0000 }, /* R1968 (0x7b0) - AIF3TX7MIX Input 1 Source */ 642 642 + { 0x000007b1, 0x0080 }, /* R1969 (0x7b1) - AIF3TX7MIX Input 1 Volume */ 643 643 + { 0x000007b2, 0x0000 }, /* R1970 (0x7b2) - AIF3TX7MIX Input 2 Source */ 644 644 + { 0x000007b3, 0x0080 }, /* R1971 (0x7b3) - AIF3TX7MIX Input 2 Volume */ 645 645 + { 0x000007b4, 0x0000 }, /* R1972 (0x7b4) - AIF3TX7MIX Input 3 Source */ 646 646 + { 0x000007b5, 0x0080 }, /* R1973 (0x7b5) - AIF3TX7MIX Input 3 Volume */ 647 647 + { 0x000007b6, 0x0000 }, /* R1974 (0x7b6) - AIF3TX7MIX Input 4 Source */ 648 648 + { 0x000007b7, 0x0080 }, /* R1975 (0x7b7) - AIF3TX7MIX Input 4 Volume */ 649 649 + { 0x000007b8, 0x0000 }, /* R1976 (0x7b8) - AIF3TX8MIX Input 1 Source */ 650 650 + { 0x000007b9, 0x0080 }, /* R1977 (0x7b9) - AIF3TX8MIX Input 1 Volume */ 651 651 + { 0x000007ba, 0x0000 }, /* R1978 (0x7ba) - AIF3TX8MIX Input 2 Source */ 652 652 + { 0x000007bb, 0x0080 }, /* R1979 (0x7bb) - AIF3TX8MIX Input 2 Volume */ 653 653 + { 0x000007bc, 0x0000 }, /* R1980 (0x7bc) - AIF3TX8MIX Input 3 Source */ 654 654 + { 0x000007bd, 0x0080 }, /* R1981 (0x7bd) - AIF3TX8MIX Input 3 Volume */ 655 655 + { 0x000007be, 0x0000 }, /* R1982 (0x7be) - AIF3TX8MIX Input 4 Source */ 656 656 + { 0x000007bf, 0x0080 }, /* R1983 (0x7bf) - AIF3TX8MIX Input 4 Volume */ 657 657 + { 0x000007c0, 0x0000 }, /* R1984 (0x7c0) - SLIMTX1MIX Input 1 Source */ 658 658 + { 0x000007c1, 0x0080 }, /* R1985 (0x7c1) - SLIMTX1MIX Input 1 Volume */ 659 659 + { 0x000007c2, 0x0000 }, /* R1986 (0x7c2) - SLIMTX1MIX Input 2 Source */ 660 660 + { 0x000007c3, 0x0080 }, /* R1987 (0x7c3) - SLIMTX1MIX Input 2 Volume */ 661 661 + { 0x000007c4, 0x0000 }, /* R1988 (0x7c4) - SLIMTX1MIX Input 3 Source */ 662 662 + { 0x000007c5, 0x0080 }, /* R1989 (0x7c5) - SLIMTX1MIX Input 3 Volume */ 663 663 + { 0x000007c6, 0x0000 }, /* R1990 (0x7c6) - SLIMTX1MIX Input 4 Source */ 664 664 + { 0x000007c7, 0x0080 }, /* R1991 (0x7c7) - SLIMTX1MIX Input 4 Volume */ 665 665 + { 0x000007c8, 0x0000 }, /* R1992 (0x7c8) - SLIMTX2MIX Input 1 Source */ 666 666 + { 0x000007c9, 0x0080 }, /* R1993 (0x7c9) - SLIMTX2MIX Input 1 Volume */ 667 667 + { 0x000007ca, 0x0000 }, /* R1994 (0x7ca) - SLIMTX2MIX Input 2 Source */ 668 668 + { 0x000007cb, 0x0080 }, /* R1995 (0x7cb) - SLIMTX2MIX Input 2 Volume */ 669 669 + { 0x000007cc, 0x0000 }, /* R1996 (0x7cc) - SLIMTX2MIX Input 3 Source */ 670 670 + { 0x000007cd, 0x0080 }, /* R1997 (0x7cd) - SLIMTX2MIX Input 3 Volume */ 671 671 + { 0x000007ce, 0x0000 }, /* R1998 (0x7ce) - SLIMTX2MIX Input 4 Source */ 672 672 + { 0x000007cf, 0x0080 }, /* R1999 (0x7cf) - SLIMTX2MIX Input 4 Volume */ 673 673 + { 0x000007d0, 0x0000 }, /* R2000 (0x7d0) - SLIMTX3MIX Input 1 Source */ 674 674 + { 0x000007d1, 0x0080 }, /* R2001 (0x7d1) - SLIMTX3MIX Input 1 Volume */ 675 675 + { 0x000007d2, 0x0000 }, /* R2002 (0x7d2) - SLIMTX3MIX Input 2 Source */ 676 676 + { 0x000007d3, 0x0080 }, /* R2003 (0x7d3) - SLIMTX3MIX Input 2 Volume */ 677 677 + { 0x000007d4, 0x0000 }, /* R2004 (0x7d4) - SLIMTX3MIX Input 3 Source */ 678 678 + { 0x000007d5, 0x0080 }, /* R2005 (0x7d5) - SLIMTX3MIX Input 3 Volume */ 679 679 + { 0x000007d6, 0x0000 }, /* R2006 (0x7d6) - SLIMTX3MIX Input 4 Source */ 680 680 + { 0x000007d7, 0x0080 }, /* R2007 (0x7d7) - SLIMTX3MIX Input 4 Volume */ 681 681 + { 0x000007d8, 0x0000 }, /* R2008 (0x7d8) - SLIMTX4MIX Input 1 Source */ 682 682 + { 0x000007d9, 0x0080 }, /* R2009 (0x7d9) - SLIMTX4MIX Input 1 Volume */ 683 683 + { 0x000007da, 0x0000 }, /* R2010 (0x7da) - SLIMTX4MIX Input 2 Source */ 684 684 + { 0x000007db, 0x0080 }, /* R2011 (0x7db) - SLIMTX4MIX Input 2 Volume */ 685 685 + { 0x000007dc, 0x0000 }, /* R2012 (0x7dc) - SLIMTX4MIX Input 3 Source */ 686 686 + { 0x000007dd, 0x0080 }, /* R2013 (0x7dd) - SLIMTX4MIX Input 3 Volume */ 687 687 + { 0x000007de, 0x0000 }, /* R2014 (0x7de) - SLIMTX4MIX Input 4 Source */ 688 688 + { 0x000007df, 0x0080 }, /* R2015 (0x7df) - SLIMTX4MIX Input 4 Volume */ 689 689 + { 0x000007e0, 0x0000 }, /* R2016 (0x7e0) - SLIMTX5MIX Input 1 Source */ 690 690 + { 0x000007e1, 0x0080 }, /* R2017 (0x7e1) - SLIMTX5MIX Input 1 Volume */ 691 691 + { 0x000007e2, 0x0000 }, /* R2018 (0x7e2) - SLIMTX5MIX Input 2 Source */ 692 692 + { 0x000007e3, 0x0080 }, /* R2019 (0x7e3) - SLIMTX5MIX Input 2 Volume */ 693 693 + { 0x000007e4, 0x0000 }, /* R2020 (0x7e4) - SLIMTX5MIX Input 3 Source */ 694 694 + { 0x000007e5, 0x0080 }, /* R2021 (0x7e5) - SLIMTX5MIX Input 3 Volume */ 695 695 + { 0x000007e6, 0x0000 }, /* R2022 (0x7e6) - SLIMTX5MIX Input 4 Source */ 696 696 + { 0x000007e7, 0x0080 }, /* R2023 (0x7e7) - SLIMTX5MIX Input 4 Volume */ 697 697 + { 0x000007e8, 0x0000 }, /* R2024 (0x7e8) - SLIMTX6MIX Input 1 Source */ 698 698 + { 0x000007e9, 0x0080 }, /* R2025 (0x7e9) - SLIMTX6MIX Input 1 Volume */ 699 699 + { 0x000007ea, 0x0000 }, /* R2026 (0x7ea) - SLIMTX6MIX Input 2 Source */ 700 700 + { 0x000007eb, 0x0080 }, /* R2027 (0x7eb) - SLIMTX6MIX Input 2 Volume */ 701 701 + { 0x000007ec, 0x0000 }, /* R2028 (0x7ec) - SLIMTX6MIX Input 3 Source */ 702 702 + { 0x000007ed, 0x0080 }, /* R2029 (0x7ed) - SLIMTX6MIX Input 3 Volume */ 703 703 + { 0x000007ee, 0x0000 }, /* R2030 (0x7ee) - SLIMTX6MIX Input 4 Source */ 704 704 + { 0x000007ef, 0x0080 }, /* R2031 (0x7ef) - SLIMTX6MIX Input 4 Volume */ 705 705 + { 0x000007f0, 0x0000 }, /* R2032 (0x7f0) - SLIMTX7MIX Input 1 Source */ 706 706 + { 0x000007f1, 0x0080 }, /* R2033 (0x7f1) - SLIMTX7MIX Input 1 Volume */ 707 707 + { 0x000007f2, 0x0000 }, /* R2034 (0x7f2) - SLIMTX7MIX Input 2 Source */ 708 708 + { 0x000007f3, 0x0080 }, /* R2035 (0x7f3) - SLIMTX7MIX Input 2 Volume */ 709 709 + { 0x000007f4, 0x0000 }, /* R2036 (0x7f4) - SLIMTX7MIX Input 3 Source */ 710 710 + { 0x000007f5, 0x0080 }, /* R2037 (0x7f5) - SLIMTX7MIX Input 3 Volume */ 711 711 + { 0x000007f6, 0x0000 }, /* R2038 (0x7f6) - SLIMTX7MIX Input 4 Source */ 712 712 + { 0x000007f7, 0x0080 }, /* R2039 (0x7f7) - SLIMTX7MIX Input 4 Volume */ 713 713 + { 0x000007f8, 0x0000 }, /* R2040 (0x7f8) - SLIMTX8MIX Input 1 Source */ 714 714 + { 0x000007f9, 0x0080 }, /* R2041 (0x7f9) - SLIMTX8MIX Input 1 Volume */ 715 715 + { 0x000007fa, 0x0000 }, /* R2042 (0x7fa) - SLIMTX8MIX Input 2 Source */ 716 716 + { 0x000007fb, 0x0080 }, /* R2043 (0x7fb) - SLIMTX8MIX Input 2 Volume */ 717 717 + { 0x000007fc, 0x0000 }, /* R2044 (0x7fc) - SLIMTX8MIX Input 3 Source */ 718 718 + { 0x000007fd, 0x0080 }, /* R2045 (0x7fd) - SLIMTX8MIX Input 3 Volume */ 719 719 + { 0x000007fe, 0x0000 }, /* R2046 (0x7fe) - SLIMTX8MIX Input 4 Source */ 720 720 + { 0x000007ff, 0x0080 }, /* R2047 (0x7ff) - SLIMTX8MIX Input 4 Volume */ 721 721 + { 0x00000800, 0x0000 }, /* R2048 (0x800) - SPDIF1TX1MIX Input 1 Source */ 722 722 + { 0x00000801, 0x0080 }, /* R2049 (0x801) - SPDIF1TX1MIX Input 1 Volume */ 723 723 + { 0x00000808, 0x0000 }, /* R2056 (0x808) - SPDIF1TX2MIX Input 1 Source */ 724 724 + { 0x00000809, 0x0080 }, /* R2057 (0x809) - SPDIF1TX2MIX Input 1 Volume */ 725 725 + { 0x00000880, 0x0000 }, /* R2176 (0x880) - EQ1MIX Input 1 Source */ 726 726 + { 0x00000881, 0x0080 }, /* R2177 (0x881) - EQ1MIX Input 1 Volume */ 727 727 + { 0x00000882, 0x0000 }, /* R2178 (0x882) - EQ1MIX Input 2 Source */ 728 728 + { 0x00000883, 0x0080 }, /* R2179 (0x883) - EQ1MIX Input 2 Volume */ 729 729 + { 0x00000884, 0x0000 }, /* R2180 (0x884) - EQ1MIX Input 3 Source */ 730 730 + { 0x00000885, 0x0080 }, /* R2181 (0x885) - EQ1MIX Input 3 Volume */ 731 731 + { 0x00000886, 0x0000 }, /* R2182 (0x886) - EQ1MIX Input 4 Source */ 732 732 + { 0x00000887, 0x0080 }, /* R2183 (0x887) - EQ1MIX Input 4 Volume */ 733 733 + { 0x00000888, 0x0000 }, /* R2184 (0x888) - EQ2MIX Input 1 Source */ 734 734 + { 0x00000889, 0x0080 }, /* R2185 (0x889) - EQ2MIX Input 1 Volume */ 735 735 + { 0x0000088a, 0x0000 }, /* R2186 (0x88a) - EQ2MIX Input 2 Source */ 736 736 + { 0x0000088b, 0x0080 }, /* R2187 (0x88b) - EQ2MIX Input 2 Volume */ 737 737 + { 0x0000088c, 0x0000 }, /* R2188 (0x88c) - EQ2MIX Input 3 Source */ 738 738 + { 0x0000088d, 0x0080 }, /* R2189 (0x88d) - EQ2MIX Input 3 Volume */ 739 739 + { 0x0000088e, 0x0000 }, /* R2190 (0x88e) - EQ2MIX Input 4 Source */ 740 740 + { 0x0000088f, 0x0080 }, /* R2191 (0x88f) - EQ2MIX Input 4 Volume */ 741 741 + { 0x00000890, 0x0000 }, /* R2192 (0x890) - EQ3MIX Input 1 Source */ 742 742 + { 0x00000891, 0x0080 }, /* R2193 (0x891) - EQ3MIX Input 1 Volume */ 743 743 + { 0x00000892, 0x0000 }, /* R2194 (0x892) - EQ3MIX Input 2 Source */ 744 744 + { 0x00000893, 0x0080 }, /* R2195 (0x893) - EQ3MIX Input 2 Volume */ 745 745 + { 0x00000894, 0x0000 }, /* R2196 (0x894) - EQ3MIX Input 3 Source */ 746 746 + { 0x00000895, 0x0080 }, /* R2197 (0x895) - EQ3MIX Input 3 Volume */ 747 747 + { 0x00000896, 0x0000 }, /* R2198 (0x896) - EQ3MIX Input 4 Source */ 748 748 + { 0x00000897, 0x0080 }, /* R2199 (0x897) - EQ3MIX Input 4 Volume */ 749 749 + { 0x00000898, 0x0000 }, /* R2200 (0x898) - EQ4MIX Input 1 Source */ 750 750 + { 0x00000899, 0x0080 }, /* R2201 (0x899) - EQ4MIX Input 1 Volume */ 751 751 + { 0x0000089a, 0x0000 }, /* R2202 (0x89a) - EQ4MIX Input 2 Source */ 752 752 + { 0x0000089b, 0x0080 }, /* R2203 (0x89b) - EQ4MIX Input 2 Volume */ 753 753 + { 0x0000089c, 0x0000 }, /* R2204 (0x89c) - EQ4MIX Input 3 Source */ 754 754 + { 0x0000089d, 0x0080 }, /* R2205 (0x89d) - EQ4MIX Input 3 Volume */ 755 755 + { 0x0000089e, 0x0000 }, /* R2206 (0x89e) - EQ4MIX Input 4 Source */ 756 756 + { 0x0000089f, 0x0080 }, /* R2207 (0x89f) - EQ4MIX Input 4 Volume */ 757 757 + { 0x000008c0, 0x0000 }, /* R2240 (0x8c0) - DRC1LMIX Input 1 Source */ 758 758 + { 0x000008c1, 0x0080 }, /* R2241 (0x8c1) - DRC1LMIX Input 1 Volume */ 759 759 + { 0x000008c2, 0x0000 }, /* R2242 (0x8c2) - DRC1LMIX Input 2 Source */ 760 760 + { 0x000008c3, 0x0080 }, /* R2243 (0x8c3) - DRC1LMIX Input 2 Volume */ 761 761 + { 0x000008c4, 0x0000 }, /* R2244 (0x8c4) - DRC1LMIX Input 3 Source */ 762 762 + { 0x000008c5, 0x0080 }, /* R2245 (0x8c5) - DRC1LMIX Input 3 Volume */ 763 763 + { 0x000008c6, 0x0000 }, /* R2246 (0x8c6) - DRC1LMIX Input 4 Source */ 764 764 + { 0x000008c7, 0x0080 }, /* R2247 (0x8c7) - DRC1LMIX Input 4 Volume */ 765 765 + { 0x000008c8, 0x0000 }, /* R2248 (0x8c8) - DRC1RMIX Input 1 Source */ 766 766 + { 0x000008c9, 0x0080 }, /* R2249 (0x8c9) - DRC1RMIX Input 1 Volume */ 767 767 + { 0x000008ca, 0x0000 }, /* R2250 (0x8ca) - DRC1RMIX Input 2 Source */ 768 768 + { 0x000008cb, 0x0080 }, /* R2251 (0x8cb) - DRC1RMIX Input 2 Volume */ 769 769 + { 0x000008cc, 0x0000 }, /* R2252 (0x8cc) - DRC1RMIX Input 3 Source */ 770 770 + { 0x000008cd, 0x0080 }, /* R2253 (0x8cd) - DRC1RMIX Input 3 Volume */ 771 771 + { 0x000008ce, 0x0000 }, /* R2254 (0x8ce) - DRC1RMIX Input 4 Source */ 772 772 + { 0x000008cf, 0x0080 }, /* R2255 (0x8cf) - DRC1RMIX Input 4 Volume */ 773 773 + { 0x000008d0, 0x0000 }, /* R2256 (0x8d0) - DRC2LMIX Input 1 Source */ 774 774 + { 0x000008d1, 0x0080 }, /* R2257 (0x8d1) - DRC2LMIX Input 1 Volume */ 775 775 + { 0x000008d2, 0x0000 }, /* R2258 (0x8d2) - DRC2LMIX Input 2 Source */ 776 776 + { 0x000008d3, 0x0080 }, /* R2259 (0x8d3) - DRC2LMIX Input 2 Volume */ 777 777 + { 0x000008d4, 0x0000 }, /* R2260 (0x8d4) - DRC2LMIX Input 3 Source */ 778 778 + { 0x000008d5, 0x0080 }, /* R2261 (0x8d5) - DRC2LMIX Input 3 Volume */ 779 779 + { 0x000008d6, 0x0000 }, /* R2262 (0x8d6) - DRC2LMIX Input 4 Source */ 780 780 + { 0x000008d7, 0x0080 }, /* R2263 (0x8d7) - DRC2LMIX Input 4 Volume */ 781 781 + { 0x000008d8, 0x0000 }, /* R2264 (0x8d8) - DRC2RMIX Input 1 Source */ 782 782 + { 0x000008d9, 0x0080 }, /* R2265 (0x8d9) - DRC2RMIX Input 1 Volume */ 783 783 + { 0x000008da, 0x0000 }, /* R2266 (0x8da) - DRC2RMIX Input 2 Source */ 784 784 + { 0x000008db, 0x0080 }, /* R2267 (0x8db) - DRC2RMIX Input 2 Volume */ 785 785 + { 0x000008dc, 0x0000 }, /* R2268 (0x8dc) - DRC2RMIX Input 3 Source */ 786 786 + { 0x000008dd, 0x0080 }, /* R2269 (0x8dd) - DRC2RMIX Input 3 Volume */ 787 787 + { 0x000008de, 0x0000 }, /* R2270 (0x8de) - DRC2RMIX Input 4 Source */ 788 788 + { 0x000008df, 0x0080 }, /* R2271 (0x8df) - DRC2RMIX Input 4 Volume */ 789 789 + { 0x00000900, 0x0000 }, /* R2304 (0x900) - HPLP1MIX Input 1 Source */ 790 790 + { 0x00000901, 0x0080 }, /* R2305 (0x901) - HPLP1MIX Input 1 Volume */ 791 791 + { 0x00000902, 0x0000 }, /* R2306 (0x902) - HPLP1MIX Input 2 Source */ 792 792 + { 0x00000903, 0x0080 }, /* R2307 (0x903) - HPLP1MIX Input 2 Volume */ 793 793 + { 0x00000904, 0x0000 }, /* R2308 (0x904) - HPLP1MIX Input 3 Source */ 794 794 + { 0x00000905, 0x0080 }, /* R2309 (0x905) - HPLP1MIX Input 3 Volume */ 795 795 + { 0x00000906, 0x0000 }, /* R2310 (0x906) - HPLP1MIX Input 4 Source */ 796 796 + { 0x00000907, 0x0080 }, /* R2311 (0x907) - HPLP1MIX Input 4 Volume */ 797 797 + { 0x00000908, 0x0000 }, /* R2312 (0x908) - HPLP2MIX Input 1 Source */ 798 798 + { 0x00000909, 0x0080 }, /* R2313 (0x909) - HPLP2MIX Input 1 Volume */ 799 799 + { 0x0000090a, 0x0000 }, /* R2314 (0x90a) - HPLP2MIX Input 2 Source */ 800 800 + { 0x0000090b, 0x0080 }, /* R2315 (0x90b) - HPLP2MIX Input 2 Volume */ 801 801 + { 0x0000090c, 0x0000 }, /* R2316 (0x90c) - HPLP2MIX Input 3 Source */ 802 802 + { 0x0000090d, 0x0080 }, /* R2317 (0x90d) - HPLP2MIX Input 3 Volume */ 803 803 + { 0x0000090e, 0x0000 }, /* R2318 (0x90e) - HPLP2MIX Input 4 Source */ 804 804 + { 0x0000090f, 0x0080 }, /* R2319 (0x90f) - HPLP2MIX Input 4 Volume */ 805 805 + { 0x00000910, 0x0000 }, /* R2320 (0x910) - HPLP3MIX Input 1 Source */ 806 806 + { 0x00000911, 0x0080 }, /* R2321 (0x911) - HPLP3MIX Input 1 Volume */ 807 807 + { 0x00000912, 0x0000 }, /* R2322 (0x912) - HPLP3MIX Input 2 Source */ 808 808 + { 0x00000913, 0x0080 }, /* R2323 (0x913) - HPLP3MIX Input 2 Volume */ 809 809 + { 0x00000914, 0x0000 }, /* R2324 (0x914) - HPLP3MIX Input 3 Source */ 810 810 + { 0x00000915, 0x0080 }, /* R2325 (0x915) - HPLP3MIX Input 3 Volume */ 811 811 + { 0x00000916, 0x0000 }, /* R2326 (0x916) - HPLP3MIX Input 4 Source */ 812 812 + { 0x00000917, 0x0080 }, /* R2327 (0x917) - HPLP3MIX Input 4 Volume */ 813 813 + { 0x00000918, 0x0000 }, /* R2328 (0x918) - HPLP4MIX Input 1 Source */ 814 814 + { 0x00000919, 0x0080 }, /* R2329 (0x919) - HPLP4MIX Input 1 Volume */ 815 815 + { 0x0000091a, 0x0000 }, /* R2330 (0x91a) - HPLP4MIX Input 2 Source */ 816 816 + { 0x0000091b, 0x0080 }, /* R2331 (0x91b) - HPLP4MIX Input 2 Volume */ 817 817 + { 0x0000091c, 0x0000 }, /* R2332 (0x91c) - HPLP4MIX Input 3 Source */ 818 818 + { 0x0000091d, 0x0080 }, /* R2333 (0x91d) - HPLP4MIX Input 3 Volume */ 819 819 + { 0x0000091e, 0x0000 }, /* R2334 (0x91e) - HPLP4MIX Input 4 Source */ 820 820 + { 0x0000091f, 0x0080 }, /* R2335 (0x91f) - HPLP4MIX Input 4 Volume */ 821 821 + { 0x00000940, 0x0000 }, /* R2368 (0x940) - DSP1LMIX Input 1 Source */ 822 822 + { 0x00000941, 0x0080 }, /* R2369 (0x941) - DSP1LMIX Input 1 Volume */ 823 823 + { 0x00000942, 0x0000 }, /* R2370 (0x942) - DSP1LMIX Input 2 Source */ 824 824 + { 0x00000943, 0x0080 }, /* R2371 (0x943) - DSP1LMIX Input 2 Volume */ 825 825 + { 0x00000944, 0x0000 }, /* R2372 (0x944) - DSP1LMIX Input 3 Source */ 826 826 + { 0x00000945, 0x0080 }, /* R2373 (0x945) - DSP1LMIX Input 3 Volume */ 827 827 + { 0x00000946, 0x0000 }, /* R2374 (0x946) - DSP1LMIX Input 4 Source */ 828 828 + { 0x00000947, 0x0080 }, /* R2375 (0x947) - DSP1LMIX Input 4 Volume */ 829 829 + { 0x00000948, 0x0000 }, /* R2376 (0x948) - DSP1RMIX Input 1 Source */ 830 830 + { 0x00000949, 0x0080 }, /* R2377 (0x949) - DSP1RMIX Input 1 Volume */ 831 831 + { 0x0000094a, 0x0000 }, /* R2378 (0x94a) - DSP1RMIX Input 2 Source */ 832 832 + { 0x0000094b, 0x0080 }, /* R2379 (0x94b) - DSP1RMIX Input 2 Volume */ 833 833 + { 0x0000094c, 0x0000 }, /* R2380 (0x94c) - DSP1RMIX Input 3 Source */ 834 834 + { 0x0000094d, 0x0080 }, /* R2381 (0x94d) - DSP1RMIX Input 3 Volume */ 835 835 + { 0x0000094e, 0x0000 }, /* R2382 (0x94e) - DSP1RMIX Input 4 Source */ 836 836 + { 0x0000094f, 0x0080 }, /* R2383 (0x94f) - DSP1RMIX Input 4 Volume */ 837 837 + { 0x00000950, 0x0000 }, /* R2384 (0x950) - DSP1AUX1MIX Input 1 Source */ 838 838 + { 0x00000958, 0x0000 }, /* R2392 (0x958) - DSP1AUX2MIX Input 1 Source */ 839 839 + { 0x00000960, 0x0000 }, /* R2400 (0x960) - DSP1AUX3MIX Input 1 Source */ 840 840 + { 0x00000968, 0x0000 }, /* R2408 (0x968) - DSP1AUX4MIX Input 1 Source */ 841 841 + { 0x00000970, 0x0000 }, /* R2416 (0x970) - DSP1AUX5MIX Input 1 Source */ 842 842 + { 0x00000978, 0x0000 }, /* R2424 (0x978) - DSP1AUX6MIX Input 1 Source */ 843 843 + { 0x00000a80, 0x0000 }, /* R2688 (0xa80) - ASRC1 1LMIX Input 1 Source */ 844 844 + { 0x00000a88, 0x0000 }, /* R2696 (0xa88) - ASRC1 1RMIX Input 1 Source */ 845 845 + { 0x00000a90, 0x0000 }, /* R2704 (0xa90) - ASRC1 2LMIX Input 1 Source */ 846 846 + { 0x00000a98, 0x0000 }, /* R2712 (0xa98) - ASRC1 2RMIX Input 1 Source */ 847 847 + { 0x00000b00, 0x0000 }, /* R2816 (0xb00) - ISRC1DEC1MIX Input 1 Source */ 848 848 + { 0x00000b08, 0x0000 }, /* R2824 (0xb08) - ISRC1DEC2MIX Input 1 Source */ 849 849 + { 0x00000b20, 0x0000 }, /* R2848 (0xb20) - ISRC1INT1MIX Input 1 Source */ 850 850 + { 0x00000b28, 0x0000 }, /* R2856 (0xb28) - ISRC1INT2MIX Input 1 Source */ 851 851 + { 0x00000b40, 0x0000 }, /* R2880 (0xb40) - ISRC2DEC1MIX Input 1 Source */ 852 852 + { 0x00000b48, 0x0000 }, /* R2888 (0xb48) - ISRC2DEC2MIX Input 1 Source */ 853 853 + { 0x00000b60, 0x0000 }, /* R2912 (0xb60) - ISRC2INT1MIX Input 1 Source */ 854 854 + { 0x00000b68, 0x0000 }, /* R2920 (0xb68) - ISRC2INT2MIX Input 1 Source */ 855 855 + { 0x00000dc0, 0x0000 }, /* R3520 (0xdc0) - DFC1MIX Input 1 Source */ 856 856 + { 0x00000dc8, 0x0000 }, /* R3528 (0xdc8) - DFC2MIX Input 1 Source */ 857 857 + { 0x00000dd0, 0x0000 }, /* R3536 (0xdd0) - DFC3MIX Input 1 Source */ 858 858 + { 0x00000dd8, 0x0000 }, /* R3544 (0xdd8) - DFC4MIX Input 1 Source */ 859 859 + { 0x00000de0, 0x0000 }, /* R3552 (0xde0) - DFC5MIX Input 1 Source */ 860 860 + { 0x00000de8, 0x0000 }, /* R3560 (0xde8) - DFC6MIX Input 1 Source */ 861 861 + { 0x00000df0, 0x0000 }, /* R3568 (0xdf0) - DFC7MIX Input 1 Source */ 862 862 + { 0x00000df8, 0x0000 }, /* R3576 (0xdf8) - DFC8MIX Input 1 Source */ 863 863 + { 0x00000e00, 0x0000 }, /* R3584 (0xe00) - FX Ctrl 1 */ 864 864 + { 0x00000e10, 0x6318 }, /* R3600 (0xe10) - EQ1 1 */ 865 865 + { 0x00000e11, 0x6300 }, /* R3601 (0xe11) - EQ1 2 */ 866 866 + { 0x00000e12, 0x0fc8 }, /* R3602 (0xe12) - EQ1 3 */ 867 867 + { 0x00000e13, 0x03fe }, /* R3603 (0xe13) - EQ1 4 */ 868 868 + { 0x00000e14, 0x00e0 }, /* R3604 (0xe14) - EQ1 5 */ 869 869 + { 0x00000e15, 0x1ec4 }, /* R3605 (0xe15) - EQ1 6 */ 870 870 + { 0x00000e16, 0xf136 }, /* R3606 (0xe16) - EQ1 7 */ 871 871 + { 0x00000e17, 0x0409 }, /* R3607 (0xe17) - EQ1 8 */ 872 872 + { 0x00000e18, 0x04cc }, /* R3608 (0xe18) - EQ1 9 */ 873 873 + { 0x00000e19, 0x1c9b }, /* R3609 (0xe19) - EQ1 10 */ 874 874 + { 0x00000e1a, 0xf337 }, /* R3610 (0xe1a) - EQ1 11 */ 875 875 + { 0x00000e1b, 0x040b }, /* R3611 (0xe1b) - EQ1 12 */ 876 876 + { 0x00000e1c, 0x0cbb }, /* R3612 (0xe1c) - EQ1 13 */ 877 877 + { 0x00000e1d, 0x16f8 }, /* R3613 (0xe1d) - EQ1 14 */ 878 878 + { 0x00000e1e, 0xf7d9 }, /* R3614 (0xe1e) - EQ1 15 */ 879 879 + { 0x00000e1f, 0x040a }, /* R3615 (0xe1f) - EQ1 16 */ 880 880 + { 0x00000e20, 0x1f14 }, /* R3616 (0xe20) - EQ1 17 */ 881 881 + { 0x00000e21, 0x058c }, /* R3617 (0xe21) - EQ1 18 */ 882 882 + { 0x00000e22, 0x0563 }, /* R3618 (0xe22) - EQ1 19 */ 883 883 + { 0x00000e23, 0x4000 }, /* R3619 (0xe23) - EQ1 20 */ 884 884 + { 0x00000e24, 0x0b75 }, /* R3620 (0xe24) - EQ1 21 */ 885 885 + { 0x00000e26, 0x6318 }, /* R3622 (0xe26) - EQ2 1 */ 886 886 + { 0x00000e27, 0x6300 }, /* R3623 (0xe27) - EQ2 2 */ 887 887 + { 0x00000e28, 0x0fc8 }, /* R3624 (0xe28) - EQ2 3 */ 888 888 + { 0x00000e29, 0x03fe }, /* R3625 (0xe29) - EQ2 4 */ 889 889 + { 0x00000e2a, 0x00e0 }, /* R3626 (0xe2a) - EQ2 5 */ 890 890 + { 0x00000e2b, 0x1ec4 }, /* R3627 (0xe2b) - EQ2 6 */ 891 891 + { 0x00000e2c, 0xf136 }, /* R3628 (0xe2c) - EQ2 7 */ 892 892 + { 0x00000e2d, 0x0409 }, /* R3629 (0xe2d) - EQ2 8 */ 893 893 + { 0x00000e2e, 0x04cc }, /* R3630 (0xe2e) - EQ2 9 */ 894 894 + { 0x00000e2f, 0x1c9b }, /* R3631 (0xe2f) - EQ2 10 */ 895 895 + { 0x00000e30, 0xf337 }, /* R3632 (0xe30) - EQ2 11 */ 896 896 + { 0x00000e31, 0x040b }, /* R3633 (0xe31) - EQ2 12 */ 897 897 + { 0x00000e32, 0x0cbb }, /* R3634 (0xe32) - EQ2 13 */ 898 898 + { 0x00000e33, 0x16f8 }, /* R3635 (0xe33) - EQ2 14 */ 899 899 + { 0x00000e34, 0xf7d9 }, /* R3636 (0xe34) - EQ2 15 */ 900 900 + { 0x00000e35, 0x040a }, /* R3637 (0xe35) - EQ2 16 */ 901 901 + { 0x00000e36, 0x1f14 }, /* R3638 (0xe36) - EQ2 17 */ 902 902 + { 0x00000e37, 0x058c }, /* R3639 (0xe37) - EQ2 18 */ 903 903 + { 0x00000e38, 0x0563 }, /* R3640 (0xe38) - EQ2 19 */ 904 904 + { 0x00000e39, 0x4000 }, /* R3641 (0xe39) - EQ2 20 */ 905 905 + { 0x00000e3a, 0x0b75 }, /* R3642 (0xe3a) - EQ2 21 */ 906 906 + { 0x00000e3c, 0x6318 }, /* R3644 (0xe3c) - EQ3 1 */ 907 907 + { 0x00000e3d, 0x6300 }, /* R3645 (0xe3d) - EQ3 2 */ 908 908 + { 0x00000e3e, 0x0fc8 }, /* R3646 (0xe3e) - EQ3 3 */ 909 909 + { 0x00000e3f, 0x03fe }, /* R3647 (0xe3f) - EQ3 4 */ 910 910 + { 0x00000e40, 0x00e0 }, /* R3648 (0xe40) - EQ3 5 */ 911 911 + { 0x00000e41, 0x1ec4 }, /* R3649 (0xe41) - EQ3 6 */ 912 912 + { 0x00000e42, 0xf136 }, /* R3650 (0xe42) - EQ3 7 */ 913 913 + { 0x00000e43, 0x0409 }, /* R3651 (0xe43) - EQ3 8 */ 914 914 + { 0x00000e44, 0x04cc }, /* R3652 (0xe44) - EQ3 9 */ 915 915 + { 0x00000e45, 0x1c9b }, /* R3653 (0xe45) - EQ3 10 */ 916 916 + { 0x00000e46, 0xf337 }, /* R3654 (0xe46) - EQ3 11 */ 917 917 + { 0x00000e47, 0x040b }, /* R3655 (0xe47) - EQ3 12 */ 918 918 + { 0x00000e48, 0x0cbb }, /* R3656 (0xe48) - EQ3 13 */ 919 919 + { 0x00000e49, 0x16f8 }, /* R3657 (0xe49) - EQ3 14 */ 920 920 + { 0x00000e4a, 0xf7d9 }, /* R3658 (0xe4a) - EQ3 15 */ 921 921 + { 0x00000e4b, 0x040a }, /* R3659 (0xe4b) - EQ3 16 */ 922 922 + { 0x00000e4c, 0x1f14 }, /* R3660 (0xe4c) - EQ3 17 */ 923 923 + { 0x00000e4d, 0x058c }, /* R3661 (0xe4d) - EQ3 18 */ 924 924 + { 0x00000e4e, 0x0563 }, /* R3662 (0xe4e) - EQ3 19 */ 925 925 + { 0x00000e4f, 0x4000 }, /* R3663 (0xe4f) - EQ3 20 */ 926 926 + { 0x00000e50, 0x0b75 }, /* R3664 (0xe50) - EQ3 21 */ 927 927 + { 0x00000e52, 0x6318 }, /* R3666 (0xe52) - EQ4 1 */ 928 928 + { 0x00000e53, 0x6300 }, /* R3667 (0xe53) - EQ4 2 */ 929 929 + { 0x00000e54, 0x0fc8 }, /* R3668 (0xe54) - EQ4 3 */ 930 930 + { 0x00000e55, 0x03fe }, /* R3669 (0xe55) - EQ4 4 */ 931 931 + { 0x00000e56, 0x00e0 }, /* R3670 (0xe56) - EQ4 5 */ 932 932 + { 0x00000e57, 0x1ec4 }, /* R3671 (0xe57) - EQ4 6 */ 933 933 + { 0x00000e58, 0xf136 }, /* R3672 (0xe58) - EQ4 7 */ 934 934 + { 0x00000e59, 0x0409 }, /* R3673 (0xe59) - EQ4 8 */ 935 935 + { 0x00000e5a, 0x04cc }, /* R3674 (0xe5a) - EQ4 9 */ 936 936 + { 0x00000e5b, 0x1c9b }, /* R3675 (0xe5b) - EQ4 10 */ 937 937 + { 0x00000e5c, 0xf337 }, /* R3676 (0xe5c) - EQ4 11 */ 938 938 + { 0x00000e5d, 0x040b }, /* R3677 (0xe5d) - EQ4 12 */ 939 939 + { 0x00000e5e, 0x0cbb }, /* R3678 (0xe5e) - EQ4 13 */ 940 940 + { 0x00000e5f, 0x16f8 }, /* R3679 (0xe5f) - EQ4 14 */ 941 941 + { 0x00000e60, 0xf7d9 }, /* R3680 (0xe60) - EQ4 15 */ 942 942 + { 0x00000e61, 0x040a }, /* R3681 (0xe61) - EQ4 16 */ 943 943 + { 0x00000e62, 0x1f14 }, /* R3682 (0xe62) - EQ4 17 */ 944 944 + { 0x00000e63, 0x058c }, /* R3683 (0xe63) - EQ4 18 */ 945 945 + { 0x00000e64, 0x0563 }, /* R3684 (0xe64) - EQ4 19 */ 946 946 + { 0x00000e65, 0x4000 }, /* R3685 (0xe65) - EQ4 20 */ 947 947 + { 0x00000e66, 0x0b75 }, /* R3686 (0xe66) - EQ4 21 */ 948 948 + { 0x00000e80, 0x0018 }, /* R3712 (0xe80) - DRC1 Ctrl 1 */ 949 949 + { 0x00000e81, 0x0933 }, /* R3713 (0xe81) - DRC1 Ctrl 2 */ 950 950 + { 0x00000e82, 0x0018 }, /* R3714 (0xe82) - DRC1 Ctrl 3 */ 951 951 + { 0x00000e83, 0x0000 }, /* R3715 (0xe83) - DRC1 Ctrl 4 */ 952 952 + { 0x00000e84, 0x0000 }, /* R3716 (0xe84) - DRC1 Ctrl 5 */ 953 953 + { 0x00000e88, 0x0018 }, /* R3720 (0xe88) - DRC2 Ctrl 1 */ 954 954 + { 0x00000e89, 0x0933 }, /* R3721 (0xe89) - DRC2 Ctrl 2 */ 955 955 + { 0x00000e8a, 0x0018 }, /* R3722 (0xe8a) - DRC2 Ctrl 3 */ 956 956 + { 0x00000e8b, 0x0000 }, /* R3723 (0xe8b) - DRC2 Ctrl 4 */ 957 957 + { 0x00000e8c, 0x0000 }, /* R3724 (0xe8c) - DRC2 Ctrl 5 */ 958 958 + { 0x00000ec0, 0x0000 }, /* R3776 (0xec0) - HPLPF1 1 */ 959 959 + { 0x00000ec1, 0x0000 }, /* R3777 (0xec1) - HPLPF1 2 */ 960 960 + { 0x00000ec4, 0x0000 }, /* R3780 (0xec4) - HPLPF2 1 */ 961 961 + { 0x00000ec5, 0x0000 }, /* R3781 (0xec5) - HPLPF2 2 */ 962 962 + { 0x00000ec8, 0x0000 }, /* R3784 (0xec8) - HPLPF3 1 */ 963 963 + { 0x00000ec9, 0x0000 }, /* R3785 (0xec9) - HPLPF3 2 */ 964 964 + { 0x00000ecc, 0x0000 }, /* R3788 (0xecc) - HPLPF4 1 */ 965 965 + { 0x00000ecd, 0x0000 }, /* R3789 (0xecd) - HPLPF4 2 */ 966 966 + { 0x00000ee0, 0x0000 }, /* R3808 (0xee0) - ASRC1 Enable */ 967 967 + { 0x00000ee2, 0x0000 }, /* R3810 (0xee2) - ASRC1 Rate 1 */ 968 968 + { 0x00000ee3, 0x4000 }, /* R3811 (0xee3) - ASRC1 Rate 2 */ 969 969 + { 0x00000ef0, 0x0000 }, /* R3824 (0xef0) - ISRC1 Ctrl 1 */ 970 970 + { 0x00000ef1, 0x0001 }, /* R3825 (0xef1) - ISRC1 Ctrl 2 */ 971 971 + { 0x00000ef2, 0x0000 }, /* R3826 (0xef2) - ISRC1 Ctrl 3 */ 972 972 + { 0x00000ef3, 0x0000 }, /* R3827 (0xef3) - ISRC2 Ctrl 1 */ 973 973 + { 0x00000ef4, 0x0001 }, /* R3828 (0xef4) - ISRC2 Ctrl 2 */ 974 974 + { 0x00000ef5, 0x0000 }, /* R3829 (0xef5) - ISRC2 Ctrl 3 */ 975 975 + { 0x000010c0, 0x0008 }, /* R4288 (0x10c0) - AUXPDM1 Ctrl 0 */ 976 976 + { 0x000010c1, 0x4000 }, /* R4289 (0x10c1) - AUXPDM1 Ctrl 1 */ 977 977 + { 0x00001480, 0x0000 }, /* R5248 (0x1480) - DFC1 Ctrl W0 */ 978 978 + { 0x00001482, 0x1f00 }, /* R5250 (0x1482) - DFC1 Rx W0 */ 979 979 + { 0x00001484, 0x1f00 }, /* R5252 (0x1484) - DFC1 Tx W0 */ 980 980 + { 0x00001486, 0x0000 }, /* R5254 (0x1486) - DFC2 Ctrl W0 */ 981 981 + { 0x00001488, 0x1f00 }, /* R5256 (0x1488) - DFC2 Rx W0 */ 982 982 + { 0x0000148a, 0x1f00 }, /* R5258 (0x148a) - DFC2 Tx W0 */ 983 983 + { 0x0000148c, 0x0000 }, /* R5260 (0x148c) - DFC3 Ctrl W0 */ 984 984 + { 0x0000148e, 0x1f00 }, /* R5262 (0x148e) - DFC3 Rx W0 */ 985 985 + { 0x00001490, 0x1f00 }, /* R5264 (0x1490) - DFC3 Tx W0 */ 986 986 + { 0x00001492, 0x0000 }, /* R5266 (0x1492) - DFC4 Ctrl W0 */ 987 987 + { 0x00001494, 0x1f00 }, /* R5268 (0x1494) - DFC4 Rx W0 */ 988 988 + { 0x00001496, 0x1f00 }, /* R5270 (0x1496) - DFC4 Tx W0 */ 989 989 + { 0x00001498, 0x0000 }, /* R5272 (0x1498) - DFC5 Ctrl W0 */ 990 990 + { 0x0000149a, 0x1f00 }, /* R5274 (0x149a) - DFC5 Rx W0 */ 991 991 + { 0x0000149c, 0x1f00 }, /* R5276 (0x149c) - DFC5 Tx W0 */ 992 992 + { 0x0000149e, 0x0000 }, /* R5278 (0x149e) - DFC6 Ctrl W0 */ 993 993 + { 0x000014a0, 0x1f00 }, /* R5280 (0x14a0) - DFC6 Rx W0 */ 994 994 + { 0x000014a2, 0x1f00 }, /* R5282 (0x14a2) - DFC6 Tx W0 */ 995 995 + { 0x000014a4, 0x0000 }, /* R5284 (0x14a4) - DFC7 Ctrl W0 */ 996 996 + { 0x000014a6, 0x1f00 }, /* R5286 (0x14a6) - DFC7 Rx W0 */ 997 997 + { 0x000014a8, 0x1f00 }, /* R5288 (0x14a8) - DFC7 Tx W0 */ 998 998 + { 0x000014aa, 0x0000 }, /* R5290 (0x14aa) - DFC8 Ctrl W0 */ 999 999 + { 0x000014ac, 0x1f00 }, /* R5292 (0x14ac) - DFC8 Rx W0 */ 1000 1000 + { 0x000014ae, 0x1f00 }, /* R5294 (0x14ae) - DFC8 Tx W0 */ 1001 1001 + { 0x00001700, 0x2001 }, /* R5888 (0x1700) - GPIO1 Ctrl 1 */ 1002 1002 + { 0x00001701, 0xf000 }, /* R5889 (0x1701) - GPIO1 Ctrl 2 */ 1003 1003 + { 0x00001702, 0x2001 }, /* R5890 (0x1702) - GPIO2 Ctrl 1 */ 1004 1004 + { 0x00001703, 0xf000 }, /* R5891 (0x1703) - GPIO2 Ctrl 2 */ 1005 1005 + { 0x00001704, 0x2001 }, /* R5892 (0x1704) - GPIO3 Ctrl 1 */ 1006 1006 + { 0x00001705, 0xf000 }, /* R5893 (0x1705) - GPIO3 Ctrl 2 */ 1007 1007 + { 0x00001706, 0x2001 }, /* R5894 (0x1706) - GPIO4 Ctrl 1 */ 1008 1008 + { 0x00001707, 0xf000 }, /* R5895 (0x1707) - GPIO4 Ctrl 2 */ 1009 1009 + { 0x00001708, 0x2001 }, /* R5896 (0x1708) - GPIO5 Ctrl 1 */ 1010 1010 + { 0x00001709, 0xf000 }, /* R5897 (0x1709) - GPIO5 Ctrl 2 */ 1011 1011 + { 0x0000170a, 0x2001 }, /* R5898 (0x170a) - GPIO6 Ctrl 1 */ 1012 1012 + { 0x0000170b, 0xf000 }, /* R5899 (0x170b) - GPIO6 Ctrl 2 */ 1013 1013 + { 0x0000170c, 0x2001 }, /* R5900 (0x170c) - GPIO7 Ctrl 1 */ 1014 1014 + { 0x0000170d, 0xf000 }, /* R5901 (0x170d) - GPIO7 Ctrl 2 */ 1015 1015 + { 0x0000170e, 0x2001 }, /* R5902 (0x170e) - GPIO8 Ctrl 1 */ 1016 1016 + { 0x0000170f, 0xf000 }, /* R5903 (0x170f) - GPIO8 Ctrl 2 */ 1017 1017 + { 0x00001710, 0x2001 }, /* R5904 (0x1710) - GPIO9 Ctrl 1 */ 1018 1018 + { 0x00001711, 0xf000 }, /* R5905 (0x1711) - GPIO9 Ctrl 2 */ 1019 1019 + { 0x00001712, 0x2001 }, /* R5906 (0x1712) - GPIO10 Ctrl 1 */ 1020 1020 + { 0x00001713, 0xf000 }, /* R5907 (0x1713) - GPIO10 Ctrl 2 */ 1021 1021 + { 0x00001714, 0x2001 }, /* R5908 (0x1714) - GPIO11 Ctrl 1 */ 1022 1022 + { 0x00001715, 0xf000 }, /* R5909 (0x1715) - GPIO11 Ctrl 2 */ 1023 1023 + { 0x00001716, 0x2001 }, /* R5910 (0x1716) - GPIO12 Ctrl 1 */ 1024 1024 + { 0x00001717, 0xf000 }, /* R5911 (0x1717) - GPIO12 Ctrl 2 */ 1025 1025 + { 0x00001718, 0x2001 }, /* R5912 (0x1718) - GPIO13 Ctrl 1 */ 1026 1026 + { 0x00001719, 0xf000 }, /* R5913 (0x1719) - GPIO13 Ctrl 2 */ 1027 1027 + { 0x0000171a, 0x2001 }, /* R5914 (0x171a) - GPIO14 Ctrl 1 */ 1028 1028 + { 0x0000171b, 0xf000 }, /* R5915 (0x171b) - GPIO14 Ctrl 2 */ 1029 1029 + { 0x0000171c, 0x2001 }, /* R5916 (0x171c) - GPIO15 Ctrl 1 */ 1030 1030 + { 0x0000171d, 0xf000 }, /* R5917 (0x171d) - GPIO15 Ctrl 2 */ 1031 1031 + { 0x0000171e, 0x2001 }, /* R5918 (0x171e) - GPIO16 Ctrl 1 */ 1032 1032 + { 0x0000171f, 0xf000 }, /* R5919 (0x171f) - GPIO16 Ctrl 2 */ 1033 1033 + { 0x00001840, 0x1200 }, /* R6208 (0x1840) - IRQ1 Mask 1 */ 1034 1034 + { 0x00001841, 0x77e0 }, /* R6209 (0x1841) - IRQ1 Mask 2 */ 1035 1035 + { 0x00001842, 0xffff }, /* R6210 (0x1842) - IRQ1 Mask 3 */ 1036 1036 + { 0x00001843, 0xffff }, /* R6211 (0x1843) - IRQ1 Mask 4 */ 1037 1037 + { 0x00001844, 0xffff }, /* R6212 (0x1844) - IRQ1 Mask 5 */ 1038 1038 + { 0x00001845, 0x0301 }, /* R6213 (0x1845) - IRQ1 Mask 6 */ 1039 1039 + { 0x00001846, 0x0f3f }, /* R6214 (0x1846) - IRQ1 Mask 7 */ 1040 1040 + { 0x00001847, 0xffff }, /* R6215 (0x1847) - IRQ1 Mask 8 */ 1041 1041 + { 0x00001848, 0x031f }, /* R6216 (0x1848) - IRQ1 Mask 9 */ 1042 1042 + { 0x00001849, 0x031f }, /* R6217 (0x1849) - IRQ1 Mask 10 */ 1043 1043 + { 0x0000184a, 0xffff }, /* R6218 (0x184a) - IRQ1 Mask 11 */ 1044 1044 + { 0x0000184b, 0x033f }, /* R6219 (0x184b) - IRQ1 Mask 12 */ 1045 1045 + { 0x0000184c, 0x003f }, /* R6220 (0x184c) - IRQ1 Mask 13 */ 1046 1046 + { 0x0000184d, 0x003f }, /* R6221 (0x184d) - IRQ1 Mask 14 */ 1047 1047 + { 0x0000184e, 0x1000 }, /* R6222 (0x184e) - IRQ1 Mask 15 */ 1048 1048 + { 0x0000184f, 0xffff }, /* R6223 (0x184f) - IRQ1 Mask 16 */ 1049 1049 + { 0x00001850, 0xffff }, /* R6224 (0x1850) - IRQ1 Mask 17 */ 1050 1050 + { 0x00001851, 0xffff }, /* R6225 (0x1851) - IRQ1 Mask 18 */ 1051 1051 + { 0x00001852, 0xffff }, /* R6226 (0x1852) - IRQ1 Mask 19 */ 1052 1052 + { 0x00001853, 0xffff }, /* R6227 (0x1853) - IRQ1 Mask 20 */ 1053 1053 + { 0x00001854, 0x0001 }, /* R6228 (0x1854) - IRQ1 Mask 21 */ 1054 1054 + { 0x00001855, 0x0001 }, /* R6229 (0x1855) - IRQ1 Mask 22 */ 1055 1055 + { 0x00001856, 0x0001 }, /* R6230 (0x1856) - IRQ1 Mask 23 */ 1056 1056 + { 0x00001857, 0x0001 }, /* R6231 (0x1857) - IRQ1 Mask 24 */ 1057 1057 + { 0x00001858, 0x0001 }, /* R6232 (0x1858) - IRQ1 Mask 25 */ 1058 1058 + { 0x00001859, 0xffff }, /* R6233 (0x1859) - IRQ1 Mask 26 */ 1059 1059 + { 0x0000185a, 0x0001 }, /* R6234 (0x185a) - IRQ1 Mask 27 */ 1060 1060 + { 0x0000185b, 0x0001 }, /* R6235 (0x185b) - IRQ1 Mask 28 */ 1061 1061 + { 0x0000185c, 0xffff }, /* R6236 (0x185c) - IRQ1 Mask 29 */ 1062 1062 + { 0x0000185d, 0x0001 }, /* R6237 (0x185d) - IRQ1 Mask 30 */ 1063 1063 + { 0x0000185e, 0xffff }, /* R6238 (0x185e) - IRQ1 Mask 31 */ 1064 1064 + { 0x0000185f, 0xffff }, /* R6239 (0x185f) - IRQ1 Mask 32 */ 1065 1065 + { 0x00001860, 0x0001 }, /* R6240 (0x1860) - IRQ1 Mask 33 */ 1066 1066 + { 0x00001a06, 0x0000 }, /* R6662 (0x1a06) - Interrupt Debounce 7 */ 1067 1067 + { 0x00001a80, 0x4400 }, /* R6784 (0x1a80) - IRQ1 Ctrl */ 1068 1068 + }; 1069 1069 + 1070 1070 + static bool cs47l92_is_adsp_memory(unsigned int reg) 1071 1071 + { 1072 1072 + switch (reg) { 1073 1073 + case 0x080000 ... 0x082ffe: 1074 1074 + case 0x0a0000 ... 0x0a1ffe: 1075 1075 + case 0x0c0000 ... 0x0c1ffe: 1076 1076 + case 0x0e0000 ... 0x0e1ffe: 1077 1077 + return true; 1078 1078 + default: 1079 1079 + return false; 1080 1080 + } 1081 1081 + } 1082 1082 + 1083 1083 + static bool cs47l92_16bit_readable_register(struct device *dev, 1084 1084 + unsigned int reg) 1085 1085 + { 1086 1086 + switch (reg) { 1087 1087 + case MADERA_SOFTWARE_RESET: 1088 1088 + case MADERA_HARDWARE_REVISION: 1089 1089 + case MADERA_WRITE_SEQUENCER_CTRL_0 ... MADERA_WRITE_SEQUENCER_CTRL_2: 1090 1090 + case MADERA_TONE_GENERATOR_1 ... MADERA_TONE_GENERATOR_5: 1091 1091 + case MADERA_PWM_DRIVE_1 ... MADERA_PWM_DRIVE_3: 1092 1092 + case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_1: 1093 1093 + case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_2: 1094 1094 + case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_3: 1095 1095 + case MADERA_SAMPLE_RATE_SEQUENCE_SELECT_4: 1096 1096 + case MADERA_HAPTICS_CONTROL_1 ... MADERA_HAPTICS_CONTROL_2: 1097 1097 + case MADERA_HAPTICS_PHASE_1_INTENSITY: 1098 1098 + case MADERA_HAPTICS_PHASE_1_DURATION: 1099 1099 + case MADERA_HAPTICS_PHASE_2_INTENSITY: 1100 1100 + case MADERA_HAPTICS_PHASE_2_DURATION: 1101 1101 + case MADERA_HAPTICS_PHASE_3_INTENSITY: 1102 1102 + case MADERA_HAPTICS_PHASE_3_DURATION: 1103 1103 + case MADERA_HAPTICS_STATUS: 1104 1104 + case MADERA_COMFORT_NOISE_GENERATOR: 1105 1105 + case MADERA_CLOCK_32K_1: 1106 1106 + case MADERA_SYSTEM_CLOCK_1: 1107 1107 + case MADERA_SAMPLE_RATE_1 ... MADERA_SAMPLE_RATE_3: 1108 1108 + case MADERA_SAMPLE_RATE_1_STATUS: 1109 1109 + case MADERA_SAMPLE_RATE_2_STATUS: 1110 1110 + case MADERA_SAMPLE_RATE_3_STATUS: 1111 1111 + case MADERA_ASYNC_CLOCK_1: 1112 1112 + case MADERA_ASYNC_SAMPLE_RATE_1: 1113 1113 + case MADERA_ASYNC_SAMPLE_RATE_1_STATUS: 1114 1114 + case MADERA_ASYNC_SAMPLE_RATE_2: 1115 1115 + case MADERA_ASYNC_SAMPLE_RATE_2_STATUS: 1116 1116 + case MADERA_DSP_CLOCK_1: 1117 1117 + case MADERA_DSP_CLOCK_2: 1118 1118 + case MADERA_OUTPUT_SYSTEM_CLOCK: 1119 1119 + case MADERA_OUTPUT_ASYNC_CLOCK: 1120 1120 + case MADERA_RATE_ESTIMATOR_1 ... MADERA_RATE_ESTIMATOR_5: 1121 1121 + case MADERA_FLL1_CONTROL_1 ... MADERA_FLL1_CONTROL_6: 1122 1122 + case CS47L92_FLL1_CONTROL_7 ... CS47L92_FLL1_CONTROL_10: 1123 1123 + case MADERA_FLL1_CONTROL_11: 1124 1124 + case MADERA_FLL1_DIGITAL_TEST_1: 1125 1125 + case MADERA_FLL1_SYNCHRONISER_1 ... MADERA_FLL1_SYNCHRONISER_6: 1126 1126 + case CS47L92_FLL1_GPIO_CLOCK: 1127 1127 + case MADERA_FLL2_CONTROL_1 ... MADERA_FLL2_CONTROL_6: 1128 1128 + case CS47L92_FLL2_CONTROL_7 ... CS47L92_FLL2_CONTROL_10: 1129 1129 + case MADERA_FLL2_CONTROL_11: 1130 1130 + case MADERA_FLL2_DIGITAL_TEST_1: 1131 1131 + case MADERA_FLL2_SYNCHRONISER_1 ... MADERA_FLL2_SYNCHRONISER_6: 1132 1132 + case CS47L92_FLL2_GPIO_CLOCK: 1133 1133 + case MADERA_MIC_CHARGE_PUMP_1: 1134 1134 + case MADERA_LDO2_CONTROL_1: 1135 1135 + case MADERA_MIC_BIAS_CTRL_1: 1136 1136 + case MADERA_MIC_BIAS_CTRL_2: 1137 1137 + case MADERA_MIC_BIAS_CTRL_5: 1138 1138 + case MADERA_MIC_BIAS_CTRL_6: 1139 1139 + case MADERA_HP_CTRL_1L: 1140 1140 + case MADERA_HP_CTRL_1R: 1141 1141 + case MADERA_HP_CTRL_2L: 1142 1142 + case MADERA_HP_CTRL_2R: 1143 1143 + case MADERA_HP_CTRL_3L: 1144 1144 + case MADERA_HP_CTRL_3R: 1145 1145 + case MADERA_ACCESSORY_DETECT_MODE_1: 1146 1146 + case MADERA_HEADPHONE_DETECT_0: 1147 1147 + case MADERA_HEADPHONE_DETECT_1: 1148 1148 + case MADERA_HEADPHONE_DETECT_2: 1149 1149 + case MADERA_HEADPHONE_DETECT_3: 1150 1150 + case MADERA_HEADPHONE_DETECT_5: 1151 1151 + case MADERA_MICD_CLAMP_CONTROL: 1152 1152 + case MADERA_MIC_DETECT_1_CONTROL_0: 1153 1153 + case MADERA_MIC_DETECT_1_CONTROL_1: 1154 1154 + case MADERA_MIC_DETECT_1_CONTROL_2: 1155 1155 + case MADERA_MIC_DETECT_1_CONTROL_3: 1156 1156 + case MADERA_MIC_DETECT_1_CONTROL_4: 1157 1157 + case MADERA_MIC_DETECT_1_LEVEL_1 ... MADERA_MIC_DETECT_1_LEVEL_4: 1158 1158 + case MADERA_MIC_DETECT_2_CONTROL_0: 1159 1159 + case MADERA_MIC_DETECT_2_CONTROL_1: 1160 1160 + case MADERA_MIC_DETECT_2_CONTROL_2: 1161 1161 + case MADERA_MIC_DETECT_2_CONTROL_3: 1162 1162 + case MADERA_MIC_DETECT_2_CONTROL_4: 1163 1163 + case MADERA_MIC_DETECT_2_LEVEL_1 ... MADERA_MIC_DETECT_2_LEVEL_4: 1164 1164 + case MADERA_GP_SWITCH_1: 1165 1165 + case MADERA_JACK_DETECT_ANALOGUE: 1166 1166 + case MADERA_INPUT_ENABLES: 1167 1167 + case MADERA_INPUT_ENABLES_STATUS: 1168 1168 + case MADERA_INPUT_RATE: 1169 1169 + case MADERA_INPUT_VOLUME_RAMP: 1170 1170 + case MADERA_HPF_CONTROL: 1171 1171 + case MADERA_IN1L_CONTROL: 1172 1172 + case MADERA_ADC_DIGITAL_VOLUME_1L: 1173 1173 + case MADERA_DMIC1L_CONTROL: 1174 1174 + case MADERA_IN1L_RATE_CONTROL: 1175 1175 + case MADERA_IN1R_CONTROL: 1176 1176 + case MADERA_ADC_DIGITAL_VOLUME_1R: 1177 1177 + case MADERA_DMIC1R_CONTROL: 1178 1178 + case MADERA_IN1R_RATE_CONTROL: 1179 1179 + case MADERA_IN2L_CONTROL: 1180 1180 + case MADERA_ADC_DIGITAL_VOLUME_2L: 1181 1181 + case MADERA_DMIC2L_CONTROL: 1182 1182 + case MADERA_IN2L_RATE_CONTROL: 1183 1183 + case MADERA_IN2R_CONTROL: 1184 1184 + case MADERA_ADC_DIGITAL_VOLUME_2R: 1185 1185 + case MADERA_DMIC2R_CONTROL: 1186 1186 + case MADERA_IN2R_RATE_CONTROL: 1187 1187 + case MADERA_IN3L_CONTROL: 1188 1188 + case MADERA_ADC_DIGITAL_VOLUME_3L: 1189 1189 + case MADERA_DMIC3L_CONTROL: 1190 1190 + case MADERA_IN3L_RATE_CONTROL: 1191 1191 + case MADERA_IN3R_CONTROL: 1192 1192 + case MADERA_ADC_DIGITAL_VOLUME_3R: 1193 1193 + case MADERA_DMIC3R_CONTROL: 1194 1194 + case MADERA_IN3R_RATE_CONTROL: 1195 1195 + case MADERA_IN4L_CONTROL: 1196 1196 + case MADERA_ADC_DIGITAL_VOLUME_4L: 1197 1197 + case MADERA_DMIC4L_CONTROL: 1198 1198 + case MADERA_IN4L_RATE_CONTROL: 1199 1199 + case MADERA_IN4R_CONTROL: 1200 1200 + case MADERA_ADC_DIGITAL_VOLUME_4R: 1201 1201 + case MADERA_DMIC4R_CONTROL: 1202 1202 + case MADERA_IN4R_RATE_CONTROL: 1203 1203 + case MADERA_OUTPUT_ENABLES_1: 1204 1204 + case MADERA_OUTPUT_STATUS_1: 1205 1205 + case MADERA_RAW_OUTPUT_STATUS_1: 1206 1206 + case MADERA_OUTPUT_RATE_1: 1207 1207 + case MADERA_OUTPUT_VOLUME_RAMP: 1208 1208 + case MADERA_OUTPUT_PATH_CONFIG_1L: 1209 1209 + case MADERA_DAC_DIGITAL_VOLUME_1L: 1210 1210 + case MADERA_OUTPUT_PATH_CONFIG_1: 1211 1211 + case MADERA_NOISE_GATE_SELECT_1L: 1212 1212 + case MADERA_OUTPUT_PATH_CONFIG_1R: 1213 1213 + case MADERA_DAC_DIGITAL_VOLUME_1R: 1214 1214 + case MADERA_NOISE_GATE_SELECT_1R: 1215 1215 + case MADERA_OUTPUT_PATH_CONFIG_2L: 1216 1216 + case MADERA_DAC_DIGITAL_VOLUME_2L: 1217 1217 + case MADERA_OUTPUT_PATH_CONFIG_2: 1218 1218 + case MADERA_NOISE_GATE_SELECT_2L: 1219 1219 + case MADERA_OUTPUT_PATH_CONFIG_2R: 1220 1220 + case MADERA_DAC_DIGITAL_VOLUME_2R: 1221 1221 + case MADERA_NOISE_GATE_SELECT_2R: 1222 1222 + case MADERA_OUTPUT_PATH_CONFIG_3L: 1223 1223 + case MADERA_DAC_DIGITAL_VOLUME_3L: 1224 1224 + case MADERA_OUTPUT_PATH_CONFIG_3: 1225 1225 + case MADERA_NOISE_GATE_SELECT_3L: 1226 1226 + case MADERA_OUTPUT_PATH_CONFIG_3R: 1227 1227 + case MADERA_DAC_DIGITAL_VOLUME_3R: 1228 1228 + case MADERA_NOISE_GATE_SELECT_3R: 1229 1229 + case MADERA_OUTPUT_PATH_CONFIG_5L: 1230 1230 + case MADERA_DAC_DIGITAL_VOLUME_5L: 1231 1231 + case MADERA_NOISE_GATE_SELECT_5L: 1232 1232 + case MADERA_OUTPUT_PATH_CONFIG_5R: 1233 1233 + case MADERA_DAC_DIGITAL_VOLUME_5R: 1234 1234 + case MADERA_NOISE_GATE_SELECT_5R: 1235 1235 + case MADERA_DAC_AEC_CONTROL_1 ... MADERA_DAC_AEC_CONTROL_2: 1236 1236 + case MADERA_NOISE_GATE_CONTROL: 1237 1237 + case MADERA_PDM_SPK1_CTRL_1 ... MADERA_PDM_SPK1_CTRL_2: 1238 1238 + case MADERA_HP1_SHORT_CIRCUIT_CTRL: 1239 1239 + case MADERA_HP2_SHORT_CIRCUIT_CTRL: 1240 1240 + case MADERA_HP3_SHORT_CIRCUIT_CTRL: 1241 1241 + case MADERA_AIF1_BCLK_CTRL: 1242 1242 + case MADERA_AIF1_TX_PIN_CTRL: 1243 1243 + case MADERA_AIF1_RX_PIN_CTRL: 1244 1244 + case MADERA_AIF1_RATE_CTRL: 1245 1245 + case MADERA_AIF1_FORMAT: 1246 1246 + case MADERA_AIF1_RX_BCLK_RATE: 1247 1247 + case MADERA_AIF1_FRAME_CTRL_1 ... MADERA_AIF1_FRAME_CTRL_18: 1248 1248 + case MADERA_AIF1_TX_ENABLES: 1249 1249 + case MADERA_AIF1_RX_ENABLES: 1250 1250 + case MADERA_AIF2_BCLK_CTRL: 1251 1251 + case MADERA_AIF2_TX_PIN_CTRL: 1252 1252 + case MADERA_AIF2_RX_PIN_CTRL: 1253 1253 + case MADERA_AIF2_RATE_CTRL: 1254 1254 + case MADERA_AIF2_FORMAT: 1255 1255 + case MADERA_AIF2_RX_BCLK_RATE: 1256 1256 + case MADERA_AIF2_FRAME_CTRL_1 ... MADERA_AIF2_FRAME_CTRL_18: 1257 1257 + case MADERA_AIF2_TX_ENABLES: 1258 1258 + case MADERA_AIF2_RX_ENABLES: 1259 1259 + case MADERA_AIF3_BCLK_CTRL: 1260 1260 + case MADERA_AIF3_TX_PIN_CTRL: 1261 1261 + case MADERA_AIF3_RX_PIN_CTRL: 1262 1262 + case MADERA_AIF3_RATE_CTRL: 1263 1263 + case MADERA_AIF3_FORMAT: 1264 1264 + case MADERA_AIF3_RX_BCLK_RATE: 1265 1265 + case MADERA_AIF3_FRAME_CTRL_1 ... MADERA_AIF3_FRAME_CTRL_18: 1266 1266 + case MADERA_AIF3_TX_ENABLES: 1267 1267 + case MADERA_AIF3_RX_ENABLES: 1268 1268 + case MADERA_SPD1_TX_CONTROL: 1269 1269 + case MADERA_SPD1_TX_CHANNEL_STATUS_1: 1270 1270 + case MADERA_SPD1_TX_CHANNEL_STATUS_2: 1271 1271 + case MADERA_SPD1_TX_CHANNEL_STATUS_3: 1272 1272 + case MADERA_SLIMBUS_FRAMER_REF_GEAR: 1273 1273 + case MADERA_SLIMBUS_RATES_1 ... MADERA_SLIMBUS_RATES_8: 1274 1274 + case MADERA_SLIMBUS_RX_CHANNEL_ENABLE: 1275 1275 + case MADERA_SLIMBUS_TX_CHANNEL_ENABLE: 1276 1276 + case MADERA_SLIMBUS_RX_PORT_STATUS: 1277 1277 + case MADERA_SLIMBUS_TX_PORT_STATUS: 1278 1278 + case MADERA_PWM1MIX_INPUT_1_SOURCE: 1279 1279 + case MADERA_PWM1MIX_INPUT_1_VOLUME: 1280 1280 + case MADERA_PWM1MIX_INPUT_2_SOURCE: 1281 1281 + case MADERA_PWM1MIX_INPUT_2_VOLUME: 1282 1282 + case MADERA_PWM1MIX_INPUT_3_SOURCE: 1283 1283 + case MADERA_PWM1MIX_INPUT_3_VOLUME: 1284 1284 + case MADERA_PWM1MIX_INPUT_4_SOURCE: 1285 1285 + case MADERA_PWM1MIX_INPUT_4_VOLUME: 1286 1286 + case MADERA_PWM2MIX_INPUT_1_SOURCE: 1287 1287 + case MADERA_PWM2MIX_INPUT_1_VOLUME: 1288 1288 + case MADERA_PWM2MIX_INPUT_2_SOURCE: 1289 1289 + case MADERA_PWM2MIX_INPUT_2_VOLUME: 1290 1290 + case MADERA_PWM2MIX_INPUT_3_SOURCE: 1291 1291 + case MADERA_PWM2MIX_INPUT_3_VOLUME: 1292 1292 + case MADERA_PWM2MIX_INPUT_4_SOURCE: 1293 1293 + case MADERA_PWM2MIX_INPUT_4_VOLUME: 1294 1294 + case MADERA_OUT1LMIX_INPUT_1_SOURCE: 1295 1295 + case MADERA_OUT1LMIX_INPUT_1_VOLUME: 1296 1296 + case MADERA_OUT1LMIX_INPUT_2_SOURCE: 1297 1297 + case MADERA_OUT1LMIX_INPUT_2_VOLUME: 1298 1298 + case MADERA_OUT1LMIX_INPUT_3_SOURCE: 1299 1299 + case MADERA_OUT1LMIX_INPUT_3_VOLUME: 1300 1300 + case MADERA_OUT1LMIX_INPUT_4_SOURCE: 1301 1301 + case MADERA_OUT1LMIX_INPUT_4_VOLUME: 1302 1302 + case MADERA_OUT1RMIX_INPUT_1_SOURCE: 1303 1303 + case MADERA_OUT1RMIX_INPUT_1_VOLUME: 1304 1304 + case MADERA_OUT1RMIX_INPUT_2_SOURCE: 1305 1305 + case MADERA_OUT1RMIX_INPUT_2_VOLUME: 1306 1306 + case MADERA_OUT1RMIX_INPUT_3_SOURCE: 1307 1307 + case MADERA_OUT1RMIX_INPUT_3_VOLUME: 1308 1308 + case MADERA_OUT1RMIX_INPUT_4_SOURCE: 1309 1309 + case MADERA_OUT1RMIX_INPUT_4_VOLUME: 1310 1310 + case MADERA_OUT2LMIX_INPUT_1_SOURCE: 1311 1311 + case MADERA_OUT2LMIX_INPUT_1_VOLUME: 1312 1312 + case MADERA_OUT2LMIX_INPUT_2_SOURCE: 1313 1313 + case MADERA_OUT2LMIX_INPUT_2_VOLUME: 1314 1314 + case MADERA_OUT2LMIX_INPUT_3_SOURCE: 1315 1315 + case MADERA_OUT2LMIX_INPUT_3_VOLUME: 1316 1316 + case MADERA_OUT2LMIX_INPUT_4_SOURCE: 1317 1317 + case MADERA_OUT2LMIX_INPUT_4_VOLUME: 1318 1318 + case MADERA_OUT2RMIX_INPUT_1_SOURCE: 1319 1319 + case MADERA_OUT2RMIX_INPUT_1_VOLUME: 1320 1320 + case MADERA_OUT2RMIX_INPUT_2_SOURCE: 1321 1321 + case MADERA_OUT2RMIX_INPUT_2_VOLUME: 1322 1322 + case MADERA_OUT2RMIX_INPUT_3_SOURCE: 1323 1323 + case MADERA_OUT2RMIX_INPUT_3_VOLUME: 1324 1324 + case MADERA_OUT2RMIX_INPUT_4_SOURCE: 1325 1325 + case MADERA_OUT2RMIX_INPUT_4_VOLUME: 1326 1326 + case MADERA_OUT3LMIX_INPUT_1_SOURCE: 1327 1327 + case MADERA_OUT3LMIX_INPUT_1_VOLUME: 1328 1328 + case MADERA_OUT3LMIX_INPUT_2_SOURCE: 1329 1329 + case MADERA_OUT3LMIX_INPUT_2_VOLUME: 1330 1330 + case MADERA_OUT3LMIX_INPUT_3_SOURCE: 1331 1331 + case MADERA_OUT3LMIX_INPUT_3_VOLUME: 1332 1332 + case MADERA_OUT3LMIX_INPUT_4_SOURCE: 1333 1333 + case MADERA_OUT3LMIX_INPUT_4_VOLUME: 1334 1334 + case MADERA_OUT3RMIX_INPUT_1_SOURCE: 1335 1335 + case MADERA_OUT3RMIX_INPUT_1_VOLUME: 1336 1336 + case MADERA_OUT3RMIX_INPUT_2_SOURCE: 1337 1337 + case MADERA_OUT3RMIX_INPUT_2_VOLUME: 1338 1338 + case MADERA_OUT3RMIX_INPUT_3_SOURCE: 1339 1339 + case MADERA_OUT3RMIX_INPUT_3_VOLUME: 1340 1340 + case MADERA_OUT3RMIX_INPUT_4_SOURCE: 1341 1341 + case MADERA_OUT3RMIX_INPUT_4_VOLUME: 1342 1342 + case MADERA_OUT5LMIX_INPUT_1_SOURCE: 1343 1343 + case MADERA_OUT5LMIX_INPUT_1_VOLUME: 1344 1344 + case MADERA_OUT5LMIX_INPUT_2_SOURCE: 1345 1345 + case MADERA_OUT5LMIX_INPUT_2_VOLUME: 1346 1346 + case MADERA_OUT5LMIX_INPUT_3_SOURCE: 1347 1347 + case MADERA_OUT5LMIX_INPUT_3_VOLUME: 1348 1348 + case MADERA_OUT5LMIX_INPUT_4_SOURCE: 1349 1349 + case MADERA_OUT5LMIX_INPUT_4_VOLUME: 1350 1350 + case MADERA_OUT5RMIX_INPUT_1_SOURCE: 1351 1351 + case MADERA_OUT5RMIX_INPUT_1_VOLUME: 1352 1352 + case MADERA_OUT5RMIX_INPUT_2_SOURCE: 1353 1353 + case MADERA_OUT5RMIX_INPUT_2_VOLUME: 1354 1354 + case MADERA_OUT5RMIX_INPUT_3_SOURCE: 1355 1355 + case MADERA_OUT5RMIX_INPUT_3_VOLUME: 1356 1356 + case MADERA_OUT5RMIX_INPUT_4_SOURCE: 1357 1357 + case MADERA_OUT5RMIX_INPUT_4_VOLUME: 1358 1358 + case MADERA_AIF1TX1MIX_INPUT_1_SOURCE: 1359 1359 + case MADERA_AIF1TX1MIX_INPUT_1_VOLUME: 1360 1360 + case MADERA_AIF1TX1MIX_INPUT_2_SOURCE: 1361 1361 + case MADERA_AIF1TX1MIX_INPUT_2_VOLUME: 1362 1362 + case MADERA_AIF1TX1MIX_INPUT_3_SOURCE: 1363 1363 + case MADERA_AIF1TX1MIX_INPUT_3_VOLUME: 1364 1364 + case MADERA_AIF1TX1MIX_INPUT_4_SOURCE: 1365 1365 + case MADERA_AIF1TX1MIX_INPUT_4_VOLUME: 1366 1366 + case MADERA_AIF1TX2MIX_INPUT_1_SOURCE: 1367 1367 + case MADERA_AIF1TX2MIX_INPUT_1_VOLUME: 1368 1368 + case MADERA_AIF1TX2MIX_INPUT_2_SOURCE: 1369 1369 + case MADERA_AIF1TX2MIX_INPUT_2_VOLUME: 1370 1370 + case MADERA_AIF1TX2MIX_INPUT_3_SOURCE: 1371 1371 + case MADERA_AIF1TX2MIX_INPUT_3_VOLUME: 1372 1372 + case MADERA_AIF1TX2MIX_INPUT_4_SOURCE: 1373 1373 + case MADERA_AIF1TX2MIX_INPUT_4_VOLUME: 1374 1374 + case MADERA_AIF1TX3MIX_INPUT_1_SOURCE: 1375 1375 + case MADERA_AIF1TX3MIX_INPUT_1_VOLUME: 1376 1376 + case MADERA_AIF1TX3MIX_INPUT_2_SOURCE: 1377 1377 + case MADERA_AIF1TX3MIX_INPUT_2_VOLUME: 1378 1378 + case MADERA_AIF1TX3MIX_INPUT_3_SOURCE: 1379 1379 + case MADERA_AIF1TX3MIX_INPUT_3_VOLUME: 1380 1380 + case MADERA_AIF1TX3MIX_INPUT_4_SOURCE: 1381 1381 + case MADERA_AIF1TX3MIX_INPUT_4_VOLUME: 1382 1382 + case MADERA_AIF1TX4MIX_INPUT_1_SOURCE: 1383 1383 + case MADERA_AIF1TX4MIX_INPUT_1_VOLUME: 1384 1384 + case MADERA_AIF1TX4MIX_INPUT_2_SOURCE: 1385 1385 + case MADERA_AIF1TX4MIX_INPUT_2_VOLUME: 1386 1386 + case MADERA_AIF1TX4MIX_INPUT_3_SOURCE: 1387 1387 + case MADERA_AIF1TX4MIX_INPUT_3_VOLUME: 1388 1388 + case MADERA_AIF1TX4MIX_INPUT_4_SOURCE: 1389 1389 + case MADERA_AIF1TX4MIX_INPUT_4_VOLUME: 1390 1390 + case MADERA_AIF1TX5MIX_INPUT_1_SOURCE: 1391 1391 + case MADERA_AIF1TX5MIX_INPUT_1_VOLUME: 1392 1392 + case MADERA_AIF1TX5MIX_INPUT_2_SOURCE: 1393 1393 + case MADERA_AIF1TX5MIX_INPUT_2_VOLUME: 1394 1394 + case MADERA_AIF1TX5MIX_INPUT_3_SOURCE: 1395 1395 + case MADERA_AIF1TX5MIX_INPUT_3_VOLUME: 1396 1396 + case MADERA_AIF1TX5MIX_INPUT_4_SOURCE: 1397 1397 + case MADERA_AIF1TX5MIX_INPUT_4_VOLUME: 1398 1398 + case MADERA_AIF1TX6MIX_INPUT_1_SOURCE: 1399 1399 + case MADERA_AIF1TX6MIX_INPUT_1_VOLUME: 1400 1400 + case MADERA_AIF1TX6MIX_INPUT_2_SOURCE: 1401 1401 + case MADERA_AIF1TX6MIX_INPUT_2_VOLUME: 1402 1402 + case MADERA_AIF1TX6MIX_INPUT_3_SOURCE: 1403 1403 + case MADERA_AIF1TX6MIX_INPUT_3_VOLUME: 1404 1404 + case MADERA_AIF1TX6MIX_INPUT_4_SOURCE: 1405 1405 + case MADERA_AIF1TX6MIX_INPUT_4_VOLUME: 1406 1406 + case MADERA_AIF1TX7MIX_INPUT_1_SOURCE: 1407 1407 + case MADERA_AIF1TX7MIX_INPUT_1_VOLUME: 1408 1408 + case MADERA_AIF1TX7MIX_INPUT_2_SOURCE: 1409 1409 + case MADERA_AIF1TX7MIX_INPUT_2_VOLUME: 1410 1410 + case MADERA_AIF1TX7MIX_INPUT_3_SOURCE: 1411 1411 + case MADERA_AIF1TX7MIX_INPUT_3_VOLUME: 1412 1412 + case MADERA_AIF1TX7MIX_INPUT_4_SOURCE: 1413 1413 + case MADERA_AIF1TX7MIX_INPUT_4_VOLUME: 1414 1414 + case MADERA_AIF1TX8MIX_INPUT_1_SOURCE: 1415 1415 + case MADERA_AIF1TX8MIX_INPUT_1_VOLUME: 1416 1416 + case MADERA_AIF1TX8MIX_INPUT_2_SOURCE: 1417 1417 + case MADERA_AIF1TX8MIX_INPUT_2_VOLUME: 1418 1418 + case MADERA_AIF1TX8MIX_INPUT_3_SOURCE: 1419 1419 + case MADERA_AIF1TX8MIX_INPUT_3_VOLUME: 1420 1420 + case MADERA_AIF1TX8MIX_INPUT_4_SOURCE: 1421 1421 + case MADERA_AIF1TX8MIX_INPUT_4_VOLUME: 1422 1422 + case MADERA_AIF2TX1MIX_INPUT_1_SOURCE: 1423 1423 + case MADERA_AIF2TX1MIX_INPUT_1_VOLUME: 1424 1424 + case MADERA_AIF2TX1MIX_INPUT_2_SOURCE: 1425 1425 + case MADERA_AIF2TX1MIX_INPUT_2_VOLUME: 1426 1426 + case MADERA_AIF2TX1MIX_INPUT_3_SOURCE: 1427 1427 + case MADERA_AIF2TX1MIX_INPUT_3_VOLUME: 1428 1428 + case MADERA_AIF2TX1MIX_INPUT_4_SOURCE: 1429 1429 + case MADERA_AIF2TX1MIX_INPUT_4_VOLUME: 1430 1430 + case MADERA_AIF2TX2MIX_INPUT_1_SOURCE: 1431 1431 + case MADERA_AIF2TX2MIX_INPUT_1_VOLUME: 1432 1432 + case MADERA_AIF2TX2MIX_INPUT_2_SOURCE: 1433 1433 + case MADERA_AIF2TX2MIX_INPUT_2_VOLUME: 1434 1434 + case MADERA_AIF2TX2MIX_INPUT_3_SOURCE: 1435 1435 + case MADERA_AIF2TX2MIX_INPUT_3_VOLUME: 1436 1436 + case MADERA_AIF2TX2MIX_INPUT_4_SOURCE: 1437 1437 + case MADERA_AIF2TX2MIX_INPUT_4_VOLUME: 1438 1438 + case MADERA_AIF2TX3MIX_INPUT_1_SOURCE: 1439 1439 + case MADERA_AIF2TX3MIX_INPUT_1_VOLUME: 1440 1440 + case MADERA_AIF2TX3MIX_INPUT_2_SOURCE: 1441 1441 + case MADERA_AIF2TX3MIX_INPUT_2_VOLUME: 1442 1442 + case MADERA_AIF2TX3MIX_INPUT_3_SOURCE: 1443 1443 + case MADERA_AIF2TX3MIX_INPUT_3_VOLUME: 1444 1444 + case MADERA_AIF2TX3MIX_INPUT_4_SOURCE: 1445 1445 + case MADERA_AIF2TX3MIX_INPUT_4_VOLUME: 1446 1446 + case MADERA_AIF2TX4MIX_INPUT_1_SOURCE: 1447 1447 + case MADERA_AIF2TX4MIX_INPUT_1_VOLUME: 1448 1448 + case MADERA_AIF2TX4MIX_INPUT_2_SOURCE: 1449 1449 + case MADERA_AIF2TX4MIX_INPUT_2_VOLUME: 1450 1450 + case MADERA_AIF2TX4MIX_INPUT_3_SOURCE: 1451 1451 + case MADERA_AIF2TX4MIX_INPUT_3_VOLUME: 1452 1452 + case MADERA_AIF2TX4MIX_INPUT_4_SOURCE: 1453 1453 + case MADERA_AIF2TX4MIX_INPUT_4_VOLUME: 1454 1454 + case MADERA_AIF2TX5MIX_INPUT_1_SOURCE: 1455 1455 + case MADERA_AIF2TX5MIX_INPUT_1_VOLUME: 1456 1456 + case MADERA_AIF2TX5MIX_INPUT_2_SOURCE: 1457 1457 + case MADERA_AIF2TX5MIX_INPUT_2_VOLUME: 1458 1458 + case MADERA_AIF2TX5MIX_INPUT_3_SOURCE: 1459 1459 + case MADERA_AIF2TX5MIX_INPUT_3_VOLUME: 1460 1460 + case MADERA_AIF2TX5MIX_INPUT_4_SOURCE: 1461 1461 + case MADERA_AIF2TX5MIX_INPUT_4_VOLUME: 1462 1462 + case MADERA_AIF2TX6MIX_INPUT_1_SOURCE: 1463 1463 + case MADERA_AIF2TX6MIX_INPUT_1_VOLUME: 1464 1464 + case MADERA_AIF2TX6MIX_INPUT_2_SOURCE: 1465 1465 + case MADERA_AIF2TX6MIX_INPUT_2_VOLUME: 1466 1466 + case MADERA_AIF2TX6MIX_INPUT_3_SOURCE: 1467 1467 + case MADERA_AIF2TX6MIX_INPUT_3_VOLUME: 1468 1468 + case MADERA_AIF2TX6MIX_INPUT_4_SOURCE: 1469 1469 + case MADERA_AIF2TX6MIX_INPUT_4_VOLUME: 1470 1470 + case MADERA_AIF2TX7MIX_INPUT_1_SOURCE: 1471 1471 + case MADERA_AIF2TX7MIX_INPUT_1_VOLUME: 1472 1472 + case MADERA_AIF2TX7MIX_INPUT_2_SOURCE: 1473 1473 + case MADERA_AIF2TX7MIX_INPUT_2_VOLUME: 1474 1474 + case MADERA_AIF2TX7MIX_INPUT_3_SOURCE: 1475 1475 + case MADERA_AIF2TX7MIX_INPUT_3_VOLUME: 1476 1476 + case MADERA_AIF2TX7MIX_INPUT_4_SOURCE: 1477 1477 + case MADERA_AIF2TX7MIX_INPUT_4_VOLUME: 1478 1478 + case MADERA_AIF2TX8MIX_INPUT_1_SOURCE: 1479 1479 + case MADERA_AIF2TX8MIX_INPUT_1_VOLUME: 1480 1480 + case MADERA_AIF2TX8MIX_INPUT_2_SOURCE: 1481 1481 + case MADERA_AIF2TX8MIX_INPUT_2_VOLUME: 1482 1482 + case MADERA_AIF2TX8MIX_INPUT_3_SOURCE: 1483 1483 + case MADERA_AIF2TX8MIX_INPUT_3_VOLUME: 1484 1484 + case MADERA_AIF2TX8MIX_INPUT_4_SOURCE: 1485 1485 + case MADERA_AIF2TX8MIX_INPUT_4_VOLUME: 1486 1486 + case MADERA_AIF3TX1MIX_INPUT_1_SOURCE: 1487 1487 + case MADERA_AIF3TX1MIX_INPUT_1_VOLUME: 1488 1488 + case MADERA_AIF3TX1MIX_INPUT_2_SOURCE: 1489 1489 + case MADERA_AIF3TX1MIX_INPUT_2_VOLUME: 1490 1490 + case MADERA_AIF3TX1MIX_INPUT_3_SOURCE: 1491 1491 + case MADERA_AIF3TX1MIX_INPUT_3_VOLUME: 1492 1492 + case MADERA_AIF3TX1MIX_INPUT_4_SOURCE: 1493 1493 + case MADERA_AIF3TX1MIX_INPUT_4_VOLUME: 1494 1494 + case MADERA_AIF3TX2MIX_INPUT_1_SOURCE: 1495 1495 + case MADERA_AIF3TX2MIX_INPUT_1_VOLUME: 1496 1496 + case MADERA_AIF3TX2MIX_INPUT_2_SOURCE: 1497 1497 + case MADERA_AIF3TX2MIX_INPUT_2_VOLUME: 1498 1498 + case MADERA_AIF3TX2MIX_INPUT_3_SOURCE: 1499 1499 + case MADERA_AIF3TX2MIX_INPUT_3_VOLUME: 1500 1500 + case MADERA_AIF3TX2MIX_INPUT_4_SOURCE: 1501 1501 + case MADERA_AIF3TX2MIX_INPUT_4_VOLUME: 1502 1502 + case MADERA_AIF3TX3MIX_INPUT_1_SOURCE: 1503 1503 + case MADERA_AIF3TX3MIX_INPUT_1_VOLUME: 1504 1504 + case MADERA_AIF3TX3MIX_INPUT_2_SOURCE: 1505 1505 + case MADERA_AIF3TX3MIX_INPUT_2_VOLUME: 1506 1506 + case MADERA_AIF3TX3MIX_INPUT_3_SOURCE: 1507 1507 + case MADERA_AIF3TX3MIX_INPUT_3_VOLUME: 1508 1508 + case MADERA_AIF3TX3MIX_INPUT_4_SOURCE: 1509 1509 + case MADERA_AIF3TX3MIX_INPUT_4_VOLUME: 1510 1510 + case MADERA_AIF3TX4MIX_INPUT_1_SOURCE: 1511 1511 + case MADERA_AIF3TX4MIX_INPUT_1_VOLUME: 1512 1512 + case MADERA_AIF3TX4MIX_INPUT_2_SOURCE: 1513 1513 + case MADERA_AIF3TX4MIX_INPUT_2_VOLUME: 1514 1514 + case MADERA_AIF3TX4MIX_INPUT_3_SOURCE: 1515 1515 + case MADERA_AIF3TX4MIX_INPUT_3_VOLUME: 1516 1516 + case MADERA_AIF3TX4MIX_INPUT_4_SOURCE: 1517 1517 + case MADERA_AIF3TX4MIX_INPUT_4_VOLUME: 1518 1518 + case CS47L92_AIF3TX5MIX_INPUT_1_SOURCE: 1519 1519 + case CS47L92_AIF3TX5MIX_INPUT_1_VOLUME: 1520 1520 + case CS47L92_AIF3TX5MIX_INPUT_2_SOURCE: 1521 1521 + case CS47L92_AIF3TX5MIX_INPUT_2_VOLUME: 1522 1522 + case CS47L92_AIF3TX5MIX_INPUT_3_SOURCE: 1523 1523 + case CS47L92_AIF3TX5MIX_INPUT_3_VOLUME: 1524 1524 + case CS47L92_AIF3TX5MIX_INPUT_4_SOURCE: 1525 1525 + case CS47L92_AIF3TX5MIX_INPUT_4_VOLUME: 1526 1526 + case CS47L92_AIF3TX6MIX_INPUT_1_SOURCE: 1527 1527 + case CS47L92_AIF3TX6MIX_INPUT_1_VOLUME: 1528 1528 + case CS47L92_AIF3TX6MIX_INPUT_2_SOURCE: 1529 1529 + case CS47L92_AIF3TX6MIX_INPUT_2_VOLUME: 1530 1530 + case CS47L92_AIF3TX6MIX_INPUT_3_SOURCE: 1531 1531 + case CS47L92_AIF3TX6MIX_INPUT_3_VOLUME: 1532 1532 + case CS47L92_AIF3TX6MIX_INPUT_4_SOURCE: 1533 1533 + case CS47L92_AIF3TX6MIX_INPUT_4_VOLUME: 1534 1534 + case CS47L92_AIF3TX7MIX_INPUT_1_SOURCE: 1535 1535 + case CS47L92_AIF3TX7MIX_INPUT_1_VOLUME: 1536 1536 + case CS47L92_AIF3TX7MIX_INPUT_2_SOURCE: 1537 1537 + case CS47L92_AIF3TX7MIX_INPUT_2_VOLUME: 1538 1538 + case CS47L92_AIF3TX7MIX_INPUT_3_SOURCE: 1539 1539 + case CS47L92_AIF3TX7MIX_INPUT_3_VOLUME: 1540 1540 + case CS47L92_AIF3TX7MIX_INPUT_4_SOURCE: 1541 1541 + case CS47L92_AIF3TX7MIX_INPUT_4_VOLUME: 1542 1542 + case CS47L92_AIF3TX8MIX_INPUT_1_SOURCE: 1543 1543 + case CS47L92_AIF3TX8MIX_INPUT_1_VOLUME: 1544 1544 + case CS47L92_AIF3TX8MIX_INPUT_2_SOURCE: 1545 1545 + case CS47L92_AIF3TX8MIX_INPUT_2_VOLUME: 1546 1546 + case CS47L92_AIF3TX8MIX_INPUT_3_SOURCE: 1547 1547 + case CS47L92_AIF3TX8MIX_INPUT_3_VOLUME: 1548 1548 + case CS47L92_AIF3TX8MIX_INPUT_4_SOURCE: 1549 1549 + case CS47L92_AIF3TX8MIX_INPUT_4_VOLUME: 1550 1550 + case MADERA_SLIMTX1MIX_INPUT_1_SOURCE: 1551 1551 + case MADERA_SLIMTX1MIX_INPUT_1_VOLUME: 1552 1552 + case MADERA_SLIMTX1MIX_INPUT_2_SOURCE: 1553 1553 + case MADERA_SLIMTX1MIX_INPUT_2_VOLUME: 1554 1554 + case MADERA_SLIMTX1MIX_INPUT_3_SOURCE: 1555 1555 + case MADERA_SLIMTX1MIX_INPUT_3_VOLUME: 1556 1556 + case MADERA_SLIMTX1MIX_INPUT_4_SOURCE: 1557 1557 + case MADERA_SLIMTX1MIX_INPUT_4_VOLUME: 1558 1558 + case MADERA_SLIMTX2MIX_INPUT_1_SOURCE: 1559 1559 + case MADERA_SLIMTX2MIX_INPUT_1_VOLUME: 1560 1560 + case MADERA_SLIMTX2MIX_INPUT_2_SOURCE: 1561 1561 + case MADERA_SLIMTX2MIX_INPUT_2_VOLUME: 1562 1562 + case MADERA_SLIMTX2MIX_INPUT_3_SOURCE: 1563 1563 + case MADERA_SLIMTX2MIX_INPUT_3_VOLUME: 1564 1564 + case MADERA_SLIMTX2MIX_INPUT_4_SOURCE: 1565 1565 + case MADERA_SLIMTX2MIX_INPUT_4_VOLUME: 1566 1566 + case MADERA_SLIMTX3MIX_INPUT_1_SOURCE: 1567 1567 + case MADERA_SLIMTX3MIX_INPUT_1_VOLUME: 1568 1568 + case MADERA_SLIMTX3MIX_INPUT_2_SOURCE: 1569 1569 + case MADERA_SLIMTX3MIX_INPUT_2_VOLUME: 1570 1570 + case MADERA_SLIMTX3MIX_INPUT_3_SOURCE: 1571 1571 + case MADERA_SLIMTX3MIX_INPUT_3_VOLUME: 1572 1572 + case MADERA_SLIMTX3MIX_INPUT_4_SOURCE: 1573 1573 + case MADERA_SLIMTX3MIX_INPUT_4_VOLUME: 1574 1574 + case MADERA_SLIMTX4MIX_INPUT_1_SOURCE: 1575 1575 + case MADERA_SLIMTX4MIX_INPUT_1_VOLUME: 1576 1576 + case MADERA_SLIMTX4MIX_INPUT_2_SOURCE: 1577 1577 + case MADERA_SLIMTX4MIX_INPUT_2_VOLUME: 1578 1578 + case MADERA_SLIMTX4MIX_INPUT_3_SOURCE: 1579 1579 + case MADERA_SLIMTX4MIX_INPUT_3_VOLUME: 1580 1580 + case MADERA_SLIMTX4MIX_INPUT_4_SOURCE: 1581 1581 + case MADERA_SLIMTX4MIX_INPUT_4_VOLUME: 1582 1582 + case MADERA_SLIMTX5MIX_INPUT_1_SOURCE: 1583 1583 + case MADERA_SLIMTX5MIX_INPUT_1_VOLUME: 1584 1584 + case MADERA_SLIMTX5MIX_INPUT_2_SOURCE: 1585 1585 + case MADERA_SLIMTX5MIX_INPUT_2_VOLUME: 1586 1586 + case MADERA_SLIMTX5MIX_INPUT_3_SOURCE: 1587 1587 + case MADERA_SLIMTX5MIX_INPUT_3_VOLUME: 1588 1588 + case MADERA_SLIMTX5MIX_INPUT_4_SOURCE: 1589 1589 + case MADERA_SLIMTX5MIX_INPUT_4_VOLUME: 1590 1590 + case MADERA_SLIMTX6MIX_INPUT_1_SOURCE: 1591 1591 + case MADERA_SLIMTX6MIX_INPUT_1_VOLUME: 1592 1592 + case MADERA_SLIMTX6MIX_INPUT_2_SOURCE: 1593 1593 + case MADERA_SLIMTX6MIX_INPUT_2_VOLUME: 1594 1594 + case MADERA_SLIMTX6MIX_INPUT_3_SOURCE: 1595 1595 + case MADERA_SLIMTX6MIX_INPUT_3_VOLUME: 1596 1596 + case MADERA_SLIMTX6MIX_INPUT_4_SOURCE: 1597 1597 + case MADERA_SLIMTX6MIX_INPUT_4_VOLUME: 1598 1598 + case MADERA_SLIMTX7MIX_INPUT_1_SOURCE: 1599 1599 + case MADERA_SLIMTX7MIX_INPUT_1_VOLUME: 1600 1600 + case MADERA_SLIMTX7MIX_INPUT_2_SOURCE: 1601 1601 + case MADERA_SLIMTX7MIX_INPUT_2_VOLUME: 1602 1602 + case MADERA_SLIMTX7MIX_INPUT_3_SOURCE: 1603 1603 + case MADERA_SLIMTX7MIX_INPUT_3_VOLUME: 1604 1604 + case MADERA_SLIMTX7MIX_INPUT_4_SOURCE: 1605 1605 + case MADERA_SLIMTX7MIX_INPUT_4_VOLUME: 1606 1606 + case MADERA_SLIMTX8MIX_INPUT_1_SOURCE: 1607 1607 + case MADERA_SLIMTX8MIX_INPUT_1_VOLUME: 1608 1608 + case MADERA_SLIMTX8MIX_INPUT_2_SOURCE: 1609 1609 + case MADERA_SLIMTX8MIX_INPUT_2_VOLUME: 1610 1610 + case MADERA_SLIMTX8MIX_INPUT_3_SOURCE: 1611 1611 + case MADERA_SLIMTX8MIX_INPUT_3_VOLUME: 1612 1612 + case MADERA_SLIMTX8MIX_INPUT_4_SOURCE: 1613 1613 + case MADERA_SLIMTX8MIX_INPUT_4_VOLUME: 1614 1614 + case MADERA_SPDIF1TX1MIX_INPUT_1_SOURCE: 1615 1615 + case MADERA_SPDIF1TX1MIX_INPUT_1_VOLUME: 1616 1616 + case MADERA_SPDIF1TX2MIX_INPUT_1_SOURCE: 1617 1617 + case MADERA_SPDIF1TX2MIX_INPUT_1_VOLUME: 1618 1618 + case MADERA_EQ1MIX_INPUT_1_SOURCE: 1619 1619 + case MADERA_EQ1MIX_INPUT_1_VOLUME: 1620 1620 + case MADERA_EQ1MIX_INPUT_2_SOURCE: 1621 1621 + case MADERA_EQ1MIX_INPUT_2_VOLUME: 1622 1622 + case MADERA_EQ1MIX_INPUT_3_SOURCE: 1623 1623 + case MADERA_EQ1MIX_INPUT_3_VOLUME: 1624 1624 + case MADERA_EQ1MIX_INPUT_4_SOURCE: 1625 1625 + case MADERA_EQ1MIX_INPUT_4_VOLUME: 1626 1626 + case MADERA_EQ2MIX_INPUT_1_SOURCE: 1627 1627 + case MADERA_EQ2MIX_INPUT_1_VOLUME: 1628 1628 + case MADERA_EQ2MIX_INPUT_2_SOURCE: 1629 1629 + case MADERA_EQ2MIX_INPUT_2_VOLUME: 1630 1630 + case MADERA_EQ2MIX_INPUT_3_SOURCE: 1631 1631 + case MADERA_EQ2MIX_INPUT_3_VOLUME: 1632 1632 + case MADERA_EQ2MIX_INPUT_4_SOURCE: 1633 1633 + case MADERA_EQ2MIX_INPUT_4_VOLUME: 1634 1634 + case MADERA_EQ3MIX_INPUT_1_SOURCE: 1635 1635 + case MADERA_EQ3MIX_INPUT_1_VOLUME: 1636 1636 + case MADERA_EQ3MIX_INPUT_2_SOURCE: 1637 1637 + case MADERA_EQ3MIX_INPUT_2_VOLUME: 1638 1638 + case MADERA_EQ3MIX_INPUT_3_SOURCE: 1639 1639 + case MADERA_EQ3MIX_INPUT_3_VOLUME: 1640 1640 + case MADERA_EQ3MIX_INPUT_4_SOURCE: 1641 1641 + case MADERA_EQ3MIX_INPUT_4_VOLUME: 1642 1642 + case MADERA_EQ4MIX_INPUT_1_SOURCE: 1643 1643 + case MADERA_EQ4MIX_INPUT_1_VOLUME: 1644 1644 + case MADERA_EQ4MIX_INPUT_2_SOURCE: 1645 1645 + case MADERA_EQ4MIX_INPUT_2_VOLUME: 1646 1646 + case MADERA_EQ4MIX_INPUT_3_SOURCE: 1647 1647 + case MADERA_EQ4MIX_INPUT_3_VOLUME: 1648 1648 + case MADERA_EQ4MIX_INPUT_4_SOURCE: 1649 1649 + case MADERA_EQ4MIX_INPUT_4_VOLUME: 1650 1650 + case MADERA_DRC1LMIX_INPUT_1_SOURCE: 1651 1651 + case MADERA_DRC1LMIX_INPUT_1_VOLUME: 1652 1652 + case MADERA_DRC1LMIX_INPUT_2_SOURCE: 1653 1653 + case MADERA_DRC1LMIX_INPUT_2_VOLUME: 1654 1654 + case MADERA_DRC1LMIX_INPUT_3_SOURCE: 1655 1655 + case MADERA_DRC1LMIX_INPUT_3_VOLUME: 1656 1656 + case MADERA_DRC1LMIX_INPUT_4_SOURCE: 1657 1657 + case MADERA_DRC1LMIX_INPUT_4_VOLUME: 1658 1658 + case MADERA_DRC1RMIX_INPUT_1_SOURCE: 1659 1659 + case MADERA_DRC1RMIX_INPUT_1_VOLUME: 1660 1660 + case MADERA_DRC1RMIX_INPUT_2_SOURCE: 1661 1661 + case MADERA_DRC1RMIX_INPUT_2_VOLUME: 1662 1662 + case MADERA_DRC1RMIX_INPUT_3_SOURCE: 1663 1663 + case MADERA_DRC1RMIX_INPUT_3_VOLUME: 1664 1664 + case MADERA_DRC1RMIX_INPUT_4_SOURCE: 1665 1665 + case MADERA_DRC1RMIX_INPUT_4_VOLUME: 1666 1666 + case MADERA_DRC2LMIX_INPUT_1_SOURCE: 1667 1667 + case MADERA_DRC2LMIX_INPUT_1_VOLUME: 1668 1668 + case MADERA_DRC2LMIX_INPUT_2_SOURCE: 1669 1669 + case MADERA_DRC2LMIX_INPUT_2_VOLUME: 1670 1670 + case MADERA_DRC2LMIX_INPUT_3_SOURCE: 1671 1671 + case MADERA_DRC2LMIX_INPUT_3_VOLUME: 1672 1672 + case MADERA_DRC2LMIX_INPUT_4_SOURCE: 1673 1673 + case MADERA_DRC2LMIX_INPUT_4_VOLUME: 1674 1674 + case MADERA_DRC2RMIX_INPUT_1_SOURCE: 1675 1675 + case MADERA_DRC2RMIX_INPUT_1_VOLUME: 1676 1676 + case MADERA_DRC2RMIX_INPUT_2_SOURCE: 1677 1677 + case MADERA_DRC2RMIX_INPUT_2_VOLUME: 1678 1678 + case MADERA_DRC2RMIX_INPUT_3_SOURCE: 1679 1679 + case MADERA_DRC2RMIX_INPUT_3_VOLUME: 1680 1680 + case MADERA_DRC2RMIX_INPUT_4_SOURCE: 1681 1681 + case MADERA_DRC2RMIX_INPUT_4_VOLUME: 1682 1682 + case MADERA_HPLP1MIX_INPUT_1_SOURCE: 1683 1683 + case MADERA_HPLP1MIX_INPUT_1_VOLUME: 1684 1684 + case MADERA_HPLP1MIX_INPUT_2_SOURCE: 1685 1685 + case MADERA_HPLP1MIX_INPUT_2_VOLUME: 1686 1686 + case MADERA_HPLP1MIX_INPUT_3_SOURCE: 1687 1687 + case MADERA_HPLP1MIX_INPUT_3_VOLUME: 1688 1688 + case MADERA_HPLP1MIX_INPUT_4_SOURCE: 1689 1689 + case MADERA_HPLP1MIX_INPUT_4_VOLUME: 1690 1690 + case MADERA_HPLP2MIX_INPUT_1_SOURCE: 1691 1691 + case MADERA_HPLP2MIX_INPUT_1_VOLUME: 1692 1692 + case MADERA_HPLP2MIX_INPUT_2_SOURCE: 1693 1693 + case MADERA_HPLP2MIX_INPUT_2_VOLUME: 1694 1694 + case MADERA_HPLP2MIX_INPUT_3_SOURCE: 1695 1695 + case MADERA_HPLP2MIX_INPUT_3_VOLUME: 1696 1696 + case MADERA_HPLP2MIX_INPUT_4_SOURCE: 1697 1697 + case MADERA_HPLP2MIX_INPUT_4_VOLUME: 1698 1698 + case MADERA_HPLP3MIX_INPUT_1_SOURCE: 1699 1699 + case MADERA_HPLP3MIX_INPUT_1_VOLUME: 1700 1700 + case MADERA_HPLP3MIX_INPUT_2_SOURCE: 1701 1701 + case MADERA_HPLP3MIX_INPUT_2_VOLUME: 1702 1702 + case MADERA_HPLP3MIX_INPUT_3_SOURCE: 1703 1703 + case MADERA_HPLP3MIX_INPUT_3_VOLUME: 1704 1704 + case MADERA_HPLP3MIX_INPUT_4_SOURCE: 1705 1705 + case MADERA_HPLP3MIX_INPUT_4_VOLUME: 1706 1706 + case MADERA_HPLP4MIX_INPUT_1_SOURCE: 1707 1707 + case MADERA_HPLP4MIX_INPUT_1_VOLUME: 1708 1708 + case MADERA_HPLP4MIX_INPUT_2_SOURCE: 1709 1709 + case MADERA_HPLP4MIX_INPUT_2_VOLUME: 1710 1710 + case MADERA_HPLP4MIX_INPUT_3_SOURCE: 1711 1711 + case MADERA_HPLP4MIX_INPUT_3_VOLUME: 1712 1712 + case MADERA_HPLP4MIX_INPUT_4_SOURCE: 1713 1713 + case MADERA_HPLP4MIX_INPUT_4_VOLUME: 1714 1714 + case MADERA_DSP1LMIX_INPUT_1_SOURCE: 1715 1715 + case MADERA_DSP1LMIX_INPUT_1_VOLUME: 1716 1716 + case MADERA_DSP1LMIX_INPUT_2_SOURCE: 1717 1717 + case MADERA_DSP1LMIX_INPUT_2_VOLUME: 1718 1718 + case MADERA_DSP1LMIX_INPUT_3_SOURCE: 1719 1719 + case MADERA_DSP1LMIX_INPUT_3_VOLUME: 1720 1720 + case MADERA_DSP1LMIX_INPUT_4_SOURCE: 1721 1721 + case MADERA_DSP1LMIX_INPUT_4_VOLUME: 1722 1722 + case MADERA_DSP1RMIX_INPUT_1_SOURCE: 1723 1723 + case MADERA_DSP1RMIX_INPUT_1_VOLUME: 1724 1724 + case MADERA_DSP1RMIX_INPUT_2_SOURCE: 1725 1725 + case MADERA_DSP1RMIX_INPUT_2_VOLUME: 1726 1726 + case MADERA_DSP1RMIX_INPUT_3_SOURCE: 1727 1727 + case MADERA_DSP1RMIX_INPUT_3_VOLUME: 1728 1728 + case MADERA_DSP1RMIX_INPUT_4_SOURCE: 1729 1729 + case MADERA_DSP1RMIX_INPUT_4_VOLUME: 1730 1730 + case MADERA_DSP1AUX1MIX_INPUT_1_SOURCE: 1731 1731 + case MADERA_DSP1AUX2MIX_INPUT_1_SOURCE: 1732 1732 + case MADERA_DSP1AUX3MIX_INPUT_1_SOURCE: 1733 1733 + case MADERA_DSP1AUX4MIX_INPUT_1_SOURCE: 1734 1734 + case MADERA_DSP1AUX5MIX_INPUT_1_SOURCE: 1735 1735 + case MADERA_DSP1AUX6MIX_INPUT_1_SOURCE: 1736 1736 + case MADERA_ASRC1_1LMIX_INPUT_1_SOURCE: 1737 1737 + case MADERA_ASRC1_1RMIX_INPUT_1_SOURCE: 1738 1738 + case MADERA_ASRC1_2LMIX_INPUT_1_SOURCE: 1739 1739 + case MADERA_ASRC1_2RMIX_INPUT_1_SOURCE: 1740 1740 + case MADERA_ISRC1DEC1MIX_INPUT_1_SOURCE: 1741 1741 + case MADERA_ISRC1DEC2MIX_INPUT_1_SOURCE: 1742 1742 + case MADERA_ISRC1INT1MIX_INPUT_1_SOURCE: 1743 1743 + case MADERA_ISRC1INT2MIX_INPUT_1_SOURCE: 1744 1744 + case MADERA_ISRC2DEC1MIX_INPUT_1_SOURCE: 1745 1745 + case MADERA_ISRC2DEC2MIX_INPUT_1_SOURCE: 1746 1746 + case MADERA_ISRC2INT1MIX_INPUT_1_SOURCE: 1747 1747 + case MADERA_ISRC2INT2MIX_INPUT_1_SOURCE: 1748 1748 + case MADERA_DFC1MIX_INPUT_1_SOURCE: 1749 1749 + case MADERA_DFC2MIX_INPUT_1_SOURCE: 1750 1750 + case MADERA_DFC3MIX_INPUT_1_SOURCE: 1751 1751 + case MADERA_DFC4MIX_INPUT_1_SOURCE: 1752 1752 + case MADERA_DFC5MIX_INPUT_1_SOURCE: 1753 1753 + case MADERA_DFC6MIX_INPUT_1_SOURCE: 1754 1754 + case MADERA_DFC7MIX_INPUT_1_SOURCE: 1755 1755 + case MADERA_DFC8MIX_INPUT_1_SOURCE: 1756 1756 + case MADERA_FX_CTRL1 ... MADERA_FX_CTRL2: 1757 1757 + case MADERA_EQ1_1 ... MADERA_EQ1_21: 1758 1758 + case MADERA_EQ2_1 ... MADERA_EQ2_21: 1759 1759 + case MADERA_EQ3_1 ... MADERA_EQ3_21: 1760 1760 + case MADERA_EQ4_1 ... MADERA_EQ4_21: 1761 1761 + case MADERA_DRC1_CTRL1 ... MADERA_DRC1_CTRL5: 1762 1762 + case MADERA_DRC2_CTRL1 ... MADERA_DRC2_CTRL5: 1763 1763 + case MADERA_HPLPF1_1 ... MADERA_HPLPF1_2: 1764 1764 + case MADERA_HPLPF2_1 ... MADERA_HPLPF2_2: 1765 1765 + case MADERA_HPLPF3_1 ... MADERA_HPLPF3_2: 1766 1766 + case MADERA_HPLPF4_1 ... MADERA_HPLPF4_2: 1767 1767 + case MADERA_ASRC1_ENABLE: 1768 1768 + case MADERA_ASRC1_STATUS: 1769 1769 + case MADERA_ASRC1_RATE1 ... MADERA_ASRC1_RATE2: 1770 1770 + case MADERA_ISRC_1_CTRL_1 ... MADERA_ISRC_1_CTRL_3: 1771 1771 + case MADERA_ISRC_2_CTRL_1 ... MADERA_ISRC_2_CTRL_3: 1772 1772 + case MADERA_AUXPDM1_CTRL_0 ... MADERA_AUXPDM1_CTRL_1: 1773 1773 + case MADERA_DFC1_CTRL: 1774 1774 + case MADERA_DFC1_RX: 1775 1775 + case MADERA_DFC1_TX: 1776 1776 + case MADERA_DFC2_CTRL: 1777 1777 + case MADERA_DFC2_RX: 1778 1778 + case MADERA_DFC2_TX: 1779 1779 + case MADERA_DFC3_CTRL: 1780 1780 + case MADERA_DFC3_RX: 1781 1781 + case MADERA_DFC3_TX: 1782 1782 + case MADERA_DFC4_CTRL: 1783 1783 + case MADERA_DFC4_RX: 1784 1784 + case MADERA_DFC4_TX: 1785 1785 + case MADERA_DFC5_CTRL: 1786 1786 + case MADERA_DFC5_RX: 1787 1787 + case MADERA_DFC5_TX: 1788 1788 + case MADERA_DFC6_CTRL: 1789 1789 + case MADERA_DFC6_RX: 1790 1790 + case MADERA_DFC6_TX: 1791 1791 + case MADERA_DFC7_CTRL: 1792 1792 + case MADERA_DFC7_RX: 1793 1793 + case MADERA_DFC7_TX: 1794 1794 + case MADERA_DFC8_CTRL: 1795 1795 + case MADERA_DFC8_RX: 1796 1796 + case MADERA_DFC8_TX: 1797 1797 + case MADERA_DFC_STATUS: 1798 1798 + case MADERA_GPIO1_CTRL_1 ... MADERA_GPIO16_CTRL_2: 1799 1799 + case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33: 1800 1800 + case MADERA_IRQ1_MASK_1 ... MADERA_IRQ1_MASK_33: 1801 1801 + case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33: 1802 1802 + case MADERA_INTERRUPT_DEBOUNCE_7: 1803 1803 + case MADERA_IRQ1_CTRL: 1804 1804 + return true; 1805 1805 + default: 1806 1806 + return false; 1807 1807 + } 1808 1808 + } 1809 1809 + 1810 1810 + static bool cs47l92_16bit_volatile_register(struct device *dev, 1811 1811 + unsigned int reg) 1812 1812 + { 1813 1813 + switch (reg) { 1814 1814 + case MADERA_SOFTWARE_RESET: 1815 1815 + case MADERA_HARDWARE_REVISION: 1816 1816 + case MADERA_WRITE_SEQUENCER_CTRL_0 ... MADERA_WRITE_SEQUENCER_CTRL_2: 1817 1817 + case MADERA_HAPTICS_STATUS: 1818 1818 + case MADERA_SAMPLE_RATE_1_STATUS: 1819 1819 + case MADERA_SAMPLE_RATE_2_STATUS: 1820 1820 + case MADERA_SAMPLE_RATE_3_STATUS: 1821 1821 + case MADERA_ASYNC_SAMPLE_RATE_1_STATUS: 1822 1822 + case MADERA_ASYNC_SAMPLE_RATE_2_STATUS: 1823 1823 + case MADERA_HP_CTRL_1L: 1824 1824 + case MADERA_HP_CTRL_1R: 1825 1825 + case MADERA_HP_CTRL_2L: 1826 1826 + case MADERA_HP_CTRL_2R: 1827 1827 + case MADERA_HP_CTRL_3L: 1828 1828 + case MADERA_HP_CTRL_3R: 1829 1829 + case MADERA_MIC_DETECT_1_CONTROL_3: 1830 1830 + case MADERA_MIC_DETECT_1_CONTROL_4: 1831 1831 + case MADERA_MIC_DETECT_2_CONTROL_3: 1832 1832 + case MADERA_MIC_DETECT_2_CONTROL_4: 1833 1833 + case MADERA_HEADPHONE_DETECT_2: 1834 1834 + case MADERA_HEADPHONE_DETECT_3: 1835 1835 + case MADERA_HEADPHONE_DETECT_5: 1836 1836 + case MADERA_INPUT_ENABLES_STATUS: 1837 1837 + case MADERA_OUTPUT_STATUS_1: 1838 1838 + case MADERA_RAW_OUTPUT_STATUS_1: 1839 1839 + case MADERA_SPD1_TX_CHANNEL_STATUS_1: 1840 1840 + case MADERA_SPD1_TX_CHANNEL_STATUS_2: 1841 1841 + case MADERA_SPD1_TX_CHANNEL_STATUS_3: 1842 1842 + case MADERA_SLIMBUS_RX_PORT_STATUS: 1843 1843 + case MADERA_SLIMBUS_TX_PORT_STATUS: 1844 1844 + case MADERA_FX_CTRL2: 1845 1845 + case MADERA_ASRC1_STATUS: 1846 1846 + case MADERA_DFC_STATUS: 1847 1847 + case MADERA_IRQ1_STATUS_1 ... MADERA_IRQ1_STATUS_33: 1848 1848 + case MADERA_IRQ1_RAW_STATUS_1 ... MADERA_IRQ1_RAW_STATUS_33: 1849 1849 + return true; 1850 1850 + default: 1851 1851 + return false; 1852 1852 + } 1853 1853 + } 1854 1854 + 1855 1855 + static bool cs47l92_32bit_readable_register(struct device *dev, 1856 1856 + unsigned int reg) 1857 1857 + { 1858 1858 + switch (reg) { 1859 1859 + case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_508: 1860 1860 + case MADERA_OTP_HPDET_CAL_1 ... MADERA_OTP_HPDET_CAL_2: 1861 1861 + case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR: 1862 1862 + return true; 1863 1863 + default: 1864 1864 + return cs47l92_is_adsp_memory(reg); 1865 1865 + } 1866 1866 + } 1867 1867 + 1868 1868 + static bool cs47l92_32bit_volatile_register(struct device *dev, 1869 1869 + unsigned int reg) 1870 1870 + { 1871 1871 + switch (reg) { 1872 1872 + case MADERA_WSEQ_SEQUENCE_1 ... MADERA_WSEQ_SEQUENCE_508: 1873 1873 + case MADERA_OTP_HPDET_CAL_1 ... MADERA_OTP_HPDET_CAL_2: 1874 1874 + case MADERA_DSP1_CONFIG_1 ... MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR: 1875 1875 + return true; 1876 1876 + default: 1877 1877 + return cs47l92_is_adsp_memory(reg); 1878 1878 + } 1879 1879 + } 1880 1880 + 1881 1881 + const struct regmap_config cs47l92_16bit_spi_regmap = { 1882 1882 + .name = "cs47l92_16bit", 1883 1883 + .reg_bits = 32, 1884 1884 + .pad_bits = 16, 1885 1885 + .val_bits = 16, 1886 1886 + .reg_format_endian = REGMAP_ENDIAN_BIG, 1887 1887 + .val_format_endian = REGMAP_ENDIAN_BIG, 1888 1888 + 1889 1889 + .max_register = MADERA_INTERRUPT_RAW_STATUS_1, 1890 1890 + .readable_reg = &cs47l92_16bit_readable_register, 1891 1891 + .volatile_reg = &cs47l92_16bit_volatile_register, 1892 1892 + 1893 1893 + .cache_type = REGCACHE_RBTREE, 1894 1894 + .reg_defaults = cs47l92_reg_default, 1895 1895 + .num_reg_defaults = ARRAY_SIZE(cs47l92_reg_default), 1896 1896 + }; 1897 1897 + EXPORT_SYMBOL_GPL(cs47l92_16bit_spi_regmap); 1898 1898 + 1899 1899 + const struct regmap_config cs47l92_16bit_i2c_regmap = { 1900 1900 + .name = "cs47l92_16bit", 1901 1901 + .reg_bits = 32, 1902 1902 + .val_bits = 16, 1903 1903 + .reg_format_endian = REGMAP_ENDIAN_BIG, 1904 1904 + .val_format_endian = REGMAP_ENDIAN_BIG, 1905 1905 + 1906 1906 + .max_register = MADERA_INTERRUPT_RAW_STATUS_1, 1907 1907 + .readable_reg = &cs47l92_16bit_readable_register, 1908 1908 + .volatile_reg = &cs47l92_16bit_volatile_register, 1909 1909 + 1910 1910 + .cache_type = REGCACHE_RBTREE, 1911 1911 + .reg_defaults = cs47l92_reg_default, 1912 1912 + .num_reg_defaults = ARRAY_SIZE(cs47l92_reg_default), 1913 1913 + }; 1914 1914 + EXPORT_SYMBOL_GPL(cs47l92_16bit_i2c_regmap); 1915 1915 + 1916 1916 + const struct regmap_config cs47l92_32bit_spi_regmap = { 1917 1917 + .name = "cs47l92_32bit", 1918 1918 + .reg_bits = 32, 1919 1919 + .reg_stride = 2, 1920 1920 + .pad_bits = 16, 1921 1921 + .val_bits = 32, 1922 1922 + .reg_format_endian = REGMAP_ENDIAN_BIG, 1923 1923 + .val_format_endian = REGMAP_ENDIAN_BIG, 1924 1924 + 1925 1925 + .max_register = MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR, 1926 1926 + .readable_reg = &cs47l92_32bit_readable_register, 1927 1927 + .volatile_reg = &cs47l92_32bit_volatile_register, 1928 1928 + 1929 1929 + .cache_type = REGCACHE_RBTREE, 1930 1930 + }; 1931 1931 + EXPORT_SYMBOL_GPL(cs47l92_32bit_spi_regmap); 1932 1932 + 1933 1933 + const struct regmap_config cs47l92_32bit_i2c_regmap = { 1934 1934 + .name = "cs47l92_32bit", 1935 1935 + .reg_bits = 32, 1936 1936 + .reg_stride = 2, 1937 1937 + .val_bits = 32, 1938 1938 + .reg_format_endian = REGMAP_ENDIAN_BIG, 1939 1939 + .val_format_endian = REGMAP_ENDIAN_BIG, 1940 1940 + 1941 1941 + .max_register = MADERA_DSP1_PMEM_ERR_ADDR___XMEM_ERR_ADDR, 1942 1942 + .readable_reg = &cs47l92_32bit_readable_register, 1943 1943 + .volatile_reg = &cs47l92_32bit_volatile_register, 1944 1944 + 1945 1945 + .cache_type = REGCACHE_RBTREE, 1946 1946 + }; 1947 1947 + EXPORT_SYMBOL_GPL(cs47l92_32bit_i2c_regmap);

+7 -17

drivers/mfd/cs5535-mfd.c

reviewed

··· 100 100 }, 101 101 }; 102 102 103 103 - #ifdef CONFIG_OLPC 104 104 - static void cs5535_clone_olpc_cells(void) 105 105 - { 106 106 - static const char *acpi_clones[] = { 107 107 - "olpc-xo1-pm-acpi", 108 108 - "olpc-xo1-sci-acpi" 109 109 - }; 110 110 - 111 111 - if (!machine_is_olpc()) 112 112 - return; 113 113 - 114 114 - mfd_clone_cell("cs5535-acpi", acpi_clones, ARRAY_SIZE(acpi_clones)); 115 115 - } 116 116 - #else 117 117 - static void cs5535_clone_olpc_cells(void) { } 118 118 - #endif 103 103 + static const char *olpc_acpi_clones[] = { 104 104 + "olpc-xo1-pm-acpi", 105 105 + "olpc-xo1-sci-acpi" 106 106 + }; 119 107 120 108 static int cs5535_mfd_probe(struct pci_dev *pdev, 121 109 const struct pci_device_id *id) ··· 133 145 dev_err(&pdev->dev, "MFD add devices failed: %d\n", err); 134 146 goto err_disable; 135 147 } 136 136 - cs5535_clone_olpc_cells(); 148 148 + 149 149 + if (machine_is_olpc()) 150 150 + mfd_clone_cell("cs5535-acpi", olpc_acpi_clones, ARRAY_SIZE(olpc_acpi_clones)); 137 151 138 152 dev_info(&pdev->dev, "%zu devices registered.\n", 139 153 ARRAY_SIZE(cs5535_mfd_cells));

+2

drivers/mfd/hi655x-pmic.c

reviewed

··· 109 109 110 110 pmic->regmap = devm_regmap_init_mmio_clk(dev, NULL, base, 111 111 &hi655x_regmap_config); 112 112 + if (IS_ERR(pmic->regmap)) 113 113 + return PTR_ERR(pmic->regmap); 112 114 113 115 regmap_read(pmic->regmap, HI655X_BUS_ADDR(HI655X_VER_REG), &pmic->ver); 114 116 if ((pmic->ver < PMU_VER_START) || (pmic->ver > PMU_VER_END)) {

+18 -3

drivers/mfd/intel-lpss-pci.c

reviewed

··· 183 183 { PCI_VDEVICE(INTEL, 0x31bc), (kernel_ulong_t)&bxt_uart_info }, 184 184 { PCI_VDEVICE(INTEL, 0x31be), (kernel_ulong_t)&bxt_uart_info }, 185 185 { PCI_VDEVICE(INTEL, 0x31c0), (kernel_ulong_t)&bxt_uart_info }, 186 186 - { PCI_VDEVICE(INTEL, 0x31ee), (kernel_ulong_t)&bxt_uart_info }, 187 186 { PCI_VDEVICE(INTEL, 0x31c2), (kernel_ulong_t)&bxt_info }, 188 187 { PCI_VDEVICE(INTEL, 0x31c4), (kernel_ulong_t)&bxt_info }, 189 188 { PCI_VDEVICE(INTEL, 0x31c6), (kernel_ulong_t)&bxt_info }, 189 189 + { PCI_VDEVICE(INTEL, 0x31ee), (kernel_ulong_t)&bxt_uart_info }, 190 190 /* ICL-LP */ 191 191 { PCI_VDEVICE(INTEL, 0x34a8), (kernel_ulong_t)&spt_uart_info }, 192 192 { PCI_VDEVICE(INTEL, 0x34a9), (kernel_ulong_t)&spt_uart_info }, ··· 200 200 { PCI_VDEVICE(INTEL, 0x34ea), (kernel_ulong_t)&bxt_i2c_info }, 201 201 { PCI_VDEVICE(INTEL, 0x34eb), (kernel_ulong_t)&bxt_i2c_info }, 202 202 { PCI_VDEVICE(INTEL, 0x34fb), (kernel_ulong_t)&spt_info }, 203 203 + /* EHL */ 204 204 + { PCI_VDEVICE(INTEL, 0x4b28), (kernel_ulong_t)&bxt_uart_info }, 205 205 + { PCI_VDEVICE(INTEL, 0x4b29), (kernel_ulong_t)&bxt_uart_info }, 206 206 + { PCI_VDEVICE(INTEL, 0x4b2a), (kernel_ulong_t)&bxt_info }, 207 207 + { PCI_VDEVICE(INTEL, 0x4b2b), (kernel_ulong_t)&bxt_info }, 208 208 + { PCI_VDEVICE(INTEL, 0x4b37), (kernel_ulong_t)&bxt_info }, 209 209 + { PCI_VDEVICE(INTEL, 0x4b44), (kernel_ulong_t)&bxt_i2c_info }, 210 210 + { PCI_VDEVICE(INTEL, 0x4b45), (kernel_ulong_t)&bxt_i2c_info }, 211 211 + { PCI_VDEVICE(INTEL, 0x4b4b), (kernel_ulong_t)&bxt_i2c_info }, 212 212 + { PCI_VDEVICE(INTEL, 0x4b4c), (kernel_ulong_t)&bxt_i2c_info }, 213 213 + { PCI_VDEVICE(INTEL, 0x4b4d), (kernel_ulong_t)&bxt_uart_info }, 214 214 + { PCI_VDEVICE(INTEL, 0x4b78), (kernel_ulong_t)&bxt_i2c_info }, 215 215 + { PCI_VDEVICE(INTEL, 0x4b79), (kernel_ulong_t)&bxt_i2c_info }, 216 216 + { PCI_VDEVICE(INTEL, 0x4b7a), (kernel_ulong_t)&bxt_i2c_info }, 217 217 + { PCI_VDEVICE(INTEL, 0x4b7b), (kernel_ulong_t)&bxt_i2c_info }, 203 218 /* APL */ 204 219 { PCI_VDEVICE(INTEL, 0x5aac), (kernel_ulong_t)&apl_i2c_info }, 205 220 { PCI_VDEVICE(INTEL, 0x5aae), (kernel_ulong_t)&apl_i2c_info }, ··· 248 233 { PCI_VDEVICE(INTEL, 0x9da9), (kernel_ulong_t)&spt_uart_info }, 249 234 { PCI_VDEVICE(INTEL, 0x9daa), (kernel_ulong_t)&spt_info }, 250 235 { PCI_VDEVICE(INTEL, 0x9dab), (kernel_ulong_t)&spt_info }, 251 251 - { PCI_VDEVICE(INTEL, 0x9dfb), (kernel_ulong_t)&spt_info }, 252 236 { PCI_VDEVICE(INTEL, 0x9dc5), (kernel_ulong_t)&cnl_i2c_info }, 253 237 { PCI_VDEVICE(INTEL, 0x9dc6), (kernel_ulong_t)&cnl_i2c_info }, 254 238 { PCI_VDEVICE(INTEL, 0x9dc7), (kernel_ulong_t)&spt_uart_info }, ··· 255 241 { PCI_VDEVICE(INTEL, 0x9de9), (kernel_ulong_t)&cnl_i2c_info }, 256 242 { PCI_VDEVICE(INTEL, 0x9dea), (kernel_ulong_t)&cnl_i2c_info }, 257 243 { PCI_VDEVICE(INTEL, 0x9deb), (kernel_ulong_t)&cnl_i2c_info }, 244 244 + { PCI_VDEVICE(INTEL, 0x9dfb), (kernel_ulong_t)&spt_info }, 258 245 /* SPT-H */ 259 246 { PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info }, 260 247 { PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info }, ··· 280 265 { PCI_VDEVICE(INTEL, 0xa329), (kernel_ulong_t)&spt_uart_info }, 281 266 { PCI_VDEVICE(INTEL, 0xa32a), (kernel_ulong_t)&spt_info }, 282 267 { PCI_VDEVICE(INTEL, 0xa32b), (kernel_ulong_t)&spt_info }, 283 283 - { PCI_VDEVICE(INTEL, 0xa37b), (kernel_ulong_t)&spt_info }, 284 268 { PCI_VDEVICE(INTEL, 0xa347), (kernel_ulong_t)&spt_uart_info }, 285 269 { PCI_VDEVICE(INTEL, 0xa368), (kernel_ulong_t)&cnl_i2c_info }, 286 270 { PCI_VDEVICE(INTEL, 0xa369), (kernel_ulong_t)&cnl_i2c_info }, 287 271 { PCI_VDEVICE(INTEL, 0xa36a), (kernel_ulong_t)&cnl_i2c_info }, 288 272 { PCI_VDEVICE(INTEL, 0xa36b), (kernel_ulong_t)&cnl_i2c_info }, 273 273 + { PCI_VDEVICE(INTEL, 0xa37b), (kernel_ulong_t)&spt_info }, 289 274 { } 290 275 }; 291 276 MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids);

+1

drivers/mfd/intel-lpss.c

reviewed

··· 543 543 544 544 static void __exit intel_lpss_exit(void) 545 545 { 546 546 + ida_destroy(&intel_lpss_devid_ida); 546 547 debugfs_remove(intel_lpss_debugfs); 547 548 } 548 549 module_exit(intel_lpss_exit);

+4

drivers/mfd/lp87565.c

reviewed

··· 30 30 .compatible = "ti,lp87565-q1", 31 31 .data = (void *)LP87565_DEVICE_TYPE_LP87565_Q1, 32 32 }, 33 33 + { 34 34 + .compatible = "ti,lp87561-q1", 35 35 + .data = (void *)LP87565_DEVICE_TYPE_LP87561_Q1, 36 36 + }, 33 37 {} 34 38 }; 35 39 MODULE_DEVICE_TABLE(of, of_lp87565_match_table);

+120 -9

drivers/mfd/madera-core.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 3 * Core MFD support for Cirrus Logic Madera codecs 4 4 * 5 5 * Copyright (C) 2015-2018 Cirrus Logic 6 6 - * 7 7 - * This program is free software; you can redistribute it and/or modify 8 8 - * it under the terms of the GNU General Public License as published by the 9 9 - * Free Software Foundation; version 2. 10 6 */ 11 7 12 8 #include <linux/device.h> ··· 27 31 28 32 #include "madera.h" 29 33 34 34 + #define CS47L15_SILICON_ID 0x6370 30 35 #define CS47L35_SILICON_ID 0x6360 31 36 #define CS47L85_SILICON_ID 0x6338 32 37 #define CS47L90_SILICON_ID 0x6364 38 38 + #define CS47L92_SILICON_ID 0x6371 33 39 34 40 #define MADERA_32KZ_MCLK2 1 35 41 ··· 42 44 43 45 static const struct mfd_cell madera_ldo1_devs[] = { 44 46 { .name = "madera-ldo1" }, 47 47 + }; 48 48 + 49 49 + static const char * const cs47l15_supplies[] = { 50 50 + "MICVDD", 51 51 + "CPVDD1", 52 52 + "SPKVDD", 53 53 + }; 54 54 + 55 55 + static const struct mfd_cell cs47l15_devs[] = { 56 56 + { .name = "madera-pinctrl", }, 57 57 + { .name = "madera-irq" }, 58 58 + { .name = "madera-gpio" }, 59 59 + { 60 60 + .name = "madera-extcon", 61 61 + .parent_supplies = cs47l15_supplies, 62 62 + .num_parent_supplies = 1, /* We only need MICVDD */ 63 63 + }, 64 64 + { 65 65 + .name = "cs47l15-codec", 66 66 + .parent_supplies = cs47l15_supplies, 67 67 + .num_parent_supplies = ARRAY_SIZE(cs47l15_supplies), 68 68 + }, 45 69 }; 46 70 47 71 static const char * const cs47l35_supplies[] = { ··· 79 59 { .name = "madera-irq", }, 80 60 { .name = "madera-micsupp", }, 81 61 { .name = "madera-gpio", }, 82 82 - { .name = "madera-extcon", }, 62 62 + { 63 63 + .name = "madera-extcon", 64 64 + .parent_supplies = cs47l35_supplies, 65 65 + .num_parent_supplies = 1, /* We only need MICVDD */ 66 66 + }, 83 67 { 84 68 .name = "cs47l35-codec", 85 69 .parent_supplies = cs47l35_supplies, ··· 107 83 { .name = "madera-irq", }, 108 84 { .name = "madera-micsupp" }, 109 85 { .name = "madera-gpio", }, 110 110 - { .name = "madera-extcon", }, 86 86 + { 87 87 + .name = "madera-extcon", 88 88 + .parent_supplies = cs47l85_supplies, 89 89 + .num_parent_supplies = 1, /* We only need MICVDD */ 90 90 + }, 111 91 { 112 92 .name = "cs47l85-codec", 113 93 .parent_supplies = cs47l85_supplies, ··· 133 105 { .name = "madera-irq", }, 134 106 { .name = "madera-micsupp", }, 135 107 { .name = "madera-gpio", }, 136 136 - { .name = "madera-extcon", }, 108 108 + { 109 109 + .name = "madera-extcon", 110 110 + .parent_supplies = cs47l90_supplies, 111 111 + .num_parent_supplies = 1, /* We only need MICVDD */ 112 112 + }, 137 113 { 138 114 .name = "cs47l90-codec", 139 115 .parent_supplies = cs47l90_supplies, ··· 145 113 }, 146 114 }; 147 115 116 116 + static const char * const cs47l92_supplies[] = { 117 117 + "MICVDD", 118 118 + "CPVDD1", 119 119 + "CPVDD2", 120 120 + }; 121 121 + 122 122 + static const struct mfd_cell cs47l92_devs[] = { 123 123 + { .name = "madera-pinctrl" }, 124 124 + { .name = "madera-irq", }, 125 125 + { .name = "madera-micsupp", }, 126 126 + { .name = "madera-gpio" }, 127 127 + { 128 128 + .name = "madera-extcon", 129 129 + .parent_supplies = cs47l92_supplies, 130 130 + .num_parent_supplies = 1, /* We only need MICVDD */ 131 131 + }, 132 132 + { 133 133 + .name = "cs47l92-codec", 134 134 + .parent_supplies = cs47l92_supplies, 135 135 + .num_parent_supplies = ARRAY_SIZE(cs47l92_supplies), 136 136 + }, 137 137 + }; 138 138 + 148 139 /* Used by madera-i2c and madera-spi drivers */ 149 140 const char *madera_name_from_type(enum madera_type type) 150 141 { 151 142 switch (type) { 143 143 + case CS47L15: 144 144 + return "CS47L15"; 152 145 case CS47L35: 153 146 return "CS47L35"; 154 147 case CS47L85: ··· 182 125 return "CS47L90"; 183 126 case CS47L91: 184 127 return "CS47L91"; 128 128 + case CS42L92: 129 129 + return "CS42L92"; 130 130 + case CS47L92: 131 131 + return "CS47L92"; 132 132 + case CS47L93: 133 133 + return "CS47L93"; 185 134 case WM1840: 186 135 return "WM1840"; 187 136 default: ··· 202 139 static int madera_wait_for_boot(struct madera *madera) 203 140 { 204 141 ktime_t timeout; 205 205 - unsigned int val; 142 142 + unsigned int val = 0; 206 143 int ret = 0; 207 144 208 145 /* ··· 342 279 EXPORT_SYMBOL_GPL(madera_pm_ops); 343 280 344 281 const struct of_device_id madera_of_match[] = { 282 282 + { .compatible = "cirrus,cs47l15", .data = (void *)CS47L15 }, 345 283 { .compatible = "cirrus,cs47l35", .data = (void *)CS47L35 }, 346 284 { .compatible = "cirrus,cs47l85", .data = (void *)CS47L85 }, 347 285 { .compatible = "cirrus,cs47l90", .data = (void *)CS47L90 }, 348 286 { .compatible = "cirrus,cs47l91", .data = (void *)CS47L91 }, 287 287 + { .compatible = "cirrus,cs42l92", .data = (void *)CS42L92 }, 288 288 + { .compatible = "cirrus,cs47l92", .data = (void *)CS47L92 }, 289 289 + { .compatible = "cirrus,cs47l93", .data = (void *)CS47L93 }, 349 290 { .compatible = "cirrus,wm1840", .data = (void *)WM1840 }, 350 291 {} 351 292 }; 293 293 + MODULE_DEVICE_TABLE(of, madera_of_match); 352 294 EXPORT_SYMBOL_GPL(madera_of_match); 353 295 354 296 static int madera_get_reset_gpio(struct madera *madera) ··· 394 326 * childbiases for each micbias. Unspecified values default to 0. 395 327 */ 396 328 switch (madera->type) { 329 329 + case CS47L15: 330 330 + madera->num_micbias = 1; 331 331 + madera->num_childbias[0] = 3; 332 332 + return; 397 333 case CS47L35: 398 334 madera->num_micbias = 2; 399 335 madera->num_childbias[0] = 2; ··· 413 341 madera->num_micbias = 2; 414 342 madera->num_childbias[0] = 4; 415 343 madera->num_childbias[1] = 4; 344 344 + return; 345 345 + case CS42L92: 346 346 + case CS47L92: 347 347 + case CS47L93: 348 348 + madera->num_micbias = 2; 349 349 + madera->num_childbias[0] = 4; 350 350 + madera->num_childbias[1] = 2; 416 351 return; 417 352 default: 418 353 return; ··· 468 389 * No devm_ because we need to control shutdown order of children. 469 390 */ 470 391 switch (madera->type) { 392 392 + case CS47L15: 471 393 case CS47L35: 472 394 case CS47L90: 473 395 case CS47L91: 396 396 + case CS42L92: 397 397 + case CS47L92: 398 398 + case CS47L93: 474 399 break; 475 400 case CS47L85: 476 401 case WM1840: ··· 541 458 } 542 459 543 460 switch (hwid) { 461 461 + case CS47L15_SILICON_ID: 462 462 + if (IS_ENABLED(CONFIG_MFD_CS47L15)) { 463 463 + switch (madera->type) { 464 464 + case CS47L15: 465 465 + patch_fn = &cs47l15_patch; 466 466 + mfd_devs = cs47l15_devs; 467 467 + n_devs = ARRAY_SIZE(cs47l15_devs); 468 468 + break; 469 469 + default: 470 470 + break; 471 471 + } 472 472 + } 473 473 + break; 544 474 case CS47L35_SILICON_ID: 545 475 if (IS_ENABLED(CONFIG_MFD_CS47L35)) { 546 476 switch (madera->type) { ··· 589 493 patch_fn = cs47l90_patch; 590 494 mfd_devs = cs47l90_devs; 591 495 n_devs = ARRAY_SIZE(cs47l90_devs); 496 496 + break; 497 497 + default: 498 498 + break; 499 499 + } 500 500 + } 501 501 + break; 502 502 + case CS47L92_SILICON_ID: 503 503 + if (IS_ENABLED(CONFIG_MFD_CS47L92)) { 504 504 + switch (madera->type) { 505 505 + case CS42L92: 506 506 + case CS47L92: 507 507 + case CS47L93: 508 508 + patch_fn = cs47l92_patch; 509 509 + mfd_devs = cs47l92_devs; 510 510 + n_devs = ARRAY_SIZE(cs47l92_devs); 592 511 break; 593 512 default: 594 513 break;

+19 -5

drivers/mfd/madera-i2c.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 3 * I2C bus interface to Cirrus Logic Madera codecs 4 4 * 5 5 * Copyright (C) 2015-2018 Cirrus Logic 6 6 - * 7 7 - * This program is free software; you can redistribute it and/or modify 8 8 - * it under the terms of the GNU General Public License as published by the 9 9 - * Free Software Foundation; version 2. 10 6 */ 11 7 12 8 #include <linux/device.h> ··· 35 39 type = id->driver_data; 36 40 37 41 switch (type) { 42 42 + case CS47L15: 43 43 + if (IS_ENABLED(CONFIG_MFD_CS47L15)) { 44 44 + regmap_16bit_config = &cs47l15_16bit_i2c_regmap; 45 45 + regmap_32bit_config = &cs47l15_32bit_i2c_regmap; 46 46 + } 47 47 + break; 38 48 case CS47L35: 39 49 if (IS_ENABLED(CONFIG_MFD_CS47L35)) { 40 50 regmap_16bit_config = &cs47l35_16bit_i2c_regmap; ··· 59 57 if (IS_ENABLED(CONFIG_MFD_CS47L90)) { 60 58 regmap_16bit_config = &cs47l90_16bit_i2c_regmap; 61 59 regmap_32bit_config = &cs47l90_32bit_i2c_regmap; 60 60 + } 61 61 + break; 62 62 + case CS42L92: 63 63 + case CS47L92: 64 64 + case CS47L93: 65 65 + if (IS_ENABLED(CONFIG_MFD_CS47L92)) { 66 66 + regmap_16bit_config = &cs47l92_16bit_i2c_regmap; 67 67 + regmap_32bit_config = &cs47l92_32bit_i2c_regmap; 62 68 } 63 69 break; 64 70 default: ··· 123 113 } 124 114 125 115 static const struct i2c_device_id madera_i2c_id[] = { 116 116 + { "cs47l15", CS47L15 }, 126 117 { "cs47l35", CS47L35 }, 127 118 { "cs47l85", CS47L85 }, 128 119 { "cs47l90", CS47L90 }, 129 120 { "cs47l91", CS47L91 }, 121 121 + { "cs42l92", CS42L92 }, 122 122 + { "cs47l92", CS47L92 }, 123 123 + { "cs47l93", CS47L93 }, 130 124 { "wm1840", WM1840 }, 131 125 { } 132 126 };

+19 -5

drivers/mfd/madera-spi.c

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 3 * SPI bus interface to Cirrus Logic Madera codecs 4 4 * 5 5 * Copyright (C) 2015-2018 Cirrus Logic 6 6 - * 7 7 - * This program is free software; you can redistribute it and/or modify 8 8 - * it under the terms of the GNU General Public License as published by the 9 9 - * Free Software Foundation; version 2. 10 6 */ 11 7 12 8 #include <linux/device.h> ··· 35 39 type = id->driver_data; 36 40 37 41 switch (type) { 42 42 + case CS47L15: 43 43 + if (IS_ENABLED(CONFIG_MFD_CS47L15)) { 44 44 + regmap_16bit_config = &cs47l15_16bit_spi_regmap; 45 45 + regmap_32bit_config = &cs47l15_32bit_spi_regmap; 46 46 + } 47 47 + break; 38 48 case CS47L35: 39 49 if (IS_ENABLED(CONFIG_MFD_CS47L35)) { 40 50 regmap_16bit_config = &cs47l35_16bit_spi_regmap; ··· 59 57 if (IS_ENABLED(CONFIG_MFD_CS47L90)) { 60 58 regmap_16bit_config = &cs47l90_16bit_spi_regmap; 61 59 regmap_32bit_config = &cs47l90_32bit_spi_regmap; 60 60 + } 61 61 + break; 62 62 + case CS42L92: 63 63 + case CS47L92: 64 64 + case CS47L93: 65 65 + if (IS_ENABLED(CONFIG_MFD_CS47L92)) { 66 66 + regmap_16bit_config = &cs47l92_16bit_spi_regmap; 67 67 + regmap_32bit_config = &cs47l92_32bit_spi_regmap; 62 68 } 63 69 break; 64 70 default: ··· 122 112 } 123 113 124 114 static const struct spi_device_id madera_spi_ids[] = { 115 115 + { "cs47l15", CS47L15 }, 125 116 { "cs47l35", CS47L35 }, 126 117 { "cs47l85", CS47L85 }, 127 118 { "cs47l90", CS47L90 }, 128 119 { "cs47l91", CS47L91 }, 120 120 + { "cs42l92", CS42L92 }, 121 121 + { "cs47l92", CS47L92 }, 122 122 + { "cs47l93", CS47L93 }, 129 123 { "wm1840", WM1840 }, 130 124 { } 131 125 };

+13

drivers/mfd/madera.h

reviewed

··· 21 21 22 22 const char *madera_name_from_type(enum madera_type type); 23 23 24 24 + extern const struct regmap_config cs47l15_16bit_spi_regmap; 25 25 + extern const struct regmap_config cs47l15_32bit_spi_regmap; 26 26 + extern const struct regmap_config cs47l15_16bit_i2c_regmap; 27 27 + extern const struct regmap_config cs47l15_32bit_i2c_regmap; 28 28 + int cs47l15_patch(struct madera *madera); 29 29 + 24 30 extern const struct regmap_config cs47l35_16bit_spi_regmap; 25 31 extern const struct regmap_config cs47l35_32bit_spi_regmap; 26 32 extern const struct regmap_config cs47l35_16bit_i2c_regmap; ··· 44 38 extern const struct regmap_config cs47l90_16bit_i2c_regmap; 45 39 extern const struct regmap_config cs47l90_32bit_i2c_regmap; 46 40 int cs47l90_patch(struct madera *madera); 41 41 + 42 42 + extern const struct regmap_config cs47l92_16bit_spi_regmap; 43 43 + extern const struct regmap_config cs47l92_32bit_spi_regmap; 44 44 + extern const struct regmap_config cs47l92_16bit_i2c_regmap; 45 45 + extern const struct regmap_config cs47l92_32bit_i2c_regmap; 46 46 + int cs47l92_patch(struct madera *madera); 47 47 + 47 48 #endif

-2

drivers/mfd/menelaus.c

reviewed

··· 1125 1125 menelaus_remove_irq_work(MENELAUS_RTCALM_IRQ); 1126 1126 device_init_wakeup(&m->client->dev, 0); 1127 1127 } 1128 1128 - dev_err(&m->client->dev, "can't register RTC: %d\n", 1129 1129 - (int) PTR_ERR(m->rtc)); 1130 1128 the_menelaus->rtc = NULL; 1131 1129 } 1132 1130 }

+1

drivers/mfd/mfd-core.c

reviewed

··· 175 175 for_each_child_of_node(parent->of_node, np) { 176 176 if (of_device_is_compatible(np, cell->of_compatible)) { 177 177 pdev->dev.of_node = np; 178 178 + pdev->dev.fwnode = &np->fwnode; 178 179 break; 179 180 } 180 181 }

+234 -23

drivers/mfd/rk808.c

reviewed

··· 19 19 #include <linux/module.h> 20 20 #include <linux/of_device.h> 21 21 #include <linux/regmap.h> 22 22 + #include <linux/syscore_ops.h> 22 23 23 24 struct rk808_reg_data { 24 25 int addr; ··· 55 54 return false; 56 55 } 57 56 57 57 + static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg) 58 58 + { 59 59 + /* 60 60 + * Notes: 61 61 + * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but 62 62 + * we don't use that feature. It's better to cache. 63 63 + */ 64 64 + 65 65 + switch (reg) { 66 66 + case RK817_SECONDS_REG ... RK817_WEEKS_REG: 67 67 + case RK817_RTC_STATUS_REG: 68 68 + case RK817_INT_STS_REG0: 69 69 + case RK817_INT_STS_REG1: 70 70 + case RK817_INT_STS_REG2: 71 71 + case RK817_SYS_STS: 72 72 + return true; 73 73 + } 74 74 + 75 75 + return true; 76 76 + } 77 77 + 58 78 static const struct regmap_config rk818_regmap_config = { 59 79 .reg_bits = 8, 60 80 .val_bits = 8, ··· 100 78 .volatile_reg = rk808_is_volatile_reg, 101 79 }; 102 80 81 81 + static const struct regmap_config rk817_regmap_config = { 82 82 + .reg_bits = 8, 83 83 + .val_bits = 8, 84 84 + .max_register = RK817_GPIO_INT_CFG, 85 85 + .cache_type = REGCACHE_NONE, 86 86 + .volatile_reg = rk817_is_volatile_reg, 87 87 + }; 88 88 + 103 89 static struct resource rtc_resources[] = { 104 90 { 105 91 .start = RK808_IRQ_RTC_ALARM, 106 92 .end = RK808_IRQ_RTC_ALARM, 107 93 .flags = IORESOURCE_IRQ, 108 94 } 95 95 + }; 96 96 + 97 97 + static struct resource rk817_rtc_resources[] = { 98 98 + DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM), 109 99 }; 110 100 111 101 static struct resource rk805_key_resources[] = { ··· 131 97 .end = RK805_IRQ_PWRON_RISE, 132 98 .flags = IORESOURCE_IRQ, 133 99 } 100 100 + }; 101 101 + 102 102 + static struct resource rk817_pwrkey_resources[] = { 103 103 + DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE), 104 104 + DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL), 134 105 }; 135 106 136 107 static const struct mfd_cell rk805s[] = { ··· 160 121 .name = "rk808-rtc", 161 122 .num_resources = ARRAY_SIZE(rtc_resources), 162 123 .resources = rtc_resources, 124 124 + }, 125 125 + }; 126 126 + 127 127 + static const struct mfd_cell rk817s[] = { 128 128 + { .name = "rk808-clkout",}, 129 129 + { .name = "rk808-regulator",}, 130 130 + { 131 131 + .name = "rk8xx-pwrkey", 132 132 + .num_resources = ARRAY_SIZE(rk817_pwrkey_resources), 133 133 + .resources = &rk817_pwrkey_resources[0], 134 134 + }, 135 135 + { 136 136 + .name = "rk808-rtc", 137 137 + .num_resources = ARRAY_SIZE(rk817_rtc_resources), 138 138 + .resources = &rk817_rtc_resources[0], 163 139 }, 164 140 }; 165 141 ··· 211 157 { RK808_DCDC_UV_ACT_REG, BUCK_UV_ACT_MASK, BUCK_UV_ACT_DISABLE}, 212 158 { RK808_VB_MON_REG, MASK_ALL, VB_LO_ACT | 213 159 VB_LO_SEL_3500MV }, 160 160 + }; 161 161 + 162 162 + static const struct rk808_reg_data rk817_pre_init_reg[] = { 163 163 + {RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP}, 164 164 + {RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_H}, 165 165 + {RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK, 166 166 + RK817_HOTDIE_105 | RK817_TSD_140}, 214 167 }; 215 168 216 169 static const struct rk808_reg_data rk818_pre_init_reg[] = { ··· 385 324 }, 386 325 }; 387 326 327 327 + static const struct regmap_irq rk817_irqs[RK817_IRQ_END] = { 328 328 + REGMAP_IRQ_REG_LINE(0, 8), 329 329 + REGMAP_IRQ_REG_LINE(1, 8), 330 330 + REGMAP_IRQ_REG_LINE(2, 8), 331 331 + REGMAP_IRQ_REG_LINE(3, 8), 332 332 + REGMAP_IRQ_REG_LINE(4, 8), 333 333 + REGMAP_IRQ_REG_LINE(5, 8), 334 334 + REGMAP_IRQ_REG_LINE(6, 8), 335 335 + REGMAP_IRQ_REG_LINE(7, 8), 336 336 + REGMAP_IRQ_REG_LINE(8, 8), 337 337 + REGMAP_IRQ_REG_LINE(9, 8), 338 338 + REGMAP_IRQ_REG_LINE(10, 8), 339 339 + REGMAP_IRQ_REG_LINE(11, 8), 340 340 + REGMAP_IRQ_REG_LINE(12, 8), 341 341 + REGMAP_IRQ_REG_LINE(13, 8), 342 342 + REGMAP_IRQ_REG_LINE(14, 8), 343 343 + REGMAP_IRQ_REG_LINE(15, 8), 344 344 + REGMAP_IRQ_REG_LINE(16, 8), 345 345 + REGMAP_IRQ_REG_LINE(17, 8), 346 346 + REGMAP_IRQ_REG_LINE(18, 8), 347 347 + REGMAP_IRQ_REG_LINE(19, 8), 348 348 + REGMAP_IRQ_REG_LINE(20, 8), 349 349 + REGMAP_IRQ_REG_LINE(21, 8), 350 350 + REGMAP_IRQ_REG_LINE(22, 8), 351 351 + REGMAP_IRQ_REG_LINE(23, 8) 352 352 + }; 353 353 + 388 354 static struct regmap_irq_chip rk805_irq_chip = { 389 355 .name = "rk805", 390 356 .irqs = rk805_irqs, ··· 435 347 .init_ack_masked = true, 436 348 }; 437 349 350 350 + static struct regmap_irq_chip rk817_irq_chip = { 351 351 + .name = "rk817", 352 352 + .irqs = rk817_irqs, 353 353 + .num_irqs = ARRAY_SIZE(rk817_irqs), 354 354 + .num_regs = 3, 355 355 + .irq_reg_stride = 2, 356 356 + .status_base = RK817_INT_STS_REG0, 357 357 + .mask_base = RK817_INT_STS_MSK_REG0, 358 358 + .ack_base = RK817_INT_STS_REG0, 359 359 + .init_ack_masked = true, 360 360 + }; 361 361 + 438 362 static const struct regmap_irq_chip rk818_irq_chip = { 439 363 .name = "rk818", 440 364 .irqs = rk818_irqs, ··· 466 366 int ret; 467 367 struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); 468 368 469 469 - if (!rk808) { 470 470 - dev_warn(&rk808_i2c_client->dev, 471 471 - "have no rk805, so do nothing here\n"); 369 369 + if (!rk808) 472 370 return; 473 473 - } 474 371 475 372 ret = regmap_update_bits(rk808->regmap, 476 373 RK805_DEV_CTRL_REG, 477 374 DEV_OFF, DEV_OFF); 478 375 if (ret) 479 479 - dev_err(&rk808_i2c_client->dev, "power off error!\n"); 376 376 + dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n"); 377 377 + } 378 378 + 379 379 + static void rk805_device_shutdown_prepare(void) 380 380 + { 381 381 + int ret; 382 382 + struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); 383 383 + 384 384 + if (!rk808) 385 385 + return; 386 386 + 387 387 + ret = regmap_update_bits(rk808->regmap, 388 388 + RK805_GPIO_IO_POL_REG, 389 389 + SLP_SD_MSK, SHUTDOWN_FUN); 390 390 + if (ret) 391 391 + dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n"); 480 392 } 481 393 482 394 static void rk808_device_shutdown(void) ··· 496 384 int ret; 497 385 struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); 498 386 499 499 - if (!rk808) { 500 500 - dev_warn(&rk808_i2c_client->dev, 501 501 - "have no rk808, so do nothing here\n"); 387 387 + if (!rk808) 502 388 return; 503 503 - } 504 389 505 390 ret = regmap_update_bits(rk808->regmap, 506 391 RK808_DEVCTRL_REG, 507 392 DEV_OFF_RST, DEV_OFF_RST); 508 393 if (ret) 509 509 - dev_err(&rk808_i2c_client->dev, "power off error!\n"); 394 394 + dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n"); 510 395 } 511 396 512 397 static void rk818_device_shutdown(void) ··· 511 402 int ret; 512 403 struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); 513 404 514 514 - if (!rk808) { 515 515 - dev_warn(&rk808_i2c_client->dev, 516 516 - "have no rk818, so do nothing here\n"); 405 405 + if (!rk808) 517 406 return; 518 518 - } 519 407 520 408 ret = regmap_update_bits(rk808->regmap, 521 409 RK818_DEVCTRL_REG, 522 410 DEV_OFF, DEV_OFF); 523 411 if (ret) 524 524 - dev_err(&rk808_i2c_client->dev, "power off error!\n"); 412 412 + dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n"); 525 413 } 414 414 + 415 415 + static void rk8xx_syscore_shutdown(void) 416 416 + { 417 417 + struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); 418 418 + int ret; 419 419 + 420 420 + if (system_state == SYSTEM_POWER_OFF && 421 421 + (rk808->variant == RK809_ID || rk808->variant == RK817_ID)) { 422 422 + ret = regmap_update_bits(rk808->regmap, 423 423 + RK817_SYS_CFG(3), 424 424 + RK817_SLPPIN_FUNC_MSK, 425 425 + SLPPIN_DN_FUN); 426 426 + if (ret) { 427 427 + dev_warn(&rk808_i2c_client->dev, 428 428 + "Cannot switch to power down function\n"); 429 429 + } 430 430 + } 431 431 + } 432 432 + 433 433 + static struct syscore_ops rk808_syscore_ops = { 434 434 + .shutdown = rk8xx_syscore_shutdown, 435 435 + }; 526 436 527 437 static const struct of_device_id rk808_of_match[] = { 528 438 { .compatible = "rockchip,rk805" }, 529 439 { .compatible = "rockchip,rk808" }, 440 440 + { .compatible = "rockchip,rk809" }, 441 441 + { .compatible = "rockchip,rk817" }, 530 442 { .compatible = "rockchip,rk818" }, 531 443 { }, 532 444 }; ··· 560 430 struct rk808 *rk808; 561 431 const struct rk808_reg_data *pre_init_reg; 562 432 const struct mfd_cell *cells; 563 563 - void (*pm_pwroff_fn)(void); 564 433 int nr_pre_init_regs; 565 434 int nr_cells; 566 435 int pm_off = 0, msb, lsb; 436 436 + unsigned char pmic_id_msb, pmic_id_lsb; 567 437 int ret; 568 438 int i; 569 439 ··· 571 441 if (!rk808) 572 442 return -ENOMEM; 573 443 444 444 + if (of_device_is_compatible(np, "rockchip,rk817") || 445 445 + of_device_is_compatible(np, "rockchip,rk809")) { 446 446 + pmic_id_msb = RK817_ID_MSB; 447 447 + pmic_id_lsb = RK817_ID_LSB; 448 448 + } else { 449 449 + pmic_id_msb = RK808_ID_MSB; 450 450 + pmic_id_lsb = RK808_ID_LSB; 451 451 + } 452 452 + 574 453 /* Read chip variant */ 575 575 - msb = i2c_smbus_read_byte_data(client, RK808_ID_MSB); 454 454 + msb = i2c_smbus_read_byte_data(client, pmic_id_msb); 576 455 if (msb < 0) { 577 456 dev_err(&client->dev, "failed to read the chip id at 0x%x\n", 578 457 RK808_ID_MSB); 579 458 return msb; 580 459 } 581 460 582 582 - lsb = i2c_smbus_read_byte_data(client, RK808_ID_LSB); 461 461 + lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb); 583 462 if (lsb < 0) { 584 463 dev_err(&client->dev, "failed to read the chip id at 0x%x\n", 585 464 RK808_ID_LSB); ··· 606 467 nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg); 607 468 cells = rk805s; 608 469 nr_cells = ARRAY_SIZE(rk805s); 609 609 - pm_pwroff_fn = rk805_device_shutdown; 470 470 + rk808->pm_pwroff_fn = rk805_device_shutdown; 471 471 + rk808->pm_pwroff_prep_fn = rk805_device_shutdown_prepare; 610 472 break; 611 473 case RK808_ID: 612 474 rk808->regmap_cfg = &rk808_regmap_config; ··· 616 476 nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg); 617 477 cells = rk808s; 618 478 nr_cells = ARRAY_SIZE(rk808s); 619 619 - pm_pwroff_fn = rk808_device_shutdown; 479 479 + rk808->pm_pwroff_fn = rk808_device_shutdown; 620 480 break; 621 481 case RK818_ID: 622 482 rk808->regmap_cfg = &rk818_regmap_config; ··· 625 485 nr_pre_init_regs = ARRAY_SIZE(rk818_pre_init_reg); 626 486 cells = rk818s; 627 487 nr_cells = ARRAY_SIZE(rk818s); 628 628 - pm_pwroff_fn = rk818_device_shutdown; 488 488 + rk808->pm_pwroff_fn = rk818_device_shutdown; 489 489 + break; 490 490 + case RK809_ID: 491 491 + case RK817_ID: 492 492 + rk808->regmap_cfg = &rk817_regmap_config; 493 493 + rk808->regmap_irq_chip = &rk817_irq_chip; 494 494 + pre_init_reg = rk817_pre_init_reg; 495 495 + nr_pre_init_regs = ARRAY_SIZE(rk817_pre_init_reg); 496 496 + cells = rk817s; 497 497 + nr_cells = ARRAY_SIZE(rk817s); 498 498 + register_syscore_ops(&rk808_syscore_ops); 629 499 break; 630 500 default: 631 501 dev_err(&client->dev, "Unsupported RK8XX ID %lu\n", ··· 690 540 "rockchip,system-power-controller"); 691 541 if (pm_off && !pm_power_off) { 692 542 rk808_i2c_client = client; 693 693 - pm_power_off = pm_pwroff_fn; 543 543 + pm_power_off = rk808->pm_pwroff_fn; 544 544 + } 545 545 + 546 546 + if (pm_off && !pm_power_off_prepare) { 547 547 + if (!rk808_i2c_client) 548 548 + rk808_i2c_client = client; 549 549 + pm_power_off_prepare = rk808->pm_pwroff_prep_fn; 694 550 } 695 551 696 552 return 0; ··· 711 555 struct rk808 *rk808 = i2c_get_clientdata(client); 712 556 713 557 regmap_del_irq_chip(client->irq, rk808->irq_data); 714 714 - pm_power_off = NULL; 558 558 + 559 559 + /** 560 560 + * pm_power_off may points to a function from another module. 561 561 + * Check if the pointer is set by us and only then overwrite it. 562 562 + */ 563 563 + if (rk808->pm_pwroff_fn && pm_power_off == rk808->pm_pwroff_fn) 564 564 + pm_power_off = NULL; 565 565 + 566 566 + /** 567 567 + * As above, check if the pointer is set by us before overwrite. 568 568 + */ 569 569 + if (rk808->pm_pwroff_prep_fn && 570 570 + pm_power_off_prepare == rk808->pm_pwroff_prep_fn) 571 571 + pm_power_off_prepare = NULL; 715 572 716 573 return 0; 717 574 } 575 575 + 576 576 + static int rk8xx_suspend(struct device *dev) 577 577 + { 578 578 + struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); 579 579 + int ret = 0; 580 580 + 581 581 + switch (rk808->variant) { 582 582 + case RK809_ID: 583 583 + case RK817_ID: 584 584 + ret = regmap_update_bits(rk808->regmap, 585 585 + RK817_SYS_CFG(3), 586 586 + RK817_SLPPIN_FUNC_MSK, 587 587 + SLPPIN_SLP_FUN); 588 588 + break; 589 589 + default: 590 590 + break; 591 591 + } 592 592 + 593 593 + return ret; 594 594 + } 595 595 + 596 596 + static int rk8xx_resume(struct device *dev) 597 597 + { 598 598 + struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); 599 599 + int ret = 0; 600 600 + 601 601 + switch (rk808->variant) { 602 602 + case RK809_ID: 603 603 + case RK817_ID: 604 604 + ret = regmap_update_bits(rk808->regmap, 605 605 + RK817_SYS_CFG(3), 606 606 + RK817_SLPPIN_FUNC_MSK, 607 607 + SLPPIN_NULL_FUN); 608 608 + break; 609 609 + default: 610 610 + break; 611 611 + } 612 612 + 613 613 + return ret; 614 614 + } 615 615 + SIMPLE_DEV_PM_OPS(rk8xx_pm_ops, rk8xx_suspend, rk8xx_resume); 718 616 719 617 static struct i2c_driver rk808_i2c_driver = { 720 618 .driver = { 721 619 .name = "rk808", 722 620 .of_match_table = rk808_of_match, 621 621 + .pm = &rk8xx_pm_ops, 723 622 }, 724 623 .probe = rk808_probe, 725 624 .remove = rk808_remove,

+316

drivers/mfd/rohm-bd70528.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 2 + // 3 3 + // Copyright (C) 2019 ROHM Semiconductors 4 4 + // 5 5 + // ROHM BD70528 PMIC driver 6 6 + 7 7 + #include <linux/i2c.h> 8 8 + #include <linux/interrupt.h> 9 9 + #include <linux/ioport.h> 10 10 + #include <linux/irq.h> 11 11 + #include <linux/mfd/core.h> 12 12 + #include <linux/mfd/rohm-bd70528.h> 13 13 + #include <linux/module.h> 14 14 + #include <linux/of_device.h> 15 15 + #include <linux/regmap.h> 16 16 + #include <linux/types.h> 17 17 + 18 18 + #define BD70528_NUM_OF_GPIOS 4 19 19 + 20 20 + static const struct resource rtc_irqs[] = { 21 21 + DEFINE_RES_IRQ_NAMED(BD70528_INT_RTC_ALARM, "bd70528-rtc-alm"), 22 22 + DEFINE_RES_IRQ_NAMED(BD70528_INT_ELPS_TIM, "bd70528-elapsed-timer"), 23 23 + }; 24 24 + 25 25 + static const struct resource charger_irqs[] = { 26 26 + DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_RES, "bd70528-bat-ov-res"), 27 27 + DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_DET, "bd70528-bat-ov-det"), 28 28 + DEFINE_RES_IRQ_NAMED(BD70528_INT_DBAT_DET, "bd70528-bat-dead"), 29 29 + DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_RES, "bd70528-bat-warmed"), 30 30 + DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_DET, "bd70528-bat-cold"), 31 31 + DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_RES, "bd70528-bat-cooled"), 32 32 + DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_DET, "bd70528-bat-hot"), 33 33 + DEFINE_RES_IRQ_NAMED(BD70528_INT_CHG_TSD, "bd70528-chg-tshd"), 34 34 + DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_RMV, "bd70528-bat-removed"), 35 35 + DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_DET, "bd70528-bat-detected"), 36 36 + DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_RES, "bd70528-dcin2-ov-res"), 37 37 + DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_DET, "bd70528-dcin2-ov-det"), 38 38 + DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_RMV, "bd70528-dcin2-removed"), 39 39 + DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_DET, "bd70528-dcin2-detected"), 40 40 + DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_RMV, "bd70528-dcin1-removed"), 41 41 + DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_DET, "bd70528-dcin1-detected"), 42 42 + }; 43 43 + 44 44 + static struct mfd_cell bd70528_mfd_cells[] = { 45 45 + { .name = "bd70528-pmic", }, 46 46 + { .name = "bd70528-gpio", }, 47 47 + /* 48 48 + * We use BD71837 driver to drive the clock block. Only differences to 49 49 + * BD70528 clock gate are the register address and mask. 50 50 + */ 51 51 + { .name = "bd718xx-clk", }, 52 52 + { .name = "bd70528-wdt", }, 53 53 + { 54 54 + .name = "bd70528-power", 55 55 + .resources = charger_irqs, 56 56 + .num_resources = ARRAY_SIZE(charger_irqs), 57 57 + }, { 58 58 + .name = "bd70528-rtc", 59 59 + .resources = rtc_irqs, 60 60 + .num_resources = ARRAY_SIZE(rtc_irqs), 61 61 + }, 62 62 + }; 63 63 + 64 64 + static const struct regmap_range volatile_ranges[] = { 65 65 + { 66 66 + .range_min = BD70528_REG_INT_MAIN, 67 67 + .range_max = BD70528_REG_INT_OP_FAIL, 68 68 + }, { 69 69 + .range_min = BD70528_REG_RTC_COUNT_H, 70 70 + .range_max = BD70528_REG_RTC_ALM_REPEAT, 71 71 + }, { 72 72 + /* 73 73 + * WDT control reg is special. Magic values must be written to 74 74 + * it in order to change the control. Should not be cached. 75 75 + */ 76 76 + .range_min = BD70528_REG_WDT_CTRL, 77 77 + .range_max = BD70528_REG_WDT_CTRL, 78 78 + }, { 79 79 + /* 80 80 + * BD70528 also contains a few other registers which require 81 81 + * magic sequences to be written in order to update the value. 82 82 + * At least SHIPMODE, HWRESET, WARMRESET,and STANDBY 83 83 + */ 84 84 + .range_min = BD70528_REG_SHIPMODE, 85 85 + .range_max = BD70528_REG_STANDBY, 86 86 + }, 87 87 + }; 88 88 + 89 89 + static const struct regmap_access_table volatile_regs = { 90 90 + .yes_ranges = &volatile_ranges[0], 91 91 + .n_yes_ranges = ARRAY_SIZE(volatile_ranges), 92 92 + }; 93 93 + 94 94 + static struct regmap_config bd70528_regmap = { 95 95 + .reg_bits = 8, 96 96 + .val_bits = 8, 97 97 + .volatile_table = &volatile_regs, 98 98 + .max_register = BD70528_MAX_REGISTER, 99 99 + .cache_type = REGCACHE_RBTREE, 100 100 + }; 101 101 + 102 102 + /* 103 103 + * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can 104 104 + * access corect sub-IRQ registers based on bits that are set in main IRQ 105 105 + * register. 106 106 + */ 107 107 + 108 108 + /* bit [0] - Shutdown register */ 109 109 + unsigned int bit0_offsets[] = {0}; /* Shutdown register */ 110 110 + unsigned int bit1_offsets[] = {1}; /* Power failure register */ 111 111 + unsigned int bit2_offsets[] = {2}; /* VR FAULT register */ 112 112 + unsigned int bit3_offsets[] = {3}; /* PMU register interrupts */ 113 113 + unsigned int bit4_offsets[] = {4, 5}; /* Charger 1 and Charger 2 registers */ 114 114 + unsigned int bit5_offsets[] = {6}; /* RTC register */ 115 115 + unsigned int bit6_offsets[] = {7}; /* GPIO register */ 116 116 + unsigned int bit7_offsets[] = {8}; /* Invalid operation register */ 117 117 + 118 118 + static struct regmap_irq_sub_irq_map bd70528_sub_irq_offsets[] = { 119 119 + REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 120 120 + REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 121 121 + REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), 122 122 + REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), 123 123 + REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), 124 124 + REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), 125 125 + REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), 126 126 + REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 127 127 + }; 128 128 + 129 129 + static struct regmap_irq bd70528_irqs[] = { 130 130 + REGMAP_IRQ_REG(BD70528_INT_LONGPUSH, 0, BD70528_INT_LONGPUSH_MASK), 131 131 + REGMAP_IRQ_REG(BD70528_INT_WDT, 0, BD70528_INT_WDT_MASK), 132 132 + REGMAP_IRQ_REG(BD70528_INT_HWRESET, 0, BD70528_INT_HWRESET_MASK), 133 133 + REGMAP_IRQ_REG(BD70528_INT_RSTB_FAULT, 0, BD70528_INT_RSTB_FAULT_MASK), 134 134 + REGMAP_IRQ_REG(BD70528_INT_VBAT_UVLO, 0, BD70528_INT_VBAT_UVLO_MASK), 135 135 + REGMAP_IRQ_REG(BD70528_INT_TSD, 0, BD70528_INT_TSD_MASK), 136 136 + REGMAP_IRQ_REG(BD70528_INT_RSTIN, 0, BD70528_INT_RSTIN_MASK), 137 137 + REGMAP_IRQ_REG(BD70528_INT_BUCK1_FAULT, 1, 138 138 + BD70528_INT_BUCK1_FAULT_MASK), 139 139 + REGMAP_IRQ_REG(BD70528_INT_BUCK2_FAULT, 1, 140 140 + BD70528_INT_BUCK2_FAULT_MASK), 141 141 + REGMAP_IRQ_REG(BD70528_INT_BUCK3_FAULT, 1, 142 142 + BD70528_INT_BUCK3_FAULT_MASK), 143 143 + REGMAP_IRQ_REG(BD70528_INT_LDO1_FAULT, 1, BD70528_INT_LDO1_FAULT_MASK), 144 144 + REGMAP_IRQ_REG(BD70528_INT_LDO2_FAULT, 1, BD70528_INT_LDO2_FAULT_MASK), 145 145 + REGMAP_IRQ_REG(BD70528_INT_LDO3_FAULT, 1, BD70528_INT_LDO3_FAULT_MASK), 146 146 + REGMAP_IRQ_REG(BD70528_INT_LED1_FAULT, 1, BD70528_INT_LED1_FAULT_MASK), 147 147 + REGMAP_IRQ_REG(BD70528_INT_LED2_FAULT, 1, BD70528_INT_LED2_FAULT_MASK), 148 148 + REGMAP_IRQ_REG(BD70528_INT_BUCK1_OCP, 2, BD70528_INT_BUCK1_OCP_MASK), 149 149 + REGMAP_IRQ_REG(BD70528_INT_BUCK2_OCP, 2, BD70528_INT_BUCK2_OCP_MASK), 150 150 + REGMAP_IRQ_REG(BD70528_INT_BUCK3_OCP, 2, BD70528_INT_BUCK3_OCP_MASK), 151 151 + REGMAP_IRQ_REG(BD70528_INT_LED1_OCP, 2, BD70528_INT_LED1_OCP_MASK), 152 152 + REGMAP_IRQ_REG(BD70528_INT_LED2_OCP, 2, BD70528_INT_LED2_OCP_MASK), 153 153 + REGMAP_IRQ_REG(BD70528_INT_BUCK1_FULLON, 2, 154 154 + BD70528_INT_BUCK1_FULLON_MASK), 155 155 + REGMAP_IRQ_REG(BD70528_INT_BUCK2_FULLON, 2, 156 156 + BD70528_INT_BUCK2_FULLON_MASK), 157 157 + REGMAP_IRQ_REG(BD70528_INT_SHORTPUSH, 3, BD70528_INT_SHORTPUSH_MASK), 158 158 + REGMAP_IRQ_REG(BD70528_INT_AUTO_WAKEUP, 3, 159 159 + BD70528_INT_AUTO_WAKEUP_MASK), 160 160 + REGMAP_IRQ_REG(BD70528_INT_STATE_CHANGE, 3, 161 161 + BD70528_INT_STATE_CHANGE_MASK), 162 162 + REGMAP_IRQ_REG(BD70528_INT_BAT_OV_RES, 4, BD70528_INT_BAT_OV_RES_MASK), 163 163 + REGMAP_IRQ_REG(BD70528_INT_BAT_OV_DET, 4, BD70528_INT_BAT_OV_DET_MASK), 164 164 + REGMAP_IRQ_REG(BD70528_INT_DBAT_DET, 4, BD70528_INT_DBAT_DET_MASK), 165 165 + REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_RES, 4, 166 166 + BD70528_INT_BATTSD_COLD_RES_MASK), 167 167 + REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_DET, 4, 168 168 + BD70528_INT_BATTSD_COLD_DET_MASK), 169 169 + REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_RES, 4, 170 170 + BD70528_INT_BATTSD_HOT_RES_MASK), 171 171 + REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_DET, 4, 172 172 + BD70528_INT_BATTSD_HOT_DET_MASK), 173 173 + REGMAP_IRQ_REG(BD70528_INT_CHG_TSD, 4, BD70528_INT_CHG_TSD_MASK), 174 174 + REGMAP_IRQ_REG(BD70528_INT_BAT_RMV, 5, BD70528_INT_BAT_RMV_MASK), 175 175 + REGMAP_IRQ_REG(BD70528_INT_BAT_DET, 5, BD70528_INT_BAT_DET_MASK), 176 176 + REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_RES, 5, 177 177 + BD70528_INT_DCIN2_OV_RES_MASK), 178 178 + REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_DET, 5, 179 179 + BD70528_INT_DCIN2_OV_DET_MASK), 180 180 + REGMAP_IRQ_REG(BD70528_INT_DCIN2_RMV, 5, BD70528_INT_DCIN2_RMV_MASK), 181 181 + REGMAP_IRQ_REG(BD70528_INT_DCIN2_DET, 5, BD70528_INT_DCIN2_DET_MASK), 182 182 + REGMAP_IRQ_REG(BD70528_INT_DCIN1_RMV, 5, BD70528_INT_DCIN1_RMV_MASK), 183 183 + REGMAP_IRQ_REG(BD70528_INT_DCIN1_DET, 5, BD70528_INT_DCIN1_DET_MASK), 184 184 + REGMAP_IRQ_REG(BD70528_INT_RTC_ALARM, 6, BD70528_INT_RTC_ALARM_MASK), 185 185 + REGMAP_IRQ_REG(BD70528_INT_ELPS_TIM, 6, BD70528_INT_ELPS_TIM_MASK), 186 186 + REGMAP_IRQ_REG(BD70528_INT_GPIO0, 7, BD70528_INT_GPIO0_MASK), 187 187 + REGMAP_IRQ_REG(BD70528_INT_GPIO1, 7, BD70528_INT_GPIO1_MASK), 188 188 + REGMAP_IRQ_REG(BD70528_INT_GPIO2, 7, BD70528_INT_GPIO2_MASK), 189 189 + REGMAP_IRQ_REG(BD70528_INT_GPIO3, 7, BD70528_INT_GPIO3_MASK), 190 190 + REGMAP_IRQ_REG(BD70528_INT_BUCK1_DVS_OPFAIL, 8, 191 191 + BD70528_INT_BUCK1_DVS_OPFAIL_MASK), 192 192 + REGMAP_IRQ_REG(BD70528_INT_BUCK2_DVS_OPFAIL, 8, 193 193 + BD70528_INT_BUCK2_DVS_OPFAIL_MASK), 194 194 + REGMAP_IRQ_REG(BD70528_INT_BUCK3_DVS_OPFAIL, 8, 195 195 + BD70528_INT_BUCK3_DVS_OPFAIL_MASK), 196 196 + REGMAP_IRQ_REG(BD70528_INT_LED1_VOLT_OPFAIL, 8, 197 197 + BD70528_INT_LED1_VOLT_OPFAIL_MASK), 198 198 + REGMAP_IRQ_REG(BD70528_INT_LED2_VOLT_OPFAIL, 8, 199 199 + BD70528_INT_LED2_VOLT_OPFAIL_MASK), 200 200 + }; 201 201 + 202 202 + static struct regmap_irq_chip bd70528_irq_chip = { 203 203 + .name = "bd70528_irq", 204 204 + .main_status = BD70528_REG_INT_MAIN, 205 205 + .irqs = &bd70528_irqs[0], 206 206 + .num_irqs = ARRAY_SIZE(bd70528_irqs), 207 207 + .status_base = BD70528_REG_INT_SHDN, 208 208 + .mask_base = BD70528_REG_INT_SHDN_MASK, 209 209 + .ack_base = BD70528_REG_INT_SHDN, 210 210 + .type_base = BD70528_REG_GPIO1_IN, 211 211 + .init_ack_masked = true, 212 212 + .num_regs = 9, 213 213 + .num_main_regs = 1, 214 214 + .num_type_reg = 4, 215 215 + .sub_reg_offsets = &bd70528_sub_irq_offsets[0], 216 216 + .num_main_status_bits = 8, 217 217 + .irq_reg_stride = 1, 218 218 + }; 219 219 + 220 220 + static int bd70528_i2c_probe(struct i2c_client *i2c, 221 221 + const struct i2c_device_id *id) 222 222 + { 223 223 + struct bd70528_data *bd70528; 224 224 + struct regmap_irq_chip_data *irq_data; 225 225 + int ret, i; 226 226 + 227 227 + if (!i2c->irq) { 228 228 + dev_err(&i2c->dev, "No IRQ configured\n"); 229 229 + return -EINVAL; 230 230 + } 231 231 + 232 232 + bd70528 = devm_kzalloc(&i2c->dev, sizeof(*bd70528), GFP_KERNEL); 233 233 + if (!bd70528) 234 234 + return -ENOMEM; 235 235 + 236 236 + mutex_init(&bd70528->rtc_timer_lock); 237 237 + 238 238 + dev_set_drvdata(&i2c->dev, &bd70528->chip); 239 239 + 240 240 + bd70528->chip.chip_type = ROHM_CHIP_TYPE_BD70528; 241 241 + bd70528->chip.regmap = devm_regmap_init_i2c(i2c, &bd70528_regmap); 242 242 + if (IS_ERR(bd70528->chip.regmap)) { 243 243 + dev_err(&i2c->dev, "Failed to initialize Regmap\n"); 244 244 + return PTR_ERR(bd70528->chip.regmap); 245 245 + } 246 246 + 247 247 + /* 248 248 + * Disallow type setting for all IRQs by default as most of them do not 249 249 + * support setting type. 250 250 + */ 251 251 + for (i = 0; i < ARRAY_SIZE(bd70528_irqs); i++) 252 252 + bd70528_irqs[i].type.types_supported = 0; 253 253 + 254 254 + /* Set IRQ typesetting information for GPIO pins 0 - 3 */ 255 255 + for (i = 0; i < BD70528_NUM_OF_GPIOS; i++) { 256 256 + struct regmap_irq_type *type; 257 257 + 258 258 + type = &bd70528_irqs[BD70528_INT_GPIO0 + i].type; 259 259 + type->type_reg_offset = 2 * i; 260 260 + type->type_rising_val = 0x20; 261 261 + type->type_falling_val = 0x10; 262 262 + type->type_level_high_val = 0x40; 263 263 + type->type_level_low_val = 0x50; 264 264 + type->types_supported = (IRQ_TYPE_EDGE_BOTH | 265 265 + IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW); 266 266 + } 267 267 + 268 268 + ret = devm_regmap_add_irq_chip(&i2c->dev, bd70528->chip.regmap, 269 269 + i2c->irq, IRQF_ONESHOT, 0, 270 270 + &bd70528_irq_chip, &irq_data); 271 271 + if (ret) { 272 272 + dev_err(&i2c->dev, "Failed to add IRQ chip\n"); 273 273 + return ret; 274 274 + } 275 275 + dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n", 276 276 + bd70528_irq_chip.num_irqs); 277 277 + 278 278 + /* 279 279 + * BD70528 IRQ controller is not touching the main mask register. 280 280 + * So enable the GPIO block interrupts at main level. We can just leave 281 281 + * them enabled as the IRQ controller should disable IRQs from 282 282 + * sub-registers when IRQ is disabled or freed. 283 283 + */ 284 284 + ret = regmap_update_bits(bd70528->chip.regmap, 285 285 + BD70528_REG_INT_MAIN_MASK, 286 286 + BD70528_INT_GPIO_MASK, 0); 287 287 + 288 288 + ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, 289 289 + bd70528_mfd_cells, 290 290 + ARRAY_SIZE(bd70528_mfd_cells), NULL, 0, 291 291 + regmap_irq_get_domain(irq_data)); 292 292 + if (ret) 293 293 + dev_err(&i2c->dev, "Failed to create subdevices\n"); 294 294 + 295 295 + return ret; 296 296 + } 297 297 + 298 298 + static const struct of_device_id bd70528_of_match[] = { 299 299 + { .compatible = "rohm,bd70528", }, 300 300 + { }, 301 301 + }; 302 302 + MODULE_DEVICE_TABLE(of, bd70528_of_match); 303 303 + 304 304 + static struct i2c_driver bd70528_drv = { 305 305 + .driver = { 306 306 + .name = "rohm-bd70528", 307 307 + .of_match_table = bd70528_of_match, 308 308 + }, 309 309 + .probe = &bd70528_i2c_probe, 310 310 + }; 311 311 + 312 312 + module_i2c_driver(bd70528_drv); 313 313 + 314 314 + MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 315 315 + MODULE_DESCRIPTION("ROHM BD70528 Power Management IC driver"); 316 316 + MODULE_LICENSE("GPL");

+50 -30

drivers/mfd/rohm-bd718x7.c

reviewed

··· 81 81 .cache_type = REGCACHE_RBTREE, 82 82 }; 83 83 84 84 + static int bd718xx_init_press_duration(struct bd718xx *bd718xx) 85 85 + { 86 86 + struct device* dev = bd718xx->chip.dev; 87 87 + u32 short_press_ms, long_press_ms; 88 88 + u32 short_press_value, long_press_value; 89 89 + int ret; 90 90 + 91 91 + ret = of_property_read_u32(dev->of_node, "rohm,short-press-ms", 92 92 + &short_press_ms); 93 93 + if (!ret) { 94 94 + short_press_value = min(15u, (short_press_ms + 250) / 500); 95 95 + ret = regmap_update_bits(bd718xx->chip.regmap, 96 96 + BD718XX_REG_PWRONCONFIG0, 97 97 + BD718XX_PWRBTN_PRESS_DURATION_MASK, 98 98 + short_press_value); 99 99 + if (ret) { 100 100 + dev_err(dev, "Failed to init pwron short press\n"); 101 101 + return ret; 102 102 + } 103 103 + } 104 104 + 105 105 + ret = of_property_read_u32(dev->of_node, "rohm,long-press-ms", 106 106 + &long_press_ms); 107 107 + if (!ret) { 108 108 + long_press_value = min(15u, (long_press_ms + 500) / 1000); 109 109 + ret = regmap_update_bits(bd718xx->chip.regmap, 110 110 + BD718XX_REG_PWRONCONFIG1, 111 111 + BD718XX_PWRBTN_PRESS_DURATION_MASK, 112 112 + long_press_value); 113 113 + if (ret) { 114 114 + dev_err(dev, "Failed to init pwron long press\n"); 115 115 + return ret; 116 116 + } 117 117 + } 118 118 + 119 119 + return 0; 120 120 + } 121 121 + 84 122 static int bd718xx_i2c_probe(struct i2c_client *i2c, 85 123 const struct i2c_device_id *id) 86 124 { ··· 136 98 return -ENOMEM; 137 99 138 100 bd718xx->chip_irq = i2c->irq; 139 139 - bd718xx->chip_type = (unsigned int)(uintptr_t) 101 101 + bd718xx->chip.chip_type = (unsigned int)(uintptr_t) 140 102 of_device_get_match_data(&i2c->dev); 141 141 - bd718xx->dev = &i2c->dev; 103 103 + bd718xx->chip.dev = &i2c->dev; 142 104 dev_set_drvdata(&i2c->dev, bd718xx); 143 105 144 144 - bd718xx->regmap = devm_regmap_init_i2c(i2c, &bd718xx_regmap_config); 145 145 - if (IS_ERR(bd718xx->regmap)) { 106 106 + bd718xx->chip.regmap = devm_regmap_init_i2c(i2c, 107 107 + &bd718xx_regmap_config); 108 108 + if (IS_ERR(bd718xx->chip.regmap)) { 146 109 dev_err(&i2c->dev, "regmap initialization failed\n"); 147 147 - return PTR_ERR(bd718xx->regmap); 110 110 + return PTR_ERR(bd718xx->chip.regmap); 148 111 } 149 112 150 150 - ret = devm_regmap_add_irq_chip(&i2c->dev, bd718xx->regmap, 113 113 + ret = devm_regmap_add_irq_chip(&i2c->dev, bd718xx->chip.regmap, 151 114 bd718xx->chip_irq, IRQF_ONESHOT, 0, 152 115 &bd718xx_irq_chip, &bd718xx->irq_data); 153 116 if (ret) { ··· 156 117 return ret; 157 118 } 158 119 159 159 - /* Configure short press to 10 milliseconds */ 160 160 - ret = regmap_update_bits(bd718xx->regmap, 161 161 - BD718XX_REG_PWRONCONFIG0, 162 162 - BD718XX_PWRBTN_PRESS_DURATION_MASK, 163 163 - BD718XX_PWRBTN_SHORT_PRESS_10MS); 164 164 - if (ret) { 165 165 - dev_err(&i2c->dev, 166 166 - "Failed to configure button short press timeout\n"); 120 120 + ret = bd718xx_init_press_duration(bd718xx); 121 121 + if (ret) 167 122 return ret; 168 168 - } 169 169 - 170 170 - /* Configure long press to 10 seconds */ 171 171 - ret = regmap_update_bits(bd718xx->regmap, 172 172 - BD718XX_REG_PWRONCONFIG1, 173 173 - BD718XX_PWRBTN_PRESS_DURATION_MASK, 174 174 - BD718XX_PWRBTN_LONG_PRESS_10S); 175 175 - 176 176 - if (ret) { 177 177 - dev_err(&i2c->dev, 178 178 - "Failed to configure button long press timeout\n"); 179 179 - return ret; 180 180 - } 181 123 182 124 ret = regmap_irq_get_virq(bd718xx->irq_data, BD718XX_INT_PWRBTN_S); 183 125 ··· 169 149 170 150 button.irq = ret; 171 151 172 172 - ret = devm_mfd_add_devices(bd718xx->dev, PLATFORM_DEVID_AUTO, 152 152 + ret = devm_mfd_add_devices(bd718xx->chip.dev, PLATFORM_DEVID_AUTO, 173 153 bd718xx_mfd_cells, 174 154 ARRAY_SIZE(bd718xx_mfd_cells), NULL, 0, 175 155 regmap_irq_get_domain(bd718xx->irq_data)); ··· 182 162 static const struct of_device_id bd718xx_of_match[] = { 183 163 { 184 164 .compatible = "rohm,bd71837", 185 185 - .data = (void *)BD718XX_TYPE_BD71837, 165 165 + .data = (void *)ROHM_CHIP_TYPE_BD71837, 186 166 }, 187 167 { 188 168 .compatible = "rohm,bd71847", 189 189 - .data = (void *)BD718XX_TYPE_BD71847, 169 169 + .data = (void *)ROHM_CHIP_TYPE_BD71847, 190 170 }, 191 171 { } 192 172 };

+9

drivers/power/supply/Kconfig

reviewed

··· 689 689 Say Y to enable support for Microchip UCS1002 Programmable 690 690 USB Port Power Controller with Charger Emulation. 691 691 692 692 + config CHARGER_BD70528 693 693 + tristate "ROHM bd70528 charger driver" 694 694 + depends on MFD_ROHM_BD70528 695 695 + default n 696 696 + help 697 697 + Say Y here to enable support for getting battery status 698 698 + information and altering charger configurations from charger 699 699 + block of the ROHM BD70528 Power Management IC. 700 700 + 692 701 endif # POWER_SUPPLY

+1

drivers/power/supply/Makefile

reviewed

··· 90 90 obj-$(CONFIG_CHARGER_SC2731) += sc2731_charger.o 91 91 obj-$(CONFIG_FUEL_GAUGE_SC27XX) += sc27xx_fuel_gauge.o 92 92 obj-$(CONFIG_CHARGER_UCS1002) += ucs1002_power.o 93 93 + obj-$(CONFIG_CHARGER_BD70528) += bd70528-charger.o

+743

drivers/power/supply/bd70528-charger.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 2 + // 3 3 + // Copyright (C) 2018 ROHM Semiconductors 4 4 + // 5 5 + // power-supply driver for ROHM BD70528 PMIC 6 6 + 7 7 + /* 8 8 + * BD70528 charger HW state machine. 9 9 + * 10 10 + * The thermal shutdown state is not drawn. From any other state but 11 11 + * battery error and suspend it is possible to go to TSD/TMP states 12 12 + * if temperature is out of bounds. 13 13 + * 14 14 + * CHG_RST = H 15 15 + * or CHG_EN=L 16 16 + * or (DCIN2_UVLO=L && DCIN1_UVLO=L) 17 17 + * or (DCIN2_OVLO=H & DCIN1_UVKLO=L) 18 18 + * 19 19 + * +--------------+ +--------------+ 20 20 + * | | | | 21 21 + * | Any state +-------> | Suspend | 22 22 + * | | | | 23 23 + * +--------------+ +------+-------+ 24 24 + * | 25 25 + * CHG_EN = H && BAT_DET = H && | 26 26 + * No errors (temp, bat_ov, UVLO, | 27 27 + * OVLO...) | 28 28 + * | 29 29 + * BAT_OV or +---------v----------+ 30 30 + * (DBAT && TTRI) | | 31 31 + * +-----------------+ Trickle Charge | <---------------+ 32 32 + * | | | | 33 33 + * | +-------+------------+ | 34 34 + * | | | 35 35 + * | | ^ | 36 36 + * | V_BAT > VTRI_TH | | VBAT < VTRI_TH - 50mV | 37 37 + * | | | | 38 38 + * | v | | 39 39 + * | | | 40 40 + * | BAT_OV or +----------+----+ | 41 41 + * | (DBAT && TFST) | | | 42 42 + * | +----------------+ Fast Charge | | 43 43 + * | | | | | 44 44 + * v v +----+----------+ | 45 45 + * | | 46 46 + *+----------------+ ILIM_DET=L | ^ ILIM_DET | 47 47 + *| | & CV_DET=H | | or CV_DET=L | 48 48 + *| Battery Error | & VBAT > | | or VBAT < VRECHG_TH | 49 49 + *| | VRECHG_TH | | or IBAT > IFST/x | 50 50 + *+----------------+ & IBAT < | | | 51 51 + * IFST/x v | | 52 52 + * ^ | | 53 53 + * | +---------+-+ | 54 54 + * | | | | 55 55 + * +-------------------+ Top OFF | | 56 56 + * BAT_OV = H or | | | 57 57 + * (DBAT && TFST) +-----+-----+ | 58 58 + * | | 59 59 + * Stay top-off for 15s | | 60 60 + * v | 61 61 + * | 62 62 + * +--------+ | 63 63 + * | | | 64 64 + * | Done +-------------------------+ 65 65 + * | | 66 66 + * +--------+ VBAT < VRECHG_TH 67 67 + */ 68 68 + 69 69 + #include <linux/kernel.h> 70 70 + #include <linux/interrupt.h> 71 71 + #include <linux/mfd/rohm-bd70528.h> 72 72 + #include <linux/module.h> 73 73 + #include <linux/platform_device.h> 74 74 + #include <linux/power_supply.h> 75 75 + 76 76 + #define CHG_STAT_SUSPEND 0x0 77 77 + #define CHG_STAT_TRICKLE 0x1 78 78 + #define CHG_STAT_FAST 0x3 79 79 + #define CHG_STAT_TOPOFF 0xe 80 80 + #define CHG_STAT_DONE 0xf 81 81 + #define CHG_STAT_OTP_TRICKLE 0x10 82 82 + #define CHG_STAT_OTP_FAST 0x11 83 83 + #define CHG_STAT_OTP_DONE 0x12 84 84 + #define CHG_STAT_TSD_TRICKLE 0x20 85 85 + #define CHG_STAT_TSD_FAST 0x21 86 86 + #define CHG_STAT_TSD_TOPOFF 0x22 87 87 + #define CHG_STAT_BAT_ERR 0x7f 88 88 + 89 89 + static const char *bd70528_charger_model = "BD70528"; 90 90 + static const char *bd70528_charger_manufacturer = "ROHM Semiconductors"; 91 91 + 92 92 + #define BD_ERR_IRQ_HND(_name_, _wrn_) \ 93 93 + static irqreturn_t bd0528_##_name_##_interrupt(int irq, void *arg) \ 94 94 + { \ 95 95 + struct power_supply *psy = (struct power_supply *)arg; \ 96 96 + \ 97 97 + power_supply_changed(psy); \ 98 98 + dev_err(&psy->dev, (_wrn_)); \ 99 99 + \ 100 100 + return IRQ_HANDLED; \ 101 101 + } 102 102 + 103 103 + #define BD_INFO_IRQ_HND(_name_, _wrn_) \ 104 104 + static irqreturn_t bd0528_##_name_##_interrupt(int irq, void *arg) \ 105 105 + { \ 106 106 + struct power_supply *psy = (struct power_supply *)arg; \ 107 107 + \ 108 108 + power_supply_changed(psy); \ 109 109 + dev_dbg(&psy->dev, (_wrn_)); \ 110 110 + \ 111 111 + return IRQ_HANDLED; \ 112 112 + } 113 113 + 114 114 + #define BD_IRQ_HND(_name_) bd0528_##_name_##_interrupt 115 115 + 116 116 + struct bd70528_psy { 117 117 + struct regmap *regmap; 118 118 + struct device *dev; 119 119 + struct power_supply *psy; 120 120 + }; 121 121 + 122 122 + BD_ERR_IRQ_HND(BAT_OV_DET, "Battery overvoltage detected\n"); 123 123 + BD_ERR_IRQ_HND(DBAT_DET, "Dead battery detected\n"); 124 124 + BD_ERR_IRQ_HND(COLD_DET, "Battery cold\n"); 125 125 + BD_ERR_IRQ_HND(HOT_DET, "Battery hot\n"); 126 126 + BD_ERR_IRQ_HND(CHG_TSD, "Charger thermal shutdown\n"); 127 127 + BD_ERR_IRQ_HND(DCIN2_OV_DET, "DCIN2 overvoltage detected\n"); 128 128 + 129 129 + BD_INFO_IRQ_HND(BAT_OV_RES, "Battery voltage back to normal\n"); 130 130 + BD_INFO_IRQ_HND(COLD_RES, "Battery temperature back to normal\n"); 131 131 + BD_INFO_IRQ_HND(HOT_RES, "Battery temperature back to normal\n"); 132 132 + BD_INFO_IRQ_HND(BAT_RMV, "Battery removed\n"); 133 133 + BD_INFO_IRQ_HND(BAT_DET, "Battery detected\n"); 134 134 + BD_INFO_IRQ_HND(DCIN2_OV_RES, "DCIN2 voltage back to normal\n"); 135 135 + BD_INFO_IRQ_HND(DCIN2_RMV, "DCIN2 removed\n"); 136 136 + BD_INFO_IRQ_HND(DCIN2_DET, "DCIN2 detected\n"); 137 137 + BD_INFO_IRQ_HND(DCIN1_RMV, "DCIN1 removed\n"); 138 138 + BD_INFO_IRQ_HND(DCIN1_DET, "DCIN1 detected\n"); 139 139 + 140 140 + struct irq_name_pair { 141 141 + const char *n; 142 142 + irqreturn_t (*h)(int irq, void *arg); 143 143 + }; 144 144 + 145 145 + static int bd70528_get_irqs(struct platform_device *pdev, 146 146 + struct bd70528_psy *bdpsy) 147 147 + { 148 148 + int irq, i, ret; 149 149 + unsigned int mask; 150 150 + static const struct irq_name_pair bd70528_chg_irqs[] = { 151 151 + { .n = "bd70528-bat-ov-res", .h = BD_IRQ_HND(BAT_OV_RES) }, 152 152 + { .n = "bd70528-bat-ov-det", .h = BD_IRQ_HND(BAT_OV_DET) }, 153 153 + { .n = "bd70528-bat-dead", .h = BD_IRQ_HND(DBAT_DET) }, 154 154 + { .n = "bd70528-bat-warmed", .h = BD_IRQ_HND(COLD_RES) }, 155 155 + { .n = "bd70528-bat-cold", .h = BD_IRQ_HND(COLD_DET) }, 156 156 + { .n = "bd70528-bat-cooled", .h = BD_IRQ_HND(HOT_RES) }, 157 157 + { .n = "bd70528-bat-hot", .h = BD_IRQ_HND(HOT_DET) }, 158 158 + { .n = "bd70528-chg-tshd", .h = BD_IRQ_HND(CHG_TSD) }, 159 159 + { .n = "bd70528-bat-removed", .h = BD_IRQ_HND(BAT_RMV) }, 160 160 + { .n = "bd70528-bat-detected", .h = BD_IRQ_HND(BAT_DET) }, 161 161 + { .n = "bd70528-dcin2-ov-res", .h = BD_IRQ_HND(DCIN2_OV_RES) }, 162 162 + { .n = "bd70528-dcin2-ov-det", .h = BD_IRQ_HND(DCIN2_OV_DET) }, 163 163 + { .n = "bd70528-dcin2-removed", .h = BD_IRQ_HND(DCIN2_RMV) }, 164 164 + { .n = "bd70528-dcin2-detected", .h = BD_IRQ_HND(DCIN2_DET) }, 165 165 + { .n = "bd70528-dcin1-removed", .h = BD_IRQ_HND(DCIN1_RMV) }, 166 166 + { .n = "bd70528-dcin1-detected", .h = BD_IRQ_HND(DCIN1_DET) }, 167 167 + }; 168 168 + 169 169 + for (i = 0; i < ARRAY_SIZE(bd70528_chg_irqs); i++) { 170 170 + irq = platform_get_irq_byname(pdev, bd70528_chg_irqs[i].n); 171 171 + if (irq < 0) { 172 172 + dev_err(&pdev->dev, "Bad IRQ information for %s (%d)\n", 173 173 + bd70528_chg_irqs[i].n, irq); 174 174 + return irq; 175 175 + } 176 176 + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 177 177 + bd70528_chg_irqs[i].h, 178 178 + IRQF_ONESHOT, 179 179 + bd70528_chg_irqs[i].n, 180 180 + bdpsy->psy); 181 181 + 182 182 + if (ret) 183 183 + return ret; 184 184 + } 185 185 + /* 186 186 + * BD70528 irq controller is not touching the main mask register. 187 187 + * So enable the charger block interrupts at main level. We can just 188 188 + * leave them enabled as irq-controller should disable irqs 189 189 + * from sub-registers when IRQ is disabled or freed. 190 190 + */ 191 191 + mask = BD70528_REG_INT_BAT1_MASK | BD70528_REG_INT_BAT2_MASK; 192 192 + ret = regmap_update_bits(bdpsy->regmap, 193 193 + BD70528_REG_INT_MAIN_MASK, mask, 0); 194 194 + if (ret) 195 195 + dev_err(&pdev->dev, "Failed to enable charger IRQs\n"); 196 196 + 197 197 + return ret; 198 198 + } 199 199 + 200 200 + static int bd70528_get_charger_status(struct bd70528_psy *bdpsy, int *val) 201 201 + { 202 202 + int ret; 203 203 + unsigned int v; 204 204 + 205 205 + ret = regmap_read(bdpsy->regmap, BD70528_REG_CHG_CURR_STAT, &v); 206 206 + if (ret) { 207 207 + dev_err(bdpsy->dev, "Charger state read failure %d\n", 208 208 + ret); 209 209 + return ret; 210 210 + } 211 211 + 212 212 + switch (v & BD70528_MASK_CHG_STAT) { 213 213 + case CHG_STAT_SUSPEND: 214 214 + /* Maybe we should check the CHG_TTRI_EN? */ 215 215 + case CHG_STAT_OTP_TRICKLE: 216 216 + case CHG_STAT_OTP_FAST: 217 217 + case CHG_STAT_OTP_DONE: 218 218 + case CHG_STAT_TSD_TRICKLE: 219 219 + case CHG_STAT_TSD_FAST: 220 220 + case CHG_STAT_TSD_TOPOFF: 221 221 + case CHG_STAT_BAT_ERR: 222 222 + *val = POWER_SUPPLY_STATUS_NOT_CHARGING; 223 223 + break; 224 224 + case CHG_STAT_DONE: 225 225 + *val = POWER_SUPPLY_STATUS_FULL; 226 226 + break; 227 227 + case CHG_STAT_TRICKLE: 228 228 + case CHG_STAT_FAST: 229 229 + case CHG_STAT_TOPOFF: 230 230 + *val = POWER_SUPPLY_STATUS_CHARGING; 231 231 + break; 232 232 + default: 233 233 + *val = POWER_SUPPLY_STATUS_UNKNOWN; 234 234 + break; 235 235 + } 236 236 + 237 237 + return 0; 238 238 + } 239 239 + 240 240 + static int bd70528_get_charge_type(struct bd70528_psy *bdpsy, int *val) 241 241 + { 242 242 + int ret; 243 243 + unsigned int v; 244 244 + 245 245 + ret = regmap_read(bdpsy->regmap, BD70528_REG_CHG_CURR_STAT, &v); 246 246 + if (ret) { 247 247 + dev_err(bdpsy->dev, "Charger state read failure %d\n", 248 248 + ret); 249 249 + return ret; 250 250 + } 251 251 + 252 252 + switch (v & BD70528_MASK_CHG_STAT) { 253 253 + case CHG_STAT_TRICKLE: 254 254 + *val = POWER_SUPPLY_CHARGE_TYPE_TRICKLE; 255 255 + break; 256 256 + case CHG_STAT_FAST: 257 257 + case CHG_STAT_TOPOFF: 258 258 + *val = POWER_SUPPLY_CHARGE_TYPE_FAST; 259 259 + break; 260 260 + case CHG_STAT_DONE: 261 261 + case CHG_STAT_SUSPEND: 262 262 + /* Maybe we should check the CHG_TTRI_EN? */ 263 263 + case CHG_STAT_OTP_TRICKLE: 264 264 + case CHG_STAT_OTP_FAST: 265 265 + case CHG_STAT_OTP_DONE: 266 266 + case CHG_STAT_TSD_TRICKLE: 267 267 + case CHG_STAT_TSD_FAST: 268 268 + case CHG_STAT_TSD_TOPOFF: 269 269 + case CHG_STAT_BAT_ERR: 270 270 + *val = POWER_SUPPLY_CHARGE_TYPE_NONE; 271 271 + break; 272 272 + default: 273 273 + *val = POWER_SUPPLY_CHARGE_TYPE_UNKNOWN; 274 274 + break; 275 275 + } 276 276 + 277 277 + return 0; 278 278 + } 279 279 + 280 280 + static int bd70528_get_battery_health(struct bd70528_psy *bdpsy, int *val) 281 281 + { 282 282 + int ret; 283 283 + unsigned int v; 284 284 + 285 285 + ret = regmap_read(bdpsy->regmap, BD70528_REG_CHG_BAT_STAT, &v); 286 286 + if (ret) { 287 287 + dev_err(bdpsy->dev, "Battery state read failure %d\n", 288 288 + ret); 289 289 + return ret; 290 290 + } 291 291 + /* No battery? */ 292 292 + if (!(v & BD70528_MASK_CHG_BAT_DETECT)) 293 293 + *val = POWER_SUPPLY_HEALTH_DEAD; 294 294 + else if (v & BD70528_MASK_CHG_BAT_OVERVOLT) 295 295 + *val = POWER_SUPPLY_HEALTH_OVERVOLTAGE; 296 296 + else if (v & BD70528_MASK_CHG_BAT_TIMER) 297 297 + *val = POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE; 298 298 + else 299 299 + *val = POWER_SUPPLY_HEALTH_GOOD; 300 300 + 301 301 + return 0; 302 302 + } 303 303 + 304 304 + static int bd70528_get_online(struct bd70528_psy *bdpsy, int *val) 305 305 + { 306 306 + int ret; 307 307 + unsigned int v; 308 308 + 309 309 + ret = regmap_read(bdpsy->regmap, BD70528_REG_CHG_IN_STAT, &v); 310 310 + if (ret) { 311 311 + dev_err(bdpsy->dev, "DC1 IN state read failure %d\n", 312 312 + ret); 313 313 + return ret; 314 314 + } 315 315 + 316 316 + *val = (v & BD70528_MASK_CHG_DCIN1_UVLO) ? 1 : 0; 317 317 + 318 318 + return 0; 319 319 + } 320 320 + 321 321 + static int bd70528_get_present(struct bd70528_psy *bdpsy, int *val) 322 322 + { 323 323 + int ret; 324 324 + unsigned int v; 325 325 + 326 326 + ret = regmap_read(bdpsy->regmap, BD70528_REG_CHG_BAT_STAT, &v); 327 327 + if (ret) { 328 328 + dev_err(bdpsy->dev, "Battery state read failure %d\n", 329 329 + ret); 330 330 + return ret; 331 331 + } 332 332 + 333 333 + *val = (v & BD70528_MASK_CHG_BAT_DETECT) ? 1 : 0; 334 334 + 335 335 + return 0; 336 336 + } 337 337 + 338 338 + struct linear_range { 339 339 + int min; 340 340 + int step; 341 341 + int vals; 342 342 + int low_sel; 343 343 + }; 344 344 + 345 345 + static const struct linear_range current_limit_ranges[] = { 346 346 + { 347 347 + .min = 5, 348 348 + .step = 1, 349 349 + .vals = 36, 350 350 + .low_sel = 0, 351 351 + }, 352 352 + { 353 353 + .min = 40, 354 354 + .step = 5, 355 355 + .vals = 5, 356 356 + .low_sel = 0x23, 357 357 + }, 358 358 + { 359 359 + .min = 60, 360 360 + .step = 20, 361 361 + .vals = 8, 362 362 + .low_sel = 0x27, 363 363 + }, 364 364 + { 365 365 + .min = 200, 366 366 + .step = 50, 367 367 + .vals = 7, 368 368 + .low_sel = 0x2e, 369 369 + } 370 370 + }; 371 371 + 372 372 + /* 373 373 + * BD70528 would support setting and getting own charge current/ 374 374 + * voltage for low temperatures. The driver currently only reads 375 375 + * the charge current at room temperature. We do set both though. 376 376 + */ 377 377 + static const struct linear_range warm_charge_curr[] = { 378 378 + { 379 379 + .min = 10, 380 380 + .step = 10, 381 381 + .vals = 20, 382 382 + .low_sel = 0, 383 383 + }, 384 384 + { 385 385 + .min = 200, 386 386 + .step = 25, 387 387 + .vals = 13, 388 388 + .low_sel = 0x13, 389 389 + }, 390 390 + }; 391 391 + 392 392 + /* 393 393 + * Cold charge current selectors are identical to warm charge current 394 394 + * selectors. The difference is that only smaller currents are available 395 395 + * at cold charge range. 396 396 + */ 397 397 + #define MAX_COLD_CHG_CURR_SEL 0x15 398 398 + #define MAX_WARM_CHG_CURR_SEL 0x1f 399 399 + #define MIN_CHG_CURR_SEL 0x0 400 400 + 401 401 + static int find_value_for_selector_low(const struct linear_range *r, 402 402 + int selectors, unsigned int sel, 403 403 + unsigned int *val) 404 404 + { 405 405 + int i; 406 406 + 407 407 + for (i = 0; i < selectors; i++) { 408 408 + if (r[i].low_sel <= sel && r[i].low_sel + r[i].vals >= sel) { 409 409 + *val = r[i].min + (sel - r[i].low_sel) * r[i].step; 410 410 + return 0; 411 411 + } 412 412 + } 413 413 + return -EINVAL; 414 414 + } 415 415 + 416 416 + /* 417 417 + * For BD70528 voltage/current limits we happily accept any value which 418 418 + * belongs the range. We could check if value matching the selector is 419 419 + * desired by computing the range min + (sel - sel_low) * range step - but 420 420 + * I guess it is enough if we use voltage/current which is closest (below) 421 421 + * the requested? 422 422 + */ 423 423 + static int find_selector_for_value_low(const struct linear_range *r, 424 424 + int selectors, unsigned int val, 425 425 + unsigned int *sel, bool *found) 426 426 + { 427 427 + int i; 428 428 + int ret = -EINVAL; 429 429 + 430 430 + *found = false; 431 431 + for (i = 0; i < selectors; i++) { 432 432 + if (r[i].min <= val) { 433 433 + if (r[i].min + r[i].step * r[i].vals >= val) { 434 434 + *found = true; 435 435 + *sel = r[i].low_sel + (val - r[i].min) / 436 436 + r[i].step; 437 437 + ret = 0; 438 438 + break; 439 439 + } 440 440 + /* 441 441 + * If the range max is smaller than requested 442 442 + * we can set the max supported value from range 443 443 + */ 444 444 + *sel = r[i].low_sel + r[i].vals; 445 445 + ret = 0; 446 446 + } 447 447 + } 448 448 + return ret; 449 449 + } 450 450 + 451 451 + static int get_charge_current(struct bd70528_psy *bdpsy, int *ma) 452 452 + { 453 453 + unsigned int sel; 454 454 + int ret; 455 455 + 456 456 + ret = regmap_read(bdpsy->regmap, BD70528_REG_CHG_CHG_CURR_WARM, 457 457 + &sel); 458 458 + if (ret) { 459 459 + dev_err(bdpsy->dev, 460 460 + "Charge current reading failed (%d)\n", ret); 461 461 + return ret; 462 462 + } 463 463 + 464 464 + sel &= BD70528_MASK_CHG_CHG_CURR; 465 465 + 466 466 + ret = find_value_for_selector_low(&warm_charge_curr[0], 467 467 + ARRAY_SIZE(warm_charge_curr), sel, 468 468 + ma); 469 469 + if (ret) { 470 470 + dev_err(bdpsy->dev, 471 471 + "Unknown charge current value 0x%x\n", 472 472 + sel); 473 473 + } 474 474 + 475 475 + return ret; 476 476 + } 477 477 + 478 478 + static int get_current_limit(struct bd70528_psy *bdpsy, int *ma) 479 479 + { 480 480 + unsigned int sel; 481 481 + int ret; 482 482 + 483 483 + ret = regmap_read(bdpsy->regmap, BD70528_REG_CHG_DCIN_ILIM, 484 484 + &sel); 485 485 + 486 486 + if (ret) { 487 487 + dev_err(bdpsy->dev, 488 488 + "Input current limit reading failed (%d)\n", ret); 489 489 + return ret; 490 490 + } 491 491 + 492 492 + sel &= BD70528_MASK_CHG_DCIN_ILIM; 493 493 + 494 494 + ret = find_value_for_selector_low(&current_limit_ranges[0], 495 495 + ARRAY_SIZE(current_limit_ranges), sel, 496 496 + ma); 497 497 + 498 498 + if (ret) { 499 499 + /* Unspecified values mean 500 mA */ 500 500 + *ma = 500; 501 501 + } 502 502 + return 0; 503 503 + } 504 504 + 505 505 + static enum power_supply_property bd70528_charger_props[] = { 506 506 + POWER_SUPPLY_PROP_STATUS, 507 507 + POWER_SUPPLY_PROP_CHARGE_TYPE, 508 508 + POWER_SUPPLY_PROP_HEALTH, 509 509 + POWER_SUPPLY_PROP_PRESENT, 510 510 + POWER_SUPPLY_PROP_ONLINE, 511 511 + POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, 512 512 + POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT, 513 513 + POWER_SUPPLY_PROP_MODEL_NAME, 514 514 + POWER_SUPPLY_PROP_MANUFACTURER, 515 515 + }; 516 516 + 517 517 + static int bd70528_charger_get_property(struct power_supply *psy, 518 518 + enum power_supply_property psp, 519 519 + union power_supply_propval *val) 520 520 + { 521 521 + struct bd70528_psy *bdpsy = power_supply_get_drvdata(psy); 522 522 + int ret = 0; 523 523 + 524 524 + switch (psp) { 525 525 + case POWER_SUPPLY_PROP_STATUS: 526 526 + return bd70528_get_charger_status(bdpsy, &val->intval); 527 527 + case POWER_SUPPLY_PROP_CHARGE_TYPE: 528 528 + return bd70528_get_charge_type(bdpsy, &val->intval); 529 529 + case POWER_SUPPLY_PROP_HEALTH: 530 530 + return bd70528_get_battery_health(bdpsy, &val->intval); 531 531 + case POWER_SUPPLY_PROP_PRESENT: 532 532 + return bd70528_get_present(bdpsy, &val->intval); 533 533 + case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT: 534 534 + ret = get_current_limit(bdpsy, &val->intval); 535 535 + val->intval *= 1000; 536 536 + return ret; 537 537 + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT: 538 538 + ret = get_charge_current(bdpsy, &val->intval); 539 539 + val->intval *= 1000; 540 540 + return ret; 541 541 + case POWER_SUPPLY_PROP_ONLINE: 542 542 + return bd70528_get_online(bdpsy, &val->intval); 543 543 + case POWER_SUPPLY_PROP_MODEL_NAME: 544 544 + val->strval = bd70528_charger_model; 545 545 + return 0; 546 546 + case POWER_SUPPLY_PROP_MANUFACTURER: 547 547 + val->strval = bd70528_charger_manufacturer; 548 548 + return 0; 549 549 + default: 550 550 + break; 551 551 + } 552 552 + 553 553 + return -EINVAL; 554 554 + } 555 555 + 556 556 + static int bd70528_prop_is_writable(struct power_supply *psy, 557 557 + enum power_supply_property psp) 558 558 + { 559 559 + switch (psp) { 560 560 + case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT: 561 561 + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT: 562 562 + return 1; 563 563 + default: 564 564 + break; 565 565 + } 566 566 + return 0; 567 567 + } 568 568 + 569 569 + static int set_charge_current(struct bd70528_psy *bdpsy, int ma) 570 570 + { 571 571 + unsigned int reg; 572 572 + int ret = 0, tmpret; 573 573 + bool found; 574 574 + 575 575 + if (ma > 500) { 576 576 + dev_warn(bdpsy->dev, 577 577 + "Requested charge current %u exceed maximum (500mA)\n", 578 578 + ma); 579 579 + reg = MAX_WARM_CHG_CURR_SEL; 580 580 + goto set; 581 581 + } 582 582 + if (ma < 10) { 583 583 + dev_err(bdpsy->dev, 584 584 + "Requested charge current %u smaller than min (10mA)\n", 585 585 + ma); 586 586 + reg = MIN_CHG_CURR_SEL; 587 587 + ret = -EINVAL; 588 588 + goto set; 589 589 + } 590 590 + 591 591 + ret = find_selector_for_value_low(&warm_charge_curr[0], 592 592 + ARRAY_SIZE(warm_charge_curr), ma, 593 593 + &reg, &found); 594 594 + if (ret) { 595 595 + reg = MIN_CHG_CURR_SEL; 596 596 + goto set; 597 597 + } 598 598 + if (!found) { 599 599 + /* There was a gap in supported values and we hit it */ 600 600 + dev_warn(bdpsy->dev, 601 601 + "Unsupported charge current %u mA\n", ma); 602 602 + } 603 603 + set: 604 604 + 605 605 + tmpret = regmap_update_bits(bdpsy->regmap, 606 606 + BD70528_REG_CHG_CHG_CURR_WARM, 607 607 + BD70528_MASK_CHG_CHG_CURR, reg); 608 608 + if (tmpret) 609 609 + dev_err(bdpsy->dev, 610 610 + "Charge current write failure (%d)\n", tmpret); 611 611 + 612 612 + if (reg > MAX_COLD_CHG_CURR_SEL) 613 613 + reg = MAX_COLD_CHG_CURR_SEL; 614 614 + 615 615 + if (!tmpret) 616 616 + tmpret = regmap_update_bits(bdpsy->regmap, 617 617 + BD70528_REG_CHG_CHG_CURR_COLD, 618 618 + BD70528_MASK_CHG_CHG_CURR, reg); 619 619 + 620 620 + if (!ret) 621 621 + ret = tmpret; 622 622 + 623 623 + return ret; 624 624 + } 625 625 + 626 626 + #define MAX_CURR_LIMIT_SEL 0x34 627 627 + #define MIN_CURR_LIMIT_SEL 0x0 628 628 + 629 629 + static int set_current_limit(struct bd70528_psy *bdpsy, int ma) 630 630 + { 631 631 + unsigned int reg; 632 632 + int ret = 0, tmpret; 633 633 + bool found; 634 634 + 635 635 + if (ma > 500) { 636 636 + dev_warn(bdpsy->dev, 637 637 + "Requested current limit %u exceed maximum (500mA)\n", 638 638 + ma); 639 639 + reg = MAX_CURR_LIMIT_SEL; 640 640 + goto set; 641 641 + } 642 642 + if (ma < 5) { 643 643 + dev_err(bdpsy->dev, 644 644 + "Requested current limit %u smaller than min (5mA)\n", 645 645 + ma); 646 646 + reg = MIN_CURR_LIMIT_SEL; 647 647 + ret = -EINVAL; 648 648 + goto set; 649 649 + } 650 650 + 651 651 + ret = find_selector_for_value_low(&current_limit_ranges[0], 652 652 + ARRAY_SIZE(current_limit_ranges), ma, 653 653 + &reg, &found); 654 654 + if (ret) { 655 655 + reg = MIN_CURR_LIMIT_SEL; 656 656 + goto set; 657 657 + } 658 658 + if (!found) { 659 659 + /* There was a gap in supported values and we hit it ?*/ 660 660 + dev_warn(bdpsy->dev, "Unsupported current limit %umA\n", 661 661 + ma); 662 662 + } 663 663 + 664 664 + set: 665 665 + tmpret = regmap_update_bits(bdpsy->regmap, 666 666 + BD70528_REG_CHG_DCIN_ILIM, 667 667 + BD70528_MASK_CHG_DCIN_ILIM, reg); 668 668 + 669 669 + if (!ret) 670 670 + ret = tmpret; 671 671 + 672 672 + return ret; 673 673 + } 674 674 + 675 675 + static int bd70528_charger_set_property(struct power_supply *psy, 676 676 + enum power_supply_property psp, 677 677 + const union power_supply_propval *val) 678 678 + { 679 679 + struct bd70528_psy *bdpsy = power_supply_get_drvdata(psy); 680 680 + 681 681 + switch (psp) { 682 682 + case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT: 683 683 + return set_current_limit(bdpsy, val->intval / 1000); 684 684 + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT: 685 685 + return set_charge_current(bdpsy, val->intval / 1000); 686 686 + default: 687 687 + break; 688 688 + } 689 689 + return -EINVAL; 690 690 + } 691 691 + 692 692 + static const struct power_supply_desc bd70528_charger_desc = { 693 693 + .name = "bd70528-charger", 694 694 + .type = POWER_SUPPLY_TYPE_MAINS, 695 695 + .properties = bd70528_charger_props, 696 696 + .num_properties = ARRAY_SIZE(bd70528_charger_props), 697 697 + .get_property = bd70528_charger_get_property, 698 698 + .set_property = bd70528_charger_set_property, 699 699 + .property_is_writeable = bd70528_prop_is_writable, 700 700 + }; 701 701 + 702 702 + static int bd70528_power_probe(struct platform_device *pdev) 703 703 + { 704 704 + struct bd70528_psy *bdpsy; 705 705 + struct power_supply_config cfg = {}; 706 706 + 707 707 + bdpsy = devm_kzalloc(&pdev->dev, sizeof(*bdpsy), GFP_KERNEL); 708 708 + if (!bdpsy) 709 709 + return -ENOMEM; 710 710 + 711 711 + bdpsy->regmap = dev_get_regmap(pdev->dev.parent, NULL); 712 712 + if (!bdpsy->regmap) { 713 713 + dev_err(&pdev->dev, "No regmap found for chip\n"); 714 714 + return -EINVAL; 715 715 + } 716 716 + bdpsy->dev = &pdev->dev; 717 717 + 718 718 + platform_set_drvdata(pdev, bdpsy); 719 719 + cfg.drv_data = bdpsy; 720 720 + cfg.of_node = pdev->dev.parent->of_node; 721 721 + 722 722 + bdpsy->psy = devm_power_supply_register(&pdev->dev, 723 723 + &bd70528_charger_desc, &cfg); 724 724 + if (IS_ERR(bdpsy->psy)) { 725 725 + dev_err(&pdev->dev, "failed: power supply register\n"); 726 726 + return PTR_ERR(bdpsy->psy); 727 727 + } 728 728 + 729 729 + return bd70528_get_irqs(pdev, bdpsy); 730 730 + } 731 731 + 732 732 + static struct platform_driver bd70528_power = { 733 733 + .driver = { 734 734 + .name = "bd70528-power" 735 735 + }, 736 736 + .probe = bd70528_power_probe, 737 737 + }; 738 738 + 739 739 + module_platform_driver(bd70528_power); 740 740 + 741 741 + MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 742 742 + MODULE_DESCRIPTION("BD70528 power-supply driver"); 743 743 + MODULE_LICENSE("GPL");

+2 -2

drivers/regulator/Kconfig

reviewed

··· 764 764 outputs which can be controlled by i2c communication. 765 765 766 766 config REGULATOR_RK808 767 767 - tristate "Rockchip RK805/RK808/RK818 Power regulators" 767 767 + tristate "Rockchip RK805/RK808/RK809/RK817/RK818 Power regulators" 768 768 depends on MFD_RK808 769 769 help 770 770 Select this option to enable the power regulator of ROCKCHIP 771 771 - PMIC RK805,RK808 and RK818. 771 771 + PMIC RK805,RK809&RK817,RK808 and RK818. 772 772 This driver supports the control of different power rails of device 773 773 through regulator interface. The device supports multiple DCDC/LDO 774 774 outputs which can be controlled by i2c communication.

+13 -12

drivers/regulator/bd718x7-regulator.c

reviewed

··· 1151 1151 { 1152 1152 struct bd718xx *mfd; 1153 1153 struct regulator_config config = { 0 }; 1154 1154 - struct bd718xx_pmic_inits pmic_regulators[] = { 1155 1155 - [BD718XX_TYPE_BD71837] = { 1154 1154 + struct bd718xx_pmic_inits pmic_regulators[ROHM_CHIP_TYPE_AMOUNT] = { 1155 1155 + [ROHM_CHIP_TYPE_BD71837] = { 1156 1156 .r_datas = bd71837_regulators, 1157 1157 .r_amount = ARRAY_SIZE(bd71837_regulators), 1158 1158 }, 1159 1159 - [BD718XX_TYPE_BD71847] = { 1159 1159 + [ROHM_CHIP_TYPE_BD71847] = { 1160 1160 .r_datas = bd71847_regulators, 1161 1161 .r_amount = ARRAY_SIZE(bd71847_regulators), 1162 1162 }, ··· 1172 1172 goto err; 1173 1173 } 1174 1174 1175 1175 - if (mfd->chip_type >= BD718XX_TYPE_AMOUNT || 1176 1176 - !pmic_regulators[mfd->chip_type].r_datas) { 1175 1175 + if (mfd->chip.chip_type >= ROHM_CHIP_TYPE_AMOUNT || 1176 1176 + !pmic_regulators[mfd->chip.chip_type].r_datas) { 1177 1177 dev_err(&pdev->dev, "Unsupported chip type\n"); 1178 1178 err = -EINVAL; 1179 1179 goto err; 1180 1180 } 1181 1181 1182 1182 /* Register LOCK release */ 1183 1183 - err = regmap_update_bits(mfd->regmap, BD718XX_REG_REGLOCK, 1183 1183 + err = regmap_update_bits(mfd->chip.regmap, BD718XX_REG_REGLOCK, 1184 1184 (REGLOCK_PWRSEQ | REGLOCK_VREG), 0); 1185 1185 if (err) { 1186 1186 dev_err(&pdev->dev, "Failed to unlock PMIC (%d)\n", err); ··· 1199 1199 * bit allowing HW defaults for power rails to be used 1200 1200 */ 1201 1201 if (!use_snvs) { 1202 1202 - err = regmap_update_bits(mfd->regmap, BD718XX_REG_TRANS_COND1, 1202 1202 + err = regmap_update_bits(mfd->chip.regmap, 1203 1203 + BD718XX_REG_TRANS_COND1, 1203 1204 BD718XX_ON_REQ_POWEROFF_MASK | 1204 1205 BD718XX_SWRESET_POWEROFF_MASK | 1205 1206 BD718XX_WDOG_POWEROFF_MASK | ··· 1215 1214 } 1216 1215 } 1217 1216 1218 1218 - for (i = 0; i < pmic_regulators[mfd->chip_type].r_amount; i++) { 1217 1217 + for (i = 0; i < pmic_regulators[mfd->chip.chip_type].r_amount; i++) { 1219 1218 1220 1219 const struct regulator_desc *desc; 1221 1220 struct regulator_dev *rdev; 1222 1221 const struct bd718xx_regulator_data *r; 1223 1222 1224 1224 - r = &pmic_regulators[mfd->chip_type].r_datas[i]; 1223 1223 + r = &pmic_regulators[mfd->chip.chip_type].r_datas[i]; 1225 1224 desc = &r->desc; 1226 1225 1227 1226 config.dev = pdev->dev.parent; 1228 1228 - config.regmap = mfd->regmap; 1227 1227 + config.regmap = mfd->chip.regmap; 1229 1228 1230 1229 rdev = devm_regulator_register(&pdev->dev, desc, &config); 1231 1230 if (IS_ERR(rdev)) { ··· 1254 1253 */ 1255 1254 if (!use_snvs || !rdev->constraints->always_on || 1256 1255 !rdev->constraints->boot_on) { 1257 1257 - err = regmap_update_bits(mfd->regmap, r->init.reg, 1256 1256 + err = regmap_update_bits(mfd->chip.regmap, r->init.reg, 1258 1257 r->init.mask, r->init.val); 1259 1258 if (err) { 1260 1259 dev_err(&pdev->dev, ··· 1264 1263 } 1265 1264 } 1266 1265 for (j = 0; j < r->additional_init_amnt; j++) { 1267 1267 - err = regmap_update_bits(mfd->regmap, 1266 1266 + err = regmap_update_bits(mfd->chip.regmap, 1268 1267 r->additional_inits[j].reg, 1269 1268 r->additional_inits[j].mask, 1270 1269 r->additional_inits[j].val);

+17 -1

drivers/regulator/lp87565-regulator.c

reviewed

··· 150 150 LP87565_REG_BUCK2_CTRL_1, 151 151 LP87565_BUCK_CTRL_1_EN, 3230, 152 152 buck0_1_2_3_ranges, LP87565_REG_BUCK2_CTRL_2), 153 153 + LP87565_REGULATOR("BUCK3210", LP87565_BUCK_3210, "buck3210", 154 154 + lp87565_buck_ops, 256, LP87565_REG_BUCK0_VOUT, 155 155 + LP87565_BUCK_VSET, LP87565_REG_BUCK0_CTRL_1, 156 156 + LP87565_BUCK_CTRL_1_EN | 157 157 + LP87565_BUCK_CTRL_1_FPWM_MP_0_2, 3230, 158 158 + buck0_1_2_3_ranges, LP87565_REG_BUCK0_CTRL_2), 153 159 }; 154 160 155 161 static int lp87565_regulator_probe(struct platform_device *pdev) ··· 172 166 config.driver_data = lp87565; 173 167 config.regmap = lp87565->regmap; 174 168 175 175 - if (lp87565->dev_type == LP87565_DEVICE_TYPE_LP87565_Q1) { 169 169 + switch (lp87565->dev_type) { 170 170 + case LP87565_DEVICE_TYPE_LP87565_Q1: 176 171 min_idx = LP87565_BUCK_10; 177 172 max_idx = LP87565_BUCK_23; 173 173 + break; 174 174 + case LP87565_DEVICE_TYPE_LP87561_Q1: 175 175 + min_idx = LP87565_BUCK_3210; 176 176 + max_idx = LP87565_BUCK_3210; 177 177 + break; 178 178 + default: 179 179 + dev_err(lp87565->dev, "Invalid lp config %d\n", 180 180 + lp87565->dev_type); 181 181 + return -EINVAL; 178 182 } 179 183 180 184 for (i = min_idx; i <= max_idx; i++) {

+621 -27

drivers/regulator/rk808-regulator.c

reviewed

··· 28 28 #define RK808_BUCK4_VSEL_MASK 0xf 29 29 #define RK808_LDO_VSEL_MASK 0x1f 30 30 31 31 + #define RK809_BUCK5_VSEL_MASK 0x7 32 32 + 33 33 + #define RK817_LDO_VSEL_MASK 0x7f 34 34 + #define RK817_BOOST_VSEL_MASK 0x7 35 35 + #define RK817_BUCK_VSEL_MASK 0x7f 36 36 + 31 37 #define RK818_BUCK_VSEL_MASK 0x3f 32 38 #define RK818_BUCK4_VSEL_MASK 0x1f 33 39 #define RK818_LDO_VSEL_MASK 0x1f ··· 63 57 /* max steps for increase voltage of Buck1/2, equal 100mv*/ 64 58 #define MAX_STEPS_ONE_TIME 8 65 59 66 66 - #define RK805_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \ 67 67 - _vmask, _ereg, _emask, _etime) \ 68 68 - [_id] = { \ 69 69 - .name = (_match), \ 70 70 - .supply_name = (_supply), \ 71 71 - .of_match = of_match_ptr(_match), \ 72 72 - .regulators_node = of_match_ptr("regulators"), \ 73 73 - .type = REGULATOR_VOLTAGE, \ 74 74 - .id = (_id), \ 75 75 - .n_voltages = (((_max) - (_min)) / (_step) + 1), \ 76 76 - .owner = THIS_MODULE, \ 77 77 - .min_uV = (_min) * 1000, \ 78 78 - .uV_step = (_step) * 1000, \ 79 79 - .vsel_reg = (_vreg), \ 80 80 - .vsel_mask = (_vmask), \ 81 81 - .enable_reg = (_ereg), \ 82 82 - .enable_mask = (_emask), \ 83 83 - .enable_time = (_etime), \ 84 84 - .ops = &rk805_reg_ops, \ 85 85 - } 60 60 + #define ENABLE_MASK(id) (BIT(id) | BIT(4 + (id))) 61 61 + #define DISABLE_VAL(id) (BIT(4 + (id))) 86 62 87 87 - #define RK8XX_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \ 88 88 - _vmask, _ereg, _emask, _etime) \ 89 89 - [_id] = { \ 63 63 + #define RK817_BOOST_DESC(_id, _match, _supply, _min, _max, _step, _vreg,\ 64 64 + _vmask, _ereg, _emask, _enval, _disval, _etime, m_drop) \ 65 65 + { \ 90 66 .name = (_match), \ 91 67 .supply_name = (_supply), \ 92 68 .of_match = of_match_ptr(_match), \ ··· 83 95 .vsel_mask = (_vmask), \ 84 96 .enable_reg = (_ereg), \ 85 97 .enable_mask = (_emask), \ 98 98 + .enable_val = (_enval), \ 99 99 + .disable_val = (_disval), \ 86 100 .enable_time = (_etime), \ 87 87 - .ops = &rk808_reg_ops, \ 101 101 + .min_dropout_uV = (m_drop) * 1000, \ 102 102 + .ops = &rk817_boost_ops, \ 88 103 } 89 104 90 90 - #define RK8XX_DESC_SWITCH(_id, _match, _supply, _ereg, _emask) \ 91 91 - [_id] = { \ 105 105 + #define RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \ 106 106 + _vmask, _ereg, _emask, _enval, _disval, _etime, _ops) \ 107 107 + { \ 108 108 + .name = (_match), \ 109 109 + .supply_name = (_supply), \ 110 110 + .of_match = of_match_ptr(_match), \ 111 111 + .regulators_node = of_match_ptr("regulators"), \ 112 112 + .type = REGULATOR_VOLTAGE, \ 113 113 + .id = (_id), \ 114 114 + .n_voltages = (((_max) - (_min)) / (_step) + 1), \ 115 115 + .owner = THIS_MODULE, \ 116 116 + .min_uV = (_min) * 1000, \ 117 117 + .uV_step = (_step) * 1000, \ 118 118 + .vsel_reg = (_vreg), \ 119 119 + .vsel_mask = (_vmask), \ 120 120 + .enable_reg = (_ereg), \ 121 121 + .enable_mask = (_emask), \ 122 122 + .enable_val = (_enval), \ 123 123 + .disable_val = (_disval), \ 124 124 + .enable_time = (_etime), \ 125 125 + .ops = _ops, \ 126 126 + } 127 127 + 128 128 + #define RK805_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \ 129 129 + _vmask, _ereg, _emask, _etime) \ 130 130 + RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \ 131 131 + _vmask, _ereg, _emask, 0, 0, _etime, &rk805_reg_ops) 132 132 + 133 133 + #define RK8XX_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \ 134 134 + _vmask, _ereg, _emask, _etime) \ 135 135 + RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \ 136 136 + _vmask, _ereg, _emask, 0, 0, _etime, &rk808_reg_ops) 137 137 + 138 138 + #define RK817_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \ 139 139 + _vmask, _ereg, _emask, _disval, _etime) \ 140 140 + RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \ 141 141 + _vmask, _ereg, _emask, _emask, _disval, _etime, &rk817_reg_ops) 142 142 + 143 143 + #define RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \ 144 144 + _enval, _disval, _ops) \ 145 145 + { \ 92 146 .name = (_match), \ 93 147 .supply_name = (_supply), \ 94 148 .of_match = of_match_ptr(_match), \ ··· 139 109 .id = (_id), \ 140 110 .enable_reg = (_ereg), \ 141 111 .enable_mask = (_emask), \ 112 112 + .enable_val = (_enval), \ 113 113 + .disable_val = (_disval), \ 142 114 .owner = THIS_MODULE, \ 143 143 - .ops = &rk808_switch_ops \ 115 115 + .ops = _ops \ 144 116 } 145 117 118 118 + #define RK817_DESC_SWITCH(_id, _match, _supply, _ereg, _emask, \ 119 119 + _disval) \ 120 120 + RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \ 121 121 + _emask, _disval, &rk817_switch_ops) 122 122 + 123 123 + #define RK8XX_DESC_SWITCH(_id, _match, _supply, _ereg, _emask) \ 124 124 + RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \ 125 125 + 0, 0, &rk808_switch_ops) 146 126 147 127 struct rk808_regulator_data { 148 128 struct gpio_desc *dvs_gpio[2]; ··· 168 128 static const struct regulator_linear_range rk808_ldo3_voltage_ranges[] = { 169 129 REGULATOR_LINEAR_RANGE(800000, 0, 13, 100000), 170 130 REGULATOR_LINEAR_RANGE(2500000, 15, 15, 0), 131 131 + }; 132 132 + 133 133 + #define RK809_BUCK5_SEL_CNT (8) 134 134 + 135 135 + static const struct regulator_linear_range rk809_buck5_voltage_ranges[] = { 136 136 + REGULATOR_LINEAR_RANGE(1500000, 0, 0, 0), 137 137 + REGULATOR_LINEAR_RANGE(1800000, 1, 3, 200000), 138 138 + REGULATOR_LINEAR_RANGE(2800000, 4, 5, 200000), 139 139 + REGULATOR_LINEAR_RANGE(3300000, 6, 7, 300000), 140 140 + }; 141 141 + 142 142 + #define RK817_BUCK1_MIN0 500000 143 143 + #define RK817_BUCK1_MAX0 1500000 144 144 + 145 145 + #define RK817_BUCK1_MIN1 1600000 146 146 + #define RK817_BUCK1_MAX1 2400000 147 147 + 148 148 + #define RK817_BUCK3_MAX1 3400000 149 149 + 150 150 + #define RK817_BUCK1_STP0 12500 151 151 + #define RK817_BUCK1_STP1 100000 152 152 + 153 153 + #define RK817_BUCK1_SEL0 ((RK817_BUCK1_MAX0 - RK817_BUCK1_MIN0) /\ 154 154 + RK817_BUCK1_STP0) 155 155 + #define RK817_BUCK1_SEL1 ((RK817_BUCK1_MAX1 - RK817_BUCK1_MIN1) /\ 156 156 + RK817_BUCK1_STP1) 157 157 + 158 158 + #define RK817_BUCK3_SEL1 ((RK817_BUCK3_MAX1 - RK817_BUCK1_MIN1) /\ 159 159 + RK817_BUCK1_STP1) 160 160 + 161 161 + #define RK817_BUCK1_SEL_CNT (RK817_BUCK1_SEL0 + RK817_BUCK1_SEL1 + 1) 162 162 + #define RK817_BUCK3_SEL_CNT (RK817_BUCK1_SEL0 + RK817_BUCK3_SEL1 + 1) 163 163 + 164 164 + static const struct regulator_linear_range rk817_buck1_voltage_ranges[] = { 165 165 + REGULATOR_LINEAR_RANGE(RK817_BUCK1_MIN0, 0, 166 166 + RK817_BUCK1_SEL0, RK817_BUCK1_STP0), 167 167 + REGULATOR_LINEAR_RANGE(RK817_BUCK1_MIN1, RK817_BUCK1_SEL0 + 1, 168 168 + RK817_BUCK1_SEL_CNT, RK817_BUCK1_STP1), 169 169 + }; 170 170 + 171 171 + static const struct regulator_linear_range rk817_buck3_voltage_ranges[] = { 172 172 + REGULATOR_LINEAR_RANGE(RK817_BUCK1_MIN0, 0, 173 173 + RK817_BUCK1_SEL0, RK817_BUCK1_STP0), 174 174 + REGULATOR_LINEAR_RANGE(RK817_BUCK1_MIN1, RK817_BUCK1_SEL0 + 1, 175 175 + RK817_BUCK3_SEL_CNT, RK817_BUCK1_STP1), 171 176 }; 172 177 173 178 static int rk808_buck1_2_get_voltage_sel_regmap(struct regulator_dev *rdev) ··· 366 281 RK808_RAMP_RATE_MASK, ramp_value); 367 282 } 368 283 284 284 + /* 285 285 + * RK817 RK809 286 286 + */ 287 287 + static int rk817_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay) 288 288 + { 289 289 + unsigned int ramp_value = RK817_RAMP_RATE_25MV_PER_US; 290 290 + unsigned int reg = RK817_BUCK_CONFIG_REG(rdev_get_id(rdev)); 291 291 + 292 292 + switch (ramp_delay) { 293 293 + case 0 ... 3000: 294 294 + ramp_value = RK817_RAMP_RATE_3MV_PER_US; 295 295 + break; 296 296 + case 3001 ... 6300: 297 297 + ramp_value = RK817_RAMP_RATE_6_3MV_PER_US; 298 298 + break; 299 299 + case 6301 ... 12500: 300 300 + ramp_value = RK817_RAMP_RATE_12_5MV_PER_US; 301 301 + break; 302 302 + case 12501 ... 25000: 303 303 + break; 304 304 + default: 305 305 + dev_warn(&rdev->dev, 306 306 + "%s ramp_delay: %d not supported, setting 10000\n", 307 307 + rdev->desc->name, ramp_delay); 308 308 + } 309 309 + 310 310 + return regmap_update_bits(rdev->regmap, reg, 311 311 + RK817_RAMP_RATE_MASK, ramp_value); 312 312 + } 313 313 + 369 314 static int rk808_set_suspend_voltage(struct regulator_dev *rdev, int uv) 370 315 { 371 316 unsigned int reg; 372 317 int sel = regulator_map_voltage_linear(rdev, uv, uv); 373 318 319 319 + if (sel < 0) 320 320 + return -EINVAL; 321 321 + 322 322 + reg = rdev->desc->vsel_reg + RK808_SLP_REG_OFFSET; 323 323 + 324 324 + return regmap_update_bits(rdev->regmap, reg, 325 325 + rdev->desc->vsel_mask, 326 326 + sel); 327 327 + } 328 328 + 329 329 + static int rk817_set_suspend_voltage(struct regulator_dev *rdev, int uv) 330 330 + { 331 331 + unsigned int reg; 332 332 + int sel = regulator_map_voltage_linear(rdev, uv, uv); 333 333 + /* only ldo1~ldo9 */ 374 334 if (sel < 0) 375 335 return -EINVAL; 376 336 ··· 483 353 return regmap_update_bits(rdev->regmap, reg, 484 354 rdev->desc->enable_mask, 485 355 rdev->desc->enable_mask); 356 356 + } 357 357 + 358 358 + static int rk817_set_suspend_enable_ctrl(struct regulator_dev *rdev, 359 359 + unsigned int en) 360 360 + { 361 361 + unsigned int reg; 362 362 + int id = rdev_get_id(rdev); 363 363 + unsigned int id_slp, msk, val; 364 364 + 365 365 + if (id >= RK817_ID_DCDC1 && id <= RK817_ID_DCDC4) 366 366 + id_slp = id; 367 367 + else if (id >= RK817_ID_LDO1 && id <= RK817_ID_LDO8) 368 368 + id_slp = 8 + (id - RK817_ID_LDO1); 369 369 + else if (id >= RK817_ID_LDO9 && id <= RK809_ID_SW2) 370 370 + id_slp = 4 + (id - RK817_ID_LDO9); 371 371 + else 372 372 + return -EINVAL; 373 373 + 374 374 + reg = RK817_POWER_SLP_EN_REG(id_slp / 8); 375 375 + 376 376 + msk = BIT(id_slp % 8); 377 377 + if (en) 378 378 + val = msk; 379 379 + else 380 380 + val = 0; 381 381 + 382 382 + return regmap_update_bits(rdev->regmap, reg, msk, val); 383 383 + } 384 384 + 385 385 + static int rk817_set_suspend_enable(struct regulator_dev *rdev) 386 386 + { 387 387 + return rk817_set_suspend_enable_ctrl(rdev, 1); 388 388 + } 389 389 + 390 390 + static int rk817_set_suspend_disable(struct regulator_dev *rdev) 391 391 + { 392 392 + return rk817_set_suspend_enable_ctrl(rdev, 0); 393 393 + } 394 394 + 395 395 + static int rk8xx_set_suspend_mode(struct regulator_dev *rdev, unsigned int mode) 396 396 + { 397 397 + unsigned int reg; 398 398 + 399 399 + reg = rdev->desc->vsel_reg + RK808_SLP_REG_OFFSET; 400 400 + 401 401 + switch (mode) { 402 402 + case REGULATOR_MODE_FAST: 403 403 + return regmap_update_bits(rdev->regmap, reg, 404 404 + PWM_MODE_MSK, FPWM_MODE); 405 405 + case REGULATOR_MODE_NORMAL: 406 406 + return regmap_update_bits(rdev->regmap, reg, 407 407 + PWM_MODE_MSK, AUTO_PWM_MODE); 408 408 + default: 409 409 + dev_err(&rdev->dev, "do not support this mode\n"); 410 410 + return -EINVAL; 411 411 + } 412 412 + 413 413 + return 0; 414 414 + } 415 415 + 416 416 + static int rk8xx_set_mode(struct regulator_dev *rdev, unsigned int mode) 417 417 + { 418 418 + switch (mode) { 419 419 + case REGULATOR_MODE_FAST: 420 420 + return regmap_update_bits(rdev->regmap, rdev->desc->vsel_reg, 421 421 + PWM_MODE_MSK, FPWM_MODE); 422 422 + case REGULATOR_MODE_NORMAL: 423 423 + return regmap_update_bits(rdev->regmap, rdev->desc->vsel_reg, 424 424 + PWM_MODE_MSK, AUTO_PWM_MODE); 425 425 + default: 426 426 + dev_err(&rdev->dev, "do not support this mode\n"); 427 427 + return -EINVAL; 428 428 + } 429 429 + 430 430 + return 0; 431 431 + } 432 432 + 433 433 + static unsigned int rk8xx_get_mode(struct regulator_dev *rdev) 434 434 + { 435 435 + unsigned int val; 436 436 + int err; 437 437 + 438 438 + err = regmap_read(rdev->regmap, rdev->desc->vsel_reg, &val); 439 439 + if (err) 440 440 + return err; 441 441 + 442 442 + if (val & FPWM_MODE) 443 443 + return REGULATOR_MODE_FAST; 444 444 + else 445 445 + return REGULATOR_MODE_NORMAL; 446 446 + } 447 447 + 448 448 + static int rk8xx_is_enabled_wmsk_regmap(struct regulator_dev *rdev) 449 449 + { 450 450 + unsigned int val; 451 451 + int ret; 452 452 + 453 453 + ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val); 454 454 + if (ret != 0) 455 455 + return ret; 456 456 + 457 457 + /* add write mask bit */ 458 458 + val |= (rdev->desc->enable_mask & 0xf0); 459 459 + val &= rdev->desc->enable_mask; 460 460 + 461 461 + if (rdev->desc->enable_is_inverted) { 462 462 + if (rdev->desc->enable_val) 463 463 + return val != rdev->desc->enable_val; 464 464 + return (val == 0); 465 465 + } 466 466 + if (rdev->desc->enable_val) 467 467 + return val == rdev->desc->enable_val; 468 468 + return val != 0; 469 469 + } 470 470 + 471 471 + static unsigned int rk8xx_regulator_of_map_mode(unsigned int mode) 472 472 + { 473 473 + switch (mode) { 474 474 + case 1: 475 475 + return REGULATOR_MODE_FAST; 476 476 + case 2: 477 477 + return REGULATOR_MODE_NORMAL; 478 478 + default: 479 479 + return -EINVAL; 480 480 + } 486 481 } 487 482 488 483 static const struct regulator_ops rk805_reg_ops = { ··· 684 429 REGULATOR_LINEAR_RANGE(712500, 0, 59, 12500), 685 430 REGULATOR_LINEAR_RANGE(1800000, 60, 62, 200000), 686 431 REGULATOR_LINEAR_RANGE(2300000, 63, 63, 0), 432 432 + }; 433 433 + 434 434 + static struct regulator_ops rk809_buck5_ops_range = { 435 435 + .list_voltage = regulator_list_voltage_linear_range, 436 436 + .map_voltage = regulator_map_voltage_linear_range, 437 437 + .get_voltage_sel = regulator_get_voltage_sel_regmap, 438 438 + .set_voltage_sel = regulator_set_voltage_sel_regmap, 439 439 + .set_voltage_time_sel = regulator_set_voltage_time_sel, 440 440 + .enable = regulator_enable_regmap, 441 441 + .disable = regulator_disable_regmap, 442 442 + .is_enabled = rk8xx_is_enabled_wmsk_regmap, 443 443 + .set_suspend_voltage = rk808_set_suspend_voltage_range, 444 444 + .set_suspend_enable = rk817_set_suspend_enable, 445 445 + .set_suspend_disable = rk817_set_suspend_disable, 446 446 + }; 447 447 + 448 448 + static struct regulator_ops rk817_reg_ops = { 449 449 + .list_voltage = regulator_list_voltage_linear, 450 450 + .map_voltage = regulator_map_voltage_linear, 451 451 + .get_voltage_sel = regulator_get_voltage_sel_regmap, 452 452 + .set_voltage_sel = regulator_set_voltage_sel_regmap, 453 453 + .enable = regulator_enable_regmap, 454 454 + .disable = regulator_disable_regmap, 455 455 + .is_enabled = rk8xx_is_enabled_wmsk_regmap, 456 456 + .set_suspend_voltage = rk817_set_suspend_voltage, 457 457 + .set_suspend_enable = rk817_set_suspend_enable, 458 458 + .set_suspend_disable = rk817_set_suspend_disable, 459 459 + }; 460 460 + 461 461 + static struct regulator_ops rk817_boost_ops = { 462 462 + .list_voltage = regulator_list_voltage_linear, 463 463 + .map_voltage = regulator_map_voltage_linear, 464 464 + .get_voltage_sel = regulator_get_voltage_sel_regmap, 465 465 + .set_voltage_sel = regulator_set_voltage_sel_regmap, 466 466 + .enable = regulator_enable_regmap, 467 467 + .disable = regulator_disable_regmap, 468 468 + .is_enabled = rk8xx_is_enabled_wmsk_regmap, 469 469 + .set_suspend_enable = rk817_set_suspend_enable, 470 470 + .set_suspend_disable = rk817_set_suspend_disable, 471 471 + }; 472 472 + 473 473 + static struct regulator_ops rk817_buck_ops_range = { 474 474 + .list_voltage = regulator_list_voltage_linear_range, 475 475 + .map_voltage = regulator_map_voltage_linear_range, 476 476 + .get_voltage_sel = regulator_get_voltage_sel_regmap, 477 477 + .set_voltage_sel = regulator_set_voltage_sel_regmap, 478 478 + .set_voltage_time_sel = regulator_set_voltage_time_sel, 479 479 + .enable = regulator_enable_regmap, 480 480 + .disable = regulator_disable_regmap, 481 481 + .is_enabled = rk8xx_is_enabled_wmsk_regmap, 482 482 + .set_mode = rk8xx_set_mode, 483 483 + .get_mode = rk8xx_get_mode, 484 484 + .set_suspend_mode = rk8xx_set_suspend_mode, 485 485 + .set_ramp_delay = rk817_set_ramp_delay, 486 486 + .set_suspend_voltage = rk808_set_suspend_voltage_range, 487 487 + .set_suspend_enable = rk817_set_suspend_enable, 488 488 + .set_suspend_disable = rk817_set_suspend_disable, 489 489 + }; 490 490 + 491 491 + static struct regulator_ops rk817_switch_ops = { 492 492 + .enable = regulator_enable_regmap, 493 493 + .disable = regulator_disable_regmap, 494 494 + .is_enabled = rk8xx_is_enabled_wmsk_regmap, 495 495 + .set_suspend_enable = rk817_set_suspend_enable, 496 496 + .set_suspend_disable = rk817_set_suspend_disable, 687 497 }; 688 498 689 499 static const struct regulator_desc rk805_reg[] = { ··· 905 585 RK808_DCDC_EN_REG, BIT(5)), 906 586 RK8XX_DESC_SWITCH(RK808_ID_SWITCH2, "SWITCH_REG2", "vcc12", 907 587 RK808_DCDC_EN_REG, BIT(6)), 588 588 + }; 589 589 + 590 590 + static const struct regulator_desc rk809_reg[] = { 591 591 + { 592 592 + .name = "DCDC_REG1", 593 593 + .supply_name = "vcc1", 594 594 + .of_match = of_match_ptr("DCDC_REG1"), 595 595 + .regulators_node = of_match_ptr("regulators"), 596 596 + .id = RK817_ID_DCDC1, 597 597 + .ops = &rk817_buck_ops_range, 598 598 + .type = REGULATOR_VOLTAGE, 599 599 + .n_voltages = RK817_BUCK1_SEL_CNT + 1, 600 600 + .linear_ranges = rk817_buck1_voltage_ranges, 601 601 + .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges), 602 602 + .vsel_reg = RK817_BUCK1_ON_VSEL_REG, 603 603 + .vsel_mask = RK817_BUCK_VSEL_MASK, 604 604 + .enable_reg = RK817_POWER_EN_REG(0), 605 605 + .enable_mask = ENABLE_MASK(RK817_ID_DCDC1), 606 606 + .enable_val = ENABLE_MASK(RK817_ID_DCDC1), 607 607 + .disable_val = DISABLE_VAL(RK817_ID_DCDC1), 608 608 + .of_map_mode = rk8xx_regulator_of_map_mode, 609 609 + .owner = THIS_MODULE, 610 610 + }, { 611 611 + .name = "DCDC_REG2", 612 612 + .supply_name = "vcc2", 613 613 + .of_match = of_match_ptr("DCDC_REG2"), 614 614 + .regulators_node = of_match_ptr("regulators"), 615 615 + .id = RK817_ID_DCDC2, 616 616 + .ops = &rk817_buck_ops_range, 617 617 + .type = REGULATOR_VOLTAGE, 618 618 + .n_voltages = RK817_BUCK1_SEL_CNT + 1, 619 619 + .linear_ranges = rk817_buck1_voltage_ranges, 620 620 + .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges), 621 621 + .vsel_reg = RK817_BUCK2_ON_VSEL_REG, 622 622 + .vsel_mask = RK817_BUCK_VSEL_MASK, 623 623 + .enable_reg = RK817_POWER_EN_REG(0), 624 624 + .enable_mask = ENABLE_MASK(RK817_ID_DCDC2), 625 625 + .enable_val = ENABLE_MASK(RK817_ID_DCDC2), 626 626 + .disable_val = DISABLE_VAL(RK817_ID_DCDC2), 627 627 + .of_map_mode = rk8xx_regulator_of_map_mode, 628 628 + .owner = THIS_MODULE, 629 629 + }, { 630 630 + .name = "DCDC_REG3", 631 631 + .supply_name = "vcc3", 632 632 + .of_match = of_match_ptr("DCDC_REG3"), 633 633 + .regulators_node = of_match_ptr("regulators"), 634 634 + .id = RK817_ID_DCDC3, 635 635 + .ops = &rk817_buck_ops_range, 636 636 + .type = REGULATOR_VOLTAGE, 637 637 + .n_voltages = RK817_BUCK1_SEL_CNT + 1, 638 638 + .linear_ranges = rk817_buck1_voltage_ranges, 639 639 + .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges), 640 640 + .vsel_reg = RK817_BUCK3_ON_VSEL_REG, 641 641 + .vsel_mask = RK817_BUCK_VSEL_MASK, 642 642 + .enable_reg = RK817_POWER_EN_REG(0), 643 643 + .enable_mask = ENABLE_MASK(RK817_ID_DCDC3), 644 644 + .enable_val = ENABLE_MASK(RK817_ID_DCDC3), 645 645 + .disable_val = DISABLE_VAL(RK817_ID_DCDC3), 646 646 + .of_map_mode = rk8xx_regulator_of_map_mode, 647 647 + .owner = THIS_MODULE, 648 648 + }, { 649 649 + .name = "DCDC_REG4", 650 650 + .supply_name = "vcc4", 651 651 + .of_match = of_match_ptr("DCDC_REG4"), 652 652 + .regulators_node = of_match_ptr("regulators"), 653 653 + .id = RK817_ID_DCDC4, 654 654 + .ops = &rk817_buck_ops_range, 655 655 + .type = REGULATOR_VOLTAGE, 656 656 + .n_voltages = RK817_BUCK3_SEL_CNT + 1, 657 657 + .linear_ranges = rk817_buck3_voltage_ranges, 658 658 + .n_linear_ranges = ARRAY_SIZE(rk817_buck3_voltage_ranges), 659 659 + .vsel_reg = RK817_BUCK4_ON_VSEL_REG, 660 660 + .vsel_mask = RK817_BUCK_VSEL_MASK, 661 661 + .enable_reg = RK817_POWER_EN_REG(0), 662 662 + .enable_mask = ENABLE_MASK(RK817_ID_DCDC4), 663 663 + .enable_val = ENABLE_MASK(RK817_ID_DCDC4), 664 664 + .disable_val = DISABLE_VAL(RK817_ID_DCDC4), 665 665 + .of_map_mode = rk8xx_regulator_of_map_mode, 666 666 + .owner = THIS_MODULE, 667 667 + }, 668 668 + { 669 669 + .name = "DCDC_REG5", 670 670 + .supply_name = "vcc9", 671 671 + .of_match = of_match_ptr("DCDC_REG5"), 672 672 + .regulators_node = of_match_ptr("regulators"), 673 673 + .id = RK809_ID_DCDC5, 674 674 + .ops = &rk809_buck5_ops_range, 675 675 + .type = REGULATOR_VOLTAGE, 676 676 + .n_voltages = RK809_BUCK5_SEL_CNT, 677 677 + .linear_ranges = rk809_buck5_voltage_ranges, 678 678 + .n_linear_ranges = ARRAY_SIZE(rk809_buck5_voltage_ranges), 679 679 + .vsel_reg = RK809_BUCK5_CONFIG(0), 680 680 + .vsel_mask = RK809_BUCK5_VSEL_MASK, 681 681 + .enable_reg = RK817_POWER_EN_REG(3), 682 682 + .enable_mask = ENABLE_MASK(1), 683 683 + .enable_val = ENABLE_MASK(1), 684 684 + .disable_val = DISABLE_VAL(1), 685 685 + .of_map_mode = rk8xx_regulator_of_map_mode, 686 686 + .owner = THIS_MODULE, 687 687 + }, 688 688 + RK817_DESC(RK817_ID_LDO1, "LDO_REG1", "vcc5", 600, 3400, 25, 689 689 + RK817_LDO_ON_VSEL_REG(0), RK817_LDO_VSEL_MASK, 690 690 + RK817_POWER_EN_REG(1), ENABLE_MASK(0), 691 691 + DISABLE_VAL(0), 400), 692 692 + RK817_DESC(RK817_ID_LDO2, "LDO_REG2", "vcc5", 600, 3400, 25, 693 693 + RK817_LDO_ON_VSEL_REG(1), RK817_LDO_VSEL_MASK, 694 694 + RK817_POWER_EN_REG(1), ENABLE_MASK(1), 695 695 + DISABLE_VAL(1), 400), 696 696 + RK817_DESC(RK817_ID_LDO3, "LDO_REG3", "vcc5", 600, 3400, 25, 697 697 + RK817_LDO_ON_VSEL_REG(2), RK817_LDO_VSEL_MASK, 698 698 + RK817_POWER_EN_REG(1), ENABLE_MASK(2), 699 699 + DISABLE_VAL(2), 400), 700 700 + RK817_DESC(RK817_ID_LDO4, "LDO_REG4", "vcc6", 600, 3400, 25, 701 701 + RK817_LDO_ON_VSEL_REG(3), RK817_LDO_VSEL_MASK, 702 702 + RK817_POWER_EN_REG(1), ENABLE_MASK(3), 703 703 + DISABLE_VAL(3), 400), 704 704 + RK817_DESC(RK817_ID_LDO5, "LDO_REG5", "vcc6", 600, 3400, 25, 705 705 + RK817_LDO_ON_VSEL_REG(4), RK817_LDO_VSEL_MASK, 706 706 + RK817_POWER_EN_REG(2), ENABLE_MASK(0), 707 707 + DISABLE_VAL(0), 400), 708 708 + RK817_DESC(RK817_ID_LDO6, "LDO_REG6", "vcc6", 600, 3400, 25, 709 709 + RK817_LDO_ON_VSEL_REG(5), RK817_LDO_VSEL_MASK, 710 710 + RK817_POWER_EN_REG(2), ENABLE_MASK(1), 711 711 + DISABLE_VAL(1), 400), 712 712 + RK817_DESC(RK817_ID_LDO7, "LDO_REG7", "vcc7", 600, 3400, 25, 713 713 + RK817_LDO_ON_VSEL_REG(6), RK817_LDO_VSEL_MASK, 714 714 + RK817_POWER_EN_REG(2), ENABLE_MASK(2), 715 715 + DISABLE_VAL(2), 400), 716 716 + RK817_DESC(RK817_ID_LDO8, "LDO_REG8", "vcc7", 600, 3400, 25, 717 717 + RK817_LDO_ON_VSEL_REG(7), RK817_LDO_VSEL_MASK, 718 718 + RK817_POWER_EN_REG(2), ENABLE_MASK(3), 719 719 + DISABLE_VAL(3), 400), 720 720 + RK817_DESC(RK817_ID_LDO9, "LDO_REG9", "vcc7", 600, 3400, 25, 721 721 + RK817_LDO_ON_VSEL_REG(8), RK817_LDO_VSEL_MASK, 722 722 + RK817_POWER_EN_REG(3), ENABLE_MASK(0), 723 723 + DISABLE_VAL(0), 400), 724 724 + RK817_DESC_SWITCH(RK809_ID_SW1, "SWITCH_REG1", "vcc9", 725 725 + RK817_POWER_EN_REG(3), ENABLE_MASK(2), 726 726 + DISABLE_VAL(2)), 727 727 + RK817_DESC_SWITCH(RK809_ID_SW2, "SWITCH_REG2", "vcc8", 728 728 + RK817_POWER_EN_REG(3), ENABLE_MASK(3), 729 729 + DISABLE_VAL(3)), 730 730 + }; 731 731 + 732 732 + static const struct regulator_desc rk817_reg[] = { 733 733 + { 734 734 + .name = "DCDC_REG1", 735 735 + .supply_name = "vcc1", 736 736 + .of_match = of_match_ptr("DCDC_REG1"), 737 737 + .regulators_node = of_match_ptr("regulators"), 738 738 + .id = RK817_ID_DCDC1, 739 739 + .ops = &rk817_buck_ops_range, 740 740 + .type = REGULATOR_VOLTAGE, 741 741 + .n_voltages = RK817_BUCK1_SEL_CNT + 1, 742 742 + .linear_ranges = rk817_buck1_voltage_ranges, 743 743 + .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges), 744 744 + .vsel_reg = RK817_BUCK1_ON_VSEL_REG, 745 745 + .vsel_mask = RK817_BUCK_VSEL_MASK, 746 746 + .enable_reg = RK817_POWER_EN_REG(0), 747 747 + .enable_mask = ENABLE_MASK(RK817_ID_DCDC1), 748 748 + .enable_val = ENABLE_MASK(RK817_ID_DCDC1), 749 749 + .disable_val = DISABLE_VAL(RK817_ID_DCDC1), 750 750 + .of_map_mode = rk8xx_regulator_of_map_mode, 751 751 + .owner = THIS_MODULE, 752 752 + }, { 753 753 + .name = "DCDC_REG2", 754 754 + .supply_name = "vcc2", 755 755 + .of_match = of_match_ptr("DCDC_REG2"), 756 756 + .regulators_node = of_match_ptr("regulators"), 757 757 + .id = RK817_ID_DCDC2, 758 758 + .ops = &rk817_buck_ops_range, 759 759 + .type = REGULATOR_VOLTAGE, 760 760 + .n_voltages = RK817_BUCK1_SEL_CNT + 1, 761 761 + .linear_ranges = rk817_buck1_voltage_ranges, 762 762 + .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges), 763 763 + .vsel_reg = RK817_BUCK2_ON_VSEL_REG, 764 764 + .vsel_mask = RK817_BUCK_VSEL_MASK, 765 765 + .enable_reg = RK817_POWER_EN_REG(0), 766 766 + .enable_mask = ENABLE_MASK(RK817_ID_DCDC2), 767 767 + .enable_val = ENABLE_MASK(RK817_ID_DCDC2), 768 768 + .disable_val = DISABLE_VAL(RK817_ID_DCDC2), 769 769 + .of_map_mode = rk8xx_regulator_of_map_mode, 770 770 + .owner = THIS_MODULE, 771 771 + }, { 772 772 + .name = "DCDC_REG3", 773 773 + .supply_name = "vcc3", 774 774 + .of_match = of_match_ptr("DCDC_REG3"), 775 775 + .regulators_node = of_match_ptr("regulators"), 776 776 + .id = RK817_ID_DCDC3, 777 777 + .ops = &rk817_buck_ops_range, 778 778 + .type = REGULATOR_VOLTAGE, 779 779 + .n_voltages = RK817_BUCK1_SEL_CNT + 1, 780 780 + .linear_ranges = rk817_buck1_voltage_ranges, 781 781 + .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges), 782 782 + .vsel_reg = RK817_BUCK3_ON_VSEL_REG, 783 783 + .vsel_mask = RK817_BUCK_VSEL_MASK, 784 784 + .enable_reg = RK817_POWER_EN_REG(0), 785 785 + .enable_mask = ENABLE_MASK(RK817_ID_DCDC3), 786 786 + .enable_val = ENABLE_MASK(RK817_ID_DCDC3), 787 787 + .disable_val = DISABLE_VAL(RK817_ID_DCDC3), 788 788 + .of_map_mode = rk8xx_regulator_of_map_mode, 789 789 + .owner = THIS_MODULE, 790 790 + }, { 791 791 + .name = "DCDC_REG4", 792 792 + .supply_name = "vcc4", 793 793 + .of_match = of_match_ptr("DCDC_REG4"), 794 794 + .regulators_node = of_match_ptr("regulators"), 795 795 + .id = RK817_ID_DCDC4, 796 796 + .ops = &rk817_buck_ops_range, 797 797 + .type = REGULATOR_VOLTAGE, 798 798 + .n_voltages = RK817_BUCK3_SEL_CNT + 1, 799 799 + .linear_ranges = rk817_buck3_voltage_ranges, 800 800 + .n_linear_ranges = ARRAY_SIZE(rk817_buck3_voltage_ranges), 801 801 + .vsel_reg = RK817_BUCK4_ON_VSEL_REG, 802 802 + .vsel_mask = RK817_BUCK_VSEL_MASK, 803 803 + .enable_reg = RK817_POWER_EN_REG(0), 804 804 + .enable_mask = ENABLE_MASK(RK817_ID_DCDC4), 805 805 + .enable_val = ENABLE_MASK(RK817_ID_DCDC4), 806 806 + .disable_val = DISABLE_VAL(RK817_ID_DCDC4), 807 807 + .of_map_mode = rk8xx_regulator_of_map_mode, 808 808 + .owner = THIS_MODULE, 809 809 + }, 810 810 + RK817_DESC(RK817_ID_LDO1, "LDO_REG1", "vcc5", 600, 3400, 25, 811 811 + RK817_LDO_ON_VSEL_REG(0), RK817_LDO_VSEL_MASK, 812 812 + RK817_POWER_EN_REG(1), ENABLE_MASK(0), 813 813 + DISABLE_VAL(0), 400), 814 814 + RK817_DESC(RK817_ID_LDO2, "LDO_REG2", "vcc5", 600, 3400, 25, 815 815 + RK817_LDO_ON_VSEL_REG(1), RK817_LDO_VSEL_MASK, 816 816 + RK817_POWER_EN_REG(1), ENABLE_MASK(1), 817 817 + DISABLE_VAL(1), 400), 818 818 + RK817_DESC(RK817_ID_LDO3, "LDO_REG3", "vcc5", 600, 3400, 25, 819 819 + RK817_LDO_ON_VSEL_REG(2), RK817_LDO_VSEL_MASK, 820 820 + RK817_POWER_EN_REG(1), ENABLE_MASK(2), 821 821 + DISABLE_VAL(2), 400), 822 822 + RK817_DESC(RK817_ID_LDO4, "LDO_REG4", "vcc6", 600, 3400, 25, 823 823 + RK817_LDO_ON_VSEL_REG(3), RK817_LDO_VSEL_MASK, 824 824 + RK817_POWER_EN_REG(1), ENABLE_MASK(3), 825 825 + DISABLE_VAL(3), 400), 826 826 + RK817_DESC(RK817_ID_LDO5, "LDO_REG5", "vcc6", 600, 3400, 25, 827 827 + RK817_LDO_ON_VSEL_REG(4), RK817_LDO_VSEL_MASK, 828 828 + RK817_POWER_EN_REG(2), ENABLE_MASK(0), 829 829 + DISABLE_VAL(0), 400), 830 830 + RK817_DESC(RK817_ID_LDO6, "LDO_REG6", "vcc6", 600, 3400, 25, 831 831 + RK817_LDO_ON_VSEL_REG(5), RK817_LDO_VSEL_MASK, 832 832 + RK817_POWER_EN_REG(2), ENABLE_MASK(1), 833 833 + DISABLE_VAL(1), 400), 834 834 + RK817_DESC(RK817_ID_LDO7, "LDO_REG7", "vcc7", 600, 3400, 25, 835 835 + RK817_LDO_ON_VSEL_REG(6), RK817_LDO_VSEL_MASK, 836 836 + RK817_POWER_EN_REG(2), ENABLE_MASK(2), 837 837 + DISABLE_VAL(2), 400), 838 838 + RK817_DESC(RK817_ID_LDO8, "LDO_REG8", "vcc7", 600, 3400, 25, 839 839 + RK817_LDO_ON_VSEL_REG(7), RK817_LDO_VSEL_MASK, 840 840 + RK817_POWER_EN_REG(2), ENABLE_MASK(3), 841 841 + DISABLE_VAL(3), 400), 842 842 + RK817_DESC(RK817_ID_LDO9, "LDO_REG9", "vcc7", 600, 3400, 25, 843 843 + RK817_LDO_ON_VSEL_REG(8), RK817_LDO_VSEL_MASK, 844 844 + RK817_POWER_EN_REG(3), ENABLE_MASK(0), 845 845 + DISABLE_VAL(0), 400), 846 846 + RK817_BOOST_DESC(RK817_ID_BOOST, "BOOST", "vcc8", 4700, 5400, 100, 847 847 + RK817_BOOST_OTG_CFG, RK817_BOOST_VSEL_MASK, 848 848 + RK817_POWER_EN_REG(3), ENABLE_MASK(1), ENABLE_MASK(1), 849 849 + DISABLE_VAL(1), 400, 3500 - 5400), 850 850 + RK817_DESC_SWITCH(RK817_ID_BOOST_OTG_SW, "OTG_SWITCH", "vcc9", 851 851 + RK817_POWER_EN_REG(3), ENABLE_MASK(2), 852 852 + DISABLE_VAL(2)), 908 853 }; 909 854 910 855 static const struct regulator_desc rk818_reg[] = { ··· 1342 757 regulators = rk808_reg; 1343 758 nregulators = RK808_NUM_REGULATORS; 1344 759 break; 760 760 + case RK809_ID: 761 761 + regulators = rk809_reg; 762 762 + nregulators = RK809_NUM_REGULATORS; 763 763 + break; 764 764 + case RK817_ID: 765 765 + regulators = rk817_reg; 766 766 + nregulators = RK817_NUM_REGULATORS; 767 767 + break; 1345 768 case RK818_ID: 1346 769 regulators = rk818_reg; 1347 770 nregulators = RK818_NUM_REGULATORS; ··· 1388 795 module_platform_driver(rk808_regulator_driver); 1389 796 1390 797 MODULE_DESCRIPTION("regulator driver for the RK805/RK808/RK818 series PMICs"); 798 798 + MODULE_AUTHOR("Tony xie <tony.xie@rock-chips.com>"); 1391 799 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>"); 1392 800 MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>"); 1393 801 MODULE_AUTHOR("Wadim Egorov <w.egorov@phytec.de>");

+10 -2

drivers/rtc/Kconfig

reviewed

··· 374 374 will be called rtc-max77686. 375 375 376 376 config RTC_DRV_RK808 377 377 - tristate "Rockchip RK805/RK808/RK818 RTC" 377 377 + tristate "Rockchip RK805/RK808/RK809/RK817/RK818 RTC" 378 378 depends on MFD_RK808 379 379 help 380 380 If you say yes here you will get support for the 381 381 - RTC of RK805, RK808 and RK818 PMIC. 381 381 + RTC of RK805, RK809 and RK817, RK808 and RK818 PMIC. 382 382 383 383 This driver can also be built as a module. If so, the module 384 384 will be called rk808-rtc. ··· 498 498 help 499 499 If you say Y here you will get support for the 500 500 watchdog timer in the ST M41T60 and M41T80 RTC chips series. 501 501 + config RTC_DRV_BD70528 502 502 + tristate "ROHM BD70528 PMIC RTC" 503 503 + help 504 504 + If you say Y here you will get support for the RTC 505 505 + on ROHM BD70528 Power Management IC. 506 506 + 507 507 + This driver can also be built as a module. If so, the module 508 508 + will be called rtc-bd70528. 501 509 502 510 config RTC_DRV_BQ32K 503 511 tristate "TI BQ32000"

+1

drivers/rtc/Makefile

reviewed

··· 38 38 obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o 39 39 obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o 40 40 obj-$(CONFIG_RTC_DRV_AU1XXX) += rtc-au1xxx.o 41 41 + obj-$(CONFIG_RTC_DRV_BD70528) += rtc-bd70528.o 41 42 obj-$(CONFIG_RTC_DRV_BQ32K) += rtc-bq32k.o 42 43 obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o 43 44 obj-$(CONFIG_RTC_DRV_BRCMSTB) += rtc-brcmstb-waketimer.o

+500

drivers/rtc/rtc-bd70528.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 2 + // 3 3 + // Copyright (C) 2018 ROHM Semiconductors 4 4 + // 5 5 + // RTC driver for ROHM BD70528 PMIC 6 6 + 7 7 + #include <linux/bcd.h> 8 8 + #include <linux/mfd/rohm-bd70528.h> 9 9 + #include <linux/module.h> 10 10 + #include <linux/of.h> 11 11 + #include <linux/platform_device.h> 12 12 + #include <linux/regmap.h> 13 13 + #include <linux/rtc.h> 14 14 + 15 15 + /* 16 16 + * We read regs RTC_SEC => RTC_YEAR 17 17 + * this struct is ordered according to chip registers. 18 18 + * Keep it u8 only to avoid padding issues. 19 19 + */ 20 20 + struct bd70528_rtc_day { 21 21 + u8 sec; 22 22 + u8 min; 23 23 + u8 hour; 24 24 + } __packed; 25 25 + 26 26 + struct bd70528_rtc_data { 27 27 + struct bd70528_rtc_day time; 28 28 + u8 week; 29 29 + u8 day; 30 30 + u8 month; 31 31 + u8 year; 32 32 + } __packed; 33 33 + 34 34 + struct bd70528_rtc_wake { 35 35 + struct bd70528_rtc_day time; 36 36 + u8 ctrl; 37 37 + } __packed; 38 38 + 39 39 + struct bd70528_rtc_alm { 40 40 + struct bd70528_rtc_data data; 41 41 + u8 alm_mask; 42 42 + u8 alm_repeat; 43 43 + } __packed; 44 44 + 45 45 + struct bd70528_rtc { 46 46 + struct rohm_regmap_dev *mfd; 47 47 + struct device *dev; 48 48 + }; 49 49 + 50 50 + static int bd70528_set_wake(struct rohm_regmap_dev *bd70528, 51 51 + int enable, int *old_state) 52 52 + { 53 53 + int ret; 54 54 + unsigned int ctrl_reg; 55 55 + 56 56 + ret = regmap_read(bd70528->regmap, BD70528_REG_WAKE_EN, &ctrl_reg); 57 57 + if (ret) 58 58 + return ret; 59 59 + 60 60 + if (old_state) { 61 61 + if (ctrl_reg & BD70528_MASK_WAKE_EN) 62 62 + *old_state |= BD70528_WAKE_STATE_BIT; 63 63 + else 64 64 + *old_state &= ~BD70528_WAKE_STATE_BIT; 65 65 + 66 66 + if (!enable == !(*old_state & BD70528_WAKE_STATE_BIT)) 67 67 + return 0; 68 68 + } 69 69 + 70 70 + if (enable) 71 71 + ctrl_reg |= BD70528_MASK_WAKE_EN; 72 72 + else 73 73 + ctrl_reg &= ~BD70528_MASK_WAKE_EN; 74 74 + 75 75 + return regmap_write(bd70528->regmap, BD70528_REG_WAKE_EN, 76 76 + ctrl_reg); 77 77 + } 78 78 + 79 79 + static int bd70528_set_elapsed_tmr(struct rohm_regmap_dev *bd70528, 80 80 + int enable, int *old_state) 81 81 + { 82 82 + int ret; 83 83 + unsigned int ctrl_reg; 84 84 + 85 85 + /* 86 86 + * TBD 87 87 + * What is the purpose of elapsed timer ? 88 88 + * Is the timeout registers counting down, or is the disable - re-enable 89 89 + * going to restart the elapsed-time counting? If counting is restarted 90 90 + * the timeout should be decreased by the amount of time that has 91 91 + * elapsed since starting the timer. Maybe we should store the monotonic 92 92 + * clock value when timer is started so that if RTC is set while timer 93 93 + * is armed we could do the compensation. This is a hack if RTC/system 94 94 + * clk are drifting. OTOH, RTC controlled via I2C is in any case 95 95 + * inaccurate... 96 96 + */ 97 97 + ret = regmap_read(bd70528->regmap, BD70528_REG_ELAPSED_TIMER_EN, 98 98 + &ctrl_reg); 99 99 + if (ret) 100 100 + return ret; 101 101 + 102 102 + if (old_state) { 103 103 + if (ctrl_reg & BD70528_MASK_ELAPSED_TIMER_EN) 104 104 + *old_state |= BD70528_ELAPSED_STATE_BIT; 105 105 + else 106 106 + *old_state &= ~BD70528_ELAPSED_STATE_BIT; 107 107 + 108 108 + if ((!enable) == (!(*old_state & BD70528_ELAPSED_STATE_BIT))) 109 109 + return 0; 110 110 + } 111 111 + 112 112 + if (enable) 113 113 + ctrl_reg |= BD70528_MASK_ELAPSED_TIMER_EN; 114 114 + else 115 115 + ctrl_reg &= ~BD70528_MASK_ELAPSED_TIMER_EN; 116 116 + 117 117 + return regmap_write(bd70528->regmap, BD70528_REG_ELAPSED_TIMER_EN, 118 118 + ctrl_reg); 119 119 + } 120 120 + 121 121 + static int bd70528_set_rtc_based_timers(struct bd70528_rtc *r, int new_state, 122 122 + int *old_state) 123 123 + { 124 124 + int ret; 125 125 + 126 126 + ret = bd70528_wdt_set(r->mfd, new_state & BD70528_WDT_STATE_BIT, 127 127 + old_state); 128 128 + if (ret) { 129 129 + dev_err(r->dev, 130 130 + "Failed to disable WDG for RTC setting (%d)\n", ret); 131 131 + return ret; 132 132 + } 133 133 + ret = bd70528_set_elapsed_tmr(r->mfd, 134 134 + new_state & BD70528_ELAPSED_STATE_BIT, 135 135 + old_state); 136 136 + if (ret) { 137 137 + dev_err(r->dev, 138 138 + "Failed to disable 'elapsed timer' for RTC setting\n"); 139 139 + return ret; 140 140 + } 141 141 + ret = bd70528_set_wake(r->mfd, new_state & BD70528_WAKE_STATE_BIT, 142 142 + old_state); 143 143 + if (ret) { 144 144 + dev_err(r->dev, 145 145 + "Failed to disable 'wake timer' for RTC setting\n"); 146 146 + return ret; 147 147 + } 148 148 + 149 149 + return ret; 150 150 + } 151 151 + 152 152 + static int bd70528_re_enable_rtc_based_timers(struct bd70528_rtc *r, 153 153 + int old_state) 154 154 + { 155 155 + return bd70528_set_rtc_based_timers(r, old_state, NULL); 156 156 + } 157 157 + 158 158 + static int bd70528_disable_rtc_based_timers(struct bd70528_rtc *r, 159 159 + int *old_state) 160 160 + { 161 161 + return bd70528_set_rtc_based_timers(r, 0, old_state); 162 162 + } 163 163 + 164 164 + static inline void tmday2rtc(struct rtc_time *t, struct bd70528_rtc_day *d) 165 165 + { 166 166 + d->sec &= ~BD70528_MASK_RTC_SEC; 167 167 + d->min &= ~BD70528_MASK_RTC_MINUTE; 168 168 + d->hour &= ~BD70528_MASK_RTC_HOUR; 169 169 + d->sec |= bin2bcd(t->tm_sec); 170 170 + d->min |= bin2bcd(t->tm_min); 171 171 + d->hour |= bin2bcd(t->tm_hour); 172 172 + } 173 173 + 174 174 + static inline void tm2rtc(struct rtc_time *t, struct bd70528_rtc_data *r) 175 175 + { 176 176 + r->day &= ~BD70528_MASK_RTC_DAY; 177 177 + r->week &= ~BD70528_MASK_RTC_WEEK; 178 178 + r->month &= ~BD70528_MASK_RTC_MONTH; 179 179 + /* 180 180 + * PM and 24H bits are not used by Wake - thus we clear them 181 181 + * here and not in tmday2rtc() which is also used by wake. 182 182 + */ 183 183 + r->time.hour &= ~(BD70528_MASK_RTC_HOUR_PM | BD70528_MASK_RTC_HOUR_24H); 184 184 + 185 185 + tmday2rtc(t, &r->time); 186 186 + /* 187 187 + * We do always set time in 24H mode. 188 188 + */ 189 189 + r->time.hour |= BD70528_MASK_RTC_HOUR_24H; 190 190 + r->day |= bin2bcd(t->tm_mday); 191 191 + r->week |= bin2bcd(t->tm_wday); 192 192 + r->month |= bin2bcd(t->tm_mon + 1); 193 193 + r->year = bin2bcd(t->tm_year - 100); 194 194 + } 195 195 + 196 196 + static inline void rtc2tm(struct bd70528_rtc_data *r, struct rtc_time *t) 197 197 + { 198 198 + t->tm_sec = bcd2bin(r->time.sec & BD70528_MASK_RTC_SEC); 199 199 + t->tm_min = bcd2bin(r->time.min & BD70528_MASK_RTC_MINUTE); 200 200 + t->tm_hour = bcd2bin(r->time.hour & BD70528_MASK_RTC_HOUR); 201 201 + /* 202 202 + * If RTC is in 12H mode, then bit BD70528_MASK_RTC_HOUR_PM 203 203 + * is not BCD value but tells whether it is AM or PM 204 204 + */ 205 205 + if (!(r->time.hour & BD70528_MASK_RTC_HOUR_24H)) { 206 206 + t->tm_hour %= 12; 207 207 + if (r->time.hour & BD70528_MASK_RTC_HOUR_PM) 208 208 + t->tm_hour += 12; 209 209 + } 210 210 + t->tm_mday = bcd2bin(r->day & BD70528_MASK_RTC_DAY); 211 211 + t->tm_mon = bcd2bin(r->month & BD70528_MASK_RTC_MONTH) - 1; 212 212 + t->tm_year = 100 + bcd2bin(r->year & BD70528_MASK_RTC_YEAR); 213 213 + t->tm_wday = bcd2bin(r->week & BD70528_MASK_RTC_WEEK); 214 214 + } 215 215 + 216 216 + static int bd70528_set_alarm(struct device *dev, struct rtc_wkalrm *a) 217 217 + { 218 218 + struct bd70528_rtc_wake wake; 219 219 + struct bd70528_rtc_alm alm; 220 220 + int ret; 221 221 + struct bd70528_rtc *r = dev_get_drvdata(dev); 222 222 + struct rohm_regmap_dev *bd70528 = r->mfd; 223 223 + 224 224 + ret = regmap_bulk_read(bd70528->regmap, BD70528_REG_RTC_WAKE_START, 225 225 + &wake, sizeof(wake)); 226 226 + if (ret) { 227 227 + dev_err(dev, "Failed to read wake regs\n"); 228 228 + return ret; 229 229 + } 230 230 + 231 231 + ret = regmap_bulk_read(bd70528->regmap, BD70528_REG_RTC_ALM_START, 232 232 + &alm, sizeof(alm)); 233 233 + if (ret) { 234 234 + dev_err(dev, "Failed to read alarm regs\n"); 235 235 + return ret; 236 236 + } 237 237 + 238 238 + tm2rtc(&a->time, &alm.data); 239 239 + tmday2rtc(&a->time, &wake.time); 240 240 + 241 241 + if (a->enabled) { 242 242 + alm.alm_mask &= ~BD70528_MASK_ALM_EN; 243 243 + wake.ctrl |= BD70528_MASK_WAKE_EN; 244 244 + } else { 245 245 + alm.alm_mask |= BD70528_MASK_ALM_EN; 246 246 + wake.ctrl &= ~BD70528_MASK_WAKE_EN; 247 247 + } 248 248 + 249 249 + ret = regmap_bulk_write(bd70528->regmap, 250 250 + BD70528_REG_RTC_WAKE_START, &wake, 251 251 + sizeof(wake)); 252 252 + if (ret) { 253 253 + dev_err(dev, "Failed to set wake time\n"); 254 254 + return ret; 255 255 + } 256 256 + ret = regmap_bulk_write(bd70528->regmap, BD70528_REG_RTC_ALM_START, 257 257 + &alm, sizeof(alm)); 258 258 + if (ret) 259 259 + dev_err(dev, "Failed to set alarm time\n"); 260 260 + 261 261 + return ret; 262 262 + } 263 263 + 264 264 + static int bd70528_read_alarm(struct device *dev, struct rtc_wkalrm *a) 265 265 + { 266 266 + struct bd70528_rtc_alm alm; 267 267 + int ret; 268 268 + struct bd70528_rtc *r = dev_get_drvdata(dev); 269 269 + struct rohm_regmap_dev *bd70528 = r->mfd; 270 270 + 271 271 + ret = regmap_bulk_read(bd70528->regmap, BD70528_REG_RTC_ALM_START, 272 272 + &alm, sizeof(alm)); 273 273 + if (ret) { 274 274 + dev_err(dev, "Failed to read alarm regs\n"); 275 275 + return ret; 276 276 + } 277 277 + 278 278 + rtc2tm(&alm.data, &a->time); 279 279 + a->time.tm_mday = -1; 280 280 + a->time.tm_mon = -1; 281 281 + a->time.tm_year = -1; 282 282 + a->enabled = !(alm.alm_mask & BD70528_MASK_ALM_EN); 283 283 + a->pending = 0; 284 284 + 285 285 + return 0; 286 286 + } 287 287 + 288 288 + static int bd70528_set_time_locked(struct device *dev, struct rtc_time *t) 289 289 + { 290 290 + int ret, tmpret, old_states; 291 291 + struct bd70528_rtc_data rtc_data; 292 292 + struct bd70528_rtc *r = dev_get_drvdata(dev); 293 293 + struct rohm_regmap_dev *bd70528 = r->mfd; 294 294 + 295 295 + ret = bd70528_disable_rtc_based_timers(r, &old_states); 296 296 + if (ret) 297 297 + return ret; 298 298 + 299 299 + tmpret = regmap_bulk_read(bd70528->regmap, 300 300 + BD70528_REG_RTC_START, &rtc_data, 301 301 + sizeof(rtc_data)); 302 302 + if (tmpret) { 303 303 + dev_err(dev, "Failed to read RTC time registers\n"); 304 304 + goto renable_out; 305 305 + } 306 306 + tm2rtc(t, &rtc_data); 307 307 + 308 308 + tmpret = regmap_bulk_write(bd70528->regmap, 309 309 + BD70528_REG_RTC_START, &rtc_data, 310 310 + sizeof(rtc_data)); 311 311 + if (tmpret) { 312 312 + dev_err(dev, "Failed to set RTC time\n"); 313 313 + goto renable_out; 314 314 + } 315 315 + 316 316 + renable_out: 317 317 + ret = bd70528_re_enable_rtc_based_timers(r, old_states); 318 318 + if (tmpret) 319 319 + ret = tmpret; 320 320 + 321 321 + return ret; 322 322 + } 323 323 + 324 324 + static int bd70528_set_time(struct device *dev, struct rtc_time *t) 325 325 + { 326 326 + int ret; 327 327 + struct bd70528_rtc *r = dev_get_drvdata(dev); 328 328 + 329 329 + bd70528_wdt_lock(r->mfd); 330 330 + ret = bd70528_set_time_locked(dev, t); 331 331 + bd70528_wdt_unlock(r->mfd); 332 332 + return ret; 333 333 + } 334 334 + 335 335 + static int bd70528_get_time(struct device *dev, struct rtc_time *t) 336 336 + { 337 337 + struct bd70528_rtc *r = dev_get_drvdata(dev); 338 338 + struct rohm_regmap_dev *bd70528 = r->mfd; 339 339 + struct bd70528_rtc_data rtc_data; 340 340 + int ret; 341 341 + 342 342 + /* read the RTC date and time registers all at once */ 343 343 + ret = regmap_bulk_read(bd70528->regmap, 344 344 + BD70528_REG_RTC_START, &rtc_data, 345 345 + sizeof(rtc_data)); 346 346 + if (ret) { 347 347 + dev_err(dev, "Failed to read RTC time (err %d)\n", ret); 348 348 + return ret; 349 349 + } 350 350 + 351 351 + rtc2tm(&rtc_data, t); 352 352 + 353 353 + return 0; 354 354 + } 355 355 + 356 356 + static int bd70528_alm_enable(struct device *dev, unsigned int enabled) 357 357 + { 358 358 + int ret; 359 359 + unsigned int enableval = BD70528_MASK_ALM_EN; 360 360 + struct bd70528_rtc *r = dev_get_drvdata(dev); 361 361 + 362 362 + if (enabled) 363 363 + enableval = 0; 364 364 + 365 365 + bd70528_wdt_lock(r->mfd); 366 366 + ret = bd70528_set_wake(r->mfd, enabled, NULL); 367 367 + if (ret) { 368 368 + dev_err(dev, "Failed to change wake state\n"); 369 369 + goto out_unlock; 370 370 + } 371 371 + ret = regmap_update_bits(r->mfd->regmap, BD70528_REG_RTC_ALM_MASK, 372 372 + BD70528_MASK_ALM_EN, enableval); 373 373 + if (ret) 374 374 + dev_err(dev, "Failed to change alarm state\n"); 375 375 + 376 376 + out_unlock: 377 377 + bd70528_wdt_unlock(r->mfd); 378 378 + return ret; 379 379 + } 380 380 + 381 381 + static const struct rtc_class_ops bd70528_rtc_ops = { 382 382 + .read_time = bd70528_get_time, 383 383 + .set_time = bd70528_set_time, 384 384 + .read_alarm = bd70528_read_alarm, 385 385 + .set_alarm = bd70528_set_alarm, 386 386 + .alarm_irq_enable = bd70528_alm_enable, 387 387 + }; 388 388 + 389 389 + static irqreturn_t alm_hndlr(int irq, void *data) 390 390 + { 391 391 + struct rtc_device *rtc = data; 392 392 + 393 393 + rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF | RTC_PF); 394 394 + return IRQ_HANDLED; 395 395 + } 396 396 + 397 397 + static int bd70528_probe(struct platform_device *pdev) 398 398 + { 399 399 + struct bd70528_rtc *bd_rtc; 400 400 + struct rohm_regmap_dev *mfd; 401 401 + int ret; 402 402 + struct rtc_device *rtc; 403 403 + int irq; 404 404 + unsigned int hr; 405 405 + 406 406 + mfd = dev_get_drvdata(pdev->dev.parent); 407 407 + if (!mfd) { 408 408 + dev_err(&pdev->dev, "No MFD driver data\n"); 409 409 + return -EINVAL; 410 410 + } 411 411 + bd_rtc = devm_kzalloc(&pdev->dev, sizeof(*bd_rtc), GFP_KERNEL); 412 412 + if (!bd_rtc) 413 413 + return -ENOMEM; 414 414 + 415 415 + bd_rtc->mfd = mfd; 416 416 + bd_rtc->dev = &pdev->dev; 417 417 + 418 418 + irq = platform_get_irq_byname(pdev, "bd70528-rtc-alm"); 419 419 + 420 420 + if (irq < 0) { 421 421 + dev_err(&pdev->dev, "Failed to get irq\n"); 422 422 + return irq; 423 423 + } 424 424 + 425 425 + platform_set_drvdata(pdev, bd_rtc); 426 426 + 427 427 + ret = regmap_read(mfd->regmap, BD70528_REG_RTC_HOUR, &hr); 428 428 + 429 429 + if (ret) { 430 430 + dev_err(&pdev->dev, "Failed to reag RTC clock\n"); 431 431 + return ret; 432 432 + } 433 433 + 434 434 + if (!(hr & BD70528_MASK_RTC_HOUR_24H)) { 435 435 + struct rtc_time t; 436 436 + 437 437 + ret = bd70528_get_time(&pdev->dev, &t); 438 438 + 439 439 + if (!ret) 440 440 + ret = bd70528_set_time(&pdev->dev, &t); 441 441 + 442 442 + if (ret) { 443 443 + dev_err(&pdev->dev, 444 444 + "Setting 24H clock for RTC failed\n"); 445 445 + return ret; 446 446 + } 447 447 + } 448 448 + 449 449 + device_set_wakeup_capable(&pdev->dev, true); 450 450 + device_wakeup_enable(&pdev->dev); 451 451 + 452 452 + rtc = devm_rtc_allocate_device(&pdev->dev); 453 453 + if (IS_ERR(rtc)) { 454 454 + dev_err(&pdev->dev, "RTC device creation failed\n"); 455 455 + return PTR_ERR(rtc); 456 456 + } 457 457 + 458 458 + rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 459 459 + rtc->range_max = RTC_TIMESTAMP_END_2099; 460 460 + rtc->ops = &bd70528_rtc_ops; 461 461 + 462 462 + /* Request alarm IRQ prior to registerig the RTC */ 463 463 + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, &alm_hndlr, 464 464 + IRQF_ONESHOT, "bd70528-rtc", rtc); 465 465 + if (ret) 466 466 + return ret; 467 467 + 468 468 + /* 469 469 + * BD70528 irq controller is not touching the main mask register. 470 470 + * So enable the RTC block interrupts at main level. We can just 471 471 + * leave them enabled as irq-controller should disable irqs 472 472 + * from sub-registers when IRQ is disabled or freed. 473 473 + */ 474 474 + ret = regmap_update_bits(mfd->regmap, 475 475 + BD70528_REG_INT_MAIN_MASK, 476 476 + BD70528_INT_RTC_MASK, 0); 477 477 + if (ret) { 478 478 + dev_err(&pdev->dev, "Failed to enable RTC interrupts\n"); 479 479 + return ret; 480 480 + } 481 481 + 482 482 + ret = rtc_register_device(rtc); 483 483 + if (ret) 484 484 + dev_err(&pdev->dev, "Registering RTC failed\n"); 485 485 + 486 486 + return ret; 487 487 + } 488 488 + 489 489 + static struct platform_driver bd70528_rtc = { 490 490 + .driver = { 491 491 + .name = "bd70528-rtc" 492 492 + }, 493 493 + .probe = bd70528_probe, 494 494 + }; 495 495 + 496 496 + module_platform_driver(bd70528_rtc); 497 497 + 498 498 + MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 499 499 + MODULE_DESCRIPTION("BD70528 RTC driver"); 500 500 + MODULE_LICENSE("GPL");

+54 -14

drivers/rtc/rtc-rk808.c

reviewed

··· 42 42 #define NUM_TIME_REGS (RK808_WEEKS_REG - RK808_SECONDS_REG + 1) 43 43 #define NUM_ALARM_REGS (RK808_ALARM_YEARS_REG - RK808_ALARM_SECONDS_REG + 1) 44 44 45 45 + struct rk_rtc_compat_reg { 46 46 + unsigned int ctrl_reg; 47 47 + unsigned int status_reg; 48 48 + unsigned int alarm_seconds_reg; 49 49 + unsigned int int_reg; 50 50 + unsigned int seconds_reg; 51 51 + }; 52 52 + 45 53 struct rk808_rtc { 46 54 struct rk808 *rk808; 47 55 struct rtc_device *rtc; 56 56 + struct rk_rtc_compat_reg *creg; 48 57 int irq; 49 58 }; 50 59 ··· 102 93 int ret; 103 94 104 95 /* Force an update of the shadowed registers right now */ 105 105 - ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG, 96 96 + ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg, 106 97 BIT_RTC_CTRL_REG_RTC_GET_TIME, 107 98 BIT_RTC_CTRL_REG_RTC_GET_TIME); 108 99 if (ret) { ··· 116 107 * 32khz. If we clear the GET_TIME bit here, the time of i2c transfer 117 108 * certainly more than 31.25us: 16 * 2.5us at 400kHz bus frequency. 118 109 */ 119 119 - ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG, 110 110 + ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg, 120 111 BIT_RTC_CTRL_REG_RTC_GET_TIME, 121 112 0); 122 113 if (ret) { ··· 124 115 return ret; 125 116 } 126 117 127 127 - ret = regmap_bulk_read(rk808->regmap, RK808_SECONDS_REG, 118 118 + ret = regmap_bulk_read(rk808->regmap, rk808_rtc->creg->seconds_reg, 128 119 rtc_data, NUM_TIME_REGS); 129 120 if (ret) { 130 121 dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret); ··· 163 154 rtc_data[6] = bin2bcd(tm->tm_wday); 164 155 165 156 /* Stop RTC while updating the RTC registers */ 166 166 - ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG, 157 157 + ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg, 167 158 BIT_RTC_CTRL_REG_STOP_RTC_M, 168 159 BIT_RTC_CTRL_REG_STOP_RTC_M); 169 160 if (ret) { ··· 171 162 return ret; 172 163 } 173 164 174 174 - ret = regmap_bulk_write(rk808->regmap, RK808_SECONDS_REG, 165 165 + ret = regmap_bulk_write(rk808->regmap, rk808_rtc->creg->seconds_reg, 175 166 rtc_data, NUM_TIME_REGS); 176 167 if (ret) { 177 168 dev_err(dev, "Failed to bull write rtc_data: %d\n", ret); 178 169 return ret; 179 170 } 180 171 /* Start RTC again */ 181 181 - ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG, 172 172 + ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg, 182 173 BIT_RTC_CTRL_REG_STOP_RTC_M, 0); 183 174 if (ret) { 184 175 dev_err(dev, "Failed to update RTC control: %d\n", ret); ··· 196 187 uint32_t int_reg; 197 188 int ret; 198 189 199 199 - ret = regmap_bulk_read(rk808->regmap, RK808_ALARM_SECONDS_REG, 190 190 + ret = regmap_bulk_read(rk808->regmap, 191 191 + rk808_rtc->creg->alarm_seconds_reg, 200 192 alrm_data, NUM_ALARM_REGS); 193 193 + if (ret) { 194 194 + dev_err(dev, "Failed to read RTC alarm date REG: %d\n", ret); 195 195 + return ret; 196 196 + } 201 197 202 198 alrm->time.tm_sec = bcd2bin(alrm_data[0] & SECONDS_REG_MSK); 203 199 alrm->time.tm_min = bcd2bin(alrm_data[1] & MINUTES_REG_MAK); ··· 212 198 alrm->time.tm_year = (bcd2bin(alrm_data[5] & YEARS_REG_MSK)) + 100; 213 199 rockchip_to_gregorian(&alrm->time); 214 200 215 215 - ret = regmap_read(rk808->regmap, RK808_RTC_INT_REG, &int_reg); 201 201 + ret = regmap_read(rk808->regmap, rk808_rtc->creg->int_reg, &int_reg); 216 202 if (ret) { 217 203 dev_err(dev, "Failed to read RTC INT REG: %d\n", ret); 218 204 return ret; ··· 231 217 struct rk808 *rk808 = rk808_rtc->rk808; 232 218 int ret; 233 219 234 234 - ret = regmap_update_bits(rk808->regmap, RK808_RTC_INT_REG, 220 220 + ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->int_reg, 235 221 BIT_RTC_INTERRUPTS_REG_IT_ALARM_M, 0); 236 222 237 223 return ret; ··· 242 228 struct rk808 *rk808 = rk808_rtc->rk808; 243 229 int ret; 244 230 245 245 - ret = regmap_update_bits(rk808->regmap, RK808_RTC_INT_REG, 231 231 + ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->int_reg, 246 232 BIT_RTC_INTERRUPTS_REG_IT_ALARM_M, 247 233 BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); 248 234 ··· 272 258 alrm_data[4] = bin2bcd(alrm->time.tm_mon + 1); 273 259 alrm_data[5] = bin2bcd(alrm->time.tm_year - 100); 274 260 275 275 - ret = regmap_bulk_write(rk808->regmap, RK808_ALARM_SECONDS_REG, 261 261 + ret = regmap_bulk_write(rk808->regmap, 262 262 + rk808_rtc->creg->alarm_seconds_reg, 276 263 alrm_data, NUM_ALARM_REGS); 277 264 if (ret) { 278 265 dev_err(dev, "Failed to bulk write: %d\n", ret); ··· 317 302 struct i2c_client *client = rk808->i2c; 318 303 int ret; 319 304 320 320 - ret = regmap_write(rk808->regmap, RK808_RTC_STATUS_REG, 305 305 + ret = regmap_write(rk808->regmap, rk808_rtc->creg->status_reg, 321 306 RTC_STATUS_MASK); 322 307 if (ret) { 323 308 dev_err(&client->dev, ··· 368 353 static SIMPLE_DEV_PM_OPS(rk808_rtc_pm_ops, 369 354 rk808_rtc_suspend, rk808_rtc_resume); 370 355 356 356 + static struct rk_rtc_compat_reg rk808_creg = { 357 357 + .ctrl_reg = RK808_RTC_CTRL_REG, 358 358 + .status_reg = RK808_RTC_STATUS_REG, 359 359 + .alarm_seconds_reg = RK808_ALARM_SECONDS_REG, 360 360 + .int_reg = RK808_RTC_INT_REG, 361 361 + .seconds_reg = RK808_SECONDS_REG, 362 362 + }; 363 363 + 364 364 + static struct rk_rtc_compat_reg rk817_creg = { 365 365 + .ctrl_reg = RK817_RTC_CTRL_REG, 366 366 + .status_reg = RK817_RTC_STATUS_REG, 367 367 + .alarm_seconds_reg = RK817_ALARM_SECONDS_REG, 368 368 + .int_reg = RK817_RTC_INT_REG, 369 369 + .seconds_reg = RK817_SECONDS_REG, 370 370 + }; 371 371 + 371 372 static int rk808_rtc_probe(struct platform_device *pdev) 372 373 { 373 374 struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent); ··· 394 363 if (rk808_rtc == NULL) 395 364 return -ENOMEM; 396 365 366 366 + switch (rk808->variant) { 367 367 + case RK809_ID: 368 368 + case RK817_ID: 369 369 + rk808_rtc->creg = &rk817_creg; 370 370 + break; 371 371 + default: 372 372 + rk808_rtc->creg = &rk808_creg; 373 373 + break; 374 374 + } 397 375 platform_set_drvdata(pdev, rk808_rtc); 398 376 rk808_rtc->rk808 = rk808; 399 377 400 378 /* start rtc running by default, and use shadowed timer. */ 401 401 - ret = regmap_update_bits(rk808->regmap, RK808_RTC_CTRL_REG, 379 379 + ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg, 402 380 BIT_RTC_CTRL_REG_STOP_RTC_M | 403 381 BIT_RTC_CTRL_REG_RTC_READSEL_M, 404 382 BIT_RTC_CTRL_REG_RTC_READSEL_M); ··· 417 377 return ret; 418 378 } 419 379 420 420 - ret = regmap_write(rk808->regmap, RK808_RTC_STATUS_REG, 380 380 + ret = regmap_write(rk808->regmap, rk808_rtc->creg->status_reg, 421 381 RTC_STATUS_MASK); 422 382 if (ret) { 423 383 dev_err(&pdev->dev,

+1

include/linux/mfd/cros_ec.h

reviewed

··· 19 19 #define CROS_EC_DEV_PD_NAME "cros_pd" 20 20 #define CROS_EC_DEV_TP_NAME "cros_tp" 21 21 #define CROS_EC_DEV_ISH_NAME "cros_ish" 22 22 + #define CROS_EC_DEV_SCP_NAME "cros_scp" 22 23 23 24 /* 24 25 * The EC is unresponsive for a time after a reboot command. Add a

+2

include/linux/mfd/lp87565.h

reviewed

··· 14 14 15 15 enum lp87565_device_type { 16 16 LP87565_DEVICE_TYPE_UNKNOWN = 0, 17 17 + LP87565_DEVICE_TYPE_LP87561_Q1, 17 18 LP87565_DEVICE_TYPE_LP87565_Q1, 18 19 }; 19 20 ··· 247 246 LP87565_BUCK_3, 248 247 LP87565_BUCK_10, 249 248 LP87565_BUCK_23, 249 249 + LP87565_BUCK_3210, 250 250 }; 251 251 252 252 /**

+7 -5

include/linux/mfd/madera/core.h

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 1 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 2 /* 3 3 * MFD internals for Cirrus Logic Madera codecs 4 4 * 5 5 * Copyright (C) 2015-2018 Cirrus Logic 6 6 - * 7 7 - * This program is free software; you can redistribute it and/or modify 8 8 - * it under the terms of the GNU General Public License as published by the 9 9 - * Free Software Foundation; version 2. 10 6 */ 11 7 12 8 #ifndef MADERA_CORE_H ··· 22 26 CS47L85 = 2, 23 27 CS47L90 = 3, 24 28 CS47L91 = 4, 29 29 + CS47L92 = 5, 30 30 + CS47L93 = 6, 25 31 WM1840 = 7, 32 32 + CS47L15 = 8, 33 33 + CS42L92 = 9, 26 34 }; 27 35 28 36 #define MADERA_MAX_CORE_SUPPLIES 2 29 37 #define MADERA_MAX_GPIOS 40 30 38 39 39 + #define CS47L15_NUM_GPIOS 15 31 40 #define CS47L35_NUM_GPIOS 16 32 41 #define CS47L85_NUM_GPIOS 40 33 42 #define CS47L90_NUM_GPIOS 38 43 43 + #define CS47L92_NUM_GPIOS 16 34 44 35 45 #define MADERA_MAX_MICBIAS 4 36 46

+3 -6

include/linux/mfd/madera/pdata.h

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 1 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 2 /* 3 3 * Platform data for Cirrus Logic Madera codecs 4 4 * 5 5 * Copyright (C) 2015-2018 Cirrus Logic 6 6 - * 7 7 - * This program is free software; you can redistribute it and/or modify 8 8 - * it under the terms of the GNU General Public License as published by the 9 9 - * Free Software Foundation; version 2. 10 6 */ 11 7 12 8 #ifndef MADERA_PDATA_H ··· 31 35 * @micvdd: Substruct of pdata for the MICVDD regulator 32 36 * @irq_flags: Mode for primary IRQ (defaults to active low) 33 37 * @gpio_base: Base GPIO number 34 34 - * @gpio_configs: Array of GPIO configurations (See Documentation/pinctrl.txt) 38 38 + * @gpio_configs: Array of GPIO configurations (See 39 39 + * Documentation/driver-api/pinctl.rst) 35 40 * @n_gpio_configs: Number of entries in gpio_configs 36 41 * @gpsw: General purpose switch mode setting. Depends on the external 37 42 * hardware connected to the switch. (See the SW1_MODE field

+201 -85

include/linux/mfd/madera/registers.h

reviewed

··· 1 1 - // SPDX-License-Identifier: GPL-2.0 1 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 2 /* 3 3 * Madera register definitions 4 4 * 5 5 * Copyright (C) 2015-2018 Cirrus Logic 6 6 - * 7 7 - * This program is free software; you can redistribute it and/or modify 8 8 - * it under the terms of the GNU General Public License as published by the 9 9 - * Free Software Foundation; version 2. 10 6 */ 11 7 12 8 #ifndef MADERA_REGISTERS_H ··· 72 76 #define MADERA_FLL1_CONTROL_4 0x174 73 77 #define MADERA_FLL1_CONTROL_5 0x175 74 78 #define MADERA_FLL1_CONTROL_6 0x176 75 75 - #define MADERA_FLL1_LOOP_FILTER_TEST_1 0x177 76 76 - #define MADERA_FLL1_NCO_TEST_0 0x178 79 79 + #define CS47L92_FLL1_CONTROL_7 0x177 80 80 + #define CS47L92_FLL1_CONTROL_8 0x178 77 81 #define MADERA_FLL1_CONTROL_7 0x179 82 82 + #define CS47L92_FLL1_CONTROL_9 0x179 78 83 #define MADERA_FLL1_EFS_2 0x17A 84 84 + #define CS47L92_FLL1_CONTROL_10 0x17A 85 85 + #define MADERA_FLL1_CONTROL_11 0x17B 86 86 + #define MADERA_FLL1_DIGITAL_TEST_1 0x17D 79 87 #define CS47L35_FLL1_SYNCHRONISER_1 0x17F 80 88 #define CS47L35_FLL1_SYNCHRONISER_2 0x180 81 89 #define CS47L35_FLL1_SYNCHRONISER_3 0x181 ··· 98 98 #define MADERA_FLL1_SYNCHRONISER_7 0x187 99 99 #define MADERA_FLL1_SPREAD_SPECTRUM 0x189 100 100 #define MADERA_FLL1_GPIO_CLOCK 0x18A 101 101 + #define CS47L92_FLL1_GPIO_CLOCK 0x18E 101 102 #define MADERA_FLL2_CONTROL_1 0x191 102 103 #define MADERA_FLL2_CONTROL_2 0x192 103 104 #define MADERA_FLL2_CONTROL_3 0x193 104 105 #define MADERA_FLL2_CONTROL_4 0x194 105 106 #define MADERA_FLL2_CONTROL_5 0x195 106 107 #define MADERA_FLL2_CONTROL_6 0x196 107 107 - #define MADERA_FLL2_LOOP_FILTER_TEST_1 0x197 108 108 - #define MADERA_FLL2_NCO_TEST_0 0x198 108 108 + #define CS47L92_FLL2_CONTROL_7 0x197 109 109 + #define CS47L92_FLL2_CONTROL_8 0x198 109 110 #define MADERA_FLL2_CONTROL_7 0x199 111 111 + #define CS47L92_FLL2_CONTROL_9 0x199 110 112 #define MADERA_FLL2_EFS_2 0x19A 113 113 + #define CS47L92_FLL2_CONTROL_10 0x19A 114 114 + #define MADERA_FLL2_CONTROL_11 0x19B 115 115 + #define MADERA_FLL2_DIGITAL_TEST_1 0x19D 111 116 #define MADERA_FLL2_SYNCHRONISER_1 0x1A1 112 117 #define MADERA_FLL2_SYNCHRONISER_2 0x1A2 113 118 #define MADERA_FLL2_SYNCHRONISER_3 0x1A3 ··· 122 117 #define MADERA_FLL2_SYNCHRONISER_7 0x1A7 123 118 #define MADERA_FLL2_SPREAD_SPECTRUM 0x1A9 124 119 #define MADERA_FLL2_GPIO_CLOCK 0x1AA 120 120 + #define CS47L92_FLL2_GPIO_CLOCK 0x1AE 125 121 #define MADERA_FLL3_CONTROL_1 0x1B1 126 122 #define MADERA_FLL3_CONTROL_2 0x1B2 127 123 #define MADERA_FLL3_CONTROL_3 0x1B3 128 124 #define MADERA_FLL3_CONTROL_4 0x1B4 129 125 #define MADERA_FLL3_CONTROL_5 0x1B5 130 126 #define MADERA_FLL3_CONTROL_6 0x1B6 131 131 - #define MADERA_FLL3_LOOP_FILTER_TEST_1 0x1B7 132 132 - #define MADERA_FLL3_NCO_TEST_0 0x1B8 133 127 #define MADERA_FLL3_CONTROL_7 0x1B9 134 128 #define MADERA_FLL3_SYNCHRONISER_1 0x1C1 135 129 #define MADERA_FLL3_SYNCHRONISER_2 0x1C2 ··· 248 244 #define MADERA_IN6R_CONTROL 0x33C 249 245 #define MADERA_ADC_DIGITAL_VOLUME_6R 0x33D 250 246 #define MADERA_DMIC6R_CONTROL 0x33E 247 247 + #define CS47L15_ADC_INT_BIAS 0x3A8 248 248 + #define CS47L15_PGA_BIAS_SEL 0x3C4 251 249 #define MADERA_OUTPUT_ENABLES_1 0x400 252 250 #define MADERA_OUTPUT_STATUS_1 0x401 253 251 #define MADERA_RAW_OUTPUT_STATUS_1 0x406 ··· 271 265 #define MADERA_NOISE_GATE_SELECT_2R 0x41F 272 266 #define MADERA_OUTPUT_PATH_CONFIG_3L 0x420 273 267 #define MADERA_DAC_DIGITAL_VOLUME_3L 0x421 268 268 + #define MADERA_OUTPUT_PATH_CONFIG_3 0x422 274 269 #define MADERA_NOISE_GATE_SELECT_3L 0x423 275 270 #define MADERA_OUTPUT_PATH_CONFIG_3R 0x424 276 271 #define MADERA_DAC_DIGITAL_VOLUME_3R 0x425 ··· 294 287 #define MADERA_OUTPUT_PATH_CONFIG_6R 0x43C 295 288 #define MADERA_DAC_DIGITAL_VOLUME_6R 0x43D 296 289 #define MADERA_NOISE_GATE_SELECT_6R 0x43F 297 297 - #define MADERA_DRE_ENABLE 0x440 298 298 - #define MADERA_EDRE_ENABLE 0x448 299 299 - #define MADERA_EDRE_MANUAL 0x44A 300 290 #define MADERA_DAC_AEC_CONTROL_1 0x450 301 291 #define MADERA_DAC_AEC_CONTROL_2 0x451 302 292 #define MADERA_NOISE_GATE_CONTROL 0x458 ··· 371 367 #define MADERA_AIF3_FRAME_CTRL_2 0x588 372 368 #define MADERA_AIF3_FRAME_CTRL_3 0x589 373 369 #define MADERA_AIF3_FRAME_CTRL_4 0x58A 370 370 + #define MADERA_AIF3_FRAME_CTRL_5 0x58B 371 371 + #define MADERA_AIF3_FRAME_CTRL_6 0x58C 372 372 + #define MADERA_AIF3_FRAME_CTRL_7 0x58D 373 373 + #define MADERA_AIF3_FRAME_CTRL_8 0x58E 374 374 + #define MADERA_AIF3_FRAME_CTRL_9 0x58F 375 375 + #define MADERA_AIF3_FRAME_CTRL_10 0x590 374 376 #define MADERA_AIF3_FRAME_CTRL_11 0x591 375 377 #define MADERA_AIF3_FRAME_CTRL_12 0x592 378 378 + #define MADERA_AIF3_FRAME_CTRL_13 0x593 379 379 + #define MADERA_AIF3_FRAME_CTRL_14 0x594 380 380 + #define MADERA_AIF3_FRAME_CTRL_15 0x595 381 381 + #define MADERA_AIF3_FRAME_CTRL_16 0x596 382 382 + #define MADERA_AIF3_FRAME_CTRL_17 0x597 383 383 + #define MADERA_AIF3_FRAME_CTRL_18 0x598 376 384 #define MADERA_AIF3_TX_ENABLES 0x599 377 385 #define MADERA_AIF3_RX_ENABLES 0x59A 378 386 #define MADERA_AIF3_FORCE_WRITE 0x59B ··· 676 660 #define MADERA_AIF3TX2MIX_INPUT_3_VOLUME 0x78D 677 661 #define MADERA_AIF3TX2MIX_INPUT_4_SOURCE 0x78E 678 662 #define MADERA_AIF3TX2MIX_INPUT_4_VOLUME 0x78F 663 663 + #define MADERA_AIF3TX3MIX_INPUT_1_SOURCE 0x790 664 664 + #define MADERA_AIF3TX3MIX_INPUT_1_VOLUME 0x791 665 665 + #define MADERA_AIF3TX3MIX_INPUT_2_SOURCE 0x792 666 666 + #define MADERA_AIF3TX3MIX_INPUT_2_VOLUME 0x793 667 667 + #define MADERA_AIF3TX3MIX_INPUT_3_SOURCE 0x794 668 668 + #define MADERA_AIF3TX3MIX_INPUT_3_VOLUME 0x795 669 669 + #define MADERA_AIF3TX3MIX_INPUT_4_SOURCE 0x796 670 670 + #define MADERA_AIF3TX3MIX_INPUT_4_VOLUME 0x797 671 671 + #define MADERA_AIF3TX4MIX_INPUT_1_SOURCE 0x798 672 672 + #define MADERA_AIF3TX4MIX_INPUT_1_VOLUME 0x799 673 673 + #define MADERA_AIF3TX4MIX_INPUT_2_SOURCE 0x79A 674 674 + #define MADERA_AIF3TX4MIX_INPUT_2_VOLUME 0x79B 675 675 + #define MADERA_AIF3TX4MIX_INPUT_3_SOURCE 0x79C 676 676 + #define MADERA_AIF3TX4MIX_INPUT_3_VOLUME 0x79D 677 677 + #define MADERA_AIF3TX4MIX_INPUT_4_SOURCE 0x79E 678 678 + #define MADERA_AIF3TX4MIX_INPUT_4_VOLUME 0x79F 679 679 + #define CS47L92_AIF3TX5MIX_INPUT_1_SOURCE 0x7A0 680 680 + #define CS47L92_AIF3TX5MIX_INPUT_1_VOLUME 0x7A1 681 681 + #define CS47L92_AIF3TX5MIX_INPUT_2_SOURCE 0x7A2 682 682 + #define CS47L92_AIF3TX5MIX_INPUT_2_VOLUME 0x7A3 683 683 + #define CS47L92_AIF3TX5MIX_INPUT_3_SOURCE 0x7A4 684 684 + #define CS47L92_AIF3TX5MIX_INPUT_3_VOLUME 0x7A5 685 685 + #define CS47L92_AIF3TX5MIX_INPUT_4_SOURCE 0x7A6 686 686 + #define CS47L92_AIF3TX5MIX_INPUT_4_VOLUME 0x7A7 687 687 + #define CS47L92_AIF3TX6MIX_INPUT_1_SOURCE 0x7A8 688 688 + #define CS47L92_AIF3TX6MIX_INPUT_1_VOLUME 0x7A9 689 689 + #define CS47L92_AIF3TX6MIX_INPUT_2_SOURCE 0x7AA 690 690 + #define CS47L92_AIF3TX6MIX_INPUT_2_VOLUME 0x7AB 691 691 + #define CS47L92_AIF3TX6MIX_INPUT_3_SOURCE 0x7AC 692 692 + #define CS47L92_AIF3TX6MIX_INPUT_3_VOLUME 0x7AD 693 693 + #define CS47L92_AIF3TX6MIX_INPUT_4_SOURCE 0x7AE 694 694 + #define CS47L92_AIF3TX6MIX_INPUT_4_VOLUME 0x7AF 695 695 + #define CS47L92_AIF3TX7MIX_INPUT_1_SOURCE 0x7B0 696 696 + #define CS47L92_AIF3TX7MIX_INPUT_1_VOLUME 0x7B1 697 697 + #define CS47L92_AIF3TX7MIX_INPUT_2_SOURCE 0x7B2 698 698 + #define CS47L92_AIF3TX7MIX_INPUT_2_VOLUME 0x7B3 699 699 + #define CS47L92_AIF3TX7MIX_INPUT_3_SOURCE 0x7B4 700 700 + #define CS47L92_AIF3TX7MIX_INPUT_3_VOLUME 0x7B5 701 701 + #define CS47L92_AIF3TX7MIX_INPUT_4_SOURCE 0x7B6 702 702 + #define CS47L92_AIF3TX7MIX_INPUT_4_VOLUME 0x7B7 703 703 + #define CS47L92_AIF3TX8MIX_INPUT_1_SOURCE 0x7B8 704 704 + #define CS47L92_AIF3TX8MIX_INPUT_1_VOLUME 0x7B9 705 705 + #define CS47L92_AIF3TX8MIX_INPUT_2_SOURCE 0x7BA 706 706 + #define CS47L92_AIF3TX8MIX_INPUT_2_VOLUME 0x7BB 707 707 + #define CS47L92_AIF3TX8MIX_INPUT_3_SOURCE 0x7BC 708 708 + #define CS47L92_AIF3TX8MIX_INPUT_3_VOLUME 0x7BD 709 709 + #define CS47L92_AIF3TX8MIX_INPUT_4_SOURCE 0x7BE 710 710 + #define CS47L92_AIF3TX8MIX_INPUT_4_VOLUME 0x7BF 679 711 #define MADERA_AIF4TX1MIX_INPUT_1_SOURCE 0x7A0 680 712 #define MADERA_AIF4TX1MIX_INPUT_1_VOLUME 0x7A1 681 713 #define MADERA_AIF4TX1MIX_INPUT_2_SOURCE 0x7A2 ··· 1167 1103 #define MADERA_FCR_ADC_REFORMATTER_CONTROL 0xF73 1168 1104 #define MADERA_FCR_COEFF_START 0xF74 1169 1105 #define MADERA_FCR_COEFF_END 0xFC5 1170 1170 - #define MADERA_DAC_COMP_1 0x1300 1171 1171 - #define MADERA_DAC_COMP_2 0x1302 1172 1172 - #define MADERA_FRF_COEFFICIENT_1L_1 0x1380 1173 1173 - #define MADERA_FRF_COEFFICIENT_1L_2 0x1381 1174 1174 - #define MADERA_FRF_COEFFICIENT_1L_3 0x1382 1175 1175 - #define MADERA_FRF_COEFFICIENT_1L_4 0x1383 1176 1176 - #define MADERA_FRF_COEFFICIENT_1R_1 0x1390 1177 1177 - #define MADERA_FRF_COEFFICIENT_1R_2 0x1391 1178 1178 - #define MADERA_FRF_COEFFICIENT_1R_3 0x1392 1179 1179 - #define MADERA_FRF_COEFFICIENT_1R_4 0x1393 1180 1180 - #define MADERA_FRF_COEFFICIENT_2L_1 0x13A0 1181 1181 - #define MADERA_FRF_COEFFICIENT_2L_2 0x13A1 1182 1182 - #define MADERA_FRF_COEFFICIENT_2L_3 0x13A2 1183 1183 - #define MADERA_FRF_COEFFICIENT_2L_4 0x13A3 1184 1184 - #define MADERA_FRF_COEFFICIENT_2R_1 0x13B0 1185 1185 - #define MADERA_FRF_COEFFICIENT_2R_2 0x13B1 1186 1186 - #define MADERA_FRF_COEFFICIENT_2R_3 0x13B2 1187 1187 - #define MADERA_FRF_COEFFICIENT_2R_4 0x13B3 1188 1188 - #define MADERA_FRF_COEFFICIENT_3L_1 0x13C0 1189 1189 - #define MADERA_FRF_COEFFICIENT_3L_2 0x13C1 1190 1190 - #define MADERA_FRF_COEFFICIENT_3L_3 0x13C2 1191 1191 - #define MADERA_FRF_COEFFICIENT_3L_4 0x13C3 1192 1192 - #define MADERA_FRF_COEFFICIENT_3R_1 0x13D0 1193 1193 - #define MADERA_FRF_COEFFICIENT_3R_2 0x13D1 1194 1194 - #define MADERA_FRF_COEFFICIENT_3R_3 0x13D2 1195 1195 - #define MADERA_FRF_COEFFICIENT_3R_4 0x13D3 1196 1196 - #define MADERA_FRF_COEFFICIENT_4L_1 0x13E0 1197 1197 - #define MADERA_FRF_COEFFICIENT_4L_2 0x13E1 1198 1198 - #define MADERA_FRF_COEFFICIENT_4L_3 0x13E2 1199 1199 - #define MADERA_FRF_COEFFICIENT_4L_4 0x13E3 1200 1200 - #define MADERA_FRF_COEFFICIENT_4R_1 0x13F0 1201 1201 - #define MADERA_FRF_COEFFICIENT_4R_2 0x13F1 1202 1202 - #define MADERA_FRF_COEFFICIENT_4R_3 0x13F2 1203 1203 - #define MADERA_FRF_COEFFICIENT_4R_4 0x13F3 1204 1204 - #define CS47L35_FRF_COEFFICIENT_4L_1 0x13A0 1205 1205 - #define CS47L35_FRF_COEFFICIENT_4L_2 0x13A1 1206 1206 - #define CS47L35_FRF_COEFFICIENT_4L_3 0x13A2 1207 1207 - #define CS47L35_FRF_COEFFICIENT_4L_4 0x13A3 1208 1208 - #define CS47L35_FRF_COEFFICIENT_5L_1 0x13B0 1209 1209 - #define CS47L35_FRF_COEFFICIENT_5L_2 0x13B1 1210 1210 - #define CS47L35_FRF_COEFFICIENT_5L_3 0x13B2 1211 1211 - #define CS47L35_FRF_COEFFICIENT_5L_4 0x13B3 1212 1212 - #define CS47L35_FRF_COEFFICIENT_5R_1 0x13C0 1213 1213 - #define CS47L35_FRF_COEFFICIENT_5R_2 0x13C1 1214 1214 - #define CS47L35_FRF_COEFFICIENT_5R_3 0x13C2 1215 1215 - #define CS47L35_FRF_COEFFICIENT_5R_4 0x13C3 1216 1216 - #define MADERA_FRF_COEFFICIENT_5L_1 0x1400 1217 1217 - #define MADERA_FRF_COEFFICIENT_5L_2 0x1401 1218 1218 - #define MADERA_FRF_COEFFICIENT_5L_3 0x1402 1219 1219 - #define MADERA_FRF_COEFFICIENT_5L_4 0x1403 1220 1220 - #define MADERA_FRF_COEFFICIENT_5R_1 0x1410 1221 1221 - #define MADERA_FRF_COEFFICIENT_5R_2 0x1411 1222 1222 - #define MADERA_FRF_COEFFICIENT_5R_3 0x1412 1223 1223 - #define MADERA_FRF_COEFFICIENT_5R_4 0x1413 1224 1224 - #define MADERA_FRF_COEFFICIENT_6L_1 0x1420 1225 1225 - #define MADERA_FRF_COEFFICIENT_6L_2 0x1421 1226 1226 - #define MADERA_FRF_COEFFICIENT_6L_3 0x1422 1227 1227 - #define MADERA_FRF_COEFFICIENT_6L_4 0x1423 1228 1228 - #define MADERA_FRF_COEFFICIENT_6R_1 0x1430 1229 1229 - #define MADERA_FRF_COEFFICIENT_6R_2 0x1431 1230 1230 - #define MADERA_FRF_COEFFICIENT_6R_3 0x1432 1231 1231 - #define MADERA_FRF_COEFFICIENT_6R_4 0x1433 1106 1106 + #define MADERA_AUXPDM1_CTRL_0 0x10C0 1107 1107 + #define MADERA_AUXPDM1_CTRL_1 0x10C1 1232 1108 #define MADERA_DFC1_CTRL 0x1480 1233 1109 #define MADERA_DFC1_RX 0x1482 1234 1110 #define MADERA_DFC1_TX 0x1484 ··· 1206 1202 #define MADERA_GPIO1_CTRL_2 0x1701 1207 1203 #define MADERA_GPIO2_CTRL_1 0x1702 1208 1204 #define MADERA_GPIO2_CTRL_2 0x1703 1205 1205 + #define MADERA_GPIO15_CTRL_1 0x171C 1206 1206 + #define MADERA_GPIO15_CTRL_2 0x171D 1209 1207 #define MADERA_GPIO16_CTRL_1 0x171E 1210 1208 #define MADERA_GPIO16_CTRL_2 0x171F 1211 1209 #define MADERA_GPIO38_CTRL_1 0x174A ··· 1238 1232 #define MADERA_IRQ2_CTRL 0x1A82 1239 1233 #define MADERA_INTERRUPT_RAW_STATUS_1 0x1AA0 1240 1234 #define MADERA_WSEQ_SEQUENCE_1 0x3000 1235 1235 + #define MADERA_WSEQ_SEQUENCE_225 0x31C0 1241 1236 #define MADERA_WSEQ_SEQUENCE_252 0x31F6 1242 1237 #define CS47L35_OTP_HPDET_CAL_1 0x31F8 1243 1238 #define CS47L35_OTP_HPDET_CAL_2 0x31FA ··· 1448 1441 #define MADERA_OPCLK_ASYNC_SEL_WIDTH 3 1449 1442 1450 1443 /* (0x0171) FLL1_Control_1 */ 1444 1444 + #define CS47L92_FLL1_REFCLK_SRC_MASK 0xF000 1445 1445 + #define CS47L92_FLL1_REFCLK_SRC_SHIFT 12 1446 1446 + #define CS47L92_FLL1_REFCLK_SRC_WIDTH 4 1447 1447 + #define MADERA_FLL1_HOLD_MASK 0x0004 1448 1448 + #define MADERA_FLL1_HOLD_SHIFT 2 1449 1449 + #define MADERA_FLL1_HOLD_WIDTH 1 1451 1450 #define MADERA_FLL1_FREERUN 0x0002 1452 1451 #define MADERA_FLL1_FREERUN_MASK 0x0002 1453 1452 #define MADERA_FLL1_FREERUN_SHIFT 1 ··· 1486 1473 #define MADERA_FLL1_FRATIO_MASK 0x0F00 1487 1474 #define MADERA_FLL1_FRATIO_SHIFT 8 1488 1475 #define MADERA_FLL1_FRATIO_WIDTH 4 1476 1476 + #define MADERA_FLL1_FB_DIV_MASK 0x03FF 1477 1477 + #define MADERA_FLL1_FB_DIV_SHIFT 0 1478 1478 + #define MADERA_FLL1_FB_DIV_WIDTH 10 1489 1479 1490 1480 /* (0x0176) FLL1_Control_6 */ 1491 1481 #define MADERA_FLL1_REFCLK_DIV_MASK 0x00C0 ··· 1497 1481 #define MADERA_FLL1_REFCLK_SRC_MASK 0x000F 1498 1482 #define MADERA_FLL1_REFCLK_SRC_SHIFT 0 1499 1483 #define MADERA_FLL1_REFCLK_SRC_WIDTH 4 1500 1500 - 1501 1501 - /* (0x0177) FLL1_Loop_Filter_Test_1 */ 1502 1502 - #define MADERA_FLL1_FRC_INTEG_UPD 0x8000 1503 1503 - #define MADERA_FLL1_FRC_INTEG_UPD_MASK 0x8000 1504 1504 - #define MADERA_FLL1_FRC_INTEG_UPD_SHIFT 15 1505 1505 - #define MADERA_FLL1_FRC_INTEG_UPD_WIDTH 1 1506 1506 - #define MADERA_FLL1_FRC_INTEG_VAL_MASK 0x0FFF 1507 1507 - #define MADERA_FLL1_FRC_INTEG_VAL_SHIFT 0 1508 1508 - #define MADERA_FLL1_FRC_INTEG_VAL_WIDTH 12 1509 1484 1510 1485 /* (0x0179) FLL1_Control_7 */ 1511 1486 #define MADERA_FLL1_GAIN_MASK 0x003c ··· 1510 1503 #define MADERA_FLL1_PHASE_ENA_MASK 0x0800 1511 1504 #define MADERA_FLL1_PHASE_ENA_SHIFT 11 1512 1505 #define MADERA_FLL1_PHASE_ENA_WIDTH 1 1506 1506 + 1507 1507 + /* (0x017A) FLL1_Control_10 */ 1508 1508 + #define MADERA_FLL1_HP_MASK 0xC000 1509 1509 + #define MADERA_FLL1_HP_SHIFT 14 1510 1510 + #define MADERA_FLL1_HP_WIDTH 2 1511 1511 + #define MADERA_FLL1_PHASEDET_ENA_MASK 0x1000 1512 1512 + #define MADERA_FLL1_PHASEDET_ENA_SHIFT 12 1513 1513 + #define MADERA_FLL1_PHASEDET_ENA_WIDTH 1 1514 1514 + 1515 1515 + /* (0x017B) FLL1_Control_11 */ 1516 1516 + #define MADERA_FLL1_LOCKDET_THR_MASK 0x001E 1517 1517 + #define MADERA_FLL1_LOCKDET_THR_SHIFT 1 1518 1518 + #define MADERA_FLL1_LOCKDET_THR_WIDTH 4 1519 1519 + #define MADERA_FLL1_LOCKDET_MASK 0x0001 1520 1520 + #define MADERA_FLL1_LOCKDET_SHIFT 0 1521 1521 + #define MADERA_FLL1_LOCKDET_WIDTH 1 1522 1522 + 1523 1523 + /* (0x017D) FLL1_Digital_Test_1 */ 1524 1524 + #define MADERA_FLL1_SYNC_EFS_ENA_MASK 0x0100 1525 1525 + #define MADERA_FLL1_SYNC_EFS_ENA_SHIFT 8 1526 1526 + #define MADERA_FLL1_SYNC_EFS_ENA_WIDTH 1 1527 1527 + #define MADERA_FLL1_CLK_VCO_FAST_SRC_MASK 0x0003 1528 1528 + #define MADERA_FLL1_CLK_VCO_FAST_SRC_SHIFT 0 1529 1529 + #define MADERA_FLL1_CLK_VCO_FAST_SRC_WIDTH 2 1513 1530 1514 1531 /* (0x0181) FLL1_Synchroniser_1 */ 1515 1532 #define MADERA_FLL1_SYNC_ENA 0x0001 ··· 1656 1625 #define MADERA_LDO2_ENA_WIDTH 1 1657 1626 1658 1627 /* (0x0218) Mic_Bias_Ctrl_1 */ 1628 1628 + #define MADERA_MICB1_EXT_CAP 0x8000 1629 1629 + #define MADERA_MICB1_EXT_CAP_MASK 0x8000 1630 1630 + #define MADERA_MICB1_EXT_CAP_SHIFT 15 1631 1631 + #define MADERA_MICB1_EXT_CAP_WIDTH 1 1632 1632 + #define MADERA_MICB1_LVL_MASK 0x01E0 1633 1633 + #define MADERA_MICB1_LVL_SHIFT 5 1634 1634 + #define MADERA_MICB1_LVL_WIDTH 4 1659 1635 #define MADERA_MICB1_ENA 0x0001 1660 1636 #define MADERA_MICB1_ENA_MASK 0x0001 1661 1637 #define MADERA_MICB1_ENA_SHIFT 0 ··· 2346 2308 #define MADERA_OUT1R_ENA_SHIFT 0 2347 2309 #define MADERA_OUT1R_ENA_WIDTH 1 2348 2310 2311 2311 + /* (0x0408) Output_Rate_1 */ 2312 2312 + #define MADERA_CP_DAC_MODE_MASK 0x0040 2313 2313 + #define MADERA_CP_DAC_MODE_SHIFT 6 2314 2314 + #define MADERA_CP_DAC_MODE_WIDTH 1 2315 2315 + #define MADERA_OUT_EXT_CLK_DIV_MASK 0x0030 2316 2316 + #define MADERA_OUT_EXT_CLK_DIV_SHIFT 4 2317 2317 + #define MADERA_OUT_EXT_CLK_DIV_WIDTH 2 2318 2318 + #define MADERA_OUT_CLK_SRC_MASK 0x0007 2319 2319 + #define MADERA_OUT_CLK_SRC_SHIFT 0 2320 2320 + #define MADERA_OUT_CLK_SRC_WIDTH 3 2321 2321 + 2349 2322 /* (0x0409) Output_Volume_Ramp */ 2350 2323 #define MADERA_OUT_VD_RAMP_MASK 0x0070 2351 2324 #define MADERA_OUT_VD_RAMP_SHIFT 4 ··· 2878 2829 #define MADERA_AIF2RX1_ENA_WIDTH 1 2879 2830 2880 2831 /* (0x0599) AIF3_Tx_Enables */ 2832 2832 + #define MADERA_AIF3TX8_ENA 0x0080 2833 2833 + #define MADERA_AIF3TX8_ENA_MASK 0x0080 2834 2834 + #define MADERA_AIF3TX8_ENA_SHIFT 7 2835 2835 + #define MADERA_AIF3TX8_ENA_WIDTH 1 2836 2836 + #define MADERA_AIF3TX7_ENA 0x0040 2837 2837 + #define MADERA_AIF3TX7_ENA_MASK 0x0040 2838 2838 + #define MADERA_AIF3TX7_ENA_SHIFT 6 2839 2839 + #define MADERA_AIF3TX7_ENA_WIDTH 1 2840 2840 + #define MADERA_AIF3TX6_ENA 0x0020 2841 2841 + #define MADERA_AIF3TX6_ENA_MASK 0x0020 2842 2842 + #define MADERA_AIF3TX6_ENA_SHIFT 5 2843 2843 + #define MADERA_AIF3TX6_ENA_WIDTH 1 2844 2844 + #define MADERA_AIF3TX5_ENA 0x0010 2845 2845 + #define MADERA_AIF3TX5_ENA_MASK 0x0010 2846 2846 + #define MADERA_AIF3TX5_ENA_SHIFT 4 2847 2847 + #define MADERA_AIF3TX5_ENA_WIDTH 1 2848 2848 + #define MADERA_AIF3TX4_ENA 0x0008 2849 2849 + #define MADERA_AIF3TX4_ENA_MASK 0x0008 2850 2850 + #define MADERA_AIF3TX4_ENA_SHIFT 3 2851 2851 + #define MADERA_AIF3TX4_ENA_WIDTH 1 2852 2852 + #define MADERA_AIF3TX3_ENA 0x0004 2853 2853 + #define MADERA_AIF3TX3_ENA_MASK 0x0004 2854 2854 + #define MADERA_AIF3TX3_ENA_SHIFT 2 2855 2855 + #define MADERA_AIF3TX3_ENA_WIDTH 1 2881 2856 #define MADERA_AIF3TX2_ENA 0x0002 2882 2857 #define MADERA_AIF3TX2_ENA_MASK 0x0002 2883 2858 #define MADERA_AIF3TX2_ENA_SHIFT 1 ··· 2912 2839 #define MADERA_AIF3TX1_ENA_WIDTH 1 2913 2840 2914 2841 /* (0x059A) AIF3_Rx_Enables */ 2842 2842 + #define MADERA_AIF3RX8_ENA 0x0080 2843 2843 + #define MADERA_AIF3RX8_ENA_MASK 0x0080 2844 2844 + #define MADERA_AIF3RX8_ENA_SHIFT 7 2845 2845 + #define MADERA_AIF3RX8_ENA_WIDTH 1 2846 2846 + #define MADERA_AIF3RX7_ENA 0x0040 2847 2847 + #define MADERA_AIF3RX7_ENA_MASK 0x0040 2848 2848 + #define MADERA_AIF3RX7_ENA_SHIFT 6 2849 2849 + #define MADERA_AIF3RX7_ENA_WIDTH 1 2850 2850 + #define MADERA_AIF3RX6_ENA 0x0020 2851 2851 + #define MADERA_AIF3RX6_ENA_MASK 0x0020 2852 2852 + #define MADERA_AIF3RX6_ENA_SHIFT 5 2853 2853 + #define MADERA_AIF3RX6_ENA_WIDTH 1 2854 2854 + #define MADERA_AIF3RX5_ENA 0x0010 2855 2855 + #define MADERA_AIF3RX5_ENA_MASK 0x0010 2856 2856 + #define MADERA_AIF3RX5_ENA_SHIFT 4 2857 2857 + #define MADERA_AIF3RX5_ENA_WIDTH 1 2858 2858 + #define MADERA_AIF3RX4_ENA 0x0008 2859 2859 + #define MADERA_AIF3RX4_ENA_MASK 0x0008 2860 2860 + #define MADERA_AIF3RX4_ENA_SHIFT 3 2861 2861 + #define MADERA_AIF3RX4_ENA_WIDTH 1 2862 2862 + #define MADERA_AIF3RX3_ENA 0x0004 2863 2863 + #define MADERA_AIF3RX3_ENA_MASK 0x0004 2864 2864 + #define MADERA_AIF3RX3_ENA_SHIFT 2 2865 2865 + #define MADERA_AIF3RX3_ENA_WIDTH 1 2915 2866 #define MADERA_AIF3RX2_ENA 0x0002 2916 2867 #define MADERA_AIF3RX2_ENA_MASK 0x0002 2917 2868 #define MADERA_AIF3RX2_ENA_SHIFT 1 ··· 3549 3452 #define MADERA_FCR_MIC_MODE_SEL 0x000C 3550 3453 #define MADERA_FCR_MIC_MODE_SEL_SHIFT 2 3551 3454 #define MADERA_FCR_MIC_MODE_SEL_WIDTH 2 3455 3455 + 3456 3456 + /* (0x10C0) AUXPDM1_CTRL_0 */ 3457 3457 + #define MADERA_AUXPDM1_SRC_MASK 0x0F00 3458 3458 + #define MADERA_AUXPDM1_SRC_SHIFT 8 3459 3459 + #define MADERA_AUXPDM1_SRC_WIDTH 4 3460 3460 + #define MADERA_AUXPDM1_TXEDGE_MASK 0x0010 3461 3461 + #define MADERA_AUXPDM1_TXEDGE_SHIFT 4 3462 3462 + #define MADERA_AUXPDM1_TXEDGE_WIDTH 1 3463 3463 + #define MADERA_AUXPDM1_MSTR_MASK 0x0008 3464 3464 + #define MADERA_AUXPDM1_MSTR_SHIFT 3 3465 3465 + #define MADERA_AUXPDM1_MSTR_WIDTH 1 3466 3466 + #define MADERA_AUXPDM1_ENABLE_MASK 0x0001 3467 3467 + #define MADERA_AUXPDM1_ENABLE_SHIFT 0 3468 3468 + #define MADERA_AUXPDM1_ENABLE_WIDTH 1 3469 3469 + 3470 3470 + /* (0x10C1) AUXPDM1_CTRL_1 */ 3471 3471 + #define MADERA_AUXPDM1_CLK_FREQ_MASK 0xC000 3472 3472 + #define MADERA_AUXPDM1_CLK_FREQ_SHIFT 14 3473 3473 + #define MADERA_AUXPDM1_CLK_FREQ_WIDTH 2 3552 3474 3553 3475 /* (0x1480) DFC1_CTRL_W0 */ 3554 3476 #define MADERA_DFC1_RATE_MASK 0x007C

+177

include/linux/mfd/rk808.h

reviewed

··· 374 374 #define SWITCH1_EN BIT(5) 375 375 #define DEV_OFF_RST BIT(3) 376 376 #define DEV_OFF BIT(0) 377 377 + #define RTC_STOP BIT(0) 377 378 378 379 #define VB_LO_ACT BIT(4) 379 380 #define VB_LO_SEL_3500MV (7 << 0) ··· 388 387 #define SHUTDOWN_FUN (0x2 << 2) 389 388 #define SLEEP_FUN (0x1 << 2) 390 389 #define RK8XX_ID_MSK 0xfff0 390 390 + #define PWM_MODE_MSK BIT(7) 391 391 #define FPWM_MODE BIT(7) 392 392 + #define AUTO_PWM_MODE 0 393 393 + 394 394 + enum rk817_reg_id { 395 395 + RK817_ID_DCDC1 = 0, 396 396 + RK817_ID_DCDC2, 397 397 + RK817_ID_DCDC3, 398 398 + RK817_ID_DCDC4, 399 399 + RK817_ID_LDO1, 400 400 + RK817_ID_LDO2, 401 401 + RK817_ID_LDO3, 402 402 + RK817_ID_LDO4, 403 403 + RK817_ID_LDO5, 404 404 + RK817_ID_LDO6, 405 405 + RK817_ID_LDO7, 406 406 + RK817_ID_LDO8, 407 407 + RK817_ID_LDO9, 408 408 + RK817_ID_BOOST, 409 409 + RK817_ID_BOOST_OTG_SW, 410 410 + RK817_NUM_REGULATORS 411 411 + }; 412 412 + 413 413 + enum rk809_reg_id { 414 414 + RK809_ID_DCDC5 = RK817_ID_BOOST, 415 415 + RK809_ID_SW1, 416 416 + RK809_ID_SW2, 417 417 + RK809_NUM_REGULATORS 418 418 + }; 419 419 + 420 420 + #define RK817_SECONDS_REG 0x00 421 421 + #define RK817_MINUTES_REG 0x01 422 422 + #define RK817_HOURS_REG 0x02 423 423 + #define RK817_DAYS_REG 0x03 424 424 + #define RK817_MONTHS_REG 0x04 425 425 + #define RK817_YEARS_REG 0x05 426 426 + #define RK817_WEEKS_REG 0x06 427 427 + #define RK817_ALARM_SECONDS_REG 0x07 428 428 + #define RK817_ALARM_MINUTES_REG 0x08 429 429 + #define RK817_ALARM_HOURS_REG 0x09 430 430 + #define RK817_ALARM_DAYS_REG 0x0a 431 431 + #define RK817_ALARM_MONTHS_REG 0x0b 432 432 + #define RK817_ALARM_YEARS_REG 0x0c 433 433 + #define RK817_RTC_CTRL_REG 0xd 434 434 + #define RK817_RTC_STATUS_REG 0xe 435 435 + #define RK817_RTC_INT_REG 0xf 436 436 + #define RK817_RTC_COMP_LSB_REG 0x10 437 437 + #define RK817_RTC_COMP_MSB_REG 0x11 438 438 + 439 439 + #define RK817_POWER_EN_REG(i) (0xb1 + (i)) 440 440 + #define RK817_POWER_SLP_EN_REG(i) (0xb5 + (i)) 441 441 + 442 442 + #define RK817_POWER_CONFIG (0xb9) 443 443 + 444 444 + #define RK817_BUCK_CONFIG_REG(i) (0xba + (i) * 3) 445 445 + 446 446 + #define RK817_BUCK1_ON_VSEL_REG 0xBB 447 447 + #define RK817_BUCK1_SLP_VSEL_REG 0xBC 448 448 + 449 449 + #define RK817_BUCK2_CONFIG_REG 0xBD 450 450 + #define RK817_BUCK2_ON_VSEL_REG 0xBE 451 451 + #define RK817_BUCK2_SLP_VSEL_REG 0xBF 452 452 + 453 453 + #define RK817_BUCK3_CONFIG_REG 0xC0 454 454 + #define RK817_BUCK3_ON_VSEL_REG 0xC1 455 455 + #define RK817_BUCK3_SLP_VSEL_REG 0xC2 456 456 + 457 457 + #define RK817_BUCK4_CONFIG_REG 0xC3 458 458 + #define RK817_BUCK4_ON_VSEL_REG 0xC4 459 459 + #define RK817_BUCK4_SLP_VSEL_REG 0xC5 460 460 + 461 461 + #define RK817_LDO_ON_VSEL_REG(idx) (0xcc + (idx) * 2) 462 462 + #define RK817_BOOST_OTG_CFG (0xde) 463 463 + 464 464 + #define RK817_ID_MSB 0xed 465 465 + #define RK817_ID_LSB 0xee 466 466 + 467 467 + #define RK817_SYS_STS 0xf0 468 468 + #define RK817_SYS_CFG(i) (0xf1 + (i)) 469 469 + 470 470 + #define RK817_ON_SOURCE_REG 0xf5 471 471 + #define RK817_OFF_SOURCE_REG 0xf6 472 472 + 473 473 + /* INTERRUPT REGISTER */ 474 474 + #define RK817_INT_STS_REG0 0xf8 475 475 + #define RK817_INT_STS_MSK_REG0 0xf9 476 476 + #define RK817_INT_STS_REG1 0xfa 477 477 + #define RK817_INT_STS_MSK_REG1 0xfb 478 478 + #define RK817_INT_STS_REG2 0xfc 479 479 + #define RK817_INT_STS_MSK_REG2 0xfd 480 480 + #define RK817_GPIO_INT_CFG 0xfe 481 481 + 482 482 + /* IRQ Definitions */ 483 483 + #define RK817_IRQ_PWRON_FALL 0 484 484 + #define RK817_IRQ_PWRON_RISE 1 485 485 + #define RK817_IRQ_PWRON 2 486 486 + #define RK817_IRQ_PWMON_LP 3 487 487 + #define RK817_IRQ_HOTDIE 4 488 488 + #define RK817_IRQ_RTC_ALARM 5 489 489 + #define RK817_IRQ_RTC_PERIOD 6 490 490 + #define RK817_IRQ_VB_LO 7 491 491 + #define RK817_IRQ_PLUG_IN 8 492 492 + #define RK817_IRQ_PLUG_OUT 9 493 493 + #define RK817_IRQ_CHRG_TERM 10 494 494 + #define RK817_IRQ_CHRG_TIME 11 495 495 + #define RK817_IRQ_CHRG_TS 12 496 496 + #define RK817_IRQ_USB_OV 13 497 497 + #define RK817_IRQ_CHRG_IN_CLMP 14 498 498 + #define RK817_IRQ_BAT_DIS_ILIM 15 499 499 + #define RK817_IRQ_GATE_GPIO 16 500 500 + #define RK817_IRQ_TS_GPIO 17 501 501 + #define RK817_IRQ_CODEC_PD 18 502 502 + #define RK817_IRQ_CODEC_PO 19 503 503 + #define RK817_IRQ_CLASSD_MUTE_DONE 20 504 504 + #define RK817_IRQ_CLASSD_OCP 21 505 505 + #define RK817_IRQ_BAT_OVP 22 506 506 + #define RK817_IRQ_CHRG_BAT_HI 23 507 507 + #define RK817_IRQ_END (RK817_IRQ_CHRG_BAT_HI + 1) 508 508 + 509 509 + /* 510 510 + * rtc_ctrl 0xd 511 511 + * same as 808, except bit4 512 512 + */ 513 513 + #define RK817_RTC_CTRL_RSV4 BIT(4) 514 514 + 515 515 + /* power config 0xb9 */ 516 516 + #define RK817_BUCK3_FB_RES_MSK BIT(6) 517 517 + #define RK817_BUCK3_FB_RES_INTER BIT(6) 518 518 + #define RK817_BUCK3_FB_RES_EXT 0 519 519 + 520 520 + /* buck config 0xba */ 521 521 + #define RK817_RAMP_RATE_OFFSET 6 522 522 + #define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET) 523 523 + #define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET) 524 524 + #define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET) 525 525 + #define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET) 526 526 + #define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET) 527 527 + 528 528 + /* sys_cfg1 0xf2 */ 529 529 + #define RK817_HOTDIE_TEMP_MSK (0x3 << 4) 530 530 + #define RK817_HOTDIE_85 (0x0 << 4) 531 531 + #define RK817_HOTDIE_95 (0x1 << 4) 532 532 + #define RK817_HOTDIE_105 (0x2 << 4) 533 533 + #define RK817_HOTDIE_115 (0x3 << 4) 534 534 + 535 535 + #define RK817_TSD_TEMP_MSK BIT(6) 536 536 + #define RK817_TSD_140 0 537 537 + #define RK817_TSD_160 BIT(6) 538 538 + 539 539 + #define RK817_CLK32KOUT2_EN BIT(7) 540 540 + 541 541 + /* sys_cfg3 0xf4 */ 542 542 + #define RK817_SLPPIN_FUNC_MSK (0x3 << 3) 543 543 + #define SLPPIN_NULL_FUN (0x0 << 3) 544 544 + #define SLPPIN_SLP_FUN (0x1 << 3) 545 545 + #define SLPPIN_DN_FUN (0x2 << 3) 546 546 + #define SLPPIN_RST_FUN (0x3 << 3) 547 547 + 548 548 + #define RK817_RST_FUNC_MSK (0x3 << 6) 549 549 + #define RK817_RST_FUNC_SFT (6) 550 550 + #define RK817_RST_FUNC_CNT (3) 551 551 + #define RK817_RST_FUNC_DEV (0) /* reset the dev */ 552 552 + #define RK817_RST_FUNC_REG (0x1 << 6) /* reset the reg only */ 553 553 + 554 554 + #define RK817_SLPPOL_MSK BIT(5) 555 555 + #define RK817_SLPPOL_H BIT(5) 556 556 + #define RK817_SLPPOL_L (0) 557 557 + 558 558 + /* gpio&int 0xfe */ 559 559 + #define RK817_INT_POL_MSK BIT(1) 560 560 + #define RK817_INT_POL_H BIT(1) 561 561 + #define RK817_INT_POL_L 0 562 562 + #define RK809_BUCK5_CONFIG(i) (RK817_BOOST_OTG_CFG + (i) * 1) 392 563 393 564 enum { 394 565 BUCK_ILMIN_50MA, ··· 608 435 enum { 609 436 RK805_ID = 0x8050, 610 437 RK808_ID = 0x0000, 438 438 + RK809_ID = 0x8090, 439 439 + RK817_ID = 0x8170, 611 440 RK818_ID = 0x8181, 612 441 }; 613 442 ··· 620 445 long variant; 621 446 const struct regmap_config *regmap_cfg; 622 447 const struct regmap_irq_chip *regmap_irq_chip; 448 448 + void (*pm_pwroff_fn)(void); 449 449 + void (*pm_pwroff_prep_fn)(void); 623 450 }; 624 451 #endif /* __LINUX_REGULATOR_RK808_H */

+408

include/linux/mfd/rohm-bd70528.h

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··· 1 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 2 + /* Copyright (C) 2018 ROHM Semiconductors */ 3 3 + 4 4 + #ifndef __LINUX_MFD_BD70528_H__ 5 5 + #define __LINUX_MFD_BD70528_H__ 6 6 + 7 7 + #include <linux/bits.h> 8 8 + #include <linux/device.h> 9 9 + #include <linux/mfd/rohm-generic.h> 10 10 + #include <linux/regmap.h> 11 11 + 12 12 + enum { 13 13 + BD70528_BUCK1, 14 14 + BD70528_BUCK2, 15 15 + BD70528_BUCK3, 16 16 + BD70528_LDO1, 17 17 + BD70528_LDO2, 18 18 + BD70528_LDO3, 19 19 + BD70528_LED1, 20 20 + BD70528_LED2, 21 21 + }; 22 22 + 23 23 + struct bd70528_data { 24 24 + struct rohm_regmap_dev chip; 25 25 + struct mutex rtc_timer_lock; 26 26 + }; 27 27 + 28 28 + #define BD70528_BUCK_VOLTS 17 29 29 + #define BD70528_BUCK_VOLTS 17 30 30 + #define BD70528_BUCK_VOLTS 17 31 31 + #define BD70528_LDO_VOLTS 0x20 32 32 + 33 33 + #define BD70528_REG_BUCK1_EN 0x0F 34 34 + #define BD70528_REG_BUCK1_VOLT 0x15 35 35 + #define BD70528_REG_BUCK2_EN 0x10 36 36 + #define BD70528_REG_BUCK2_VOLT 0x16 37 37 + #define BD70528_REG_BUCK3_EN 0x11 38 38 + #define BD70528_REG_BUCK3_VOLT 0x17 39 39 + #define BD70528_REG_LDO1_EN 0x1b 40 40 + #define BD70528_REG_LDO1_VOLT 0x1e 41 41 + #define BD70528_REG_LDO2_EN 0x1c 42 42 + #define BD70528_REG_LDO2_VOLT 0x1f 43 43 + #define BD70528_REG_LDO3_EN 0x1d 44 44 + #define BD70528_REG_LDO3_VOLT 0x20 45 45 + #define BD70528_REG_LED_CTRL 0x2b 46 46 + #define BD70528_REG_LED_VOLT 0x29 47 47 + #define BD70528_REG_LED_EN 0x2a 48 48 + 49 49 + /* main irq registers */ 50 50 + #define BD70528_REG_INT_MAIN 0x7E 51 51 + #define BD70528_REG_INT_MAIN_MASK 0x74 52 52 + 53 53 + /* 'sub irq' registers */ 54 54 + #define BD70528_REG_INT_SHDN 0x7F 55 55 + #define BD70528_REG_INT_PWR_FLT 0x80 56 56 + #define BD70528_REG_INT_VR_FLT 0x81 57 57 + #define BD70528_REG_INT_MISC 0x82 58 58 + #define BD70528_REG_INT_BAT1 0x83 59 59 + #define BD70528_REG_INT_BAT2 0x84 60 60 + #define BD70528_REG_INT_RTC 0x85 61 61 + #define BD70528_REG_INT_GPIO 0x86 62 62 + #define BD70528_REG_INT_OP_FAIL 0x87 63 63 + 64 64 + #define BD70528_REG_INT_SHDN_MASK 0x75 65 65 + #define BD70528_REG_INT_PWR_FLT_MASK 0x76 66 66 + #define BD70528_REG_INT_VR_FLT_MASK 0x77 67 67 + #define BD70528_REG_INT_MISC_MASK 0x78 68 68 + #define BD70528_REG_INT_BAT1_MASK 0x79 69 69 + #define BD70528_REG_INT_BAT2_MASK 0x7a 70 70 + #define BD70528_REG_INT_RTC_MASK 0x7b 71 71 + #define BD70528_REG_INT_GPIO_MASK 0x7c 72 72 + #define BD70528_REG_INT_OP_FAIL_MASK 0x7d 73 73 + 74 74 + /* Reset related 'magic' registers */ 75 75 + #define BD70528_REG_SHIPMODE 0x03 76 76 + #define BD70528_REG_HWRESET 0x04 77 77 + #define BD70528_REG_WARMRESET 0x05 78 78 + #define BD70528_REG_STANDBY 0x06 79 79 + 80 80 + /* GPIO registers */ 81 81 + #define BD70528_REG_GPIO_STATE 0x8F 82 82 + 83 83 + #define BD70528_REG_GPIO1_IN 0x4d 84 84 + #define BD70528_REG_GPIO2_IN 0x4f 85 85 + #define BD70528_REG_GPIO3_IN 0x51 86 86 + #define BD70528_REG_GPIO4_IN 0x53 87 87 + #define BD70528_REG_GPIO1_OUT 0x4e 88 88 + #define BD70528_REG_GPIO2_OUT 0x50 89 89 + #define BD70528_REG_GPIO3_OUT 0x52 90 90 + #define BD70528_REG_GPIO4_OUT 0x54 91 91 + 92 92 + /* clk control */ 93 93 + 94 94 + #define BD70528_REG_CLK_OUT 0x2c 95 95 + 96 96 + /* RTC */ 97 97 + 98 98 + #define BD70528_REG_RTC_COUNT_H 0x2d 99 99 + #define BD70528_REG_RTC_COUNT_L 0x2e 100 100 + #define BD70528_REG_RTC_SEC 0x2f 101 101 + #define BD70528_REG_RTC_MINUTE 0x30 102 102 + #define BD70528_REG_RTC_HOUR 0x31 103 103 + #define BD70528_REG_RTC_WEEK 0x32 104 104 + #define BD70528_REG_RTC_DAY 0x33 105 105 + #define BD70528_REG_RTC_MONTH 0x34 106 106 + #define BD70528_REG_RTC_YEAR 0x35 107 107 + 108 108 + #define BD70528_REG_RTC_ALM_SEC 0x36 109 109 + #define BD70528_REG_RTC_ALM_START BD70528_REG_RTC_ALM_SEC 110 110 + #define BD70528_REG_RTC_ALM_MINUTE 0x37 111 111 + #define BD70528_REG_RTC_ALM_HOUR 0x38 112 112 + #define BD70528_REG_RTC_ALM_WEEK 0x39 113 113 + #define BD70528_REG_RTC_ALM_DAY 0x3a 114 114 + #define BD70528_REG_RTC_ALM_MONTH 0x3b 115 115 + #define BD70528_REG_RTC_ALM_YEAR 0x3c 116 116 + #define BD70528_REG_RTC_ALM_MASK 0x3d 117 117 + #define BD70528_REG_RTC_ALM_REPEAT 0x3e 118 118 + #define BD70528_REG_RTC_START BD70528_REG_RTC_SEC 119 119 + 120 120 + #define BD70528_REG_RTC_WAKE_SEC 0x43 121 121 + #define BD70528_REG_RTC_WAKE_START BD70528_REG_RTC_WAKE_SEC 122 122 + #define BD70528_REG_RTC_WAKE_MIN 0x44 123 123 + #define BD70528_REG_RTC_WAKE_HOUR 0x45 124 124 + #define BD70528_REG_RTC_WAKE_CTRL 0x46 125 125 + 126 126 + #define BD70528_REG_ELAPSED_TIMER_EN 0x42 127 127 + #define BD70528_REG_WAKE_EN 0x46 128 128 + 129 129 + /* WDT registers */ 130 130 + #define BD70528_REG_WDT_CTRL 0x4A 131 131 + #define BD70528_REG_WDT_HOUR 0x49 132 132 + #define BD70528_REG_WDT_MINUTE 0x48 133 133 + #define BD70528_REG_WDT_SEC 0x47 134 134 + 135 135 + /* Charger / Battery */ 136 136 + #define BD70528_REG_CHG_CURR_STAT 0x59 137 137 + #define BD70528_REG_CHG_BAT_STAT 0x57 138 138 + #define BD70528_REG_CHG_BAT_TEMP 0x58 139 139 + #define BD70528_REG_CHG_IN_STAT 0x56 140 140 + #define BD70528_REG_CHG_DCIN_ILIM 0x5d 141 141 + #define BD70528_REG_CHG_CHG_CURR_WARM 0x61 142 142 + #define BD70528_REG_CHG_CHG_CURR_COLD 0x62 143 143 + 144 144 + /* Masks for main IRQ register bits */ 145 145 + enum { 146 146 + BD70528_INT_SHDN, 147 147 + #define BD70528_INT_SHDN_MASK BIT(BD70528_INT_SHDN) 148 148 + BD70528_INT_PWR_FLT, 149 149 + #define BD70528_INT_PWR_FLT_MASK BIT(BD70528_INT_PWR_FLT) 150 150 + BD70528_INT_VR_FLT, 151 151 + #define BD70528_INT_VR_FLT_MASK BIT(BD70528_INT_VR_FLT) 152 152 + BD70528_INT_MISC, 153 153 + #define BD70528_INT_MISC_MASK BIT(BD70528_INT_MISC) 154 154 + BD70528_INT_BAT1, 155 155 + #define BD70528_INT_BAT1_MASK BIT(BD70528_INT_BAT1) 156 156 + BD70528_INT_RTC, 157 157 + #define BD70528_INT_RTC_MASK BIT(BD70528_INT_RTC) 158 158 + BD70528_INT_GPIO, 159 159 + #define BD70528_INT_GPIO_MASK BIT(BD70528_INT_GPIO) 160 160 + BD70528_INT_OP_FAIL, 161 161 + #define BD70528_INT_OP_FAIL_MASK BIT(BD70528_INT_OP_FAIL) 162 162 + }; 163 163 + 164 164 + /* IRQs */ 165 165 + enum { 166 166 + /* Shutdown register IRQs */ 167 167 + BD70528_INT_LONGPUSH, 168 168 + BD70528_INT_WDT, 169 169 + BD70528_INT_HWRESET, 170 170 + BD70528_INT_RSTB_FAULT, 171 171 + BD70528_INT_VBAT_UVLO, 172 172 + BD70528_INT_TSD, 173 173 + BD70528_INT_RSTIN, 174 174 + /* Power failure register IRQs */ 175 175 + BD70528_INT_BUCK1_FAULT, 176 176 + BD70528_INT_BUCK2_FAULT, 177 177 + BD70528_INT_BUCK3_FAULT, 178 178 + BD70528_INT_LDO1_FAULT, 179 179 + BD70528_INT_LDO2_FAULT, 180 180 + BD70528_INT_LDO3_FAULT, 181 181 + BD70528_INT_LED1_FAULT, 182 182 + BD70528_INT_LED2_FAULT, 183 183 + /* VR FAULT register IRQs */ 184 184 + BD70528_INT_BUCK1_OCP, 185 185 + BD70528_INT_BUCK2_OCP, 186 186 + BD70528_INT_BUCK3_OCP, 187 187 + BD70528_INT_LED1_OCP, 188 188 + BD70528_INT_LED2_OCP, 189 189 + BD70528_INT_BUCK1_FULLON, 190 190 + BD70528_INT_BUCK2_FULLON, 191 191 + /* PMU register interrupts */ 192 192 + BD70528_INT_SHORTPUSH, 193 193 + BD70528_INT_AUTO_WAKEUP, 194 194 + BD70528_INT_STATE_CHANGE, 195 195 + /* Charger 1 register IRQs */ 196 196 + BD70528_INT_BAT_OV_RES, 197 197 + BD70528_INT_BAT_OV_DET, 198 198 + BD70528_INT_DBAT_DET, 199 199 + BD70528_INT_BATTSD_COLD_RES, 200 200 + BD70528_INT_BATTSD_COLD_DET, 201 201 + BD70528_INT_BATTSD_HOT_RES, 202 202 + BD70528_INT_BATTSD_HOT_DET, 203 203 + BD70528_INT_CHG_TSD, 204 204 + /* Charger 2 register IRQs */ 205 205 + BD70528_INT_BAT_RMV, 206 206 + BD70528_INT_BAT_DET, 207 207 + BD70528_INT_DCIN2_OV_RES, 208 208 + BD70528_INT_DCIN2_OV_DET, 209 209 + BD70528_INT_DCIN2_RMV, 210 210 + BD70528_INT_DCIN2_DET, 211 211 + BD70528_INT_DCIN1_RMV, 212 212 + BD70528_INT_DCIN1_DET, 213 213 + /* RTC register IRQs */ 214 214 + BD70528_INT_RTC_ALARM, 215 215 + BD70528_INT_ELPS_TIM, 216 216 + /* GPIO register IRQs */ 217 217 + BD70528_INT_GPIO0, 218 218 + BD70528_INT_GPIO1, 219 219 + BD70528_INT_GPIO2, 220 220 + BD70528_INT_GPIO3, 221 221 + /* Invalid operation register IRQs */ 222 222 + BD70528_INT_BUCK1_DVS_OPFAIL, 223 223 + BD70528_INT_BUCK2_DVS_OPFAIL, 224 224 + BD70528_INT_BUCK3_DVS_OPFAIL, 225 225 + BD70528_INT_LED1_VOLT_OPFAIL, 226 226 + BD70528_INT_LED2_VOLT_OPFAIL, 227 227 + }; 228 228 + 229 229 + /* Masks */ 230 230 + #define BD70528_INT_LONGPUSH_MASK 0x1 231 231 + #define BD70528_INT_WDT_MASK 0x2 232 232 + #define BD70528_INT_HWRESET_MASK 0x4 233 233 + #define BD70528_INT_RSTB_FAULT_MASK 0x8 234 234 + #define BD70528_INT_VBAT_UVLO_MASK 0x10 235 235 + #define BD70528_INT_TSD_MASK 0x20 236 236 + #define BD70528_INT_RSTIN_MASK 0x40 237 237 + 238 238 + #define BD70528_INT_BUCK1_FAULT_MASK 0x1 239 239 + #define BD70528_INT_BUCK2_FAULT_MASK 0x2 240 240 + #define BD70528_INT_BUCK3_FAULT_MASK 0x4 241 241 + #define BD70528_INT_LDO1_FAULT_MASK 0x8 242 242 + #define BD70528_INT_LDO2_FAULT_MASK 0x10 243 243 + #define BD70528_INT_LDO3_FAULT_MASK 0x20 244 244 + #define BD70528_INT_LED1_FAULT_MASK 0x40 245 245 + #define BD70528_INT_LED2_FAULT_MASK 0x80 246 246 + 247 247 + #define BD70528_INT_BUCK1_OCP_MASK 0x1 248 248 + #define BD70528_INT_BUCK2_OCP_MASK 0x2 249 249 + #define BD70528_INT_BUCK3_OCP_MASK 0x4 250 250 + #define BD70528_INT_LED1_OCP_MASK 0x8 251 251 + #define BD70528_INT_LED2_OCP_MASK 0x10 252 252 + #define BD70528_INT_BUCK1_FULLON_MASK 0x20 253 253 + #define BD70528_INT_BUCK2_FULLON_MASK 0x40 254 254 + 255 255 + #define BD70528_INT_SHORTPUSH_MASK 0x1 256 256 + #define BD70528_INT_AUTO_WAKEUP_MASK 0x2 257 257 + #define BD70528_INT_STATE_CHANGE_MASK 0x10 258 258 + 259 259 + #define BD70528_INT_BAT_OV_RES_MASK 0x1 260 260 + #define BD70528_INT_BAT_OV_DET_MASK 0x2 261 261 + #define BD70528_INT_DBAT_DET_MASK 0x4 262 262 + #define BD70528_INT_BATTSD_COLD_RES_MASK 0x8 263 263 + #define BD70528_INT_BATTSD_COLD_DET_MASK 0x10 264 264 + #define BD70528_INT_BATTSD_HOT_RES_MASK 0x20 265 265 + #define BD70528_INT_BATTSD_HOT_DET_MASK 0x40 266 266 + #define BD70528_INT_CHG_TSD_MASK 0x80 267 267 + 268 268 + #define BD70528_INT_BAT_RMV_MASK 0x1 269 269 + #define BD70528_INT_BAT_DET_MASK 0x2 270 270 + #define BD70528_INT_DCIN2_OV_RES_MASK 0x4 271 271 + #define BD70528_INT_DCIN2_OV_DET_MASK 0x8 272 272 + #define BD70528_INT_DCIN2_RMV_MASK 0x10 273 273 + #define BD70528_INT_DCIN2_DET_MASK 0x20 274 274 + #define BD70528_INT_DCIN1_RMV_MASK 0x40 275 275 + #define BD70528_INT_DCIN1_DET_MASK 0x80 276 276 + 277 277 + #define BD70528_INT_RTC_ALARM_MASK 0x1 278 278 + #define BD70528_INT_ELPS_TIM_MASK 0x2 279 279 + 280 280 + #define BD70528_INT_GPIO0_MASK 0x1 281 281 + #define BD70528_INT_GPIO1_MASK 0x2 282 282 + #define BD70528_INT_GPIO2_MASK 0x4 283 283 + #define BD70528_INT_GPIO3_MASK 0x8 284 284 + 285 285 + #define BD70528_INT_BUCK1_DVS_OPFAIL_MASK 0x1 286 286 + #define BD70528_INT_BUCK2_DVS_OPFAIL_MASK 0x2 287 287 + #define BD70528_INT_BUCK3_DVS_OPFAIL_MASK 0x4 288 288 + #define BD70528_INT_LED1_VOLT_OPFAIL_MASK 0x10 289 289 + #define BD70528_INT_LED2_VOLT_OPFAIL_MASK 0x20 290 290 + 291 291 + #define BD70528_DEBOUNCE_MASK 0x3 292 292 + 293 293 + #define BD70528_DEBOUNCE_DISABLE 0 294 294 + #define BD70528_DEBOUNCE_15MS 1 295 295 + #define BD70528_DEBOUNCE_30MS 2 296 296 + #define BD70528_DEBOUNCE_50MS 3 297 297 + 298 298 + #define BD70528_GPIO_DRIVE_MASK 0x2 299 299 + #define BD70528_GPIO_PUSH_PULL 0x0 300 300 + #define BD70528_GPIO_OPEN_DRAIN 0x2 301 301 + 302 302 + #define BD70528_GPIO_OUT_EN_MASK 0x80 303 303 + #define BD70528_GPIO_OUT_ENABLE 0x80 304 304 + #define BD70528_GPIO_OUT_DISABLE 0x0 305 305 + 306 306 + #define BD70528_GPIO_OUT_HI 0x1 307 307 + #define BD70528_GPIO_OUT_LO 0x0 308 308 + #define BD70528_GPIO_OUT_MASK 0x1 309 309 + 310 310 + #define BD70528_GPIO_IN_STATE_BASE 1 311 311 + 312 312 + #define BD70528_CLK_OUT_EN_MASK 0x1 313 313 + 314 314 + /* RTC masks to mask out reserved bits */ 315 315 + 316 316 + #define BD70528_MASK_RTC_SEC 0x7f 317 317 + #define BD70528_MASK_RTC_MINUTE 0x7f 318 318 + #define BD70528_MASK_RTC_HOUR_24H 0x80 319 319 + #define BD70528_MASK_RTC_HOUR_PM 0x20 320 320 + #define BD70528_MASK_RTC_HOUR 0x1f 321 321 + #define BD70528_MASK_RTC_DAY 0x3f 322 322 + #define BD70528_MASK_RTC_WEEK 0x07 323 323 + #define BD70528_MASK_RTC_MONTH 0x1f 324 324 + #define BD70528_MASK_RTC_YEAR 0xff 325 325 + #define BD70528_MASK_RTC_COUNT_L 0x7f 326 326 + 327 327 + #define BD70528_MASK_ELAPSED_TIMER_EN 0x1 328 328 + /* Mask second, min and hour fields 329 329 + * HW would support ALM irq for over 24h 330 330 + * (by setting day, month and year too) 331 331 + * but as we wish to keep this same as for 332 332 + * wake-up we limit ALM to 24H and only 333 333 + * unmask sec, min and hour 334 334 + */ 335 335 + #define BD70528_MASK_ALM_EN 0x7 336 336 + #define BD70528_MASK_WAKE_EN 0x1 337 337 + 338 338 + /* WDT masks */ 339 339 + #define BD70528_MASK_WDT_EN 0x1 340 340 + #define BD70528_MASK_WDT_HOUR 0x1 341 341 + #define BD70528_MASK_WDT_MINUTE 0x7f 342 342 + #define BD70528_MASK_WDT_SEC 0x7f 343 343 + 344 344 + #define BD70528_WDT_STATE_BIT 0x1 345 345 + #define BD70528_ELAPSED_STATE_BIT 0x2 346 346 + #define BD70528_WAKE_STATE_BIT 0x4 347 347 + 348 348 + /* Charger masks */ 349 349 + #define BD70528_MASK_CHG_STAT 0x7f 350 350 + #define BD70528_MASK_CHG_BAT_TIMER 0x20 351 351 + #define BD70528_MASK_CHG_BAT_OVERVOLT 0x10 352 352 + #define BD70528_MASK_CHG_BAT_DETECT 0x1 353 353 + #define BD70528_MASK_CHG_DCIN1_UVLO 0x1 354 354 + #define BD70528_MASK_CHG_DCIN_ILIM 0x3f 355 355 + #define BD70528_MASK_CHG_CHG_CURR 0x1f 356 356 + #define BD70528_MASK_CHG_TRICKLE_CURR 0x10 357 357 + 358 358 + /* 359 359 + * Note, external battery register is the lonely rider at 360 360 + * address 0xc5. See how to stuff that in the regmap 361 361 + */ 362 362 + #define BD70528_MAX_REGISTER 0x94 363 363 + 364 364 + /* Buck control masks */ 365 365 + #define BD70528_MASK_RUN_EN 0x4 366 366 + #define BD70528_MASK_STBY_EN 0x2 367 367 + #define BD70528_MASK_IDLE_EN 0x1 368 368 + #define BD70528_MASK_LED1_EN 0x1 369 369 + #define BD70528_MASK_LED2_EN 0x10 370 370 + 371 371 + #define BD70528_MASK_BUCK_VOLT 0xf 372 372 + #define BD70528_MASK_LDO_VOLT 0x1f 373 373 + #define BD70528_MASK_LED1_VOLT 0x1 374 374 + #define BD70528_MASK_LED2_VOLT 0x10 375 375 + 376 376 + /* Misc irq masks */ 377 377 + #define BD70528_INT_MASK_SHORT_PUSH 1 378 378 + #define BD70528_INT_MASK_AUTO_WAKE 2 379 379 + #define BD70528_INT_MASK_POWER_STATE 4 380 380 + 381 381 + #define BD70528_MASK_BUCK_RAMP 0x10 382 382 + #define BD70528_SIFT_BUCK_RAMP 4 383 383 + 384 384 + #if IS_ENABLED(CONFIG_BD70528_WATCHDOG) 385 385 + 386 386 + int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, int *old_state); 387 387 + void bd70528_wdt_lock(struct rohm_regmap_dev *data); 388 388 + void bd70528_wdt_unlock(struct rohm_regmap_dev *data); 389 389 + 390 390 + #else /* CONFIG_BD70528_WATCHDOG */ 391 391 + 392 392 + static inline int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, 393 393 + int *old_state) 394 394 + { 395 395 + return 0; 396 396 + } 397 397 + 398 398 + static inline void bd70528_wdt_lock(struct rohm_regmap_dev *data) 399 399 + { 400 400 + } 401 401 + 402 402 + static inline void bd70528_wdt_unlock(struct rohm_regmap_dev *data) 403 403 + { 404 404 + } 405 405 + 406 406 + #endif /* CONFIG_BD70528_WATCHDOG */ 407 407 + 408 408 + #endif /* __LINUX_MFD_BD70528_H__ */

+8 -14

include/linux/mfd/rohm-bd718x7.h

reviewed

··· 4 4 #ifndef __LINUX_MFD_BD718XX_H__ 5 5 #define __LINUX_MFD_BD718XX_H__ 6 6 7 7 + #include <linux/mfd/rohm-generic.h> 7 8 #include <linux/regmap.h> 8 8 - 9 9 - enum { 10 10 - BD718XX_TYPE_BD71837 = 0, 11 11 - BD718XX_TYPE_BD71847, 12 12 - BD718XX_TYPE_AMOUNT 13 13 - }; 14 9 15 10 enum { 16 11 BD718XX_BUCK1 = 0, ··· 316 321 BD718XX_PWRBTN_LONG_PRESS_15S 317 322 }; 318 323 319 319 - struct bd718xx_clk; 320 320 - 321 324 struct bd718xx { 322 322 - unsigned int chip_type; 323 323 - struct device *dev; 324 324 - struct regmap *regmap; 325 325 - unsigned long int id; 325 325 + /* 326 326 + * Please keep this as the first member here as some 327 327 + * drivers (clk) supporting more than one chip may only know this 328 328 + * generic struct 'struct rohm_regmap_dev' and assume it is 329 329 + * the first chunk of parent device's private data. 330 330 + */ 331 331 + struct rohm_regmap_dev chip; 326 332 327 333 int chip_irq; 328 334 struct regmap_irq_chip_data *irq_data; 329 329 - 330 330 - struct bd718xx_clk *clk; 331 335 }; 332 336 333 337 #endif /* __LINUX_MFD_BD718XX_H__ */

+20

include/linux/mfd/rohm-generic.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 2 + /* Copyright (C) 2018 ROHM Semiconductors */ 3 3 + 4 4 + #ifndef __LINUX_MFD_ROHM_H__ 5 5 + #define __LINUX_MFD_ROHM_H__ 6 6 + 7 7 + enum { 8 8 + ROHM_CHIP_TYPE_BD71837 = 0, 9 9 + ROHM_CHIP_TYPE_BD71847, 10 10 + ROHM_CHIP_TYPE_BD70528, 11 11 + ROHM_CHIP_TYPE_AMOUNT 12 12 + }; 13 13 + 14 14 + struct rohm_regmap_dev { 15 15 + unsigned int chip_type; 16 16 + struct device *dev; 17 17 + struct regmap *regmap; 18 18 + }; 19 19 + 20 20 + #endif

+1 -1

include/linux/mfd/stmfx.h

reviewed

··· 5 5 */ 6 6 7 7 #ifndef MFD_STMFX_H 8 8 - #define MFX_STMFX_H 8 8 + #define MFD_STMFX_H 9 9 10 10 #include <linux/regmap.h> 11 11