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Merge tag 'spacemit-clk-for-6.18-1' of https://github.com/spacemit-com/linux into clk-spacemit

Pull RISC-V SpacemiT clk driver updates from Yixun Lan:

- Convert to use clk_ops::determine_rate()
- Fix parent clocks of SSPA in SpacemiT driver

* tag 'spacemit-clk-for-6.18-1' of https://github.com/spacemit-com/linux:
clk: spacemit: ccu_pll: convert from round_rate() to determine_rate()
clk: spacemit: ccu_mix: convert from round_rate() to determine_rate()
clk: spacemit: ccu_ddn: convert from round_rate() to determine_rate()
clk: spacemit: fix sspax_clk
dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA

+47 -17
+25 -4
drivers/clk/spacemit/ccu-k1.c
··· 247 247 248 248 CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0); 249 249 250 - static const struct clk_parent_data sspa_parents[] = { 250 + /* 251 + * When i2s_bclk is selected as the parent clock of sspa, 252 + * the hardware requires bit3 to be set 253 + */ 254 + CCU_GATE_DEFINE(sspa0_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA0_CLK_RST, BIT(3), 0); 255 + CCU_GATE_DEFINE(sspa1_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA1_CLK_RST, BIT(3), 0); 256 + 257 + static const struct clk_parent_data sspa0_parents[] = { 251 258 CCU_PARENT_HW(pll1_d384_6p4), 252 259 CCU_PARENT_HW(pll1_d192_12p8), 253 260 CCU_PARENT_HW(pll1_d96_25p6), ··· 262 255 CCU_PARENT_HW(pll1_d768_3p2), 263 256 CCU_PARENT_HW(pll1_d1536_1p6), 264 257 CCU_PARENT_HW(pll1_d3072_0p8), 265 - CCU_PARENT_HW(i2s_bclk), 258 + CCU_PARENT_HW(sspa0_i2s_bclk), 266 259 }; 267 - CCU_MUX_GATE_DEFINE(sspa0_clk, sspa_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); 268 - CCU_MUX_GATE_DEFINE(sspa1_clk, sspa_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); 260 + CCU_MUX_GATE_DEFINE(sspa0_clk, sspa0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); 261 + 262 + static const struct clk_parent_data sspa1_parents[] = { 263 + CCU_PARENT_HW(pll1_d384_6p4), 264 + CCU_PARENT_HW(pll1_d192_12p8), 265 + CCU_PARENT_HW(pll1_d96_25p6), 266 + CCU_PARENT_HW(pll1_d48_51p2), 267 + CCU_PARENT_HW(pll1_d768_3p2), 268 + CCU_PARENT_HW(pll1_d1536_1p6), 269 + CCU_PARENT_HW(pll1_d3072_0p8), 270 + CCU_PARENT_HW(sspa1_i2s_bclk), 271 + }; 272 + CCU_MUX_GATE_DEFINE(sspa1_clk, sspa1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); 273 + 269 274 CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0); 270 275 CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0); 271 276 CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0); ··· 884 865 [CLK_SSPA1_BUS] = &sspa1_bus_clk.common.hw, 885 866 [CLK_TSEN_BUS] = &tsen_bus_clk.common.hw, 886 867 [CLK_IPC_AP2AUD_BUS] = &ipc_ap2aud_bus_clk.common.hw, 868 + [CLK_SSPA0_I2S_BCLK] = &sspa0_i2s_bclk.common.hw, 869 + [CLK_SSPA1_I2S_BCLK] = &sspa1_i2s_bclk.common.hw, 887 870 }; 888 871 889 872 static const struct spacemit_ccu_data k1_ccu_apbc_data = {
+7 -4
drivers/clk/spacemit/ccu_ddn.c
··· 39 39 return ccu_ddn_calc_rate(prate, *num, *den); 40 40 } 41 41 42 - static long ccu_ddn_round_rate(struct clk_hw *hw, unsigned long rate, 43 - unsigned long *prate) 42 + static int ccu_ddn_determine_rate(struct clk_hw *hw, 43 + struct clk_rate_request *req) 44 44 { 45 45 struct ccu_ddn *ddn = hw_to_ccu_ddn(hw); 46 46 unsigned long num, den; 47 47 48 - return ccu_ddn_calc_best_rate(ddn, rate, *prate, &num, &den); 48 + req->rate = ccu_ddn_calc_best_rate(ddn, req->rate, 49 + req->best_parent_rate, &num, &den); 50 + 51 + return 0; 49 52 } 50 53 51 54 static unsigned long ccu_ddn_recalc_rate(struct clk_hw *hw, unsigned long prate) ··· 81 78 82 79 const struct clk_ops spacemit_ccu_ddn_ops = { 83 80 .recalc_rate = ccu_ddn_recalc_rate, 84 - .round_rate = ccu_ddn_round_rate, 81 + .determine_rate = ccu_ddn_determine_rate, 85 82 .set_rate = ccu_ddn_set_rate, 86 83 };
+7 -5
drivers/clk/spacemit/ccu_mix.c
··· 80 80 MIX_FC_TIMEOUT_US); 81 81 } 82 82 83 - static long ccu_factor_round_rate(struct clk_hw *hw, unsigned long rate, 84 - unsigned long *prate) 83 + static int ccu_factor_determine_rate(struct clk_hw *hw, 84 + struct clk_rate_request *req) 85 85 { 86 - return ccu_factor_recalc_rate(hw, *prate); 86 + req->rate = ccu_factor_recalc_rate(hw, req->best_parent_rate); 87 + 88 + return 0; 87 89 } 88 90 89 91 static int ccu_factor_set_rate(struct clk_hw *hw, unsigned long rate, ··· 200 198 }; 201 199 202 200 const struct clk_ops spacemit_ccu_factor_ops = { 203 - .round_rate = ccu_factor_round_rate, 201 + .determine_rate = ccu_factor_determine_rate, 204 202 .recalc_rate = ccu_factor_recalc_rate, 205 203 .set_rate = ccu_factor_set_rate, 206 204 }; ··· 222 220 .enable = ccu_gate_enable, 223 221 .is_enabled = ccu_gate_is_enabled, 224 222 225 - .round_rate = ccu_factor_round_rate, 223 + .determine_rate = ccu_factor_determine_rate, 226 224 .recalc_rate = ccu_factor_recalc_rate, 227 225 .set_rate = ccu_factor_set_rate, 228 226 };
+6 -4
drivers/clk/spacemit/ccu_pll.c
··· 125 125 return entry ? entry->rate : 0; 126 126 } 127 127 128 - static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate, 129 - unsigned long *prate) 128 + static int ccu_pll_determine_rate(struct clk_hw *hw, 129 + struct clk_rate_request *req) 130 130 { 131 131 struct ccu_pll *pll = hw_to_ccu_pll(hw); 132 132 133 - return ccu_pll_lookup_best_rate(pll, rate)->rate; 133 + req->rate = ccu_pll_lookup_best_rate(pll, req->rate)->rate; 134 + 135 + return 0; 134 136 } 135 137 136 138 static int ccu_pll_init(struct clk_hw *hw) ··· 154 152 .disable = ccu_pll_disable, 155 153 .set_rate = ccu_pll_set_rate, 156 154 .recalc_rate = ccu_pll_recalc_rate, 157 - .round_rate = ccu_pll_round_rate, 155 + .determine_rate = ccu_pll_determine_rate, 158 156 .is_enabled = ccu_pll_is_enabled, 159 157 };
+2
include/dt-bindings/clock/spacemit,k1-syscon.h
··· 182 182 #define CLK_SSPA1_BUS 97 183 183 #define CLK_TSEN_BUS 98 184 184 #define CLK_IPC_AP2AUD_BUS 99 185 + #define CLK_SSPA0_I2S_BCLK 100 186 + #define CLK_SSPA1_I2S_BCLK 101 185 187 186 188 /* APBC resets */ 187 189 #define RESET_UART0 0