Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v6.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
- Mark the Meson GPIO controller as sleeping to avoid a
context splat
- Fix up the I2S2 and SWR TX group settings in the
Qualcomm SM8350 LPASS pin controller, and implement the
proper .get_direction() callback
- Fix a pin typo in the TG1520 pin controller
- Fix a group name in the Marvell armada 3710 XB pin
controller that got mangled in a DT schema rewrite
* tag 'pinctrl-v6.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
dt-bindings: pinctrl: marvell,armada3710-xb-pinctrl: fix 'usb32_drvvbus0' group name
pinctrl: lpass-lpi: implement .get_direction() for the GPIO driver
pinctrl: th1520: Fix typo
pinctrl: qcom: sm8350-lpass-lpi: Merge with SC7280 to fix I2S2 and SWR TX pins
pinctrl: meson: mark the GPIO controller as sleeping
+26
-168
+1
-1
Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml
···
88
88
pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,
89
89
ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi,
90
90
spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,
91
-
usb2_drvvbus1, usb32_drvvbus ]
91
+
usb2_drvvbus1, usb32_drvvbus0 ]
92
92
93
93
function:
94
94
enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire,
-1
arch/arm64/configs/defconfig
-1
arch/arm64/configs/defconfig
+1
-1
drivers/pinctrl/meson/pinctrl-meson.c
+1
-1
drivers/pinctrl/meson/pinctrl-meson.c
+1
-1
drivers/pinctrl/pinctrl-th1520.c
+1
-1
drivers/pinctrl/pinctrl-th1520.c
···
287
287
TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0),
288
288
TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0),
289
289
TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0),
290
-
TH1520_PAD(8, QSPI1_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0),
290
+
TH1520_PAD(8, QSPI0_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0),
291
291
TH1520_PAD(9, I2C2_SCL, I2C, UART, ____, GPIO, ____, ____, 0),
292
292
TH1520_PAD(10, I2C2_SDA, I2C, UART, ____, GPIO, ____, ____, 0),
293
293
TH1520_PAD(11, I2C3_SCL, I2C, ____, ____, GPIO, ____, ____, 0),
+3
-12
drivers/pinctrl/qcom/Kconfig
+3
-12
drivers/pinctrl/qcom/Kconfig
···
61
61
(Low Power Island) found on the Qualcomm Technologies Inc SoCs.
62
62
63
63
config PINCTRL_SC7280_LPASS_LPI
64
-
tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
64
+
tristate "Qualcomm Technologies Inc SC7280 and SM8350 LPASS LPI pin controller driver"
65
65
depends on ARM64 || COMPILE_TEST
66
66
depends on PINCTRL_LPASS_LPI
67
67
help
68
68
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
69
69
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
70
-
(Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
70
+
(Low Power Island) found on the Qualcomm Technologies Inc SC7280
71
+
and SM8350 platforms.
71
72
72
73
config PINCTRL_SDM660_LPASS_LPI
73
74
tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller driver"
···
106
105
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
107
106
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
108
107
(Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
109
-
110
-
config PINCTRL_SM8350_LPASS_LPI
111
-
tristate "Qualcomm Technologies Inc SM8350 LPASS LPI pin controller driver"
112
-
depends on ARM64 || COMPILE_TEST
113
-
depends on PINCTRL_LPASS_LPI
114
-
help
115
-
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
116
-
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
117
-
(Low Power Island) found on the Qualcomm Technologies Inc SM8350
118
-
platform.
119
108
120
109
config PINCTRL_SM8450_LPASS_LPI
121
110
tristate "Qualcomm Technologies Inc SM8450 LPASS LPI pin controller driver"
-1
drivers/pinctrl/qcom/Makefile
-1
drivers/pinctrl/qcom/Makefile
···
64
64
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
65
65
obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
66
66
obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
67
-
obj-$(CONFIG_PINCTRL_SM8350_LPASS_LPI) += pinctrl-sm8350-lpass-lpi.o
68
67
obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o
69
68
obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o
70
69
obj-$(CONFIG_PINCTRL_SM8550) += pinctrl-sm8550.o
+17
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+17
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
···
312
312
.pin_config_group_set = lpi_config_set,
313
313
};
314
314
315
+
static int lpi_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
316
+
{
317
+
unsigned long config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, 0);
318
+
struct lpi_pinctrl *state = gpiochip_get_data(chip);
319
+
unsigned long arg;
320
+
int ret;
321
+
322
+
ret = lpi_config_get(state->ctrl, pin, &config);
323
+
if (ret)
324
+
return ret;
325
+
326
+
arg = pinconf_to_config_argument(config);
327
+
328
+
return arg ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
329
+
}
330
+
315
331
static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
316
332
{
317
333
struct lpi_pinctrl *state = gpiochip_get_data(chip);
···
425
409
#endif
426
410
427
411
static const struct gpio_chip lpi_gpio_template = {
412
+
.get_direction = lpi_gpio_get_direction,
428
413
.direction_input = lpi_gpio_direction_input,
429
414
.direction_output = lpi_gpio_direction_output,
430
415
.get = lpi_gpio_get,
+3
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
+3
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
-151
drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
-151
drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
4
-
* Copyright (c) 2020-2023 Linaro Ltd.
5
-
*/
6
-
7
-
#include <linux/gpio/driver.h>
8
-
#include <linux/module.h>
9
-
#include <linux/platform_device.h>
10
-
11
-
#include "pinctrl-lpass-lpi.h"
12
-
13
-
enum lpass_lpi_functions {
14
-
LPI_MUX_dmic1_clk,
15
-
LPI_MUX_dmic1_data,
16
-
LPI_MUX_dmic2_clk,
17
-
LPI_MUX_dmic2_data,
18
-
LPI_MUX_dmic3_clk,
19
-
LPI_MUX_dmic3_data,
20
-
LPI_MUX_i2s1_clk,
21
-
LPI_MUX_i2s1_data,
22
-
LPI_MUX_i2s1_ws,
23
-
LPI_MUX_i2s2_clk,
24
-
LPI_MUX_i2s2_data,
25
-
LPI_MUX_i2s2_ws,
26
-
LPI_MUX_qua_mi2s_data,
27
-
LPI_MUX_qua_mi2s_sclk,
28
-
LPI_MUX_qua_mi2s_ws,
29
-
LPI_MUX_swr_rx_clk,
30
-
LPI_MUX_swr_rx_data,
31
-
LPI_MUX_swr_tx_clk,
32
-
LPI_MUX_swr_tx_data,
33
-
LPI_MUX_wsa_swr_clk,
34
-
LPI_MUX_wsa_swr_data,
35
-
LPI_MUX_gpio,
36
-
LPI_MUX__,
37
-
};
38
-
39
-
static const struct pinctrl_pin_desc sm8350_lpi_pins[] = {
40
-
PINCTRL_PIN(0, "gpio0"),
41
-
PINCTRL_PIN(1, "gpio1"),
42
-
PINCTRL_PIN(2, "gpio2"),
43
-
PINCTRL_PIN(3, "gpio3"),
44
-
PINCTRL_PIN(4, "gpio4"),
45
-
PINCTRL_PIN(5, "gpio5"),
46
-
PINCTRL_PIN(6, "gpio6"),
47
-
PINCTRL_PIN(7, "gpio7"),
48
-
PINCTRL_PIN(8, "gpio8"),
49
-
PINCTRL_PIN(9, "gpio9"),
50
-
PINCTRL_PIN(10, "gpio10"),
51
-
PINCTRL_PIN(11, "gpio11"),
52
-
PINCTRL_PIN(12, "gpio12"),
53
-
PINCTRL_PIN(13, "gpio13"),
54
-
PINCTRL_PIN(14, "gpio14"),
55
-
};
56
-
57
-
static const char * const swr_tx_clk_groups[] = { "gpio0" };
58
-
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5", "gpio14" };
59
-
static const char * const swr_rx_clk_groups[] = { "gpio3" };
60
-
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
61
-
static const char * const dmic1_clk_groups[] = { "gpio6" };
62
-
static const char * const dmic1_data_groups[] = { "gpio7" };
63
-
static const char * const dmic2_clk_groups[] = { "gpio8" };
64
-
static const char * const dmic2_data_groups[] = { "gpio9" };
65
-
static const char * const i2s2_clk_groups[] = { "gpio10" };
66
-
static const char * const i2s2_ws_groups[] = { "gpio11" };
67
-
static const char * const dmic3_clk_groups[] = { "gpio12" };
68
-
static const char * const dmic3_data_groups[] = { "gpio13" };
69
-
static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
70
-
static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
71
-
static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
72
-
static const char * const i2s1_clk_groups[] = { "gpio6" };
73
-
static const char * const i2s1_ws_groups[] = { "gpio7" };
74
-
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
75
-
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
76
-
static const char * const wsa_swr_data_groups[] = { "gpio11" };
77
-
static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
78
-
79
-
static const struct lpi_pingroup sm8350_groups[] = {
80
-
LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
81
-
LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
82
-
LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
83
-
LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
84
-
LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
85
-
LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
86
-
LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
87
-
LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
88
-
LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
89
-
LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _),
90
-
LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
91
-
LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
92
-
LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
93
-
LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _),
94
-
LPI_PINGROUP(14, 6, swr_tx_data, _, _, _),
95
-
};
96
-
97
-
static const struct lpi_function sm8350_functions[] = {
98
-
LPI_FUNCTION(dmic1_clk),
99
-
LPI_FUNCTION(dmic1_data),
100
-
LPI_FUNCTION(dmic2_clk),
101
-
LPI_FUNCTION(dmic2_data),
102
-
LPI_FUNCTION(dmic3_clk),
103
-
LPI_FUNCTION(dmic3_data),
104
-
LPI_FUNCTION(i2s1_clk),
105
-
LPI_FUNCTION(i2s1_data),
106
-
LPI_FUNCTION(i2s1_ws),
107
-
LPI_FUNCTION(i2s2_clk),
108
-
LPI_FUNCTION(i2s2_data),
109
-
LPI_FUNCTION(i2s2_ws),
110
-
LPI_FUNCTION(qua_mi2s_data),
111
-
LPI_FUNCTION(qua_mi2s_sclk),
112
-
LPI_FUNCTION(qua_mi2s_ws),
113
-
LPI_FUNCTION(swr_rx_clk),
114
-
LPI_FUNCTION(swr_rx_data),
115
-
LPI_FUNCTION(swr_tx_clk),
116
-
LPI_FUNCTION(swr_tx_data),
117
-
LPI_FUNCTION(wsa_swr_clk),
118
-
LPI_FUNCTION(wsa_swr_data),
119
-
};
120
-
121
-
static const struct lpi_pinctrl_variant_data sm8350_lpi_data = {
122
-
.pins = sm8350_lpi_pins,
123
-
.npins = ARRAY_SIZE(sm8350_lpi_pins),
124
-
.groups = sm8350_groups,
125
-
.ngroups = ARRAY_SIZE(sm8350_groups),
126
-
.functions = sm8350_functions,
127
-
.nfunctions = ARRAY_SIZE(sm8350_functions),
128
-
};
129
-
130
-
static const struct of_device_id lpi_pinctrl_of_match[] = {
131
-
{
132
-
.compatible = "qcom,sm8350-lpass-lpi-pinctrl",
133
-
.data = &sm8350_lpi_data,
134
-
},
135
-
{ }
136
-
};
137
-
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
138
-
139
-
static struct platform_driver lpi_pinctrl_driver = {
140
-
.driver = {
141
-
.name = "qcom-sm8350-lpass-lpi-pinctrl",
142
-
.of_match_table = lpi_pinctrl_of_match,
143
-
},
144
-
.probe = lpi_pinctrl_probe,
145
-
.remove = lpi_pinctrl_remove,
146
-
};
147
-
module_platform_driver(lpi_pinctrl_driver);
148
-
149
-
MODULE_AUTHOR("Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>");
150
-
MODULE_DESCRIPTION("QTI SM8350 LPI GPIO pin control driver");
151
-
MODULE_LICENSE("GPL");