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drm/amdgpu: renovate sdma fw struct

Add sdma firmware struct version 2 to support new SDMA v6 and forward
firmware version.

v2: squash in fix

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Likun Gao and committed by
Alex Deucher 8e070831 a8bc8923

+25
+11
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
··· 244 244 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 245 245 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 246 246 } 247 + } else if (version_major == 2) { 248 + const struct sdma_firmware_header_v2_0 *sdma_hdr = 249 + container_of(hdr, struct sdma_firmware_header_v2_0, header); 250 + 251 + DRM_DEBUG("ucode_feature_version: %u\n", 252 + le32_to_cpu(sdma_hdr->ucode_feature_version)); 253 + DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset)); 254 + DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size)); 255 + DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset)); 256 + DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset)); 257 + DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size)); 247 258 } else { 248 259 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 249 260 version_major, version_minor);
+14
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
··· 281 281 uint32_t digest_size; 282 282 }; 283 283 284 + /* version_major=2, version_minor=0 */ 285 + struct sdma_firmware_header_v2_0 { 286 + struct common_firmware_header header; 287 + uint32_t ucode_feature_version; 288 + uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ 289 + uint32_t ctx_jt_offset; /* context thread jt location */ 290 + uint32_t ctx_jt_size; /* context thread size of jt */ 291 + uint32_t ctl_ucode_offset; 292 + uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ 293 + uint32_t ctl_jt_offset; /* control thread jt location */ 294 + uint32_t ctl_jt_size; /* control thread size of jt */ 295 + }; 296 + 284 297 /* gpu info payload */ 285 298 struct gpu_info_firmware_v1_0 { 286 299 uint32_t gc_num_se; ··· 377 364 struct rlc_firmware_header_v2_3 rlc_v2_3; 378 365 struct sdma_firmware_header_v1_0 sdma; 379 366 struct sdma_firmware_header_v1_1 sdma_v1_1; 367 + struct sdma_firmware_header_v2_0 sdma_v2_0; 380 368 struct gpu_info_firmware_header_v1_0 gpu_info; 381 369 struct dmcu_firmware_header_v1_0 dmcu; 382 370 struct dmcub_firmware_header_v1_0 dmcub;