Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpio: sifive: use new generic GPIO chip API
Convert the driver to using the new generic GPIO chip interfaces from
linux/gpio/generic.h.
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250910-gpio-mmio-gpio-conv-part4-v2-11-f3d1a4c57124@linaro.org
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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drivers/gpio/gpio-sifive.c
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drivers/gpio/gpio-sifive.c
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio/generic.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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struct sifive_gpio {
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void __iomem *base;
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struct gpio_chip gc;
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struct gpio_generic_chip gen_gc;
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struct regmap *regs;
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unsigned long irq_state;
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unsigned int trigger[SIFIVE_GPIO_MAX];
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static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
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{
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unsigned long flags;
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unsigned int trigger;
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raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
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guard(gpio_generic_lock_irqsave)(&chip->gen_gc);
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trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;
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regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),
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(trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0);
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(trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0);
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regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),
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(trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0);
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raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
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}
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static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
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}
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static void sifive_gpio_irq_enable(struct irq_data *d)
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{
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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int offset = hwirq % SIFIVE_GPIO_MAX;
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u32 bit = BIT(offset);
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unsigned long flags;
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gpiochip_enable_irq(gc, hwirq);
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irq_chip_enable_parent(d);
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/* Switch to input */
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gc->direction_input(gc, offset);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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/* Clear any sticky pending interrupts */
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regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) {
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/* Clear any sticky pending interrupts */
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regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
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}
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/* Enable interrupts */
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assign_bit(offset, &chip->irq_state, 1);
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struct sifive_gpio *chip = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
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u32 bit = BIT(offset);
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unsigned long flags;
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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/* Clear all pending interrupts */
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regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) {
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/* Clear all pending interrupts */
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regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
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regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
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}
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irq_chip_eoi_parent(d);
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}
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static int sifive_gpio_probe(struct platform_device *pdev)
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{
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struct gpio_generic_chip_config config;
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struct device *dev = &pdev->dev;
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struct irq_domain *parent;
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struct gpio_irq_chip *girq;
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*/
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parent = irq_get_irq_data(chip->irq_number[0])->domain;
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ret = bgpio_init(&chip->gc, dev, 4,
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chip->base + SIFIVE_GPIO_INPUT_VAL,
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chip->base + SIFIVE_GPIO_OUTPUT_VAL,
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NULL,
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chip->base + SIFIVE_GPIO_OUTPUT_EN,
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chip->base + SIFIVE_GPIO_INPUT_EN,
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BGPIOF_READ_OUTPUT_REG_SET);
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config = (struct gpio_generic_chip_config) {
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.dev = dev,
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.sz = 4,
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.dat = chip->base + SIFIVE_GPIO_INPUT_VAL,
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.set = chip->base + SIFIVE_GPIO_OUTPUT_VAL,
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.dirout = chip->base + SIFIVE_GPIO_OUTPUT_EN,
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.dirin = chip->base + SIFIVE_GPIO_INPUT_EN,
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.flags = BGPIOF_READ_OUTPUT_REG_SET,
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};
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ret = gpio_generic_chip_init(&chip->gen_gc, &config);
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if (ret) {
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dev_err(dev, "unable to init generic GPIO\n");
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return ret;
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regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);
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chip->irq_state = 0;
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chip->gc.base = -1;
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chip->gc.ngpio = ngpio;
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chip->gc.label = dev_name(dev);
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chip->gc.parent = dev;
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chip->gc.owner = THIS_MODULE;
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girq = &chip->gc.irq;
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chip->gen_gc.gc.base = -1;
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chip->gen_gc.gc.ngpio = ngpio;
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chip->gen_gc.gc.label = dev_name(dev);
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chip->gen_gc.gc.parent = dev;
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chip->gen_gc.gc.owner = THIS_MODULE;
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girq = &chip->gen_gc.gc.irq;
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gpio_irq_chip_set_chip(girq, &sifive_gpio_irqchip);
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girq->fwnode = dev_fwnode(dev);
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girq->parent_domain = parent;
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girq->handler = handle_bad_irq;
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girq->default_type = IRQ_TYPE_NONE;
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return gpiochip_add_data(&chip->gc, chip);
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return gpiochip_add_data(&chip->gen_gc.gc, chip);
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}
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static const struct of_device_id sifive_gpio_match[] = {