Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Some new drivers is the main part, the rest is cleanups and nonurgent
fixes.
Nothing much special about this, no core changes this time.
New drivers:
- Renesas RZ/V2H(P) SoC
- NXP Freescale i.MX91 SoC
- Nuvoton MA35D1 SoC
- Qualcomm PMC8380, SM4250, SM4250 LPI
Enhancements:
- A slew of scoped-based simplifications of of_node_put()"
* tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits)
pinctrl: renesas: rzg2l: Support output enable on RZ/G2L
pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions
pinctrl: renesas: rzg2l: Clarify OEN read/write support
dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description
dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function
dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties
pinctrl: freescale: Use scope based of_node_put() cleanups
pinctrl: equilibrium: Use scope based of_node_put() cleanups
pinctrl: ti: iodelay: Use scope based of_node_put() cleanups
pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32
pinctrl: cy8c95x0: Update cache modification
pinctrl: cy8c95x0: Use cleanup.h
pinctrl: renesas: r8a779h0: Remove unneeded separators
pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function
pinctrl: renesas: r8a779g0: Remove unneeded separators
pinctrl: renesas: r8a779h0: Add AVB MII pins and groups
pinctrl: renesas: r8a779g0: Fix TPU suffixes
pinctrl: renesas: r8a779g0: Fix TCLK suffixes
pinctrl: renesas: r8a779g0: FIX PWM suffixes
pinctrl: renesas: r8a779g0: Fix IRQ suffixes
...
+7436
-1967
+3
-1
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
+3
-1
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
+53
Documentation/devicetree/bindings/firmware/nxp,imx95-scmi-pinctrl.yaml
+53
Documentation/devicetree/bindings/firmware/nxp,imx95-scmi-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
# Copyright 2024 NXP
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/firmware/nxp,imx95-scmi-pinctrl.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: i.MX System Control and Management Interface (SCMI) Pinctrl Protocol
9
+
10
+
maintainers:
11
+
- Peng Fan <peng.fan@nxp.com>
12
+
13
+
allOf:
14
+
- $ref: /schemas/pinctrl/pinctrl.yaml
15
+
16
+
patternProperties:
17
+
'grp$':
18
+
type: object
19
+
description:
20
+
Pinctrl node's client devices use subnodes for desired pin configuration.
21
+
Client device subnodes use below standard properties.
22
+
23
+
unevaluatedProperties: false
24
+
25
+
properties:
26
+
fsl,pins:
27
+
description:
28
+
each entry consists of 6 integers and represents the mux and config
29
+
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
30
+
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
31
+
be found in <arch/arm64/boot/dts/freescale/imx95-pinfunc.h>. The last
32
+
integer CONFIG is the pad setting value like pull-up on this pin.
33
+
Please refer to i.MX95 Reference Manual for detailed CONFIG settings.
34
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
35
+
items:
36
+
items:
37
+
- description: |
38
+
"mux_reg" indicates the offset of mux register.
39
+
- description: |
40
+
"conf_reg" indicates the offset of pad configuration register.
41
+
- description: |
42
+
"input_reg" indicates the offset of select input register.
43
+
- description: |
44
+
"mux_val" indicates the mux value to be applied.
45
+
- description: |
46
+
"input_val" indicates the select input value to be applied.
47
+
- description: |
48
+
"pad_setting" indicates the pad configuration value to be applied.
49
+
50
+
required:
51
+
- fsl,pins
52
+
53
+
additionalProperties: true
+153
-16
Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
+153
-16
Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
···
35
35
36
36
patternProperties:
37
37
"^function|groups$":
38
-
enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
39
-
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
40
-
EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0,
41
-
GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4,
42
-
I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK,
43
-
MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2,
44
-
NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4,
45
-
NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0,
46
-
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
47
-
RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3,
48
-
RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD,
49
-
SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO,
50
-
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU,
51
-
SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2,
52
-
TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM,
53
-
VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2]
38
+
enum:
39
+
- ACPI
40
+
- ADC0
41
+
- ADC1
42
+
- ADC10
43
+
- ADC11
44
+
- ADC12
45
+
- ADC13
46
+
- ADC14
47
+
- ADC15
48
+
- ADC2
49
+
- ADC3
50
+
- ADC4
51
+
- ADC5
52
+
- ADC6
53
+
- ADC7
54
+
- ADC8
55
+
- ADC9
56
+
- BMCINT
57
+
- DDCCLK
58
+
- DDCDAT
59
+
- EXTRST
60
+
- FLACK
61
+
- FLBUSY
62
+
- FLWP
63
+
- GPID
64
+
- GPID0
65
+
- GPID2
66
+
- GPID4
67
+
- GPID6
68
+
- GPIE0
69
+
- GPIE2
70
+
- GPIE4
71
+
- GPIE6
72
+
- I2C10
73
+
- I2C11
74
+
- I2C12
75
+
- I2C13
76
+
- I2C14
77
+
- I2C3
78
+
- I2C4
79
+
- I2C5
80
+
- I2C6
81
+
- I2C7
82
+
- I2C8
83
+
- I2C9
84
+
- LPCPD
85
+
- LPCPME
86
+
- LPCRST
87
+
- LPCSMI
88
+
- MAC1LINK
89
+
- MAC2LINK
90
+
- MDIO1
91
+
- MDIO2
92
+
- NCTS1
93
+
- NCTS2
94
+
- NCTS3
95
+
- NCTS4
96
+
- NDCD1
97
+
- NDCD2
98
+
- NDCD3
99
+
- NDCD4
100
+
- NDSR1
101
+
- NDSR2
102
+
- NDSR3
103
+
- NDSR4
104
+
- NDTR1
105
+
- NDTR2
106
+
- NDTR3
107
+
- NDTR4
108
+
- NDTS4
109
+
- NRI1
110
+
- NRI2
111
+
- NRI3
112
+
- NRI4
113
+
- NRTS1
114
+
- NRTS2
115
+
- NRTS3
116
+
- OSCCLK
117
+
- PWM0
118
+
- PWM1
119
+
- PWM2
120
+
- PWM3
121
+
- PWM4
122
+
- PWM5
123
+
- PWM6
124
+
- PWM7
125
+
- RGMII1
126
+
- RGMII2
127
+
- RMII1
128
+
- RMII2
129
+
- ROM16
130
+
- ROM8
131
+
- ROMCS1
132
+
- ROMCS2
133
+
- ROMCS3
134
+
- ROMCS4
135
+
- RXD1
136
+
- RXD2
137
+
- RXD3
138
+
- RXD4
139
+
- SALT1
140
+
- SALT2
141
+
- SALT3
142
+
- SALT4
143
+
- SD1
144
+
- SD2
145
+
- SGPMCK
146
+
- SGPMI
147
+
- SGPMLD
148
+
- SGPMO
149
+
- SGPSCK
150
+
- SGPSI0
151
+
- SGPSI1
152
+
- SGPSLD
153
+
- SIOONCTRL
154
+
- SIOPBI
155
+
- SIOPBO
156
+
- SIOPWREQ
157
+
- SIOPWRGD
158
+
- SIOS3
159
+
- SIOS5
160
+
- SIOSCI
161
+
- SPI1
162
+
- SPI1DEBUG
163
+
- SPI1PASSTHRU
164
+
- SPICS1
165
+
- TIMER3
166
+
- TIMER4
167
+
- TIMER5
168
+
- TIMER6
169
+
- TIMER7
170
+
- TIMER8
171
+
- TXD1
172
+
- TXD2
173
+
- TXD3
174
+
- TXD4
175
+
- UART6
176
+
- USB11D1
177
+
- USB11H2
178
+
- USB2D1
179
+
- USB2H1
180
+
- USBCKI
181
+
- VGABIOS_ROM
182
+
- VGAHS
183
+
- VGAVS
184
+
- VPI18
185
+
- VPI24
186
+
- VPI30
187
+
- VPO12
188
+
- VPO24
189
+
- WDTRST1
190
+
- WDTRST2
54
191
55
192
allOf:
56
193
- $ref: pinctrl.yaml#
+169
-19
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
+169
-19
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
···
35
35
description: |
36
36
A cell of phandles to external controller nodes:
37
37
0: compatible with "aspeed,ast2500-gfx", "syscon"
38
-
1: compatible with "aspeed,ast2500-lhc", "syscon"
38
+
1: compatible with "aspeed,ast2500-lpc", "syscon"
39
39
40
40
additionalProperties:
41
41
$ref: pinmux-node.yaml#
···
47
47
48
48
patternProperties:
49
49
"^function|groups$":
50
-
enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
51
-
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
52
-
ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2,
53
-
GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5,
54
-
I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC,
55
-
LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK,
56
-
MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
57
-
NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2,
58
-
NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0,
59
-
PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
60
-
RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13,
61
-
SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1,
62
-
SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
63
-
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG,
64
-
SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3,
65
-
TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6,
66
-
USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS,
67
-
VGAVS, VPI24, VPO, WDTRST1, WDTRST2]
50
+
enum:
51
+
- ACPI
52
+
- ADC0
53
+
- ADC1
54
+
- ADC10
55
+
- ADC11
56
+
- ADC12
57
+
- ADC13
58
+
- ADC14
59
+
- ADC15
60
+
- ADC2
61
+
- ADC3
62
+
- ADC4
63
+
- ADC5
64
+
- ADC6
65
+
- ADC7
66
+
- ADC8
67
+
- ADC9
68
+
- BMCINT
69
+
- DDCCLK
70
+
- DDCDAT
71
+
- ESPI
72
+
- FWSPICS1
73
+
- FWSPICS2
74
+
- GPID0
75
+
- GPID2
76
+
- GPID4
77
+
- GPID6
78
+
- GPIE0
79
+
- GPIE2
80
+
- GPIE4
81
+
- GPIE6
82
+
- I2C10
83
+
- I2C11
84
+
- I2C12
85
+
- I2C13
86
+
- I2C14
87
+
- I2C3
88
+
- I2C4
89
+
- I2C5
90
+
- I2C6
91
+
- I2C7
92
+
- I2C8
93
+
- I2C9
94
+
- LAD0
95
+
- LAD1
96
+
- LAD2
97
+
- LAD3
98
+
- LCLK
99
+
- LFRAME
100
+
- LPCHC
101
+
- LPCPD
102
+
- LPCPLUS
103
+
- LPCPME
104
+
- LPCRST
105
+
- LPCSMI
106
+
- LSIRQ
107
+
- MAC1LINK
108
+
- MAC2LINK
109
+
- MDIO1
110
+
- MDIO2
111
+
- NCTS1
112
+
- NCTS2
113
+
- NCTS3
114
+
- NCTS4
115
+
- NDCD1
116
+
- NDCD2
117
+
- NDCD3
118
+
- NDCD4
119
+
- NDSR1
120
+
- NDSR2
121
+
- NDSR3
122
+
- NDSR4
123
+
- NDTR1
124
+
- NDTR2
125
+
- NDTR3
126
+
- NDTR4
127
+
- NRI1
128
+
- NRI2
129
+
- NRI3
130
+
- NRI4
131
+
- NRTS1
132
+
- NRTS2
133
+
- NRTS3
134
+
- NRTS4
135
+
- OSCCLK
136
+
- PEWAKE
137
+
- PNOR
138
+
- PWM0
139
+
- PWM1
140
+
- PWM2
141
+
- PWM3
142
+
- PWM4
143
+
- PWM5
144
+
- PWM6
145
+
- PWM7
146
+
- RGMII1
147
+
- RGMII2
148
+
- RMII1
149
+
- RMII2
150
+
- RXD1
151
+
- RXD2
152
+
- RXD3
153
+
- RXD4
154
+
- SALT1
155
+
- SALT10
156
+
- SALT11
157
+
- SALT12
158
+
- SALT13
159
+
- SALT14
160
+
- SALT2
161
+
- SALT3
162
+
- SALT4
163
+
- SALT5
164
+
- SALT6
165
+
- SALT7
166
+
- SALT8
167
+
- SALT9
168
+
- SCL1
169
+
- SCL2
170
+
- SD1
171
+
- SD2
172
+
- SDA1
173
+
- SDA2
174
+
- SGPM
175
+
- SGPS1
176
+
- SGPS2
177
+
- SIOONCTRL
178
+
- SIOPBI
179
+
- SIOPBO
180
+
- SIOPWREQ
181
+
- SIOPWRGD
182
+
- SIOS3
183
+
- SIOS5
184
+
- SIOSCI
185
+
- SPI1
186
+
- SPI1CS1
187
+
- SPI1DEBUG
188
+
- SPI1PASSTHRU
189
+
- SPI2CK
190
+
- SPI2CS0
191
+
- SPI2CS1
192
+
- SPI2MISO
193
+
- SPI2MOSI
194
+
- TIMER3
195
+
- TIMER4
196
+
- TIMER5
197
+
- TIMER6
198
+
- TIMER7
199
+
- TIMER8
200
+
- TXD1
201
+
- TXD2
202
+
- TXD3
203
+
- TXD4
204
+
- UART6
205
+
- USB11BHID
206
+
- USB2AD
207
+
- USB2AH
208
+
- USB2BD
209
+
- USB2BH
210
+
- USBCKI
211
+
- VGABIOSROM
212
+
- VGAHS
213
+
- VGAVS
214
+
- VPI24
215
+
- VPO
216
+
- WDTRST1
217
+
- WDTRST2
68
218
69
219
allOf:
70
220
- $ref: pinctrl.yaml#
+466
-48
Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
+466
-48
Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
···
19
19
Refer to the bindings described in
20
20
Documentation/devicetree/bindings/mfd/syscon.yaml
21
21
22
+
Note: According to the NCSI specification, the reference clock output pin
23
+
(RMIIXRCLKO) is not required on the management controller side. To optimize
24
+
pin usage, add "NCSI" pin groups that are equivalent to the RMII pin groups,
25
+
but without the RMIIXRCLKO pin.
26
+
22
27
properties:
23
28
compatible:
24
29
const: aspeed,ast2600-pinctrl
···
34
29
35
30
properties:
36
31
function:
37
-
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
38
-
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
39
-
FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
40
-
GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
41
-
GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16,
42
-
I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5,
43
-
I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
44
-
MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4,
45
-
NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2,
46
-
NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
47
-
NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11,
48
-
PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8,
49
-
PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
50
-
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
51
-
SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8,
52
-
SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
53
-
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
54
-
SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14,
55
-
TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
56
-
THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
57
-
UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
58
-
USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ]
32
+
enum:
33
+
- ADC0
34
+
- ADC1
35
+
- ADC10
36
+
- ADC11
37
+
- ADC12
38
+
- ADC13
39
+
- ADC14
40
+
- ADC15
41
+
- ADC2
42
+
- ADC3
43
+
- ADC4
44
+
- ADC5
45
+
- ADC6
46
+
- ADC7
47
+
- ADC8
48
+
- ADC9
49
+
- BMCINT
50
+
- EMMC
51
+
- ESPI
52
+
- ESPIALT
53
+
- FSI1
54
+
- FSI2
55
+
- FWQSPI
56
+
- FWSPIABR
57
+
- FWSPID
58
+
- FWSPIWP
59
+
- GPIT0
60
+
- GPIT1
61
+
- GPIT2
62
+
- GPIT3
63
+
- GPIT4
64
+
- GPIT5
65
+
- GPIT6
66
+
- GPIT7
67
+
- GPIU0
68
+
- GPIU1
69
+
- GPIU2
70
+
- GPIU3
71
+
- GPIU4
72
+
- GPIU5
73
+
- GPIU6
74
+
- GPIU7
75
+
- I2C1
76
+
- I2C10
77
+
- I2C11
78
+
- I2C12
79
+
- I2C13
80
+
- I2C14
81
+
- I2C15
82
+
- I2C16
83
+
- I2C2
84
+
- I2C3
85
+
- I2C4
86
+
- I2C5
87
+
- I2C6
88
+
- I2C7
89
+
- I2C8
90
+
- I2C9
91
+
- I3C1
92
+
- I3C2
93
+
- I3C3
94
+
- I3C4
95
+
- I3C5
96
+
- I3C6
97
+
- JTAGM
98
+
- LHPD
99
+
- LHSIRQ
100
+
- LPC
101
+
- LPCHC
102
+
- LPCPD
103
+
- LPCPME
104
+
- LPCSMI
105
+
- LSIRQ
106
+
- MACLINK1
107
+
- MACLINK2
108
+
- MACLINK3
109
+
- MACLINK4
110
+
- MDIO1
111
+
- MDIO2
112
+
- MDIO3
113
+
- MDIO4
114
+
- NCTS1
115
+
- NCTS2
116
+
- NCTS3
117
+
- NCTS4
118
+
- NDCD1
119
+
- NDCD2
120
+
- NDCD3
121
+
- NDCD4
122
+
- NDSR1
123
+
- NDSR2
124
+
- NDSR3
125
+
- NDSR4
126
+
- NDTR1
127
+
- NDTR2
128
+
- NDTR3
129
+
- NDTR4
130
+
- NRI1
131
+
- NRI2
132
+
- NRI3
133
+
- NRI4
134
+
- NRTS1
135
+
- NRTS2
136
+
- NRTS3
137
+
- NRTS4
138
+
- OSCCLK
139
+
- PEWAKE
140
+
- PWM0
141
+
- PWM1
142
+
- PWM10
143
+
- PWM11
144
+
- PWM12
145
+
- PWM13
146
+
- PWM14
147
+
- PWM15
148
+
- PWM2
149
+
- PWM3
150
+
- PWM4
151
+
- PWM5
152
+
- PWM6
153
+
- PWM7
154
+
- PWM8
155
+
- PWM9
156
+
- RGMII1
157
+
- RGMII2
158
+
- RGMII3
159
+
- RGMII4
160
+
- RMII1
161
+
- RMII2
162
+
- RMII3
163
+
- RMII4
164
+
- RXD1
165
+
- RXD2
166
+
- RXD3
167
+
- RXD4
168
+
- SALT1
169
+
- SALT10
170
+
- SALT11
171
+
- SALT12
172
+
- SALT13
173
+
- SALT14
174
+
- SALT15
175
+
- SALT16
176
+
- SALT2
177
+
- SALT3
178
+
- SALT4
179
+
- SALT5
180
+
- SALT6
181
+
- SALT7
182
+
- SALT8
183
+
- SALT9
184
+
- SD1
185
+
- SD2
186
+
- SGPM1
187
+
- SGPM2
188
+
- SGPS1
189
+
- SGPS2
190
+
- SIOONCTRL
191
+
- SIOPBI
192
+
- SIOPBO
193
+
- SIOPWREQ
194
+
- SIOPWRGD
195
+
- SIOS3
196
+
- SIOS5
197
+
- SIOSCI
198
+
- SPI1
199
+
- SPI1ABR
200
+
- SPI1CS1
201
+
- SPI1WP
202
+
- SPI2
203
+
- SPI2CS1
204
+
- SPI2CS2
205
+
- TACH0
206
+
- TACH1
207
+
- TACH10
208
+
- TACH11
209
+
- TACH12
210
+
- TACH13
211
+
- TACH14
212
+
- TACH15
213
+
- TACH2
214
+
- TACH3
215
+
- TACH4
216
+
- TACH5
217
+
- TACH6
218
+
- TACH7
219
+
- TACH8
220
+
- TACH9
221
+
- THRU0
222
+
- THRU1
223
+
- THRU2
224
+
- THRU3
225
+
- TXD1
226
+
- TXD2
227
+
- TXD3
228
+
- TXD4
229
+
- UART10
230
+
- UART11
231
+
- UART12
232
+
- UART13
233
+
- UART6
234
+
- UART7
235
+
- UART8
236
+
- UART9
237
+
- USB11BHID
238
+
- USB2AD
239
+
- USB2AH
240
+
- USB2AHP
241
+
- USB2BD
242
+
- USB2BH
243
+
- USBAD
244
+
- USBADP
245
+
- VB
246
+
- VGAHS
247
+
- VGAVS
248
+
- WDTRST1
249
+
- WDTRST2
250
+
- WDTRST3
251
+
- WDTRST4
59
252
60
253
groups:
61
-
enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
62
-
ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
63
-
EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP,
64
-
GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
65
-
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10,
66
-
I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5,
67
-
I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
68
-
LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3,
69
-
MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4,
70
-
NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
71
-
NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
72
-
OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0,
73
-
PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2,
74
-
PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
75
-
QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
76
-
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1,
77
-
SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0,
78
-
SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6,
79
-
SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2,
80
-
SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
81
-
SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
82
-
TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6,
83
-
TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3,
84
-
TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
85
-
UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
86
-
WDTRST3, WDTRST4]
254
+
enum:
255
+
- ADC0
256
+
- ADC1
257
+
- ADC10
258
+
- ADC11
259
+
- ADC12
260
+
- ADC13
261
+
- ADC14
262
+
- ADC15
263
+
- ADC2
264
+
- ADC3
265
+
- ADC4
266
+
- ADC5
267
+
- ADC6
268
+
- ADC7
269
+
- ADC8
270
+
- ADC9
271
+
- BMCINT
272
+
- EMMCG1
273
+
- EMMCG4
274
+
- EMMCG8
275
+
- ESPI
276
+
- ESPIALT
277
+
- FSI1
278
+
- FSI2
279
+
- FWQSPI
280
+
- FWSPIABR
281
+
- FWSPID
282
+
- FWSPIWP
283
+
- GPIT0
284
+
- GPIT1
285
+
- GPIT2
286
+
- GPIT3
287
+
- GPIT4
288
+
- GPIT5
289
+
- GPIT6
290
+
- GPIT7
291
+
- GPIU0
292
+
- GPIU1
293
+
- GPIU2
294
+
- GPIU3
295
+
- GPIU4
296
+
- GPIU5
297
+
- GPIU6
298
+
- GPIU7
299
+
- HVI3C3
300
+
- HVI3C4
301
+
- I2C1
302
+
- I2C10
303
+
- I2C11
304
+
- I2C12
305
+
- I2C13
306
+
- I2C14
307
+
- I2C15
308
+
- I2C16
309
+
- I2C2
310
+
- I2C3
311
+
- I2C4
312
+
- I2C5
313
+
- I2C6
314
+
- I2C7
315
+
- I2C8
316
+
- I2C9
317
+
- I3C1
318
+
- I3C2
319
+
- I3C3
320
+
- I3C4
321
+
- I3C5
322
+
- I3C6
323
+
- JTAGM
324
+
- LHPD
325
+
- LHSIRQ
326
+
- LPC
327
+
- LPCHC
328
+
- LPCPD
329
+
- LPCPME
330
+
- LPCSMI
331
+
- LSIRQ
332
+
- MACLINK1
333
+
- MACLINK2
334
+
- MACLINK3
335
+
- MACLINK4
336
+
- MDIO1
337
+
- MDIO2
338
+
- MDIO3
339
+
- MDIO4
340
+
- NCSI3
341
+
- NCSI4
342
+
- NCTS1
343
+
- NCTS2
344
+
- NCTS3
345
+
- NCTS4
346
+
- NDCD1
347
+
- NDCD2
348
+
- NDCD3
349
+
- NDCD4
350
+
- NDSR1
351
+
- NDSR2
352
+
- NDSR3
353
+
- NDSR4
354
+
- NDTR1
355
+
- NDTR2
356
+
- NDTR3
357
+
- NDTR4
358
+
- NRI1
359
+
- NRI2
360
+
- NRI3
361
+
- NRI4
362
+
- NRTS1
363
+
- NRTS2
364
+
- NRTS3
365
+
- NRTS4
366
+
- OSCCLK
367
+
- PEWAKE
368
+
- PWM0
369
+
- PWM1
370
+
- PWM10G0
371
+
- PWM10G1
372
+
- PWM11G0
373
+
- PWM11G1
374
+
- PWM12G0
375
+
- PWM12G1
376
+
- PWM13G0
377
+
- PWM13G1
378
+
- PWM14G0
379
+
- PWM14G1
380
+
- PWM15G0
381
+
- PWM15G1
382
+
- PWM2
383
+
- PWM3
384
+
- PWM4
385
+
- PWM5
386
+
- PWM6
387
+
- PWM7
388
+
- PWM8G0
389
+
- PWM8G1
390
+
- PWM9G0
391
+
- PWM9G1
392
+
- QSPI1
393
+
- QSPI2
394
+
- RGMII1
395
+
- RGMII2
396
+
- RGMII3
397
+
- RGMII4
398
+
- RMII1
399
+
- RMII2
400
+
- RMII3
401
+
- RMII4
402
+
- RXD1
403
+
- RXD2
404
+
- RXD3
405
+
- RXD4
406
+
- SALT1
407
+
- SALT10G0
408
+
- SALT10G1
409
+
- SALT11G0
410
+
- SALT11G1
411
+
- SALT12G0
412
+
- SALT12G1
413
+
- SALT13G0
414
+
- SALT13G1
415
+
- SALT14G0
416
+
- SALT14G1
417
+
- SALT15G0
418
+
- SALT15G1
419
+
- SALT16G0
420
+
- SALT16G1
421
+
- SALT2
422
+
- SALT3
423
+
- SALT4
424
+
- SALT5
425
+
- SALT6
426
+
- SALT7
427
+
- SALT8
428
+
- SALT9G0
429
+
- SALT9G1
430
+
- SD1
431
+
- SD2
432
+
- SD3
433
+
- SGPM1
434
+
- SGPM2
435
+
- SGPS1
436
+
- SGPS2
437
+
- SIOONCTRL
438
+
- SIOPBI
439
+
- SIOPBO
440
+
- SIOPWREQ
441
+
- SIOPWRGD
442
+
- SIOS3
443
+
- SIOS5
444
+
- SIOSCI
445
+
- SPI1
446
+
- SPI1ABR
447
+
- SPI1CS1
448
+
- SPI1WP
449
+
- SPI2
450
+
- SPI2CS1
451
+
- SPI2CS2
452
+
- TACH0
453
+
- TACH1
454
+
- TACH10
455
+
- TACH11
456
+
- TACH12
457
+
- TACH13
458
+
- TACH14
459
+
- TACH15
460
+
- TACH2
461
+
- TACH3
462
+
- TACH4
463
+
- TACH5
464
+
- TACH6
465
+
- TACH7
466
+
- TACH8
467
+
- TACH9
468
+
- THRU0
469
+
- THRU1
470
+
- THRU2
471
+
- THRU3
472
+
- TXD1
473
+
- TXD2
474
+
- TXD3
475
+
- TXD4
476
+
- UART10
477
+
- UART11
478
+
- UART12G0
479
+
- UART12G1
480
+
- UART13G0
481
+
- UART13G1
482
+
- UART6
483
+
- UART7
484
+
- UART8
485
+
- UART9
486
+
- USBA
487
+
- USBB
488
+
- VB
489
+
- VGAHS
490
+
- VGAVS
491
+
- WDTRST1
492
+
- WDTRST2
493
+
- WDTRST3
494
+
- WDTRST4
87
495
88
496
pins: true
89
497
bias-disable: true
+5
-3
Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/fsl,imx9-pinctrl.yaml
+5
-3
Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/fsl,imx9-pinctrl.yaml
···
1
1
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml#
4
+
$id: http://devicetree.org/schemas/pinctrl/fsl,imx9-pinctrl.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Freescale IMX93 IOMUX Controller
7
+
title: Freescale IMX9 IOMUX Controller
8
8
9
9
maintainers:
10
10
- Peng Fan <peng.fan@nxp.com>
···
18
18
19
19
properties:
20
20
compatible:
21
-
const: fsl,imx93-iomuxc
21
+
enum:
22
+
- fsl,imx91-iomuxc
23
+
- fsl,imx93-iomuxc
22
24
23
25
reg:
24
26
maxItems: 1
+178
Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
+178
Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Nuvoton MA35D1 pin control and GPIO
8
+
9
+
maintainers:
10
+
- Shan-Chun Hung <schung@nuvoton.com>
11
+
- Jacky Huang <ychuang3@nuvoton.com>
12
+
13
+
allOf:
14
+
- $ref: pinctrl.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- nuvoton,ma35d1-pinctrl
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
'#address-cells':
25
+
const: 1
26
+
27
+
'#size-cells':
28
+
const: 1
29
+
30
+
nuvoton,sys:
31
+
$ref: /schemas/types.yaml#/definitions/phandle
32
+
description:
33
+
phandle of the system-management node.
34
+
35
+
ranges: true
36
+
37
+
patternProperties:
38
+
"^gpio@[0-9a-f]+$":
39
+
type: object
40
+
properties:
41
+
gpio-controller: true
42
+
43
+
'#gpio-cells':
44
+
const: 2
45
+
46
+
reg:
47
+
maxItems: 1
48
+
49
+
clocks:
50
+
maxItems: 1
51
+
52
+
interrupt-controller: true
53
+
54
+
'#interrupt-cells':
55
+
const: 2
56
+
57
+
interrupts:
58
+
description:
59
+
The interrupt outputs to sysirq.
60
+
maxItems: 1
61
+
62
+
required:
63
+
- gpio-controller
64
+
- '#gpio-cells'
65
+
- reg
66
+
- clocks
67
+
- interrupt-controller
68
+
- '#interrupt-cells'
69
+
- interrupts
70
+
71
+
additionalProperties: false
72
+
73
+
"-grp$":
74
+
type: object
75
+
description:
76
+
Pinctrl node's client devices use subnodes for desired pin configuration.
77
+
Client device subnodes use below standard properties.
78
+
patternProperties:
79
+
"-pins$":
80
+
type: object
81
+
description:
82
+
A pinctrl node should contain at least one subnodes representing the
83
+
pinctrl groups available on the machine. Each subnode will list the
84
+
pins it needs, and how they should be configured, with regard to muxer
85
+
configuration, pullups, drive strength, input enable/disable and input
86
+
schmitt.
87
+
$ref: /schemas/pinctrl/pincfg-node.yaml
88
+
89
+
properties:
90
+
nuvoton,pins:
91
+
description:
92
+
Each entry consists of 4 parameters and represents the mux and config
93
+
setting for one pin.
94
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
95
+
minItems: 1
96
+
items:
97
+
items:
98
+
- minimum: 0
99
+
maximum: 13
100
+
description:
101
+
Pin bank.
102
+
- minimum: 0
103
+
maximum: 15
104
+
description:
105
+
Pin bank index.
106
+
- minimum: 0
107
+
maximum: 15
108
+
description:
109
+
Mux 0 means GPIO and mux 1 to 15 means the specific device function.
110
+
111
+
power-source:
112
+
description: |
113
+
Valid arguments are described as below:
114
+
0: power supply of 1.8V
115
+
1: power supply of 3.3V
116
+
enum: [0, 1]
117
+
118
+
drive-strength-microamp:
119
+
oneOf:
120
+
- enum: [ 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000 ]
121
+
description: 1.8V I/O driving strength
122
+
- enum: [ 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000 ]
123
+
description: 3.3V I/O driving strength
124
+
125
+
bias-disable: true
126
+
127
+
bias-pull-up: true
128
+
129
+
bias-pull-down: true
130
+
131
+
input-schmitt-disable: true
132
+
133
+
additionalProperties: false
134
+
135
+
additionalProperties: false
136
+
137
+
required:
138
+
- compatible
139
+
- reg
140
+
- nuvoton,sys
141
+
142
+
additionalProperties: false
143
+
144
+
examples:
145
+
- |
146
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
147
+
#include <dt-bindings/gpio/gpio.h>
148
+
#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
149
+
150
+
pinctrl@40040000 {
151
+
compatible = "nuvoton,ma35d1-pinctrl";
152
+
reg = <0x40040000 0xc00>;
153
+
#address-cells = <1>;
154
+
#size-cells = <1>;
155
+
nuvoton,sys = <&sys>;
156
+
ranges = <0x0 0x40040000 0x400>;
157
+
158
+
gpio@0 {
159
+
reg = <0x0 0x40>;
160
+
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
161
+
clocks = <&clk GPA_GATE>;
162
+
gpio-controller;
163
+
#gpio-cells = <2>;
164
+
interrupt-controller;
165
+
#interrupt-cells = <2>;
166
+
};
167
+
168
+
uart-grp {
169
+
uart11-pins {
170
+
nuvoton,pins = <11 0 2>,
171
+
<11 1 2>,
172
+
<11 2 2>,
173
+
<11 3 2>;
174
+
power-source = <1>;
175
+
bias-disable;
176
+
};
177
+
};
178
+
};
+12
-10
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
+12
-10
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
···
85
85
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
86
86
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
87
87
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
88
-
scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
89
-
spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
90
-
smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
91
-
spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
92
-
hgpio5, hgpio6, hgpio7 ]
88
+
scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
89
+
smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
90
+
spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
91
+
wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
92
+
hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
93
+
bu4b, bu5, bu5b, bu6, gpo187 ]
93
94
94
95
function:
95
96
description:
···
110
109
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
111
110
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
112
111
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
113
-
scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
114
-
spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
115
-
smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
116
-
spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
117
-
hgpio5, hgpio6, hgpio7 ]
112
+
scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
113
+
smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
114
+
spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
115
+
wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
116
+
hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
117
+
bu4b, bu5, bu5b, bu6, gpo187 ]
118
118
119
119
dependencies:
120
120
groups: [ function ]
+12
-5
Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
+12
-5
Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
···
75
75
description: Optional list of pin base, nr pins & gpio function
76
76
$ref: /schemas/types.yaml#/definitions/phandle-array
77
77
items:
78
-
- items:
79
-
- description: phandle of a gpio-range node
80
-
- description: pin base
81
-
- description: number of pins
82
-
- description: gpio function
78
+
items:
79
+
- description: phandle of a gpio-range node
80
+
- description: pin base
81
+
- description: number of pins
82
+
- description: gpio function
83
83
84
84
'#gpio-range-cells':
85
85
description: No longer needed, may exist in older files for gpio-ranges
···
144
144
- description: drive strength mask
145
145
146
146
pinctrl-single,input-schmitt:
147
+
description: Optional schmitt strength configuration
148
+
$ref: /schemas/types.yaml#/definitions/uint32-array
149
+
items:
150
+
- description: schmitt strength current
151
+
- description: schmitt strength mask
152
+
153
+
pinctrl-single,input-schmitt-enable:
147
154
description: Optional input schmitt configuration
148
155
$ref: /schemas/types.yaml#/definitions/uint32-array
149
156
items:
+2
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
+2
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
···
56
56
- qcom,pma8084-gpio
57
57
- qcom,pmc8180-gpio
58
58
- qcom,pmc8180c-gpio
59
+
- qcom,pmc8380-gpio
59
60
- qcom,pmd8028-gpio
60
61
- qcom,pmi632-gpio
61
62
- qcom,pmi8950-gpio
···
224
223
- qcom,pm8150-gpio
225
224
- qcom,pm8350-gpio
226
225
- qcom,pmc8180-gpio
226
+
- qcom,pmc8380-gpio
227
227
- qcom,pmi8994-gpio
228
228
- qcom,pmm8155au-gpio
229
229
then:
+118
Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml
+118
Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SM4250 SoC LPASS LPI TLMM
8
+
9
+
maintainers:
10
+
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11
+
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14
+
(LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,sm4250-lpass-lpi-pinctrl
19
+
20
+
reg:
21
+
items:
22
+
- description: LPASS LPI TLMM Control and Status registers
23
+
- description: LPASS LPI MCC registers
24
+
25
+
clocks:
26
+
items:
27
+
- description: LPASS Audio voting clock
28
+
29
+
clock-names:
30
+
items:
31
+
- const: audio
32
+
33
+
patternProperties:
34
+
"-state$":
35
+
oneOf:
36
+
- $ref: "#/$defs/qcom-sm4250-lpass-state"
37
+
- patternProperties:
38
+
"-pins$":
39
+
$ref: "#/$defs/qcom-sm4250-lpass-state"
40
+
additionalProperties: false
41
+
42
+
$defs:
43
+
qcom-sm4250-lpass-state:
44
+
type: object
45
+
description:
46
+
Pinctrl node's client devices use subnodes for desired pin configuration.
47
+
Client device subnodes use below standard properties.
48
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
49
+
unevaluatedProperties: false
50
+
51
+
properties:
52
+
pins:
53
+
description:
54
+
List of gpio pins affected by the properties specified in this
55
+
subnode.
56
+
items:
57
+
pattern: "^gpio([0-9]|1[0-9]|2[0-6])$"
58
+
59
+
function:
60
+
enum: [ gpio, dmic01_clk, dmic01_data, dmic23_clk, dmic23_data,
61
+
dmic4_clk, dmic4_data, ext_mclk0_a, ext_mclk0_b, ext_mclk1_a,
62
+
ext_mclk1_b, ext_mclk1_c, i2s1_clk, i2s1_data, i2s1_ws,
63
+
i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws,
64
+
qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, slim_clk, slim_data,
65
+
swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, swr_wsa_clk,
66
+
swr_wsa_data ]
67
+
description:
68
+
Specify the alternative function to be configured for the specified
69
+
pins.
70
+
71
+
allOf:
72
+
- $ref: qcom,lpass-lpi-common.yaml#
73
+
74
+
required:
75
+
- compatible
76
+
- reg
77
+
- clocks
78
+
- clock-names
79
+
80
+
unevaluatedProperties: false
81
+
82
+
examples:
83
+
- |
84
+
#include <dt-bindings/sound/qcom,q6afe.h>
85
+
lpi_tlmm: pinctrl@a7c0000 {
86
+
compatible = "qcom,sm4250-lpass-lpi-pinctrl";
87
+
reg = <0xa7c0000 0x20000>,
88
+
<0xa950000 0x10000>;
89
+
clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
90
+
clock-names = "audio";
91
+
gpio-controller;
92
+
#gpio-cells = <2>;
93
+
gpio-ranges = <&lpi_tlmm 0 0 19>;
94
+
95
+
i2s2-active-state {
96
+
clk-pins {
97
+
pins = "gpio10";
98
+
function = "i2s2_clk";
99
+
drive-strength = <2>;
100
+
slew-rate = <1>;
101
+
bias-disable;
102
+
};
103
+
104
+
data-pins {
105
+
pins = "gpio12";
106
+
function = "i2s2_data";
107
+
drive-strength = <2>;
108
+
slew-rate = <1>;
109
+
};
110
+
};
111
+
112
+
i2s2-sleep-clk-state {
113
+
pins = "gpio10";
114
+
function = "i2s2_clk";
115
+
drive-strength = <2>;
116
+
bias-pull-down;
117
+
};
118
+
};
+33
-19
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+33
-19
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
···
26
26
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
27
27
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
28
28
- renesas,r9a08g045-pinctrl # RZ/G3S
29
+
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
29
30
30
31
- items:
31
32
- enum:
···
67
66
maxItems: 1
68
67
69
68
resets:
70
-
items:
71
-
- description: GPIO_RSTN signal
72
-
- description: GPIO_PORT_RESETN signal
73
-
- description: GPIO_SPARE_RESETN signal
69
+
oneOf:
70
+
- items:
71
+
- description: GPIO_RSTN signal
72
+
- description: GPIO_PORT_RESETN signal
73
+
- description: GPIO_SPARE_RESETN signal
74
+
- items:
75
+
- description: PFC main reset
76
+
- description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
74
77
75
78
additionalProperties:
76
79
anyOf:
···
83
78
allOf:
84
79
- $ref: pincfg-node.yaml#
85
80
- $ref: pinmux-node.yaml#
86
-
87
-
- if:
88
-
properties:
89
-
compatible:
90
-
contains:
91
-
enum:
92
-
- renesas,r9a08g045-pinctrl
93
-
then:
94
-
properties:
95
-
drive-strength: false
96
-
output-impedance-ohms: false
97
-
slew-rate: false
98
-
else:
99
-
properties:
100
-
drive-strength-microamp: false
101
81
102
82
description:
103
83
Pin controller client devices use pin configuration subnodes (children
···
116
126
output-high: true
117
127
output-low: true
118
128
line-name: true
129
+
bias-disable: true
130
+
bias-pull-down: true
131
+
bias-pull-up: true
132
+
renesas,output-impedance:
133
+
description:
134
+
Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
135
+
property corresponds to register bit values that can be set in the PFC_IOLH_mn
136
+
register, which adjusts the drive strength value and is pin-dependent.
137
+
$ref: /schemas/types.yaml#/definitions/uint32
138
+
enum: [0, 1, 2, 3]
119
139
120
140
- type: object
121
141
additionalProperties:
···
133
133
134
134
allOf:
135
135
- $ref: pinctrl.yaml#
136
+
137
+
- if:
138
+
properties:
139
+
compatible:
140
+
contains:
141
+
const: renesas,r9a09g057-pinctrl
142
+
then:
143
+
properties:
144
+
resets:
145
+
maxItems: 2
146
+
else:
147
+
properties:
148
+
resets:
149
+
minItems: 3
136
150
137
151
required:
138
152
- compatible
+180
-169
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
+180
-169
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
···
42
42
$ref: pinmux-node.yaml#
43
43
44
44
properties:
45
+
pins:
46
+
description:
47
+
List of pins to select (either this or "groups" must be specified)
48
+
items:
49
+
pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
50
+
45
51
groups:
46
52
description:
47
53
List of groups to select (either this or "pins" must be
48
54
specified), available groups for this subnode.
49
55
items:
50
-
enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
51
-
ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
52
-
gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
53
-
mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
54
-
qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
55
-
spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
56
-
spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
57
-
spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
58
-
spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
59
-
spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
60
-
spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
61
-
spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
62
-
spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
63
-
spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
64
-
spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
65
-
spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
66
-
spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
67
-
spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
68
-
spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
69
-
spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
70
-
spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
71
-
sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
72
-
sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
73
-
sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
74
-
sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
75
-
sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
76
-
sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
77
-
sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
78
-
sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
79
-
sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
80
-
sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
81
-
sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
82
-
sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
83
-
sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
84
-
sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
85
-
sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
86
-
sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
87
-
sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
88
-
sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
89
-
sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
90
-
sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
91
-
sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
92
-
sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
93
-
nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
94
-
nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
95
-
can0_1_grp, can0_2_grp, can0_3_grp,
96
-
can0_4_grp, can0_5_grp, can0_6_grp,
97
-
can0_7_grp, can0_8_grp, can0_9_grp,
98
-
can0_10_grp, can0_11_grp, can0_12_grp,
99
-
can0_13_grp, can0_14_grp, can0_15_grp,
100
-
can0_16_grp, can0_17_grp, can0_18_grp,
101
-
can1_0_grp, can1_1_grp, can1_2_grp,
102
-
can1_3_grp, can1_4_grp, can1_5_grp,
103
-
can1_6_grp, can1_7_grp, can1_8_grp,
104
-
can1_9_grp, can1_10_grp, can1_11_grp,
105
-
can1_12_grp, can1_13_grp, can1_14_grp,
106
-
can1_15_grp, can1_16_grp, can1_17_grp,
107
-
can1_18_grp, can1_19_grp, uart0_0_grp,
108
-
uart0_1_grp, uart0_2_grp, uart0_3_grp,
109
-
uart0_4_grp, uart0_5_grp, uart0_6_grp,
110
-
uart0_7_grp, uart0_8_grp, uart0_9_grp,
111
-
uart0_10_grp, uart0_11_grp, uart0_12_grp,
112
-
uart0_13_grp, uart0_14_grp, uart0_15_grp,
113
-
uart0_16_grp, uart0_17_grp, uart0_18_grp,
114
-
uart1_0_grp, uart1_1_grp, uart1_2_grp,
115
-
uart1_3_grp, uart1_4_grp, uart1_5_grp,
116
-
uart1_6_grp, uart1_7_grp, uart1_8_grp,
117
-
uart1_9_grp, uart1_10_grp, uart1_11_grp,
118
-
uart1_12_grp, uart1_13_grp, uart1_14_grp,
119
-
uart1_15_grp, uart1_16_grp, uart1_17_grp,
120
-
uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
121
-
i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
122
-
i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
123
-
i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
124
-
i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
125
-
i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
126
-
i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
127
-
i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
128
-
i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
129
-
i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
130
-
i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
131
-
i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
132
-
i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
133
-
i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
134
-
ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
135
-
ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
136
-
ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
137
-
ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
138
-
ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
139
-
ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
140
-
ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
141
-
ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
142
-
ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
143
-
ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
144
-
ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
145
-
ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
146
-
ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
147
-
ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
148
-
ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
149
-
ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
150
-
ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
151
-
ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
152
-
ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
153
-
ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
154
-
ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
155
-
ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
156
-
ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
157
-
ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
158
-
swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
159
-
swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
160
-
swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
161
-
swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
162
-
swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
163
-
swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
164
-
swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
165
-
swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
166
-
swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
167
-
swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
168
-
swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
169
-
swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
170
-
swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
171
-
swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
172
-
swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
173
-
swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
174
-
swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
175
-
gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
176
-
gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
177
-
gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
178
-
gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
179
-
gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
180
-
gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
181
-
gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
182
-
gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
183
-
gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
184
-
gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
185
-
gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
186
-
gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
187
-
gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
188
-
gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
189
-
gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
190
-
gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
191
-
gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
192
-
gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
193
-
gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
194
-
gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
195
-
gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
196
-
gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
197
-
gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
198
-
gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
199
-
gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
200
-
gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
201
-
usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
202
-
pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
203
-
pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
204
-
pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
205
-
pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
206
-
pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
207
-
pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
208
-
csu0_0_grp, csu0_1_grp, csu0_2_grp,
209
-
csu0_3_grp, csu0_4_grp, csu0_5_grp,
210
-
csu0_6_grp, csu0_7_grp, csu0_8_grp,
211
-
csu0_9_grp, csu0_10_grp, csu0_11_grp,
212
-
dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
213
-
dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
214
-
pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
215
-
pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
216
-
trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
217
-
trace0_clk_2_grp, testscan0_0_grp]
56
+
anyOf:
57
+
- pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
58
+
- enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
59
+
ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
60
+
gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
61
+
mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
62
+
qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
63
+
spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
64
+
spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
65
+
spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
66
+
spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
67
+
spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
68
+
spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
69
+
spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
70
+
spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
71
+
spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
72
+
spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
73
+
spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
74
+
spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
75
+
spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
76
+
spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
77
+
spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
78
+
spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
79
+
sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
80
+
sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
81
+
sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
82
+
sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
83
+
sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
84
+
sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
85
+
sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
86
+
sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
87
+
sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
88
+
sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
89
+
sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
90
+
sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
91
+
sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
92
+
sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
93
+
sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
94
+
sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
95
+
sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
96
+
sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
97
+
sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
98
+
sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
99
+
sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
100
+
sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
101
+
nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
102
+
nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
103
+
can0_1_grp, can0_2_grp, can0_3_grp,
104
+
can0_4_grp, can0_5_grp, can0_6_grp,
105
+
can0_7_grp, can0_8_grp, can0_9_grp,
106
+
can0_10_grp, can0_11_grp, can0_12_grp,
107
+
can0_13_grp, can0_14_grp, can0_15_grp,
108
+
can0_16_grp, can0_17_grp, can0_18_grp,
109
+
can1_0_grp, can1_1_grp, can1_2_grp,
110
+
can1_3_grp, can1_4_grp, can1_5_grp,
111
+
can1_6_grp, can1_7_grp, can1_8_grp,
112
+
can1_9_grp, can1_10_grp, can1_11_grp,
113
+
can1_12_grp, can1_13_grp, can1_14_grp,
114
+
can1_15_grp, can1_16_grp, can1_17_grp,
115
+
can1_18_grp, can1_19_grp, uart0_0_grp,
116
+
uart0_1_grp, uart0_2_grp, uart0_3_grp,
117
+
uart0_4_grp, uart0_5_grp, uart0_6_grp,
118
+
uart0_7_grp, uart0_8_grp, uart0_9_grp,
119
+
uart0_10_grp, uart0_11_grp, uart0_12_grp,
120
+
uart0_13_grp, uart0_14_grp, uart0_15_grp,
121
+
uart0_16_grp, uart0_17_grp, uart0_18_grp,
122
+
uart1_0_grp, uart1_1_grp, uart1_2_grp,
123
+
uart1_3_grp, uart1_4_grp, uart1_5_grp,
124
+
uart1_6_grp, uart1_7_grp, uart1_8_grp,
125
+
uart1_9_grp, uart1_10_grp, uart1_11_grp,
126
+
uart1_12_grp, uart1_13_grp, uart1_14_grp,
127
+
uart1_15_grp, uart1_16_grp, uart1_17_grp,
128
+
uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
129
+
i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
130
+
i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
131
+
i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
132
+
i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
133
+
i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
134
+
i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
135
+
i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
136
+
i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
137
+
i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
138
+
i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
139
+
i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
140
+
i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
141
+
i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
142
+
ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
143
+
ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
144
+
ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
145
+
ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
146
+
ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
147
+
ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
148
+
ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
149
+
ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
150
+
ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
151
+
ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
152
+
ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
153
+
ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
154
+
ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
155
+
ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
156
+
ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
157
+
ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
158
+
ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
159
+
ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
160
+
ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
161
+
ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
162
+
ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
163
+
ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
164
+
ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
165
+
ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
166
+
swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
167
+
swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
168
+
swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
169
+
swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
170
+
swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
171
+
swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
172
+
swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
173
+
swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
174
+
swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
175
+
swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
176
+
swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
177
+
swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
178
+
swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
179
+
swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
180
+
swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
181
+
swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
182
+
swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
183
+
gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
184
+
gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
185
+
gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
186
+
gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
187
+
gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
188
+
gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
189
+
gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
190
+
gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
191
+
gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
192
+
gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
193
+
gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
194
+
gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
195
+
gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
196
+
gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
197
+
gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
198
+
gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
199
+
gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
200
+
gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
201
+
gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
202
+
gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
203
+
gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
204
+
gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
205
+
gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
206
+
gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
207
+
gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
208
+
gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
209
+
usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
210
+
pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
211
+
pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
212
+
pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
213
+
pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
214
+
pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
215
+
pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
216
+
csu0_0_grp, csu0_1_grp, csu0_2_grp,
217
+
csu0_3_grp, csu0_4_grp, csu0_5_grp,
218
+
csu0_6_grp, csu0_7_grp, csu0_8_grp,
219
+
csu0_9_grp, csu0_10_grp, csu0_11_grp,
220
+
dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
221
+
dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
222
+
pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
223
+
pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
224
+
trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
225
+
trace0_clk_2_grp, testscan0_0_grp]
218
226
maxItems: 78
219
227
220
228
function:
···
238
230
pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0]
239
231
240
232
required:
241
-
- groups
242
233
- function
234
+
235
+
oneOf:
236
+
- required: [ groups ]
237
+
- required: [ pins ]
243
238
244
239
additionalProperties: false
245
240
+2
-1
Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
+2
-1
Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml
···
18
18
compatible:
19
19
items:
20
20
- const: nuvoton,ma35d1-reset
21
+
- const: syscon
21
22
22
23
reg:
23
24
maxItems: 1
···
38
37
- |
39
38
40
39
system-management@40460000 {
41
-
compatible = "nuvoton,ma35d1-reset";
40
+
compatible = "nuvoton,ma35d1-reset", "syscon";
42
41
reg = <0x40460000 0x200>;
43
42
#reset-cells = <1>;
44
43
};
+8
-2
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
+8
-2
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
···
249
249
250
250
FUNC_GROUP_DECL(RGMII3, H24, J22, H22, H23, G22, F22, G23, G24, F23, F26, F25,
251
251
E26);
252
-
FUNC_GROUP_DECL(RMII3, H24, J22, H22, H23, G23, F23, F26, F25, E26);
252
+
GROUP_DECL(RMII3, H24, J22, H22, H23, G23, F23, F26, F25, E26);
253
+
GROUP_DECL(NCSI3, J22, H22, H23, G23, F23, F26, F25, E26);
254
+
FUNC_DECL_2(RMII3, RMII3, NCSI3);
253
255
254
256
#define F24 28
255
257
SIG_EXPR_LIST_DECL_SESG(F24, NCTS3, NCTS3, SIG_DESC_SET(SCU410, 28));
···
357
355
358
356
FUNC_GROUP_DECL(RGMII4, F24, E23, E24, E25, D26, D24, C25, C26, C24, B26, B25,
359
357
B24);
360
-
FUNC_GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24);
358
+
GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24);
359
+
GROUP_DECL(NCSI4, E23, E24, E25, C25, C24, B26, B25, B24);
360
+
FUNC_DECL_2(RMII4, RMII4, NCSI4);
361
361
362
362
#define D22 40
363
363
SIG_EXPR_LIST_DECL_SESG(D22, SD1CLK, SD1, SIG_DESC_SET(SCU414, 8));
···
1981
1977
ASPEED_PINCTRL_GROUP(MDIO2),
1982
1978
ASPEED_PINCTRL_GROUP(MDIO3),
1983
1979
ASPEED_PINCTRL_GROUP(MDIO4),
1980
+
ASPEED_PINCTRL_GROUP(NCSI3),
1981
+
ASPEED_PINCTRL_GROUP(NCSI4),
1984
1982
ASPEED_PINCTRL_GROUP(NCTS1),
1985
1983
ASPEED_PINCTRL_GROUP(NCTS2),
1986
1984
ASPEED_PINCTRL_GROUP(NCTS3),
+3
-2
drivers/pinctrl/bcm/pinctrl-bcm2835.c
+3
-2
drivers/pinctrl/bcm/pinctrl-bcm2835.c
···
34
34
#include <linux/seq_file.h>
35
35
#include <linux/slab.h>
36
36
#include <linux/spinlock.h>
37
+
#include <linux/string_choices.h>
37
38
#include <linux/types.h>
38
39
#include <dt-bindings/pinctrl/bcm2835.h>
39
40
···
753
752
int irq = irq_find_mapping(chip->irq.domain, offset);
754
753
755
754
seq_printf(s, "function %s in %s; irq %d (%s)",
756
-
fname, value ? "hi" : "lo",
755
+
fname, str_hi_lo(value),
757
756
irq, irq_type_names[pc->irq_type[offset]]);
758
757
}
759
758
···
1429
1428
}
1430
1429
1431
1430
dev_info(dev, "GPIO_OUT persistence: %s\n",
1432
-
persist_gpio_outputs ? "yes" : "no");
1431
+
str_yes_no(persist_gpio_outputs));
1433
1432
1434
1433
return 0;
1435
1434
+1
drivers/pinctrl/bcm/pinctrl-bcm4908.c
+1
drivers/pinctrl/bcm/pinctrl-bcm4908.c
+1
-3
drivers/pinctrl/bcm/pinctrl-bcm63xx.c
+1
-3
drivers/pinctrl/bcm/pinctrl-bcm63xx.c
···
67
67
{
68
68
struct device *dev = &pdev->dev;
69
69
struct bcm63xx_pinctrl *pc;
70
-
struct device_node *node;
71
70
int err;
72
71
73
72
pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
···
93
94
if (IS_ERR(pc->pctl_dev))
94
95
return PTR_ERR(pc->pctl_dev);
95
96
96
-
for_each_child_of_node(dev->parent->of_node, node) {
97
+
for_each_child_of_node_scoped(dev->parent->of_node, node) {
97
98
if (of_match_node(bcm63xx_gpio_of_match, node)) {
98
99
err = bcm63xx_gpio_probe(dev, node, soc, pc);
99
100
if (err) {
100
101
dev_err(dev, "could not add GPIO chip\n");
101
-
of_node_put(node);
102
102
return err;
103
103
}
104
104
}
+9
-12
drivers/pinctrl/berlin/berlin.c
+9
-12
drivers/pinctrl/berlin/berlin.c
···
27
27
struct regmap *regmap;
28
28
struct device *dev;
29
29
const struct berlin_pinctrl_desc *desc;
30
-
struct berlin_pinctrl_function *functions;
30
+
struct pinfunction *functions;
31
31
unsigned nfunctions;
32
32
struct pinctrl_dev *pctrl_dev;
33
33
};
···
120
120
static int berlin_pinmux_get_function_groups(struct pinctrl_dev *pctrl_dev,
121
121
unsigned function,
122
122
const char * const **groups,
123
-
unsigned * const num_groups)
123
+
unsigned * const ngroups)
124
124
{
125
125
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
126
126
127
127
*groups = pctrl->functions[function].groups;
128
-
*num_groups = pctrl->functions[function].ngroups;
128
+
*ngroups = pctrl->functions[function].ngroups;
129
129
130
130
return 0;
131
131
}
···
153
153
{
154
154
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
155
155
const struct berlin_desc_group *group_desc = pctrl->desc->groups + group;
156
-
struct berlin_pinctrl_function *func = pctrl->functions + function;
156
+
struct pinfunction *func = pctrl->functions + function;
157
157
struct berlin_desc_function *function_desc =
158
158
berlin_pinctrl_find_function_by_name(pctrl, group_desc,
159
159
func->name);
···
180
180
static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl,
181
181
const char *name)
182
182
{
183
-
struct berlin_pinctrl_function *function = pctrl->functions;
183
+
struct pinfunction *function = pctrl->functions;
184
184
185
185
while (function->name) {
186
186
if (!strcmp(function->name, name)) {
···
214
214
}
215
215
216
216
/* we will reallocate later */
217
-
pctrl->functions = kcalloc(max_functions,
218
-
sizeof(*pctrl->functions), GFP_KERNEL);
217
+
pctrl->functions = kcalloc(max_functions, sizeof(*pctrl->functions), GFP_KERNEL);
219
218
if (!pctrl->functions)
220
219
return -ENOMEM;
221
220
···
241
242
desc_function = desc_group->functions;
242
243
243
244
while (desc_function->name) {
244
-
struct berlin_pinctrl_function
245
-
*function = pctrl->functions;
245
+
struct pinfunction *function = pctrl->functions;
246
246
const char **groups;
247
247
bool found = false;
248
248
···
262
264
function->groups =
263
265
devm_kcalloc(&pdev->dev,
264
266
function->ngroups,
265
-
sizeof(char *),
267
+
sizeof(*function->groups),
266
268
GFP_KERNEL);
267
-
268
269
if (!function->groups) {
269
270
kfree(pctrl->functions);
270
271
return -ENOMEM;
271
272
}
272
273
}
273
274
274
-
groups = function->groups;
275
+
groups = (const char **)function->groups;
275
276
while (*groups)
276
277
groups++;
277
278
-6
drivers/pinctrl/berlin/berlin.h
-6
drivers/pinctrl/berlin/berlin.h
+25
-5
drivers/pinctrl/core.c
+25
-5
drivers/pinctrl/core.c
···
1670
1670
seq_printf(s, "pin %d (%s) ", pin, desc->name);
1671
1671
1672
1672
#ifdef CONFIG_GPIOLIB
1673
+
gdev = NULL;
1673
1674
gpio_num = -1;
1674
1675
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
1675
-
if ((pin >= range->pin_base) &&
1676
-
(pin < (range->pin_base + range->npins))) {
1677
-
gpio_num = range->base + (pin - range->pin_base);
1678
-
break;
1676
+
if (range->pins != NULL) {
1677
+
for (int i = 0; i < range->npins; ++i) {
1678
+
if (range->pins[i] == pin) {
1679
+
gpio_num = range->base + i;
1680
+
break;
1681
+
}
1682
+
}
1683
+
} else if ((pin >= range->pin_base) &&
1684
+
(pin < (range->pin_base + range->npins))) {
1685
+
gpio_num =
1686
+
range->base + (pin - range->pin_base);
1679
1687
}
1688
+
if (gpio_num != -1)
1689
+
break;
1680
1690
}
1681
1691
if (gpio_num >= 0)
1682
1692
/*
···
2090
2080
return ERR_PTR(ret);
2091
2081
}
2092
2082
2083
+
static void pinctrl_uninit_controller(struct pinctrl_dev *pctldev, struct pinctrl_desc *pctldesc)
2084
+
{
2085
+
pinctrl_free_pindescs(pctldev, pctldesc->pins,
2086
+
pctldesc->npins);
2087
+
mutex_destroy(&pctldev->mutex);
2088
+
kfree(pctldev);
2089
+
}
2090
+
2093
2091
static int pinctrl_claim_hogs(struct pinctrl_dev *pctldev)
2094
2092
{
2095
2093
pctldev->p = create_pinctrl(pctldev->dev, pctldev);
···
2178
2160
return pctldev;
2179
2161
2180
2162
error = pinctrl_enable(pctldev);
2181
-
if (error)
2163
+
if (error) {
2164
+
pinctrl_uninit_controller(pctldev, pctldesc);
2182
2165
return ERR_PTR(error);
2166
+
}
2183
2167
2184
2168
return pctldev;
2185
2169
}
+1
-1
drivers/pinctrl/core.h
+1
-1
drivers/pinctrl/core.h
···
206
206
void *data;
207
207
};
208
208
209
-
/* Convenience macro to define a generic pin group descriptor */
209
+
/* Convenient macro to define a generic pin group descriptor */
210
210
#define PINCTRL_GROUP_DESC(_name, _pins, _num_pins, _data) \
211
211
(struct group_desc) { \
212
212
.grp = PINCTRL_PINGROUP(_name, _pins, _num_pins), \
+18
drivers/pinctrl/freescale/Kconfig
+18
drivers/pinctrl/freescale/Kconfig
···
7
7
select PINCONF
8
8
select REGMAP
9
9
10
+
config PINCTRL_IMX_SCMI
11
+
tristate "i.MX95 pinctrl driver using SCMI protocol interface"
12
+
depends on ARM_SCMI_PROTOCOL && OF || COMPILE_TEST
13
+
select PINMUX
14
+
select GENERIC_PINCONF
15
+
select GENERIC_PINCTRL_GROUPS
16
+
select GENERIC_PINMUX_FUNCTIONS
17
+
help
18
+
i.MX95 SCMI firmware provides pinctrl protocol. This driver
19
+
utilizes the SCMI interface to do pinctrl configuration.
20
+
10
21
config PINCTRL_IMX_SCU
11
22
tristate
12
23
depends on IMX_SCU
···
194
183
select PINCTRL_IMX
195
184
help
196
185
Say Y here to enable the imxrt1050 pinctrl driver
186
+
187
+
config PINCTRL_IMX91
188
+
tristate "IMX91 pinctrl driver"
189
+
depends on ARCH_MXC
190
+
select PINCTRL_IMX
191
+
help
192
+
Say Y here to enable the imx91 pinctrl driver
197
193
198
194
config PINCTRL_IMX93
199
195
tristate "IMX93 pinctrl driver"
+2
drivers/pinctrl/freescale/Makefile
+2
drivers/pinctrl/freescale/Makefile
···
2
2
# Freescale pin control drivers
3
3
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
4
4
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
5
+
obj-$(CONFIG_PINCTRL_IMX_SCMI) += pinctrl-imx-scmi.o
5
6
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
6
7
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
7
8
obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
···
26
25
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
27
26
obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o
28
27
obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
28
+
obj-$(CONFIG_PINCTRL_IMX91) += pinctrl-imx91.o
29
29
obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o
30
30
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
31
31
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
+357
drivers/pinctrl/freescale/pinctrl-imx-scmi.c
+357
drivers/pinctrl/freescale/pinctrl-imx-scmi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* System Control and Power Interface (SCMI) Protocol based i.MX pinctrl driver
4
+
*
5
+
* Copyright 2024 NXP
6
+
*/
7
+
8
+
#include <linux/device.h>
9
+
#include <linux/err.h>
10
+
#include <linux/errno.h>
11
+
#include <linux/module.h>
12
+
#include <linux/mod_devicetable.h>
13
+
#include <linux/of.h>
14
+
#include <linux/scmi_protocol.h>
15
+
#include <linux/seq_file.h>
16
+
#include <linux/slab.h>
17
+
#include <linux/types.h>
18
+
19
+
#include <linux/pinctrl/machine.h>
20
+
#include <linux/pinctrl/pinconf.h>
21
+
#include <linux/pinctrl/pinconf-generic.h>
22
+
#include <linux/pinctrl/pinctrl.h>
23
+
#include <linux/pinctrl/pinmux.h>
24
+
25
+
#include "../pinctrl-utils.h"
26
+
#include "../core.h"
27
+
#include "../pinconf.h"
28
+
#include "../pinmux.h"
29
+
30
+
#define DRV_NAME "scmi-pinctrl-imx"
31
+
32
+
struct scmi_pinctrl_imx {
33
+
struct device *dev;
34
+
struct scmi_protocol_handle *ph;
35
+
struct pinctrl_dev *pctldev;
36
+
struct pinctrl_desc pctl_desc;
37
+
const struct scmi_pinctrl_proto_ops *ops;
38
+
};
39
+
40
+
/* SCMI pin control types, aligned with SCMI firmware */
41
+
#define IMX_SCMI_NUM_CFG 4
42
+
#define IMX_SCMI_PIN_MUX 192
43
+
#define IMX_SCMI_PIN_CONFIG 193
44
+
#define IMX_SCMI_PIN_DAISY_ID 194
45
+
#define IMX_SCMI_PIN_DAISY_CFG 195
46
+
47
+
#define IMX_SCMI_NO_PAD_CTL BIT(31)
48
+
#define IMX_SCMI_PAD_SION BIT(30)
49
+
#define IMX_SCMI_IOMUXC_CONFIG_SION BIT(4)
50
+
51
+
#define IMX_SCMI_PIN_SIZE 24
52
+
53
+
#define IMX95_DAISY_OFF 0x408
54
+
55
+
static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev,
56
+
struct device_node *np,
57
+
struct pinctrl_map **map,
58
+
unsigned int *num_maps)
59
+
{
60
+
struct pinctrl_map *new_map;
61
+
const __be32 *list;
62
+
unsigned long *configs = NULL;
63
+
unsigned long cfg[IMX_SCMI_NUM_CFG];
64
+
int map_num, size, pin_size, pin_id, num_pins;
65
+
int mux_reg, conf_reg, input_reg, mux_val, conf_val, input_val;
66
+
int i, j;
67
+
uint32_t ncfg;
68
+
static uint32_t daisy_off;
69
+
70
+
if (!daisy_off) {
71
+
if (of_machine_is_compatible("fsl,imx95")) {
72
+
daisy_off = IMX95_DAISY_OFF;
73
+
} else {
74
+
dev_err(pctldev->dev, "platform not support scmi pinctrl\n");
75
+
return -EINVAL;
76
+
}
77
+
}
78
+
79
+
list = of_get_property(np, "fsl,pins", &size);
80
+
if (!list) {
81
+
dev_err(pctldev->dev, "no fsl,pins property in node %pOF\n", np);
82
+
return -EINVAL;
83
+
}
84
+
85
+
pin_size = IMX_SCMI_PIN_SIZE;
86
+
87
+
if (!size || size % pin_size) {
88
+
dev_err(pctldev->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
89
+
return -EINVAL;
90
+
}
91
+
92
+
num_pins = size / pin_size;
93
+
map_num = num_pins;
94
+
95
+
new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
96
+
GFP_KERNEL);
97
+
if (!new_map)
98
+
return -ENOMEM;
99
+
100
+
*map = new_map;
101
+
*num_maps = map_num;
102
+
103
+
/* create config map */
104
+
for (i = 0; i < num_pins; i++) {
105
+
j = 0;
106
+
ncfg = IMX_SCMI_NUM_CFG;
107
+
mux_reg = be32_to_cpu(*list++);
108
+
conf_reg = be32_to_cpu(*list++);
109
+
input_reg = be32_to_cpu(*list++);
110
+
mux_val = be32_to_cpu(*list++);
111
+
input_val = be32_to_cpu(*list++);
112
+
conf_val = be32_to_cpu(*list++);
113
+
if (conf_val & IMX_SCMI_PAD_SION)
114
+
mux_val |= IMX_SCMI_IOMUXC_CONFIG_SION;
115
+
116
+
pin_id = mux_reg / 4;
117
+
118
+
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_MUX, mux_val);
119
+
120
+
if (!conf_reg || (conf_val & IMX_SCMI_NO_PAD_CTL))
121
+
ncfg--;
122
+
else
123
+
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_CONFIG, conf_val);
124
+
125
+
if (!input_reg) {
126
+
ncfg -= 2;
127
+
} else {
128
+
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_ID,
129
+
(input_reg - daisy_off) / 4);
130
+
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_CFG, input_val);
131
+
}
132
+
133
+
configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL);
134
+
135
+
new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
136
+
new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_id);
137
+
new_map[i].data.configs.configs = configs;
138
+
new_map[i].data.configs.num_configs = ncfg;
139
+
}
140
+
141
+
return 0;
142
+
}
143
+
144
+
static void pinctrl_scmi_imx_dt_free_map(struct pinctrl_dev *pctldev,
145
+
struct pinctrl_map *map, unsigned int num_maps)
146
+
{
147
+
kfree(map);
148
+
}
149
+
150
+
static const struct pinctrl_ops pinctrl_scmi_imx_pinctrl_ops = {
151
+
.get_groups_count = pinctrl_generic_get_group_count,
152
+
.get_group_name = pinctrl_generic_get_group_name,
153
+
.get_group_pins = pinctrl_generic_get_group_pins,
154
+
.dt_node_to_map = pinctrl_scmi_imx_dt_node_to_map,
155
+
.dt_free_map = pinctrl_scmi_imx_dt_free_map,
156
+
};
157
+
158
+
static int pinctrl_scmi_imx_func_set_mux(struct pinctrl_dev *pctldev,
159
+
unsigned int selector, unsigned int group)
160
+
{
161
+
/*
162
+
* For i.MX SCMI PINCTRL , postpone the mux setting
163
+
* until config is set as they can be set together
164
+
* in one IPC call
165
+
*/
166
+
return 0;
167
+
}
168
+
169
+
static const struct pinmux_ops pinctrl_scmi_imx_pinmux_ops = {
170
+
.get_functions_count = pinmux_generic_get_function_count,
171
+
.get_function_name = pinmux_generic_get_function_name,
172
+
.get_function_groups = pinmux_generic_get_function_groups,
173
+
.set_mux = pinctrl_scmi_imx_func_set_mux,
174
+
};
175
+
176
+
static int pinctrl_scmi_imx_pinconf_get(struct pinctrl_dev *pctldev,
177
+
unsigned int pin, unsigned long *config)
178
+
{
179
+
int ret;
180
+
struct scmi_pinctrl_imx *pmx = pinctrl_dev_get_drvdata(pctldev);
181
+
u32 config_type, val;
182
+
183
+
if (!config)
184
+
return -EINVAL;
185
+
186
+
config_type = pinconf_to_config_param(*config);
187
+
188
+
ret = pmx->ops->settings_get_one(pmx->ph, pin, PIN_TYPE, config_type, &val);
189
+
/* Convert SCMI error code to PINCTRL expected error code */
190
+
if (ret == -EOPNOTSUPP)
191
+
return -ENOTSUPP;
192
+
if (ret)
193
+
return ret;
194
+
195
+
*config = pinconf_to_config_packed(config_type, val);
196
+
197
+
dev_dbg(pmx->dev, "pin:%s, conf:0x%x", pin_get_name(pctldev, pin), val);
198
+
199
+
return 0;
200
+
}
201
+
202
+
static int pinctrl_scmi_imx_pinconf_set(struct pinctrl_dev *pctldev,
203
+
unsigned int pin,
204
+
unsigned long *configs,
205
+
unsigned int num_configs)
206
+
{
207
+
struct scmi_pinctrl_imx *pmx = pinctrl_dev_get_drvdata(pctldev);
208
+
enum scmi_pinctrl_conf_type config_type[IMX_SCMI_NUM_CFG];
209
+
u32 config_value[IMX_SCMI_NUM_CFG];
210
+
enum scmi_pinctrl_conf_type *p_config_type = config_type;
211
+
u32 *p_config_value = config_value;
212
+
int ret;
213
+
int i;
214
+
215
+
if (!configs || !num_configs)
216
+
return -EINVAL;
217
+
218
+
if (num_configs > IMX_SCMI_NUM_CFG) {
219
+
dev_err(pmx->dev, "num_configs(%d) too large\n", num_configs);
220
+
return -EINVAL;
221
+
}
222
+
223
+
for (i = 0; i < num_configs; i++) {
224
+
/* cast to avoid build warning */
225
+
p_config_type[i] =
226
+
(enum scmi_pinctrl_conf_type)pinconf_to_config_param(configs[i]);
227
+
p_config_value[i] = pinconf_to_config_argument(configs[i]);
228
+
229
+
dev_dbg(pmx->dev, "pin: %u, type: %u, val: 0x%x\n",
230
+
pin, p_config_type[i], p_config_value[i]);
231
+
}
232
+
233
+
ret = pmx->ops->settings_conf(pmx->ph, pin, PIN_TYPE, num_configs,
234
+
p_config_type, p_config_value);
235
+
if (ret)
236
+
dev_err(pmx->dev, "Error set config %d\n", ret);
237
+
238
+
return ret;
239
+
}
240
+
241
+
static void pinctrl_scmi_imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
242
+
struct seq_file *s, unsigned int pin_id)
243
+
{
244
+
unsigned long config = pinconf_to_config_packed(IMX_SCMI_PIN_CONFIG, 0);
245
+
int ret;
246
+
247
+
ret = pinctrl_scmi_imx_pinconf_get(pctldev, pin_id, &config);
248
+
if (ret)
249
+
config = 0;
250
+
else
251
+
config = pinconf_to_config_argument(config);
252
+
253
+
seq_printf(s, "0x%lx", config);
254
+
}
255
+
256
+
static const struct pinconf_ops pinctrl_scmi_imx_pinconf_ops = {
257
+
.pin_config_get = pinctrl_scmi_imx_pinconf_get,
258
+
.pin_config_set = pinctrl_scmi_imx_pinconf_set,
259
+
.pin_config_dbg_show = pinctrl_scmi_imx_pinconf_dbg_show,
260
+
};
261
+
262
+
static int
263
+
scmi_pinctrl_imx_get_pins(struct scmi_pinctrl_imx *pmx, struct pinctrl_desc *desc)
264
+
{
265
+
struct pinctrl_pin_desc *pins;
266
+
unsigned int npins;
267
+
int ret, i;
268
+
269
+
npins = pmx->ops->count_get(pmx->ph, PIN_TYPE);
270
+
pins = devm_kmalloc_array(pmx->dev, npins, sizeof(*pins), GFP_KERNEL);
271
+
if (!pins)
272
+
return -ENOMEM;
273
+
274
+
for (i = 0; i < npins; i++) {
275
+
pins[i].number = i;
276
+
/* no need free name, firmware driver handles it */
277
+
ret = pmx->ops->name_get(pmx->ph, i, PIN_TYPE, &pins[i].name);
278
+
if (ret)
279
+
return dev_err_probe(pmx->dev, ret,
280
+
"Can't get name for pin %d", i);
281
+
}
282
+
283
+
desc->npins = npins;
284
+
desc->pins = pins;
285
+
dev_dbg(pmx->dev, "got pins %u", npins);
286
+
287
+
return 0;
288
+
}
289
+
290
+
static const char * const scmi_pinctrl_imx_allowlist[] = {
291
+
"fsl,imx95",
292
+
NULL
293
+
};
294
+
295
+
static int scmi_pinctrl_imx_probe(struct scmi_device *sdev)
296
+
{
297
+
struct device *dev = &sdev->dev;
298
+
const struct scmi_handle *handle = sdev->handle;
299
+
struct scmi_pinctrl_imx *pmx;
300
+
struct scmi_protocol_handle *ph;
301
+
const struct scmi_pinctrl_proto_ops *pinctrl_ops;
302
+
int ret;
303
+
304
+
if (!handle)
305
+
return -EINVAL;
306
+
307
+
if (!of_machine_compatible_match(scmi_pinctrl_imx_allowlist))
308
+
return -ENODEV;
309
+
310
+
pinctrl_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_PINCTRL, &ph);
311
+
if (IS_ERR(pinctrl_ops))
312
+
return PTR_ERR(pinctrl_ops);
313
+
314
+
pmx = devm_kzalloc(dev, sizeof(*pmx), GFP_KERNEL);
315
+
if (!pmx)
316
+
return -ENOMEM;
317
+
318
+
pmx->ph = ph;
319
+
pmx->ops = pinctrl_ops;
320
+
321
+
pmx->dev = dev;
322
+
pmx->pctl_desc.name = DRV_NAME;
323
+
pmx->pctl_desc.owner = THIS_MODULE;
324
+
pmx->pctl_desc.pctlops = &pinctrl_scmi_imx_pinctrl_ops;
325
+
pmx->pctl_desc.pmxops = &pinctrl_scmi_imx_pinmux_ops;
326
+
pmx->pctl_desc.confops = &pinctrl_scmi_imx_pinconf_ops;
327
+
328
+
ret = scmi_pinctrl_imx_get_pins(pmx, &pmx->pctl_desc);
329
+
if (ret)
330
+
return ret;
331
+
332
+
pmx->dev = &sdev->dev;
333
+
334
+
ret = devm_pinctrl_register_and_init(dev, &pmx->pctl_desc, pmx,
335
+
&pmx->pctldev);
336
+
if (ret)
337
+
return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
338
+
339
+
return pinctrl_enable(pmx->pctldev);
340
+
}
341
+
342
+
static const struct scmi_device_id scmi_id_table[] = {
343
+
{ SCMI_PROTOCOL_PINCTRL, "pinctrl-imx" },
344
+
{ }
345
+
};
346
+
MODULE_DEVICE_TABLE(scmi, scmi_id_table);
347
+
348
+
static struct scmi_driver scmi_pinctrl_imx_driver = {
349
+
.name = DRV_NAME,
350
+
.probe = scmi_pinctrl_imx_probe,
351
+
.id_table = scmi_id_table,
352
+
};
353
+
module_scmi_driver(scmi_pinctrl_imx_driver);
354
+
355
+
MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
356
+
MODULE_DESCRIPTION("i.MX SCMI pin controller driver");
357
+
MODULE_LICENSE("GPL");
+14
-25
drivers/pinctrl/freescale/pinctrl-imx.c
+14
-25
drivers/pinctrl/freescale/pinctrl-imx.c
···
266
266
npins = grp->grp.npins;
267
267
268
268
dev_dbg(ipctl->dev, "enable function %s group %s\n",
269
-
func->name, grp->grp.name);
269
+
func->func.name, grp->grp.name);
270
270
271
271
for (i = 0; i < npins; i++) {
272
272
/*
···
580
580
u32 index)
581
581
{
582
582
struct pinctrl_dev *pctl = ipctl->pctl;
583
-
struct device_node *child;
584
583
struct function_desc *func;
585
584
struct group_desc *grp;
586
585
const char **group_names;
···
592
593
return -EINVAL;
593
594
594
595
/* Initialise function */
595
-
func->name = np->name;
596
-
func->num_group_names = of_get_child_count(np);
597
-
if (func->num_group_names == 0) {
596
+
func->func.name = np->name;
597
+
func->func.ngroups = of_get_child_count(np);
598
+
if (func->func.ngroups == 0) {
598
599
dev_info(ipctl->dev, "no groups defined in %pOF\n", np);
599
600
return -EINVAL;
600
601
}
601
602
602
-
group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
603
-
sizeof(char *), GFP_KERNEL);
603
+
group_names = devm_kcalloc(ipctl->dev, func->func.ngroups,
604
+
sizeof(*func->func.groups), GFP_KERNEL);
604
605
if (!group_names)
605
606
return -ENOMEM;
606
607
i = 0;
607
-
for_each_child_of_node(np, child)
608
+
for_each_child_of_node_scoped(np, child)
608
609
group_names[i++] = child->name;
609
-
func->group_names = group_names;
610
+
func->func.groups = group_names;
610
611
611
612
i = 0;
612
-
for_each_child_of_node(np, child) {
613
+
for_each_child_of_node_scoped(np, child) {
613
614
grp = devm_kzalloc(ipctl->dev, sizeof(*grp), GFP_KERNEL);
614
-
if (!grp) {
615
-
of_node_put(child);
615
+
if (!grp)
616
616
return -ENOMEM;
617
-
}
618
617
619
618
mutex_lock(&ipctl->mutex);
620
619
radix_tree_insert(&pctl->pin_group_tree,
···
632
635
*/
633
636
static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
634
637
{
635
-
struct device_node *function_np;
636
-
struct device_node *pinctrl_np;
637
-
638
-
for_each_child_of_node(np, function_np) {
639
-
if (of_property_read_bool(function_np, "fsl,pins")) {
640
-
of_node_put(function_np);
638
+
for_each_child_of_node_scoped(np, function_np) {
639
+
if (of_property_read_bool(function_np, "fsl,pins"))
641
640
return true;
642
-
}
643
641
644
-
for_each_child_of_node(function_np, pinctrl_np) {
645
-
if (of_property_read_bool(pinctrl_np, "fsl,pins")) {
646
-
of_node_put(pinctrl_np);
647
-
of_node_put(function_np);
642
+
for_each_child_of_node_scoped(function_np, pinctrl_np) {
643
+
if (of_property_read_bool(pinctrl_np, "fsl,pins"))
648
644
return false;
649
-
}
650
645
}
651
646
}
652
647
+5
-11
drivers/pinctrl/freescale/pinctrl-imx1-core.c
+5
-11
drivers/pinctrl/freescale/pinctrl-imx1-core.c
···
508
508
struct imx1_pinctrl_soc_info *info,
509
509
u32 index)
510
510
{
511
-
struct device_node *child;
512
511
struct imx1_pmx_func *func;
513
512
struct imx1_pin_group *grp;
514
513
int ret;
···
530
531
if (!func->groups)
531
532
return -ENOMEM;
532
533
533
-
for_each_child_of_node(np, child) {
534
+
for_each_child_of_node_scoped(np, child) {
534
535
func->groups[i] = child->name;
535
536
grp = &info->groups[grp_index++];
536
537
ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
537
-
if (ret == -ENOMEM) {
538
-
of_node_put(child);
538
+
if (ret == -ENOMEM)
539
539
return ret;
540
-
}
541
540
}
542
541
543
542
return 0;
···
545
548
struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
546
549
{
547
550
struct device_node *np = pdev->dev.of_node;
548
-
struct device_node *child;
549
551
int ret;
550
552
u32 nfuncs = 0;
551
553
u32 ngroups = 0;
···
553
557
if (!np)
554
558
return -ENODEV;
555
559
556
-
for_each_child_of_node(np, child) {
560
+
for_each_child_of_node_scoped(np, child) {
557
561
++nfuncs;
558
562
ngroups += of_get_child_count(child);
559
563
}
···
575
579
if (!info->functions || !info->groups)
576
580
return -ENOMEM;
577
581
578
-
for_each_child_of_node(np, child) {
582
+
for_each_child_of_node_scoped(np, child) {
579
583
ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
580
-
if (ret == -ENOMEM) {
581
-
of_node_put(child);
584
+
if (ret == -ENOMEM)
582
585
return -ENOMEM;
583
-
}
584
586
}
585
587
586
588
return 0;
+271
drivers/pinctrl/freescale/pinctrl-imx91.c
+271
drivers/pinctrl/freescale/pinctrl-imx91.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright 2024 NXP
4
+
*/
5
+
6
+
#include <linux/init.h>
7
+
#include <linux/mod_devicetable.h>
8
+
#include <linux/module.h>
9
+
#include <linux/pinctrl/pinctrl.h>
10
+
#include <linux/platform_device.h>
11
+
12
+
#include "pinctrl-imx.h"
13
+
14
+
enum imx91_pads {
15
+
IMX91_PAD_DAP_TDI = 0,
16
+
IMX91_PAD_DAP_TMS_SWDIO = 1,
17
+
IMX91_PAD_DAP_TCLK_SWCLK = 2,
18
+
IMX91_PAD_DAP_TDO_TRACESWO = 3,
19
+
IMX91_PAD_GPIO_IO00 = 4,
20
+
IMX91_PAD_GPIO_IO01 = 5,
21
+
IMX91_PAD_GPIO_IO02 = 6,
22
+
IMX91_PAD_GPIO_IO03 = 7,
23
+
IMX91_PAD_GPIO_IO04 = 8,
24
+
IMX91_PAD_GPIO_IO05 = 9,
25
+
IMX91_PAD_GPIO_IO06 = 10,
26
+
IMX91_PAD_GPIO_IO07 = 11,
27
+
IMX91_PAD_GPIO_IO08 = 12,
28
+
IMX91_PAD_GPIO_IO09 = 13,
29
+
IMX91_PAD_GPIO_IO10 = 14,
30
+
IMX91_PAD_GPIO_IO11 = 15,
31
+
IMX91_PAD_GPIO_IO12 = 16,
32
+
IMX91_PAD_GPIO_IO13 = 17,
33
+
IMX91_PAD_GPIO_IO14 = 18,
34
+
IMX91_PAD_GPIO_IO15 = 19,
35
+
IMX91_PAD_GPIO_IO16 = 20,
36
+
IMX91_PAD_GPIO_IO17 = 21,
37
+
IMX91_PAD_GPIO_IO18 = 22,
38
+
IMX91_PAD_GPIO_IO19 = 23,
39
+
IMX91_PAD_GPIO_IO20 = 24,
40
+
IMX91_PAD_GPIO_IO21 = 25,
41
+
IMX91_PAD_GPIO_IO22 = 26,
42
+
IMX91_PAD_GPIO_IO23 = 27,
43
+
IMX91_PAD_GPIO_IO24 = 28,
44
+
IMX91_PAD_GPIO_IO25 = 29,
45
+
IMX91_PAD_GPIO_IO26 = 30,
46
+
IMX91_PAD_GPIO_IO27 = 31,
47
+
IMX91_PAD_GPIO_IO28 = 32,
48
+
IMX91_PAD_GPIO_IO29 = 33,
49
+
IMX91_PAD_CCM_CLKO1 = 34,
50
+
IMX91_PAD_CCM_CLKO2 = 35,
51
+
IMX91_PAD_CCM_CLKO3 = 36,
52
+
IMX91_PAD_CCM_CLKO4 = 37,
53
+
IMX91_PAD_ENET1_MDC = 38,
54
+
IMX91_PAD_ENET1_MDIO = 39,
55
+
IMX91_PAD_ENET1_TD3 = 40,
56
+
IMX91_PAD_ENET1_TD2 = 41,
57
+
IMX91_PAD_ENET1_TD1 = 42,
58
+
IMX91_PAD_ENET1_TD0 = 43,
59
+
IMX91_PAD_ENET1_TX_CTL = 44,
60
+
IMX91_PAD_ENET1_TXC = 45,
61
+
IMX91_PAD_ENET1_RX_CTL = 46,
62
+
IMX91_PAD_ENET1_RXC = 47,
63
+
IMX91_PAD_ENET1_RD0 = 48,
64
+
IMX91_PAD_ENET1_RD1 = 49,
65
+
IMX91_PAD_ENET1_RD2 = 50,
66
+
IMX91_PAD_ENET1_RD3 = 51,
67
+
IMX91_PAD_ENET2_MDC = 52,
68
+
IMX91_PAD_ENET2_MDIO = 53,
69
+
IMX91_PAD_ENET2_TD3 = 54,
70
+
IMX91_PAD_ENET2_TD2 = 55,
71
+
IMX91_PAD_ENET2_TD1 = 56,
72
+
IMX91_PAD_ENET2_TD0 = 57,
73
+
IMX91_PAD_ENET2_TX_CTL = 58,
74
+
IMX91_PAD_ENET2_TXC = 59,
75
+
IMX91_PAD_ENET2_RX_CTL = 60,
76
+
IMX91_PAD_ENET2_RXC = 61,
77
+
IMX91_PAD_ENET2_RD0 = 62,
78
+
IMX91_PAD_ENET2_RD1 = 63,
79
+
IMX91_PAD_ENET2_RD2 = 64,
80
+
IMX91_PAD_ENET2_RD3 = 65,
81
+
IMX91_PAD_SD1_CLK = 66,
82
+
IMX91_PAD_SD1_CMD = 67,
83
+
IMX91_PAD_SD1_DATA0 = 68,
84
+
IMX91_PAD_SD1_DATA1 = 69,
85
+
IMX91_PAD_SD1_DATA2 = 70,
86
+
IMX91_PAD_SD1_DATA3 = 71,
87
+
IMX91_PAD_SD1_DATA4 = 72,
88
+
IMX91_PAD_SD1_DATA5 = 73,
89
+
IMX91_PAD_SD1_DATA6 = 74,
90
+
IMX91_PAD_SD1_DATA7 = 75,
91
+
IMX91_PAD_SD1_STROBE = 76,
92
+
IMX91_PAD_SD2_VSELECT = 77,
93
+
IMX91_PAD_SD3_CLK = 78,
94
+
IMX91_PAD_SD3_CMD = 79,
95
+
IMX91_PAD_SD3_DATA0 = 80,
96
+
IMX91_PAD_SD3_DATA1 = 81,
97
+
IMX91_PAD_SD3_DATA2 = 82,
98
+
IMX91_PAD_SD3_DATA3 = 83,
99
+
IMX91_PAD_SD2_CD_B = 84,
100
+
IMX91_PAD_SD2_CLK = 85,
101
+
IMX91_PAD_SD2_CMD = 86,
102
+
IMX91_PAD_SD2_DATA0 = 87,
103
+
IMX91_PAD_SD2_DATA1 = 88,
104
+
IMX91_PAD_SD2_DATA2 = 89,
105
+
IMX91_PAD_SD2_DATA3 = 90,
106
+
IMX91_PAD_SD2_RESET_B = 91,
107
+
IMX91_PAD_I2C1_SCL = 92,
108
+
IMX91_PAD_I2C1_SDA = 93,
109
+
IMX91_PAD_I2C2_SCL = 94,
110
+
IMX91_PAD_I2C2_SDA = 95,
111
+
IMX91_PAD_UART1_RXD = 96,
112
+
IMX91_PAD_UART1_TXD = 97,
113
+
IMX91_PAD_UART2_RXD = 98,
114
+
IMX91_PAD_UART2_TXD = 99,
115
+
IMX91_PAD_PDM_CLK = 100,
116
+
IMX91_PAD_PDM_BIT_STREAM0 = 101,
117
+
IMX91_PAD_PDM_BIT_STREAM1 = 102,
118
+
IMX91_PAD_SAI1_TXFS = 103,
119
+
IMX91_PAD_SAI1_TXC = 104,
120
+
IMX91_PAD_SAI1_TXD0 = 105,
121
+
IMX91_PAD_SAI1_RXD0 = 106,
122
+
IMX91_PAD_WDOG_ANY = 107,
123
+
};
124
+
125
+
/* Pad names for the pinmux subsystem */
126
+
static const struct pinctrl_pin_desc imx91_pinctrl_pads[] = {
127
+
IMX_PINCTRL_PIN(IMX91_PAD_DAP_TDI),
128
+
IMX_PINCTRL_PIN(IMX91_PAD_DAP_TMS_SWDIO),
129
+
IMX_PINCTRL_PIN(IMX91_PAD_DAP_TCLK_SWCLK),
130
+
IMX_PINCTRL_PIN(IMX91_PAD_DAP_TDO_TRACESWO),
131
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO00),
132
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO01),
133
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO02),
134
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO03),
135
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO04),
136
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO05),
137
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO06),
138
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO07),
139
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO08),
140
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO09),
141
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO10),
142
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO11),
143
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO12),
144
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO13),
145
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO14),
146
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO15),
147
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO16),
148
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO17),
149
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO18),
150
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO19),
151
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO20),
152
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO21),
153
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO22),
154
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO23),
155
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO24),
156
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO25),
157
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO26),
158
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO27),
159
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO28),
160
+
IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO29),
161
+
IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO1),
162
+
IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO2),
163
+
IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO3),
164
+
IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO4),
165
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_MDC),
166
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_MDIO),
167
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD3),
168
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD2),
169
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD1),
170
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD0),
171
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TX_CTL),
172
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TXC),
173
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RX_CTL),
174
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RXC),
175
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD0),
176
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD1),
177
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD2),
178
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD3),
179
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_MDC),
180
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_MDIO),
181
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD3),
182
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD2),
183
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD1),
184
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD0),
185
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TX_CTL),
186
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TXC),
187
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RX_CTL),
188
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RXC),
189
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD0),
190
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD1),
191
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD2),
192
+
IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD3),
193
+
IMX_PINCTRL_PIN(IMX91_PAD_SD1_CLK),
194
+
IMX_PINCTRL_PIN(IMX91_PAD_SD1_CMD),
195
+
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA0),
196
+
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA1),
197
+
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA2),
198
+
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA3),
199
+
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA4),
200
+
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA5),
201
+
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA6),
202
+
IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA7),
203
+
IMX_PINCTRL_PIN(IMX91_PAD_SD1_STROBE),
204
+
IMX_PINCTRL_PIN(IMX91_PAD_SD2_VSELECT),
205
+
IMX_PINCTRL_PIN(IMX91_PAD_SD3_CLK),
206
+
IMX_PINCTRL_PIN(IMX91_PAD_SD3_CMD),
207
+
IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA0),
208
+
IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA1),
209
+
IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA2),
210
+
IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA3),
211
+
IMX_PINCTRL_PIN(IMX91_PAD_SD2_CD_B),
212
+
IMX_PINCTRL_PIN(IMX91_PAD_SD2_CLK),
213
+
IMX_PINCTRL_PIN(IMX91_PAD_SD2_CMD),
214
+
IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA0),
215
+
IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA1),
216
+
IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA2),
217
+
IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA3),
218
+
IMX_PINCTRL_PIN(IMX91_PAD_SD2_RESET_B),
219
+
IMX_PINCTRL_PIN(IMX91_PAD_I2C1_SCL),
220
+
IMX_PINCTRL_PIN(IMX91_PAD_I2C1_SDA),
221
+
IMX_PINCTRL_PIN(IMX91_PAD_I2C2_SCL),
222
+
IMX_PINCTRL_PIN(IMX91_PAD_I2C2_SDA),
223
+
IMX_PINCTRL_PIN(IMX91_PAD_UART1_RXD),
224
+
IMX_PINCTRL_PIN(IMX91_PAD_UART1_TXD),
225
+
IMX_PINCTRL_PIN(IMX91_PAD_UART2_RXD),
226
+
IMX_PINCTRL_PIN(IMX91_PAD_UART2_TXD),
227
+
IMX_PINCTRL_PIN(IMX91_PAD_PDM_CLK),
228
+
IMX_PINCTRL_PIN(IMX91_PAD_PDM_BIT_STREAM0),
229
+
IMX_PINCTRL_PIN(IMX91_PAD_PDM_BIT_STREAM1),
230
+
IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXFS),
231
+
IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXC),
232
+
IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXD0),
233
+
IMX_PINCTRL_PIN(IMX91_PAD_SAI1_RXD0),
234
+
IMX_PINCTRL_PIN(IMX91_PAD_WDOG_ANY),
235
+
};
236
+
237
+
static const struct imx_pinctrl_soc_info imx91_pinctrl_info = {
238
+
.pins = imx91_pinctrl_pads,
239
+
.npins = ARRAY_SIZE(imx91_pinctrl_pads),
240
+
.flags = ZERO_OFFSET_VALID,
241
+
};
242
+
243
+
static int imx91_pinctrl_probe(struct platform_device *pdev)
244
+
{
245
+
return imx_pinctrl_probe(pdev, &imx91_pinctrl_info);
246
+
}
247
+
248
+
static const struct of_device_id imx91_pinctrl_of_match[] = {
249
+
{ .compatible = "fsl,imx91-iomuxc", },
250
+
{ /* sentinel */ }
251
+
};
252
+
MODULE_DEVICE_TABLE(of, imx91_pinctrl_of_match);
253
+
254
+
static struct platform_driver imx91_pinctrl_driver = {
255
+
.driver = {
256
+
.name = "imx91-pinctrl",
257
+
.of_match_table = imx91_pinctrl_of_match,
258
+
.suppress_bind_attrs = true,
259
+
},
260
+
.probe = imx91_pinctrl_probe,
261
+
};
262
+
263
+
static int __init imx91_pinctrl_init(void)
264
+
{
265
+
return platform_driver_register(&imx91_pinctrl_driver);
266
+
}
267
+
arch_initcall(imx91_pinctrl_init);
268
+
269
+
MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
270
+
MODULE_DESCRIPTION("NXP i.MX91 pinctrl driver");
271
+
MODULE_LICENSE("GPL");
+6
-12
drivers/pinctrl/freescale/pinctrl-mxs.c
+6
-12
drivers/pinctrl/freescale/pinctrl-mxs.c
···
413
413
int ret;
414
414
u32 val;
415
415
416
-
child = of_get_next_child(np, NULL);
417
-
if (!child) {
416
+
val = of_get_child_count(np);
417
+
if (val == 0) {
418
418
dev_err(&pdev->dev, "no group is defined\n");
419
419
return -ENOENT;
420
420
}
···
490
490
/* Get groups for each function */
491
491
idxf = 0;
492
492
fn = fnull;
493
-
for_each_child_of_node(np, child) {
493
+
for_each_child_of_node_scoped(np, child) {
494
494
if (is_mxs_gpio(child))
495
495
continue;
496
496
if (of_property_read_u32(child, "reg", &val)) {
497
497
ret = mxs_pinctrl_parse_group(pdev, child,
498
498
idxg++, NULL);
499
-
if (ret) {
500
-
of_node_put(child);
499
+
if (ret)
501
500
return ret;
502
-
}
503
501
continue;
504
502
}
505
503
···
507
509
f->ngroups,
508
510
sizeof(*f->groups),
509
511
GFP_KERNEL);
510
-
if (!f->groups) {
511
-
of_node_put(child);
512
+
if (!f->groups)
512
513
return -ENOMEM;
513
-
}
514
514
fn = child->name;
515
515
i = 0;
516
516
}
517
517
ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
518
518
&f->groups[i++]);
519
-
if (ret) {
520
-
of_node_put(child);
519
+
if (ret)
521
520
return ret;
522
-
}
523
521
}
524
522
525
523
return 0;
+5
-5
drivers/pinctrl/mediatek/pinctrl-moore.c
+5
-5
drivers/pinctrl/mediatek/pinctrl-moore.c
···
56
56
return -EINVAL;
57
57
58
58
dev_dbg(pctldev->dev, "enable function %s group %s\n",
59
-
func->name, grp->grp.name);
59
+
func->func.name, grp->grp.name);
60
60
61
61
for (i = 0; i < grp->grp.npins; i++) {
62
62
const struct mtk_pin_desc *desc;
···
620
620
int i, err;
621
621
622
622
for (i = 0; i < hw->soc->nfuncs ; i++) {
623
-
const struct function_desc *func = hw->soc->funcs + i;
623
+
const struct function_desc *function = hw->soc->funcs + i;
624
+
const struct pinfunction *func = &function->func;
624
625
625
626
err = pinmux_generic_add_function(hw->pctrl, func->name,
626
-
func->group_names,
627
-
func->num_group_names,
628
-
func->data);
627
+
func->groups, func->ngroups,
628
+
function->data);
629
629
if (err < 0) {
630
630
dev_err(hw->dev, "Failed to register function %s\n",
631
631
func->name);
+6
drivers/pinctrl/mediatek/pinctrl-moore.h
+6
drivers/pinctrl/mediatek/pinctrl-moore.h
···
43
43
.data = id##_funcs, \
44
44
}
45
45
46
+
#define PINCTRL_PIN_FUNCTION(_name_, id) \
47
+
{ \
48
+
.func = PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups)), \
49
+
.data = NULL, \
50
+
}
51
+
46
52
int mtk_moore_pinctrl_probe(struct platform_device *pdev,
47
53
const struct mtk_pin_soc *soc);
48
54
+16
-16
drivers/pinctrl/mediatek/pinctrl-mt7622.c
+16
-16
drivers/pinctrl/mediatek/pinctrl-mt7622.c
···
823
823
static const char *mt7622_wdt_groups[] = { "watchdog", };
824
824
825
825
static const struct function_desc mt7622_functions[] = {
826
-
{"antsel", mt7622_antsel_groups, ARRAY_SIZE(mt7622_antsel_groups)},
827
-
{"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
828
-
{"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
829
-
{"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
830
-
{"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
831
-
{"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
832
-
{"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
833
-
{"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
834
-
{"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
835
-
{"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
836
-
{"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
837
-
{"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
838
-
{"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
839
-
{"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
840
-
{"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
841
-
{"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
826
+
PINCTRL_PIN_FUNCTION("antsel", mt7622_antsel),
827
+
PINCTRL_PIN_FUNCTION("emmc", mt7622_emmc),
828
+
PINCTRL_PIN_FUNCTION("eth", mt7622_ethernet),
829
+
PINCTRL_PIN_FUNCTION("i2c", mt7622_i2c),
830
+
PINCTRL_PIN_FUNCTION("i2s", mt7622_i2s),
831
+
PINCTRL_PIN_FUNCTION("ir", mt7622_ir),
832
+
PINCTRL_PIN_FUNCTION("led", mt7622_led),
833
+
PINCTRL_PIN_FUNCTION("flash", mt7622_flash),
834
+
PINCTRL_PIN_FUNCTION("pcie", mt7622_pcie),
835
+
PINCTRL_PIN_FUNCTION("pmic", mt7622_pmic_bus),
836
+
PINCTRL_PIN_FUNCTION("pwm", mt7622_pwm),
837
+
PINCTRL_PIN_FUNCTION("sd", mt7622_sd),
838
+
PINCTRL_PIN_FUNCTION("spi", mt7622_spic),
839
+
PINCTRL_PIN_FUNCTION("tdm", mt7622_tdm),
840
+
PINCTRL_PIN_FUNCTION("uart", mt7622_uart),
841
+
PINCTRL_PIN_FUNCTION("watchdog", mt7622_wdt),
842
842
};
843
843
844
844
static const struct mtk_eint_hw mt7622_eint_hw = {
+21
-21
drivers/pinctrl/mediatek/pinctrl-mt7623.c
+21
-21
drivers/pinctrl/mediatek/pinctrl-mt7623.c
···
1341
1341
static const char *mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", };
1342
1342
1343
1343
static const struct function_desc mt7623_functions[] = {
1344
-
{"audck", mt7623_aud_clk_groups, ARRAY_SIZE(mt7623_aud_clk_groups)},
1345
-
{"disp", mt7623_disp_pwm_groups, ARRAY_SIZE(mt7623_disp_pwm_groups)},
1346
-
{"eth", mt7623_ethernet_groups, ARRAY_SIZE(mt7623_ethernet_groups)},
1347
-
{"sdio", mt7623_ext_sdio_groups, ARRAY_SIZE(mt7623_ext_sdio_groups)},
1348
-
{"hdmi", mt7623_hdmi_groups, ARRAY_SIZE(mt7623_hdmi_groups)},
1349
-
{"i2c", mt7623_i2c_groups, ARRAY_SIZE(mt7623_i2c_groups)},
1350
-
{"i2s", mt7623_i2s_groups, ARRAY_SIZE(mt7623_i2s_groups)},
1351
-
{"ir", mt7623_ir_groups, ARRAY_SIZE(mt7623_ir_groups)},
1352
-
{"lcd", mt7623_lcd_groups, ARRAY_SIZE(mt7623_lcd_groups)},
1353
-
{"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)},
1354
-
{"nand", mt7623_nandc_groups, ARRAY_SIZE(mt7623_nandc_groups)},
1355
-
{"otg", mt7623_otg_groups, ARRAY_SIZE(mt7623_otg_groups)},
1356
-
{"pcie", mt7623_pcie_groups, ARRAY_SIZE(mt7623_pcie_groups)},
1357
-
{"pcm", mt7623_pcm_groups, ARRAY_SIZE(mt7623_pcm_groups)},
1358
-
{"pwm", mt7623_pwm_groups, ARRAY_SIZE(mt7623_pwm_groups)},
1359
-
{"pwrap", mt7623_pwrap_groups, ARRAY_SIZE(mt7623_pwrap_groups)},
1360
-
{"rtc", mt7623_rtc_groups, ARRAY_SIZE(mt7623_rtc_groups)},
1361
-
{"spi", mt7623_spi_groups, ARRAY_SIZE(mt7623_spi_groups)},
1362
-
{"spdif", mt7623_spdif_groups, ARRAY_SIZE(mt7623_spdif_groups)},
1363
-
{"uart", mt7623_uart_groups, ARRAY_SIZE(mt7623_uart_groups)},
1364
-
{"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
1344
+
PINCTRL_PIN_FUNCTION("audck", mt7623_aud_clk),
1345
+
PINCTRL_PIN_FUNCTION("disp", mt7623_disp_pwm),
1346
+
PINCTRL_PIN_FUNCTION("eth", mt7623_ethernet),
1347
+
PINCTRL_PIN_FUNCTION("sdio", mt7623_ext_sdio),
1348
+
PINCTRL_PIN_FUNCTION("hdmi", mt7623_hdmi),
1349
+
PINCTRL_PIN_FUNCTION("i2c", mt7623_i2c),
1350
+
PINCTRL_PIN_FUNCTION("i2s", mt7623_i2s),
1351
+
PINCTRL_PIN_FUNCTION("ir", mt7623_ir),
1352
+
PINCTRL_PIN_FUNCTION("lcd", mt7623_lcd),
1353
+
PINCTRL_PIN_FUNCTION("msdc", mt7623_msdc),
1354
+
PINCTRL_PIN_FUNCTION("nand", mt7623_nandc),
1355
+
PINCTRL_PIN_FUNCTION("otg", mt7623_otg),
1356
+
PINCTRL_PIN_FUNCTION("pcie", mt7623_pcie),
1357
+
PINCTRL_PIN_FUNCTION("pcm", mt7623_pcm),
1358
+
PINCTRL_PIN_FUNCTION("pwm", mt7623_pwm),
1359
+
PINCTRL_PIN_FUNCTION("pwrap", mt7623_pwrap),
1360
+
PINCTRL_PIN_FUNCTION("rtc", mt7623_rtc),
1361
+
PINCTRL_PIN_FUNCTION("spi", mt7623_spi),
1362
+
PINCTRL_PIN_FUNCTION("spdif", mt7623_spdif),
1363
+
PINCTRL_PIN_FUNCTION("uart", mt7623_uart),
1364
+
PINCTRL_PIN_FUNCTION("watchdog", mt7623_wdt),
1365
1365
};
1366
1366
1367
1367
static const struct mtk_eint_hw mt7623_eint_hw = {
+10
-10
drivers/pinctrl/mediatek/pinctrl-mt7629.c
+10
-10
drivers/pinctrl/mediatek/pinctrl-mt7629.c
···
385
385
static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" };
386
386
387
387
static const struct function_desc mt7629_functions[] = {
388
-
{"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)},
389
-
{"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)},
390
-
{"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)},
391
-
{"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)},
392
-
{"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)},
393
-
{"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)},
394
-
{"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)},
395
-
{"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)},
396
-
{"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)},
397
-
{"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)},
388
+
PINCTRL_PIN_FUNCTION("eth", mt7629_ethernet),
389
+
PINCTRL_PIN_FUNCTION("i2c", mt7629_i2c),
390
+
PINCTRL_PIN_FUNCTION("led", mt7629_led),
391
+
PINCTRL_PIN_FUNCTION("pcie", mt7629_pcie),
392
+
PINCTRL_PIN_FUNCTION("pwm", mt7629_pwm),
393
+
PINCTRL_PIN_FUNCTION("spi", mt7629_spi),
394
+
PINCTRL_PIN_FUNCTION("uart", mt7629_uart),
395
+
PINCTRL_PIN_FUNCTION("watchdog", mt7629_wdt),
396
+
PINCTRL_PIN_FUNCTION("wifi", mt7629_wifi),
397
+
PINCTRL_PIN_FUNCTION("flash", mt7629_flash),
398
398
};
399
399
400
400
static const struct mtk_eint_hw mt7629_eint_hw = {
+27
-61
drivers/pinctrl/mediatek/pinctrl-mt76x8.c
+27
-61
drivers/pinctrl/mediatek/pinctrl-mt76x8.c
···
37
37
38
38
static struct mtmips_pmx_func pwm1_grp[] = {
39
39
FUNC("sdxc d6", 3, 19, 1),
40
-
FUNC("utif", 2, 19, 1),
41
-
FUNC("gpio", 1, 19, 1),
40
+
FUNC("pwm1 utif", 2, 19, 1),
42
41
FUNC("pwm1", 0, 19, 1),
43
42
};
44
43
45
44
static struct mtmips_pmx_func pwm0_grp[] = {
46
45
FUNC("sdxc d7", 3, 18, 1),
47
-
FUNC("utif", 2, 18, 1),
48
-
FUNC("gpio", 1, 18, 1),
46
+
FUNC("pwm0 utif", 2, 18, 1),
49
47
FUNC("pwm0", 0, 18, 1),
50
48
};
51
49
52
50
static struct mtmips_pmx_func uart2_grp[] = {
53
51
FUNC("sdxc d5 d4", 3, 20, 2),
54
-
FUNC("pwm", 2, 20, 2),
55
-
FUNC("gpio", 1, 20, 2),
52
+
FUNC("uart2 pwm", 2, 20, 2),
56
53
FUNC("uart2", 0, 20, 2),
57
54
};
58
55
59
56
static struct mtmips_pmx_func uart1_grp[] = {
60
57
FUNC("sw_r", 3, 45, 2),
61
-
FUNC("pwm", 2, 45, 2),
62
-
FUNC("gpio", 1, 45, 2),
58
+
FUNC("uart1 pwm", 2, 45, 2),
63
59
FUNC("uart1", 0, 45, 2),
64
60
};
65
61
66
62
static struct mtmips_pmx_func i2c_grp[] = {
67
-
FUNC("-", 3, 4, 2),
68
63
FUNC("debug", 2, 4, 2),
69
-
FUNC("gpio", 1, 4, 2),
70
64
FUNC("i2c", 0, 4, 2),
71
65
};
72
66
···
70
76
static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 7, 4) };
71
77
72
78
static struct mtmips_pmx_func sd_mode_grp[] = {
73
-
FUNC("jtag", 3, 22, 8),
74
-
FUNC("utif", 2, 22, 8),
75
-
FUNC("gpio", 1, 22, 8),
79
+
FUNC("sdxc jtag", 3, 22, 8),
80
+
FUNC("sdxc utif", 2, 22, 8),
76
81
FUNC("sdxc", 0, 22, 8),
77
82
};
78
83
79
84
static struct mtmips_pmx_func uart0_grp[] = {
80
-
FUNC("-", 3, 12, 2),
81
-
FUNC("-", 2, 12, 2),
82
-
FUNC("gpio", 1, 12, 2),
83
85
FUNC("uart0", 0, 12, 2),
84
86
};
85
87
86
88
static struct mtmips_pmx_func i2s_grp[] = {
87
89
FUNC("antenna", 3, 0, 4),
88
90
FUNC("pcm", 2, 0, 4),
89
-
FUNC("gpio", 1, 0, 4),
90
91
FUNC("i2s", 0, 0, 4),
91
92
};
92
93
93
94
static struct mtmips_pmx_func spi_cs1_grp[] = {
94
-
FUNC("-", 3, 6, 1),
95
-
FUNC("refclk", 2, 6, 1),
96
-
FUNC("gpio", 1, 6, 1),
95
+
FUNC("spi refclk", 2, 6, 1),
97
96
FUNC("spi cs1", 0, 6, 1),
98
97
};
99
98
100
99
static struct mtmips_pmx_func spis_grp[] = {
101
100
FUNC("pwm_uart2", 3, 14, 4),
102
-
FUNC("utif", 2, 14, 4),
103
-
FUNC("gpio", 1, 14, 4),
101
+
FUNC("spis utif", 2, 14, 4),
104
102
FUNC("spis", 0, 14, 4),
105
103
};
106
104
107
105
static struct mtmips_pmx_func gpio_grp[] = {
108
106
FUNC("pcie", 3, 11, 1),
109
-
FUNC("refclk", 2, 11, 1),
110
-
FUNC("gpio", 1, 11, 1),
111
-
FUNC("gpio", 0, 11, 1),
107
+
FUNC("gpio refclk", 2, 11, 1),
112
108
};
113
109
114
110
static struct mtmips_pmx_func p4led_kn_grp[] = {
115
-
FUNC("jtag", 3, 30, 1),
116
-
FUNC("utif", 2, 30, 1),
117
-
FUNC("gpio", 1, 30, 1),
111
+
FUNC("p4led_kn jtag", 3, 30, 1),
112
+
FUNC("p4led_kn utif", 2, 30, 1),
118
113
FUNC("p4led_kn", 0, 30, 1),
119
114
};
120
115
121
116
static struct mtmips_pmx_func p3led_kn_grp[] = {
122
-
FUNC("jtag", 3, 31, 1),
123
-
FUNC("utif", 2, 31, 1),
124
-
FUNC("gpio", 1, 31, 1),
117
+
FUNC("p3led_kn jtag", 3, 31, 1),
118
+
FUNC("p3led_kn utif", 2, 31, 1),
125
119
FUNC("p3led_kn", 0, 31, 1),
126
120
};
127
121
128
122
static struct mtmips_pmx_func p2led_kn_grp[] = {
129
-
FUNC("jtag", 3, 32, 1),
130
-
FUNC("utif", 2, 32, 1),
131
-
FUNC("gpio", 1, 32, 1),
123
+
FUNC("p2led_kn jtag", 3, 32, 1),
124
+
FUNC("p2led_kn utif", 2, 32, 1),
132
125
FUNC("p2led_kn", 0, 32, 1),
133
126
};
134
127
135
128
static struct mtmips_pmx_func p1led_kn_grp[] = {
136
-
FUNC("jtag", 3, 33, 1),
137
-
FUNC("utif", 2, 33, 1),
138
-
FUNC("gpio", 1, 33, 1),
129
+
FUNC("p1led_kn jtag", 3, 33, 1),
130
+
FUNC("p1led_kn utif", 2, 33, 1),
139
131
FUNC("p1led_kn", 0, 33, 1),
140
132
};
141
133
142
134
static struct mtmips_pmx_func p0led_kn_grp[] = {
143
-
FUNC("jtag", 3, 34, 1),
144
-
FUNC("rsvd", 2, 34, 1),
145
-
FUNC("gpio", 1, 34, 1),
135
+
FUNC("p0led_kn jtag", 3, 34, 1),
146
136
FUNC("p0led_kn", 0, 34, 1),
147
137
};
148
138
149
139
static struct mtmips_pmx_func wled_kn_grp[] = {
150
-
FUNC("rsvd", 3, 35, 1),
151
-
FUNC("rsvd", 2, 35, 1),
152
-
FUNC("gpio", 1, 35, 1),
153
140
FUNC("wled_kn", 0, 35, 1),
154
141
};
155
142
156
143
static struct mtmips_pmx_func p4led_an_grp[] = {
157
-
FUNC("jtag", 3, 39, 1),
158
-
FUNC("utif", 2, 39, 1),
159
-
FUNC("gpio", 1, 39, 1),
144
+
FUNC("p4led_an jtag", 3, 39, 1),
145
+
FUNC("p4led_an utif", 2, 39, 1),
160
146
FUNC("p4led_an", 0, 39, 1),
161
147
};
162
148
163
149
static struct mtmips_pmx_func p3led_an_grp[] = {
164
-
FUNC("jtag", 3, 40, 1),
165
-
FUNC("utif", 2, 40, 1),
166
-
FUNC("gpio", 1, 40, 1),
150
+
FUNC("p3led_an jtag", 3, 40, 1),
151
+
FUNC("p3led_an utif", 2, 40, 1),
167
152
FUNC("p3led_an", 0, 40, 1),
168
153
};
169
154
170
155
static struct mtmips_pmx_func p2led_an_grp[] = {
171
-
FUNC("jtag", 3, 41, 1),
172
-
FUNC("utif", 2, 41, 1),
173
-
FUNC("gpio", 1, 41, 1),
156
+
FUNC("p2led_an jtag", 3, 41, 1),
157
+
FUNC("p2led_an utif", 2, 41, 1),
174
158
FUNC("p2led_an", 0, 41, 1),
175
159
};
176
160
177
161
static struct mtmips_pmx_func p1led_an_grp[] = {
178
-
FUNC("jtag", 3, 42, 1),
179
-
FUNC("utif", 2, 42, 1),
180
-
FUNC("gpio", 1, 42, 1),
162
+
FUNC("p1led_an jtag", 3, 42, 1),
163
+
FUNC("p1led_an utif", 2, 42, 1),
181
164
FUNC("p1led_an", 0, 42, 1),
182
165
};
183
166
184
167
static struct mtmips_pmx_func p0led_an_grp[] = {
185
-
FUNC("jtag", 3, 43, 1),
186
-
FUNC("rsvd", 2, 43, 1),
187
-
FUNC("gpio", 1, 43, 1),
168
+
FUNC("p0led_an jtag", 3, 43, 1),
188
169
FUNC("p0led_an", 0, 43, 1),
189
170
};
190
171
191
172
static struct mtmips_pmx_func wled_an_grp[] = {
192
-
FUNC("rsvd", 3, 44, 1),
193
-
FUNC("rsvd", 2, 44, 1),
194
-
FUNC("gpio", 1, 44, 1),
195
173
FUNC("wled_an", 0, 44, 1),
196
174
};
197
175
+17
-17
drivers/pinctrl/mediatek/pinctrl-mt7981.c
+17
-17
drivers/pinctrl/mediatek/pinctrl-mt7981.c
···
978
978
static const char *mt7981_ant_groups[] = { "ant_sel", };
979
979
980
980
static const struct function_desc mt7981_functions[] = {
981
-
{"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
982
-
{"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
983
-
{"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
984
-
{"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
985
-
{"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
986
-
{"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
987
-
{"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
988
-
{"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
989
-
{"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
990
-
{"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
991
-
{"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
992
-
{"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
993
-
{"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
994
-
{"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
995
-
{"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
996
-
{"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
997
-
{"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
981
+
PINCTRL_PIN_FUNCTION("wa_aice", mt7981_wa_aice),
982
+
PINCTRL_PIN_FUNCTION("dfd", mt7981_dfd),
983
+
PINCTRL_PIN_FUNCTION("jtag", mt7981_jtag),
984
+
PINCTRL_PIN_FUNCTION("pta", mt7981_pta),
985
+
PINCTRL_PIN_FUNCTION("pcm", mt7981_pcm),
986
+
PINCTRL_PIN_FUNCTION("udi", mt7981_udi),
987
+
PINCTRL_PIN_FUNCTION("usb", mt7981_usb),
988
+
PINCTRL_PIN_FUNCTION("ant", mt7981_ant),
989
+
PINCTRL_PIN_FUNCTION("eth", mt7981_ethernet),
990
+
PINCTRL_PIN_FUNCTION("i2c", mt7981_i2c),
991
+
PINCTRL_PIN_FUNCTION("led", mt7981_led),
992
+
PINCTRL_PIN_FUNCTION("pwm", mt7981_pwm),
993
+
PINCTRL_PIN_FUNCTION("spi", mt7981_spi),
994
+
PINCTRL_PIN_FUNCTION("uart", mt7981_uart),
995
+
PINCTRL_PIN_FUNCTION("watchdog", mt7981_wdt),
996
+
PINCTRL_PIN_FUNCTION("flash", mt7981_flash),
997
+
PINCTRL_PIN_FUNCTION("pcie", mt7981_pcie),
998
998
};
999
999
1000
1000
static const struct mtk_eint_hw mt7981_eint_hw = {
+12
-12
drivers/pinctrl/mediatek/pinctrl-mt7986.c
+12
-12
drivers/pinctrl/mediatek/pinctrl-mt7986.c
···
879
879
static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
880
880
881
881
static const struct function_desc mt7986_functions[] = {
882
-
{"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
883
-
{"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
884
-
{"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
885
-
{"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
886
-
{"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
887
-
{"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
888
-
{"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
889
-
{"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
890
-
{"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
891
-
{"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
892
-
{"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
893
-
{"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
882
+
PINCTRL_PIN_FUNCTION("audio", mt7986_audio),
883
+
PINCTRL_PIN_FUNCTION("emmc", mt7986_emmc),
884
+
PINCTRL_PIN_FUNCTION("eth", mt7986_ethernet),
885
+
PINCTRL_PIN_FUNCTION("i2c", mt7986_i2c),
886
+
PINCTRL_PIN_FUNCTION("led", mt7986_led),
887
+
PINCTRL_PIN_FUNCTION("flash", mt7986_flash),
888
+
PINCTRL_PIN_FUNCTION("pcie", mt7986_pcie),
889
+
PINCTRL_PIN_FUNCTION("pwm", mt7986_pwm),
890
+
PINCTRL_PIN_FUNCTION("spi", mt7986_spi),
891
+
PINCTRL_PIN_FUNCTION("uart", mt7986_uart),
892
+
PINCTRL_PIN_FUNCTION("watchdog", mt7986_wdt),
893
+
PINCTRL_PIN_FUNCTION("wifi", mt7986_wf),
894
894
};
895
895
896
896
static const struct mtk_eint_hw mt7986a_eint_hw = {
+1
-3
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+1
-3
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
···
621
621
struct device_node *np_config,
622
622
struct pinctrl_map **map, unsigned *num_maps)
623
623
{
624
-
struct device_node *np;
625
624
unsigned reserved_maps;
626
625
int ret;
627
626
···
628
629
*num_maps = 0;
629
630
reserved_maps = 0;
630
631
631
-
for_each_child_of_node(np_config, np) {
632
+
for_each_child_of_node_scoped(np_config, np) {
632
633
ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
633
634
&reserved_maps, num_maps);
634
635
if (ret < 0) {
635
636
pinctrl_utils_free_map(pctldev, *map, *num_maps);
636
-
of_node_put(np);
637
637
return ret;
638
638
}
639
639
}
+1
-3
drivers/pinctrl/mediatek/pinctrl-paris.c
+1
-3
drivers/pinctrl/mediatek/pinctrl-paris.c
···
536
536
struct pinctrl_map **map,
537
537
unsigned *num_maps)
538
538
{
539
-
struct device_node *np;
540
539
unsigned reserved_maps;
541
540
int ret;
542
541
···
543
544
*num_maps = 0;
544
545
reserved_maps = 0;
545
546
546
-
for_each_child_of_node(np_config, np) {
547
+
for_each_child_of_node_scoped(np_config, np) {
547
548
ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
548
549
&reserved_maps,
549
550
num_maps);
550
551
if (ret < 0) {
551
552
pinctrl_utils_free_map(pctldev, *map, *num_maps);
552
-
of_node_put(np);
553
553
return ret;
554
554
}
555
555
}
+1
drivers/pinctrl/meson/pinctrl-meson-a1.c
+1
drivers/pinctrl/meson/pinctrl-meson-a1.c
+1
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
+1
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
+1
drivers/pinctrl/meson/pinctrl-meson-axg.c
+1
drivers/pinctrl/meson/pinctrl-meson-axg.c
+1
drivers/pinctrl/meson/pinctrl-meson-g12a.c
+1
drivers/pinctrl/meson/pinctrl-meson-g12a.c
+1
drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+1
drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+1
drivers/pinctrl/meson/pinctrl-meson-gxl.c
+1
drivers/pinctrl/meson/pinctrl-meson-gxl.c
+1
drivers/pinctrl/meson/pinctrl-meson-s4.c
+1
drivers/pinctrl/meson/pinctrl-meson-s4.c
+1
drivers/pinctrl/meson/pinctrl-meson.c
+1
drivers/pinctrl/meson/pinctrl-meson.c
+1
drivers/pinctrl/meson/pinctrl-meson8-pmx.c
+1
drivers/pinctrl/meson/pinctrl-meson8-pmx.c
+1
-3
drivers/pinctrl/nomadik/pinctrl-abx500.c
+1
-3
drivers/pinctrl/nomadik/pinctrl-abx500.c
···
811
811
struct pinctrl_map **map, unsigned *num_maps)
812
812
{
813
813
unsigned reserved_maps;
814
-
struct device_node *np;
815
814
int ret;
816
815
817
816
reserved_maps = 0;
818
817
*map = NULL;
819
818
*num_maps = 0;
820
819
821
-
for_each_child_of_node(np_config, np) {
820
+
for_each_child_of_node_scoped(np_config, np) {
822
821
ret = abx500_dt_subnode_to_map(pctldev, np, map,
823
822
&reserved_maps, num_maps);
824
823
if (ret < 0) {
825
824
pinctrl_utils_free_map(pctldev, *map, *num_maps);
826
-
of_node_put(np);
827
825
return ret;
828
826
}
829
827
}
+1
-3
drivers/pinctrl/nomadik/pinctrl-nomadik.c
+1
-3
drivers/pinctrl/nomadik/pinctrl-nomadik.c
···
804
804
unsigned int *num_maps)
805
805
{
806
806
unsigned int reserved_maps;
807
-
struct device_node *np;
808
807
int ret;
809
808
810
809
reserved_maps = 0;
811
810
*map = NULL;
812
811
*num_maps = 0;
813
812
814
-
for_each_child_of_node(np_config, np) {
813
+
for_each_child_of_node_scoped(np_config, np) {
815
814
ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
816
815
&reserved_maps, num_maps);
817
816
if (ret < 0) {
818
817
pinctrl_utils_free_map(pctldev, *map, *num_maps);
819
-
of_node_put(np);
820
818
return ret;
821
819
}
822
820
}
+19
drivers/pinctrl/nuvoton/Kconfig
+19
drivers/pinctrl/nuvoton/Kconfig
···
45
45
Say Y or M here to enable pin controller and GPIO support for
46
46
the Nuvoton NPCM8XX SoC. This is strongly recommended when
47
47
building a kernel that will run on this chip.
48
+
49
+
config PINCTRL_MA35
50
+
bool
51
+
depends on (ARCH_MA35 || COMPILE_TEST) && OF
52
+
select GENERIC_PINCTRL_GROUPS
53
+
select GENERIC_PINMUX_FUNCTIONS
54
+
select GENERIC_PINCONF
55
+
select GPIOLIB
56
+
select GPIO_GENERIC
57
+
select GPIOLIB_IRQCHIP
58
+
select MFD_SYSCON
59
+
60
+
config PINCTRL_MA35D1
61
+
bool "Pinctrl and GPIO driver for Nuvoton MA35D1"
62
+
depends on (ARCH_MA35 || COMPILE_TEST) && OF
63
+
select PINCTRL_MA35
64
+
help
65
+
Say Y here to enable pin controller and GPIO support
66
+
for Nuvoton MA35D1 SoC.
+2
drivers/pinctrl/nuvoton/Makefile
+2
drivers/pinctrl/nuvoton/Makefile
+1187
drivers/pinctrl/nuvoton/pinctrl-ma35.c
+1187
drivers/pinctrl/nuvoton/pinctrl-ma35.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2024 Nuvoton Technology Corp.
4
+
*
5
+
* Author: Shan-Chun Hung <schung@nuvoton.com>
6
+
* * Jacky Huang <ychuang3@nuvoton.com>
7
+
*/
8
+
9
+
#include <linux/bitfield.h>
10
+
#include <linux/bitops.h>
11
+
#include <linux/cleanup.h>
12
+
#include <linux/clk.h>
13
+
#include <linux/gpio/driver.h>
14
+
#include <linux/mfd/syscon.h>
15
+
#include <linux/of.h>
16
+
#include <linux/platform_device.h>
17
+
#include <linux/property.h>
18
+
#include <linux/regmap.h>
19
+
20
+
#include <linux/pinctrl/pinconf.h>
21
+
#include <linux/pinctrl/pinctrl.h>
22
+
#include "../core.h"
23
+
#include "../pinconf.h"
24
+
#include "pinctrl-ma35.h"
25
+
26
+
#define MA35_MFP_REG_BASE 0x80
27
+
#define MA35_MFP_REG_SZ_PER_BANK 8
28
+
#define MA35_MFP_BITS_PER_PORT 4
29
+
30
+
#define MA35_GPIO_BANK_MAX 14
31
+
#define MA35_GPIO_PORT_MAX 16
32
+
33
+
/* GPIO control registers */
34
+
#define MA35_GP_REG_MODE 0x00
35
+
#define MA35_GP_REG_DINOFF 0x04
36
+
#define MA35_GP_REG_DOUT 0x08
37
+
#define MA35_GP_REG_DATMSK 0x0c
38
+
#define MA35_GP_REG_PIN 0x10
39
+
#define MA35_GP_REG_DBEN 0x14
40
+
#define MA35_GP_REG_INTTYPE 0x18
41
+
#define MA35_GP_REG_INTEN 0x1c
42
+
#define MA35_GP_REG_INTSRC 0x20
43
+
#define MA35_GP_REG_SMTEN 0x24
44
+
#define MA35_GP_REG_SLEWCTL 0x28
45
+
#define MA35_GP_REG_SPW 0x2c
46
+
#define MA35_GP_REG_PUSEL 0x30
47
+
#define MA35_GP_REG_DSL 0x38
48
+
#define MA35_GP_REG_DSH 0x3c
49
+
50
+
/* GPIO mode control */
51
+
#define MA35_GP_MODE_INPUT 0x0
52
+
#define MA35_GP_MODE_OUTPUT 0x1
53
+
#define MA35_GP_MODE_OPEN_DRAIN 0x2
54
+
#define MA35_GP_MODE_QUASI 0x3
55
+
#define MA35_GP_MODE_MASK(n) GENMASK(n * 2 + 1, n * 2)
56
+
57
+
#define MA35_GP_SLEWCTL_MASK(n) GENMASK(n * 2 + 1, n * 2)
58
+
59
+
/* GPIO pull-up and pull-down selection control */
60
+
#define MA35_GP_PUSEL_DISABLE 0x0
61
+
#define MA35_GP_PUSEL_PULL_UP 0x1
62
+
#define MA35_GP_PUSEL_PULL_DOWN 0x2
63
+
#define MA35_GP_PUSEL_MASK(n) GENMASK(n * 2 + 1, n * 2)
64
+
65
+
/*
66
+
* The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
67
+
* while bits 16 ~ 31 control high-level or rising edge trigger.
68
+
*/
69
+
#define MA35_GP_INTEN_L(n) BIT(n)
70
+
#define MA35_GP_INTEN_H(n) BIT(n + 16)
71
+
#define MA35_GP_INTEN_BOTH(n) (MA35_GP_INTEN_H(n) | MA35_GP_INTEN_L(n))
72
+
73
+
/*
74
+
* The MA35_GP_REG_DSL register controls ports 0 to 7, while the MA35_GP_REG_DSH
75
+
* register controls ports 8 to 15. Each port occupies a width of 4 bits, with 3
76
+
* bits being effective.
77
+
*/
78
+
#define MA35_GP_DS_REG(n) (n < 8 ? MA35_GP_REG_DSL : MA35_GP_REG_DSH)
79
+
#define MA35_GP_DS_MASK(n) GENMASK((n % 8) * 4 + 3, (n % 8) * 4)
80
+
81
+
#define MVOLT_1800 0
82
+
#define MVOLT_3300 1
83
+
84
+
/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
85
+
#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
86
+
#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
87
+
88
+
static const char * const gpio_group_name[] = {
89
+
"gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog",
90
+
"gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion",
91
+
};
92
+
93
+
static const u32 ds_1800mv_tbl[] = {
94
+
2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000,
95
+
};
96
+
97
+
static const u32 ds_3300mv_tbl[] = {
98
+
17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000,
99
+
};
100
+
101
+
struct ma35_pin_func {
102
+
const char *name;
103
+
const char **groups;
104
+
u32 ngroups;
105
+
};
106
+
107
+
struct ma35_pin_setting {
108
+
u32 offset;
109
+
u32 shift;
110
+
u32 muxval;
111
+
unsigned long *configs;
112
+
unsigned int nconfigs;
113
+
};
114
+
115
+
struct ma35_pin_group {
116
+
const char *name;
117
+
unsigned int npins;
118
+
unsigned int *pins;
119
+
struct ma35_pin_setting *settings;
120
+
};
121
+
122
+
struct ma35_pin_bank {
123
+
void __iomem *reg_base;
124
+
struct clk *clk;
125
+
int irq;
126
+
u8 bank_num;
127
+
u8 nr_pins;
128
+
bool valid;
129
+
const char *name;
130
+
struct fwnode_handle *fwnode;
131
+
struct gpio_chip chip;
132
+
u32 irqtype;
133
+
u32 irqinten;
134
+
struct regmap *regmap;
135
+
struct device *dev;
136
+
};
137
+
138
+
struct ma35_pin_ctrl {
139
+
struct ma35_pin_bank *pin_banks;
140
+
u32 nr_banks;
141
+
u32 nr_pins;
142
+
};
143
+
144
+
struct ma35_pinctrl {
145
+
struct device *dev;
146
+
struct ma35_pin_ctrl *ctrl;
147
+
struct pinctrl_dev *pctl;
148
+
const struct ma35_pinctrl_soc_info *info;
149
+
struct regmap *regmap;
150
+
struct ma35_pin_group *groups;
151
+
unsigned int ngroups;
152
+
struct ma35_pin_func *functions;
153
+
unsigned int nfunctions;
154
+
};
155
+
156
+
static DEFINE_RAW_SPINLOCK(ma35_lock);
157
+
158
+
static int ma35_get_groups_count(struct pinctrl_dev *pctldev)
159
+
{
160
+
struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
161
+
162
+
return npctl->ngroups;
163
+
}
164
+
165
+
static const char *ma35_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
166
+
{
167
+
struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
168
+
169
+
return npctl->groups[selector].name;
170
+
}
171
+
172
+
static int ma35_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
173
+
const unsigned int **pins, unsigned int *npins)
174
+
{
175
+
struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
176
+
177
+
if (selector >= npctl->ngroups)
178
+
return -EINVAL;
179
+
180
+
*pins = npctl->groups[selector].pins;
181
+
*npins = npctl->groups[selector].npins;
182
+
183
+
return 0;
184
+
}
185
+
186
+
static struct ma35_pin_group *ma35_pinctrl_find_group_by_name(
187
+
const struct ma35_pinctrl *npctl, const char *name)
188
+
{
189
+
int i;
190
+
191
+
for (i = 0; i < npctl->ngroups; i++) {
192
+
if (!strcmp(npctl->groups[i].name, name))
193
+
return &npctl->groups[i];
194
+
}
195
+
return NULL;
196
+
}
197
+
198
+
static int ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev *pctldev,
199
+
struct device_node *np,
200
+
struct pinctrl_map **map,
201
+
unsigned int *num_maps)
202
+
{
203
+
struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
204
+
struct ma35_pin_group *grp;
205
+
struct pinctrl_map *new_map;
206
+
struct device_node *parent;
207
+
int map_num = 1;
208
+
int i;
209
+
210
+
/*
211
+
* first find the group of this node and check if we need create
212
+
* config maps for pins
213
+
*/
214
+
grp = ma35_pinctrl_find_group_by_name(npctl, np->name);
215
+
if (!grp) {
216
+
dev_err(npctl->dev, "unable to find group for node %s\n", np->name);
217
+
return -EINVAL;
218
+
}
219
+
220
+
map_num += grp->npins;
221
+
new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), GFP_KERNEL);
222
+
if (!new_map)
223
+
return -ENOMEM;
224
+
225
+
*map = new_map;
226
+
*num_maps = map_num;
227
+
/* create mux map */
228
+
parent = of_get_parent(np);
229
+
if (!parent)
230
+
return -EINVAL;
231
+
232
+
new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
233
+
new_map[0].data.mux.function = parent->name;
234
+
new_map[0].data.mux.group = np->name;
235
+
of_node_put(parent);
236
+
237
+
new_map++;
238
+
for (i = 0; i < grp->npins; i++) {
239
+
new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
240
+
new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->pins[i]);
241
+
new_map[i].data.configs.configs = grp->settings[i].configs;
242
+
new_map[i].data.configs.num_configs = grp->settings[i].nconfigs;
243
+
}
244
+
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
245
+
(*map)->data.mux.function, (*map)->data.mux.group, map_num);
246
+
247
+
return 0;
248
+
}
249
+
250
+
static const struct pinctrl_ops ma35_pctrl_ops = {
251
+
.get_groups_count = ma35_get_groups_count,
252
+
.get_group_name = ma35_get_group_name,
253
+
.get_group_pins = ma35_get_group_pins,
254
+
.dt_node_to_map = ma35_pinctrl_dt_node_to_map_func,
255
+
.dt_free_map = pinconf_generic_dt_free_map,
256
+
};
257
+
258
+
static int ma35_pinmux_get_func_count(struct pinctrl_dev *pctldev)
259
+
{
260
+
struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
261
+
262
+
return npctl->nfunctions;
263
+
}
264
+
265
+
static const char *ma35_pinmux_get_func_name(struct pinctrl_dev *pctldev,
266
+
unsigned int selector)
267
+
{
268
+
struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
269
+
270
+
return npctl->functions[selector].name;
271
+
}
272
+
273
+
static int ma35_pinmux_get_func_groups(struct pinctrl_dev *pctldev,
274
+
unsigned int function,
275
+
const char *const **groups,
276
+
unsigned int *const num_groups)
277
+
{
278
+
struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
279
+
280
+
*groups = npctl->functions[function].groups;
281
+
*num_groups = npctl->functions[function].ngroups;
282
+
283
+
return 0;
284
+
}
285
+
286
+
static int ma35_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
287
+
unsigned int group)
288
+
{
289
+
struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
290
+
struct ma35_pin_group *grp = &npctl->groups[group];
291
+
struct ma35_pin_setting *setting = grp->settings;
292
+
u32 i, regval;
293
+
294
+
dev_dbg(npctl->dev, "enable function %s group %s\n",
295
+
npctl->functions[selector].name, npctl->groups[group].name);
296
+
297
+
for (i = 0; i < grp->npins; i++) {
298
+
regmap_read(npctl->regmap, setting->offset, ®val);
299
+
regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1,
300
+
setting->shift);
301
+
regval |= setting->muxval << setting->shift;
302
+
regmap_write(npctl->regmap, setting->offset, regval);
303
+
setting++;
304
+
}
305
+
return 0;
306
+
}
307
+
308
+
static const struct pinmux_ops ma35_pmx_ops = {
309
+
.get_functions_count = ma35_pinmux_get_func_count,
310
+
.get_function_name = ma35_pinmux_get_func_name,
311
+
.get_function_groups = ma35_pinmux_get_func_groups,
312
+
.set_mux = ma35_pinmux_set_mux,
313
+
.strict = true,
314
+
};
315
+
316
+
static void ma35_gpio_set_mode(void __iomem *reg_mode, unsigned int gpio, u32 mode)
317
+
{
318
+
u32 regval = readl(reg_mode);
319
+
320
+
regval &= ~MA35_GP_MODE_MASK(gpio);
321
+
regval |= field_prep(MA35_GP_MODE_MASK(gpio), mode);
322
+
323
+
writel(regval, reg_mode);
324
+
}
325
+
326
+
static u32 ma35_gpio_get_mode(void __iomem *reg_mode, unsigned int gpio)
327
+
{
328
+
u32 regval = readl(reg_mode);
329
+
330
+
return field_get(MA35_GP_MODE_MASK(gpio), regval);
331
+
}
332
+
333
+
static int ma35_gpio_core_direction_in(struct gpio_chip *gc, unsigned int gpio)
334
+
{
335
+
struct ma35_pin_bank *bank = gpiochip_get_data(gc);
336
+
void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
337
+
338
+
guard(raw_spinlock_irqsave)(&ma35_lock);
339
+
340
+
ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_INPUT);
341
+
342
+
return 0;
343
+
}
344
+
345
+
static int ma35_gpio_core_direction_out(struct gpio_chip *gc, unsigned int gpio, int val)
346
+
{
347
+
struct ma35_pin_bank *bank = gpiochip_get_data(gc);
348
+
void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
349
+
void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
350
+
unsigned int regval;
351
+
352
+
guard(raw_spinlock_irqsave)(&ma35_lock);
353
+
354
+
regval = readl(reg_dout);
355
+
if (val)
356
+
regval |= BIT(gpio);
357
+
else
358
+
regval &= ~BIT(gpio);
359
+
writel(regval, reg_dout);
360
+
361
+
ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_OUTPUT);
362
+
363
+
return 0;
364
+
}
365
+
366
+
static int ma35_gpio_core_get(struct gpio_chip *gc, unsigned int gpio)
367
+
{
368
+
struct ma35_pin_bank *bank = gpiochip_get_data(gc);
369
+
void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN;
370
+
371
+
return !!(readl(reg_pin) & BIT(gpio));
372
+
}
373
+
374
+
static void ma35_gpio_core_set(struct gpio_chip *gc, unsigned int gpio, int val)
375
+
{
376
+
struct ma35_pin_bank *bank = gpiochip_get_data(gc);
377
+
void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
378
+
u32 regval;
379
+
380
+
if (val)
381
+
regval = readl(reg_dout) | BIT(gpio);
382
+
else
383
+
regval = readl(reg_dout) & ~BIT(gpio);
384
+
385
+
writel(regval, reg_dout);
386
+
}
387
+
388
+
static int ma35_gpio_core_to_request(struct gpio_chip *gc, unsigned int gpio)
389
+
{
390
+
struct ma35_pin_bank *bank = gpiochip_get_data(gc);
391
+
u32 reg_offs, bit_offs, regval;
392
+
393
+
if (gpio < 8) {
394
+
/* The MFP low register controls port 0 ~ 7 */
395
+
reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK;
396
+
bit_offs = gpio * MA35_MFP_BITS_PER_PORT;
397
+
} else {
398
+
/* The MFP high register controls port 8 ~ 15 */
399
+
reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK + 4;
400
+
bit_offs = (gpio - 8) * MA35_MFP_BITS_PER_PORT;
401
+
}
402
+
403
+
regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, ®val);
404
+
regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs);
405
+
regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval);
406
+
407
+
return 0;
408
+
}
409
+
410
+
static void ma35_irq_gpio_ack(struct irq_data *d)
411
+
{
412
+
struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
413
+
void __iomem *reg_intsrc = bank->reg_base + MA35_GP_REG_INTSRC;
414
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
415
+
416
+
writel(BIT(hwirq), reg_intsrc);
417
+
}
418
+
419
+
static void ma35_irq_gpio_mask(struct irq_data *d)
420
+
{
421
+
struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
422
+
void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
423
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
424
+
u32 regval;
425
+
426
+
regval = readl(reg_ien);
427
+
428
+
regval &= ~MA35_GP_INTEN_BOTH(hwirq);
429
+
430
+
writel(regval, reg_ien);
431
+
}
432
+
433
+
static void ma35_irq_gpio_unmask(struct irq_data *d)
434
+
{
435
+
struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
436
+
void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE;
437
+
void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
438
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
439
+
u32 bval, regval;
440
+
441
+
bval = bank->irqtype & BIT(hwirq);
442
+
regval = readl(reg_itype);
443
+
regval &= ~BIT(hwirq);
444
+
writel(regval | bval, reg_itype);
445
+
446
+
bval = bank->irqinten & MA35_GP_INTEN_BOTH(hwirq);
447
+
regval = readl(reg_ien);
448
+
regval &= ~MA35_GP_INTEN_BOTH(hwirq);
449
+
writel(regval | bval, reg_ien);
450
+
}
451
+
452
+
static int ma35_irq_irqtype(struct irq_data *d, unsigned int type)
453
+
{
454
+
struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
455
+
irq_hw_number_t hwirq = irqd_to_hwirq(d);
456
+
457
+
switch (type) {
458
+
case IRQ_TYPE_EDGE_BOTH:
459
+
irq_set_handler_locked(d, handle_edge_irq);
460
+
bank->irqtype &= ~BIT(hwirq);
461
+
bank->irqinten |= MA35_GP_INTEN_BOTH(hwirq);
462
+
break;
463
+
case IRQ_TYPE_EDGE_RISING:
464
+
case IRQ_TYPE_LEVEL_HIGH:
465
+
irq_set_handler_locked(d, handle_edge_irq);
466
+
bank->irqtype &= ~BIT(hwirq);
467
+
bank->irqinten |= MA35_GP_INTEN_H(hwirq);
468
+
bank->irqinten &= ~MA35_GP_INTEN_L(hwirq);
469
+
break;
470
+
case IRQ_TYPE_EDGE_FALLING:
471
+
case IRQ_TYPE_LEVEL_LOW:
472
+
irq_set_handler_locked(d, handle_edge_irq);
473
+
bank->irqtype &= ~BIT(hwirq);
474
+
bank->irqinten |= MA35_GP_INTEN_L(hwirq);
475
+
bank->irqinten &= ~MA35_GP_INTEN_H(hwirq);
476
+
break;
477
+
default:
478
+
return -EINVAL;
479
+
}
480
+
481
+
writel(bank->irqtype, bank->reg_base + MA35_GP_REG_INTTYPE);
482
+
writel(bank->irqinten, bank->reg_base + MA35_GP_REG_INTEN);
483
+
484
+
return 0;
485
+
}
486
+
487
+
static struct irq_chip ma35_gpio_irqchip = {
488
+
.name = "MA35-GPIO-IRQ",
489
+
.irq_disable = ma35_irq_gpio_mask,
490
+
.irq_enable = ma35_irq_gpio_unmask,
491
+
.irq_ack = ma35_irq_gpio_ack,
492
+
.irq_mask = ma35_irq_gpio_mask,
493
+
.irq_unmask = ma35_irq_gpio_unmask,
494
+
.irq_set_type = ma35_irq_irqtype,
495
+
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
496
+
GPIOCHIP_IRQ_RESOURCE_HELPERS,
497
+
};
498
+
499
+
static void ma35_irq_demux_intgroup(struct irq_desc *desc)
500
+
{
501
+
struct ma35_pin_bank *bank = gpiochip_get_data(irq_desc_get_handler_data(desc));
502
+
struct irq_domain *irqdomain = bank->chip.irq.domain;
503
+
struct irq_chip *irqchip = irq_desc_get_chip(desc);
504
+
unsigned long isr;
505
+
int offset;
506
+
507
+
chained_irq_enter(irqchip, desc);
508
+
509
+
isr = readl(bank->reg_base + MA35_GP_REG_INTSRC);
510
+
511
+
for_each_set_bit(offset, &isr, bank->nr_pins)
512
+
generic_handle_irq(irq_find_mapping(irqdomain, offset));
513
+
514
+
chained_irq_exit(irqchip, desc);
515
+
}
516
+
517
+
static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinctrl *npctl)
518
+
{
519
+
struct ma35_pin_ctrl *ctrl = npctl->ctrl;
520
+
struct ma35_pin_bank *bank = ctrl->pin_banks;
521
+
int ret;
522
+
int i;
523
+
524
+
for (i = 0; i < ctrl->nr_banks; i++, bank++) {
525
+
if (!bank->valid) {
526
+
dev_warn(&pdev->dev, "%pfw: bank is not valid\n", bank->fwnode);
527
+
continue;
528
+
}
529
+
bank->irqtype = 0;
530
+
bank->irqinten = 0;
531
+
bank->chip.label = bank->name;
532
+
bank->chip.of_gpio_n_cells = 2;
533
+
bank->chip.parent = &pdev->dev;
534
+
bank->chip.request = ma35_gpio_core_to_request;
535
+
bank->chip.direction_input = ma35_gpio_core_direction_in;
536
+
bank->chip.direction_output = ma35_gpio_core_direction_out;
537
+
bank->chip.get = ma35_gpio_core_get;
538
+
bank->chip.set = ma35_gpio_core_set;
539
+
bank->chip.base = -1;
540
+
bank->chip.ngpio = bank->nr_pins;
541
+
bank->chip.can_sleep = false;
542
+
543
+
if (bank->irq > 0) {
544
+
struct gpio_irq_chip *girq;
545
+
546
+
girq = &bank->chip.irq;
547
+
gpio_irq_chip_set_chip(girq, &ma35_gpio_irqchip);
548
+
girq->parent_handler = ma35_irq_demux_intgroup;
549
+
girq->num_parents = 1;
550
+
551
+
girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
552
+
sizeof(*girq->parents), GFP_KERNEL);
553
+
if (!girq->parents)
554
+
return -ENOMEM;
555
+
556
+
girq->parents[0] = bank->irq;
557
+
girq->default_type = IRQ_TYPE_NONE;
558
+
girq->handler = handle_bad_irq;
559
+
}
560
+
561
+
ret = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
562
+
if (ret) {
563
+
dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
564
+
bank->chip.label, ret);
565
+
return ret;
566
+
}
567
+
}
568
+
return 0;
569
+
}
570
+
571
+
static int ma35_get_bank_data(struct ma35_pin_bank *bank)
572
+
{
573
+
bank->reg_base = fwnode_iomap(bank->fwnode, 0);
574
+
if (!bank->reg_base)
575
+
return -ENOMEM;
576
+
577
+
bank->irq = fwnode_irq_get(bank->fwnode, 0);
578
+
579
+
bank->nr_pins = MA35_GPIO_PORT_MAX;
580
+
581
+
bank->clk = of_clk_get(to_of_node(bank->fwnode), 0);
582
+
if (IS_ERR(bank->clk))
583
+
return PTR_ERR(bank->clk);
584
+
585
+
return clk_prepare_enable(bank->clk);
586
+
}
587
+
588
+
static int ma35_pinctrl_get_soc_data(struct ma35_pinctrl *pctl, struct platform_device *pdev)
589
+
{
590
+
struct fwnode_handle *child;
591
+
struct ma35_pin_ctrl *ctrl;
592
+
struct ma35_pin_bank *bank;
593
+
int i, id = 0;
594
+
595
+
ctrl = pctl->ctrl;
596
+
ctrl->nr_banks = MA35_GPIO_BANK_MAX;
597
+
598
+
ctrl->pin_banks = devm_kcalloc(&pdev->dev, ctrl->nr_banks,
599
+
sizeof(*ctrl->pin_banks), GFP_KERNEL);
600
+
if (!ctrl->pin_banks)
601
+
return -ENOMEM;
602
+
603
+
for (i = 0; i < ctrl->nr_banks; i++) {
604
+
ctrl->pin_banks[i].bank_num = i;
605
+
ctrl->pin_banks[i].name = gpio_group_name[i];
606
+
}
607
+
608
+
for_each_gpiochip_node(&pdev->dev, child) {
609
+
bank = &ctrl->pin_banks[id];
610
+
bank->fwnode = child;
611
+
bank->regmap = pctl->regmap;
612
+
bank->dev = &pdev->dev;
613
+
if (!ma35_get_bank_data(bank))
614
+
bank->valid = true;
615
+
id++;
616
+
}
617
+
return 0;
618
+
}
619
+
620
+
static void ma35_gpio_cla_port(unsigned int gpio_num, unsigned int *group,
621
+
unsigned int *num)
622
+
{
623
+
*group = gpio_num / MA35_GPIO_PORT_MAX;
624
+
*num = gpio_num % MA35_GPIO_PORT_MAX;
625
+
}
626
+
627
+
static int ma35_pinconf_set_pull(struct ma35_pinctrl *npctl, unsigned int pin,
628
+
int pull_up)
629
+
{
630
+
unsigned int port, group_num;
631
+
void __iomem *base;
632
+
u32 regval, pull_sel = MA35_GP_PUSEL_DISABLE;
633
+
634
+
ma35_gpio_cla_port(pin, &group_num, &port);
635
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
636
+
637
+
regval = readl(base + MA35_GP_REG_PUSEL);
638
+
regval &= ~MA35_GP_PUSEL_MASK(port);
639
+
640
+
switch (pull_up) {
641
+
case PIN_CONFIG_BIAS_PULL_UP:
642
+
pull_sel = MA35_GP_PUSEL_PULL_UP;
643
+
break;
644
+
645
+
case PIN_CONFIG_BIAS_PULL_DOWN:
646
+
pull_sel = MA35_GP_PUSEL_PULL_DOWN;
647
+
break;
648
+
649
+
case PIN_CONFIG_BIAS_DISABLE:
650
+
pull_sel = MA35_GP_PUSEL_DISABLE;
651
+
break;
652
+
}
653
+
654
+
regval |= field_prep(MA35_GP_PUSEL_MASK(port), pull_sel);
655
+
writel(regval, base + MA35_GP_REG_PUSEL);
656
+
657
+
return 0;
658
+
}
659
+
660
+
static int ma35_pinconf_get_output(struct ma35_pinctrl *npctl, unsigned int pin)
661
+
{
662
+
unsigned int port, group_num;
663
+
void __iomem *base;
664
+
u32 mode;
665
+
666
+
ma35_gpio_cla_port(pin, &group_num, &port);
667
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
668
+
669
+
mode = ma35_gpio_get_mode(base + MA35_GP_REG_MODE, port);
670
+
if (mode == MA35_GP_MODE_OUTPUT)
671
+
return 1;
672
+
673
+
return 0;
674
+
}
675
+
676
+
static int ma35_pinconf_get_pull(struct ma35_pinctrl *npctl, unsigned int pin)
677
+
{
678
+
unsigned int port, group_num;
679
+
void __iomem *base;
680
+
u32 regval, pull_sel;
681
+
682
+
ma35_gpio_cla_port(pin, &group_num, &port);
683
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
684
+
685
+
regval = readl(base + MA35_GP_REG_PUSEL);
686
+
687
+
pull_sel = field_get(MA35_GP_PUSEL_MASK(port), regval);
688
+
689
+
switch (pull_sel) {
690
+
case MA35_GP_PUSEL_PULL_UP:
691
+
return PIN_CONFIG_BIAS_PULL_UP;
692
+
693
+
case MA35_GP_PUSEL_PULL_DOWN:
694
+
return PIN_CONFIG_BIAS_PULL_DOWN;
695
+
696
+
case MA35_GP_PUSEL_DISABLE:
697
+
return PIN_CONFIG_BIAS_DISABLE;
698
+
}
699
+
700
+
return PIN_CONFIG_BIAS_DISABLE;
701
+
}
702
+
703
+
static int ma35_pinconf_set_output(struct ma35_pinctrl *npctl, unsigned int pin, bool out)
704
+
{
705
+
unsigned int port, group_num;
706
+
void __iomem *base;
707
+
708
+
ma35_gpio_cla_port(pin, &group_num, &port);
709
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
710
+
711
+
ma35_gpio_set_mode(base + MA35_GP_REG_MODE, port, MA35_GP_MODE_OUTPUT);
712
+
713
+
return 0;
714
+
}
715
+
716
+
static int ma35_pinconf_get_power_source(struct ma35_pinctrl *npctl, unsigned int pin)
717
+
{
718
+
unsigned int port, group_num;
719
+
void __iomem *base;
720
+
u32 regval;
721
+
722
+
ma35_gpio_cla_port(pin, &group_num, &port);
723
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
724
+
725
+
regval = readl(base + MA35_GP_REG_SPW);
726
+
727
+
if (regval & BIT(port))
728
+
return MVOLT_3300;
729
+
else
730
+
return MVOLT_1800;
731
+
}
732
+
733
+
static int ma35_pinconf_set_power_source(struct ma35_pinctrl *npctl,
734
+
unsigned int pin, int arg)
735
+
{
736
+
unsigned int port, group_num;
737
+
void __iomem *base;
738
+
u32 regval;
739
+
740
+
if ((arg != MVOLT_1800) && (arg != MVOLT_3300))
741
+
return -EINVAL;
742
+
743
+
ma35_gpio_cla_port(pin, &group_num, &port);
744
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
745
+
746
+
regval = readl(base + MA35_GP_REG_SPW);
747
+
748
+
if (arg == MVOLT_1800)
749
+
regval &= ~BIT(port);
750
+
else
751
+
regval |= BIT(port);
752
+
753
+
writel(regval, base + MA35_GP_REG_SPW);
754
+
755
+
return 0;
756
+
}
757
+
758
+
static int ma35_pinconf_get_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,
759
+
u32 *strength)
760
+
{
761
+
unsigned int port, group_num;
762
+
void __iomem *base;
763
+
u32 regval, ds_val;
764
+
765
+
ma35_gpio_cla_port(pin, &group_num, &port);
766
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
767
+
768
+
regval = readl(base + MA35_GP_DS_REG(port));
769
+
ds_val = field_get(MA35_GP_DS_MASK(port), regval);
770
+
771
+
if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800)
772
+
*strength = ds_1800mv_tbl[ds_val];
773
+
else
774
+
*strength = ds_3300mv_tbl[ds_val];
775
+
776
+
return 0;
777
+
}
778
+
779
+
static int ma35_pinconf_set_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,
780
+
int strength)
781
+
{
782
+
unsigned int port, group_num;
783
+
void __iomem *base;
784
+
int i, ds_val = -1;
785
+
u32 regval;
786
+
787
+
if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800) {
788
+
for (i = 0; i < ARRAY_SIZE(ds_1800mv_tbl); i++) {
789
+
if (ds_1800mv_tbl[i] == strength) {
790
+
ds_val = i;
791
+
break;
792
+
}
793
+
}
794
+
} else {
795
+
for (i = 0; i < ARRAY_SIZE(ds_3300mv_tbl); i++) {
796
+
if (ds_3300mv_tbl[i] == strength) {
797
+
ds_val = i;
798
+
break;
799
+
}
800
+
}
801
+
}
802
+
if (ds_val == -1)
803
+
return -EINVAL;
804
+
805
+
ma35_gpio_cla_port(pin, &group_num, &port);
806
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
807
+
808
+
regval = readl(base + MA35_GP_DS_REG(port));
809
+
regval &= ~MA35_GP_DS_MASK(port);
810
+
regval |= field_prep(MA35_GP_DS_MASK(port), ds_val);
811
+
812
+
writel(regval, base + MA35_GP_DS_REG(port));
813
+
814
+
return 0;
815
+
}
816
+
817
+
static int ma35_pinconf_get_schmitt_enable(struct ma35_pinctrl *npctl, unsigned int pin)
818
+
{
819
+
unsigned int port, group_num;
820
+
void __iomem *base;
821
+
u32 regval;
822
+
823
+
ma35_gpio_cla_port(pin, &group_num, &port);
824
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
825
+
826
+
regval = readl(base + MA35_GP_REG_SMTEN);
827
+
828
+
return !!(regval & BIT(port));
829
+
}
830
+
831
+
static int ma35_pinconf_set_schmitt(struct ma35_pinctrl *npctl, unsigned int pin, int enable)
832
+
{
833
+
unsigned int port, group_num;
834
+
void __iomem *base;
835
+
u32 regval;
836
+
837
+
ma35_gpio_cla_port(pin, &group_num, &port);
838
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
839
+
840
+
regval = readl(base + MA35_GP_REG_SMTEN);
841
+
842
+
if (enable)
843
+
regval |= BIT(port);
844
+
else
845
+
regval &= ~BIT(port);
846
+
847
+
writel(regval, base + MA35_GP_REG_SMTEN);
848
+
849
+
return 0;
850
+
}
851
+
852
+
static int ma35_pinconf_get_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin)
853
+
{
854
+
unsigned int port, group_num;
855
+
void __iomem *base;
856
+
u32 regval;
857
+
858
+
ma35_gpio_cla_port(pin, &group_num, &port);
859
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
860
+
861
+
regval = readl(base + MA35_GP_REG_SLEWCTL);
862
+
863
+
return field_get(MA35_GP_SLEWCTL_MASK(port), regval);
864
+
}
865
+
866
+
static int ma35_pinconf_set_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin, int rate)
867
+
{
868
+
unsigned int port, group_num;
869
+
void __iomem *base;
870
+
u32 regval;
871
+
872
+
ma35_gpio_cla_port(pin, &group_num, &port);
873
+
base = npctl->ctrl->pin_banks[group_num].reg_base;
874
+
875
+
regval = readl(base + MA35_GP_REG_SLEWCTL);
876
+
regval &= ~MA35_GP_SLEWCTL_MASK(port);
877
+
regval |= field_prep(MA35_GP_SLEWCTL_MASK(port), rate);
878
+
879
+
writel(regval, base + MA35_GP_REG_SLEWCTL);
880
+
881
+
return 0;
882
+
}
883
+
884
+
static int ma35_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config)
885
+
{
886
+
struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
887
+
enum pin_config_param param = pinconf_to_config_param(*config);
888
+
u32 arg;
889
+
int ret;
890
+
891
+
switch (param) {
892
+
case PIN_CONFIG_BIAS_DISABLE:
893
+
case PIN_CONFIG_BIAS_PULL_DOWN:
894
+
case PIN_CONFIG_BIAS_PULL_UP:
895
+
if (ma35_pinconf_get_pull(npctl, pin) != param)
896
+
return -EINVAL;
897
+
arg = 1;
898
+
break;
899
+
900
+
case PIN_CONFIG_DRIVE_STRENGTH:
901
+
ret = ma35_pinconf_get_drive_strength(npctl, pin, &arg);
902
+
if (ret)
903
+
return ret;
904
+
break;
905
+
906
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
907
+
arg = ma35_pinconf_get_schmitt_enable(npctl, pin);
908
+
break;
909
+
910
+
case PIN_CONFIG_SLEW_RATE:
911
+
arg = ma35_pinconf_get_slew_rate(npctl, pin);
912
+
break;
913
+
914
+
case PIN_CONFIG_OUTPUT_ENABLE:
915
+
arg = ma35_pinconf_get_output(npctl, pin);
916
+
break;
917
+
918
+
case PIN_CONFIG_POWER_SOURCE:
919
+
arg = ma35_pinconf_get_power_source(npctl, pin);
920
+
break;
921
+
922
+
default:
923
+
return -EINVAL;
924
+
}
925
+
*config = pinconf_to_config_packed(param, arg);
926
+
927
+
return 0;
928
+
}
929
+
930
+
static int ma35_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
931
+
unsigned long *configs, unsigned int num_configs)
932
+
{
933
+
struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
934
+
enum pin_config_param param;
935
+
unsigned int arg = 0;
936
+
int i, ret = 0;
937
+
938
+
for (i = 0; i < num_configs; i++) {
939
+
param = pinconf_to_config_param(configs[i]);
940
+
arg = pinconf_to_config_argument(configs[i]);
941
+
942
+
switch (param) {
943
+
case PIN_CONFIG_BIAS_DISABLE:
944
+
case PIN_CONFIG_BIAS_PULL_UP:
945
+
case PIN_CONFIG_BIAS_PULL_DOWN:
946
+
ret = ma35_pinconf_set_pull(npctl, pin, param);
947
+
break;
948
+
949
+
case PIN_CONFIG_DRIVE_STRENGTH:
950
+
ret = ma35_pinconf_set_drive_strength(npctl, pin, arg);
951
+
break;
952
+
953
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
954
+
ret = ma35_pinconf_set_schmitt(npctl, pin, 1);
955
+
break;
956
+
957
+
case PIN_CONFIG_INPUT_SCHMITT:
958
+
ret = ma35_pinconf_set_schmitt(npctl, pin, arg);
959
+
break;
960
+
961
+
case PIN_CONFIG_SLEW_RATE:
962
+
ret = ma35_pinconf_set_slew_rate(npctl, pin, arg);
963
+
break;
964
+
965
+
case PIN_CONFIG_OUTPUT_ENABLE:
966
+
ret = ma35_pinconf_set_output(npctl, pin, arg);
967
+
break;
968
+
969
+
case PIN_CONFIG_POWER_SOURCE:
970
+
ret = ma35_pinconf_set_power_source(npctl, pin, arg);
971
+
break;
972
+
973
+
default:
974
+
return -EINVAL;
975
+
}
976
+
977
+
if (ret)
978
+
break;
979
+
}
980
+
return ret;
981
+
}
982
+
983
+
static const struct pinconf_ops ma35_pinconf_ops = {
984
+
.pin_config_get = ma35_pinconf_get,
985
+
.pin_config_set = ma35_pinconf_set,
986
+
.is_generic = true,
987
+
};
988
+
989
+
static int ma35_pinctrl_parse_groups(struct device_node *np, struct ma35_pin_group *grp,
990
+
struct ma35_pinctrl *npctl, u32 index)
991
+
{
992
+
struct ma35_pin_setting *pin;
993
+
unsigned long *configs;
994
+
unsigned int nconfigs;
995
+
int i, j, count, ret;
996
+
u32 *elems;
997
+
998
+
grp->name = np->name;
999
+
1000
+
ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &nconfigs);
1001
+
if (ret)
1002
+
return ret;
1003
+
1004
+
count = of_property_count_elems_of_size(np, "nuvoton,pins", sizeof(u32));
1005
+
if (!count || count % 3)
1006
+
return -EINVAL;
1007
+
1008
+
elems = devm_kmalloc_array(npctl->dev, count, sizeof(u32), GFP_KERNEL);
1009
+
if (!elems)
1010
+
return -ENOMEM;
1011
+
1012
+
ret = of_property_read_u32_array(np, "nuvoton,pins", elems, count);
1013
+
if (ret)
1014
+
return -EINVAL;
1015
+
1016
+
grp->npins = count / 3;
1017
+
1018
+
grp->pins = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
1019
+
if (!grp->pins)
1020
+
return -ENOMEM;
1021
+
1022
+
grp->settings = devm_kcalloc(npctl->dev, grp->npins, sizeof(*grp->settings), GFP_KERNEL);
1023
+
if (!grp->settings)
1024
+
return -ENOMEM;
1025
+
1026
+
pin = grp->settings;
1027
+
1028
+
for (i = 0, j = 0; i < count; i += 3, j++) {
1029
+
pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE;
1030
+
pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32;
1031
+
pin->muxval = elems[i + 2];
1032
+
pin->configs = configs;
1033
+
pin->nconfigs = nconfigs;
1034
+
grp->pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift);
1035
+
pin++;
1036
+
}
1037
+
return 0;
1038
+
}
1039
+
1040
+
static int ma35_pinctrl_parse_functions(struct device_node *np, struct ma35_pinctrl *npctl,
1041
+
u32 index)
1042
+
{
1043
+
struct device_node *child;
1044
+
struct ma35_pin_func *func;
1045
+
struct ma35_pin_group *grp;
1046
+
static u32 grp_index;
1047
+
u32 ret, i = 0;
1048
+
1049
+
dev_dbg(npctl->dev, "parse function(%d): %s\n", index, np->name);
1050
+
1051
+
func = &npctl->functions[index];
1052
+
func->name = np->name;
1053
+
func->ngroups = of_get_child_count(np);
1054
+
1055
+
if (func->ngroups <= 0)
1056
+
return 0;
1057
+
1058
+
func->groups = devm_kcalloc(npctl->dev, func->ngroups, sizeof(char *), GFP_KERNEL);
1059
+
if (!func->groups)
1060
+
return -ENOMEM;
1061
+
1062
+
for_each_child_of_node(np, child) {
1063
+
func->groups[i] = child->name;
1064
+
grp = &npctl->groups[grp_index++];
1065
+
ret = ma35_pinctrl_parse_groups(child, grp, npctl, i++);
1066
+
if (ret) {
1067
+
of_node_put(child);
1068
+
return ret;
1069
+
}
1070
+
}
1071
+
return 0;
1072
+
}
1073
+
1074
+
static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinctrl *npctl)
1075
+
{
1076
+
struct fwnode_handle *child;
1077
+
u32 idx = 0;
1078
+
int ret;
1079
+
1080
+
device_for_each_child_node(&pdev->dev, child) {
1081
+
if (fwnode_property_present(child, "gpio-controller"))
1082
+
continue;
1083
+
npctl->nfunctions++;
1084
+
npctl->ngroups += of_get_child_count(to_of_node(child));
1085
+
}
1086
+
1087
+
if (!npctl->nfunctions)
1088
+
return -EINVAL;
1089
+
1090
+
npctl->functions = devm_kcalloc(&pdev->dev, npctl->nfunctions,
1091
+
sizeof(*npctl->functions), GFP_KERNEL);
1092
+
if (!npctl->functions)
1093
+
return -ENOMEM;
1094
+
1095
+
npctl->groups = devm_kcalloc(&pdev->dev, npctl->ngroups,
1096
+
sizeof(*npctl->groups), GFP_KERNEL);
1097
+
if (!npctl->groups)
1098
+
return -ENOMEM;
1099
+
1100
+
device_for_each_child_node(&pdev->dev, child) {
1101
+
if (fwnode_property_present(child, "gpio-controller"))
1102
+
continue;
1103
+
1104
+
ret = ma35_pinctrl_parse_functions(to_of_node(child), npctl, idx++);
1105
+
if (ret) {
1106
+
fwnode_handle_put(child);
1107
+
dev_err(&pdev->dev, "failed to parse function\n");
1108
+
return ret;
1109
+
}
1110
+
}
1111
+
return 0;
1112
+
}
1113
+
1114
+
int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info)
1115
+
{
1116
+
struct pinctrl_desc *ma35_pinctrl_desc;
1117
+
struct device *dev = &pdev->dev;
1118
+
struct ma35_pinctrl *npctl;
1119
+
int ret;
1120
+
1121
+
if (!info || !info->pins || !info->npins) {
1122
+
dev_err(&pdev->dev, "wrong pinctrl info\n");
1123
+
return -EINVAL;
1124
+
}
1125
+
1126
+
npctl = devm_kzalloc(&pdev->dev, sizeof(*npctl), GFP_KERNEL);
1127
+
if (!npctl)
1128
+
return -ENOMEM;
1129
+
1130
+
ma35_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ma35_pinctrl_desc), GFP_KERNEL);
1131
+
if (!ma35_pinctrl_desc)
1132
+
return -ENOMEM;
1133
+
1134
+
npctl->ctrl = devm_kzalloc(&pdev->dev, sizeof(*npctl->ctrl), GFP_KERNEL);
1135
+
if (!npctl->ctrl)
1136
+
return -ENOMEM;
1137
+
1138
+
ma35_pinctrl_desc->name = dev_name(&pdev->dev);
1139
+
ma35_pinctrl_desc->pins = info->pins;
1140
+
ma35_pinctrl_desc->npins = info->npins;
1141
+
ma35_pinctrl_desc->pctlops = &ma35_pctrl_ops;
1142
+
ma35_pinctrl_desc->pmxops = &ma35_pmx_ops;
1143
+
ma35_pinctrl_desc->confops = &ma35_pinconf_ops;
1144
+
ma35_pinctrl_desc->owner = THIS_MODULE;
1145
+
1146
+
npctl->info = info;
1147
+
npctl->dev = &pdev->dev;
1148
+
1149
+
npctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "nuvoton,sys");
1150
+
if (IS_ERR(npctl->regmap))
1151
+
return dev_err_probe(&pdev->dev, PTR_ERR(npctl->regmap),
1152
+
"No syscfg phandle specified\n");
1153
+
1154
+
ret = ma35_pinctrl_get_soc_data(npctl, pdev);
1155
+
if (ret)
1156
+
return dev_err_probe(&pdev->dev, ret, "fail to get soc data\n");
1157
+
1158
+
platform_set_drvdata(pdev, npctl);
1159
+
1160
+
ret = ma35_pinctrl_probe_dt(pdev, npctl);
1161
+
if (ret)
1162
+
return dev_err_probe(&pdev->dev, ret, "fail to probe MA35 pinctrl dt\n");
1163
+
1164
+
ret = devm_pinctrl_register_and_init(dev, ma35_pinctrl_desc, npctl, &npctl->pctl);
1165
+
if (ret)
1166
+
return dev_err_probe(&pdev->dev, ret, "fail to register MA35 pinctrl\n");
1167
+
1168
+
ret = pinctrl_enable(npctl->pctl);
1169
+
if (ret)
1170
+
return dev_err_probe(&pdev->dev, ret, "fail to enable MA35 pinctrl\n");
1171
+
1172
+
return ma35_gpiolib_register(pdev, npctl);
1173
+
}
1174
+
1175
+
int ma35_pinctrl_suspend(struct device *dev)
1176
+
{
1177
+
struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
1178
+
1179
+
return pinctrl_force_sleep(npctl->pctl);
1180
+
}
1181
+
1182
+
int ma35_pinctrl_resume(struct device *dev)
1183
+
{
1184
+
struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
1185
+
1186
+
return pinctrl_force_default(npctl->pctl);
1187
+
}
+52
drivers/pinctrl/nuvoton/pinctrl-ma35.h
+52
drivers/pinctrl/nuvoton/pinctrl-ma35.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2024 Nuvoton Technology Corp.
4
+
*
5
+
* Author: Shan-Chun Hung <schung@nuvoton.com>
6
+
* * Jacky Huang <ychuang3@nuvoton.com>
7
+
*/
8
+
#ifndef __PINCTRL_MA35_H
9
+
#define __PINCTRL_MA35_H
10
+
11
+
#include <linux/pinctrl/pinconf-generic.h>
12
+
#include <linux/pinctrl/pinmux.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
struct ma35_mux_desc {
16
+
const char *name;
17
+
u32 muxval;
18
+
};
19
+
20
+
struct ma35_pin_data {
21
+
u32 offset;
22
+
u32 shift;
23
+
struct ma35_mux_desc *muxes;
24
+
};
25
+
26
+
struct ma35_pinctrl_soc_info {
27
+
const struct pinctrl_pin_desc *pins;
28
+
unsigned int npins;
29
+
int (*get_pin_num)(int offset, int shift);
30
+
};
31
+
32
+
#define MA35_PIN(num, n, o, s, ...) { \
33
+
.number = num, \
34
+
.name = #n, \
35
+
.drv_data = &(struct ma35_pin_data) { \
36
+
.offset = o, \
37
+
.shift = s, \
38
+
.muxes = (struct ma35_mux_desc[]) { \
39
+
__VA_ARGS__, { } }, \
40
+
}, \
41
+
}
42
+
43
+
#define MA35_MUX(_val, _name) { \
44
+
.name = _name, \
45
+
.muxval = _val, \
46
+
}
47
+
48
+
int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info);
49
+
int ma35_pinctrl_suspend(struct device *dev);
50
+
int ma35_pinctrl_resume(struct device *dev);
51
+
52
+
#endif /* __PINCTRL_MA35_H */
+1799
drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
+1799
drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2024 Nuvoton Technology Corp.
4
+
*
5
+
* Author: Shan-Chun Hung <schung@nuvoton.com>
6
+
* * Jacky Huang <ychuang3@nuvoton.com>
7
+
*/
8
+
#include <linux/init.h>
9
+
#include <linux/io.h>
10
+
#include <linux/mod_devicetable.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/platform_device.h>
14
+
#include <linux/pm.h>
15
+
16
+
#include <linux/pinctrl/pinctrl.h>
17
+
18
+
#include "pinctrl-ma35.h"
19
+
20
+
static const struct pinctrl_pin_desc ma35d1_pins[] = {
21
+
MA35_PIN(0, PA0, 0x80, 0x0,
22
+
MA35_MUX(0x0, "GPA0"),
23
+
MA35_MUX(0x2, "UART1_nCTS"),
24
+
MA35_MUX(0x3, "UART16_RXD"),
25
+
MA35_MUX(0x6, "NAND_DATA0"),
26
+
MA35_MUX(0x7, "EBI_AD0"),
27
+
MA35_MUX(0x9, "EBI_ADR0")),
28
+
MA35_PIN(1, PA1, 0x80, 0x4,
29
+
MA35_MUX(0x0, "GPA1"),
30
+
MA35_MUX(0x2, "UART1_nRTS"),
31
+
MA35_MUX(0x3, "UART16_TXD"),
32
+
MA35_MUX(0x6, "NAND_DATA1"),
33
+
MA35_MUX(0x7, "EBI_AD1"),
34
+
MA35_MUX(0x9, "EBI_ADR1")),
35
+
MA35_PIN(2, PA2, 0x80, 0x8,
36
+
MA35_MUX(0x0, "GPA2"),
37
+
MA35_MUX(0x2, "UART1_RXD"),
38
+
MA35_MUX(0x6, "NAND_DATA2"),
39
+
MA35_MUX(0x7, "EBI_AD2"),
40
+
MA35_MUX(0x9, "EBI_ADR2")),
41
+
MA35_PIN(3, PA3, 0x80, 0xc,
42
+
MA35_MUX(0x0, "GPA3"),
43
+
MA35_MUX(0x2, "UART1_TXD"),
44
+
MA35_MUX(0x6, "NAND_DATA3"),
45
+
MA35_MUX(0x7, "EBI_AD3"),
46
+
MA35_MUX(0x9, "EBI_ADR3")),
47
+
MA35_PIN(4, PA4, 0x80, 0x10,
48
+
MA35_MUX(0x0, "GPA4"),
49
+
MA35_MUX(0x2, "UART3_nCTS"),
50
+
MA35_MUX(0x3, "UART2_RXD"),
51
+
MA35_MUX(0x6, "NAND_DATA4"),
52
+
MA35_MUX(0x7, "EBI_AD4"),
53
+
MA35_MUX(0x9, "EBI_ADR4")),
54
+
MA35_PIN(5, PA5, 0x80, 0x14,
55
+
MA35_MUX(0x0, "GPA5"),
56
+
MA35_MUX(0x2, "UART3_nRTS"),
57
+
MA35_MUX(0x3, "UART2_TXD"),
58
+
MA35_MUX(0x6, "NAND_DATA5"),
59
+
MA35_MUX(0x7, "EBI_AD5"),
60
+
MA35_MUX(0x9, "EBI_ADR5")),
61
+
MA35_PIN(6, PA6, 0x80, 0x18,
62
+
MA35_MUX(0x0, "GPA6"),
63
+
MA35_MUX(0x2, "UART3_RXD"),
64
+
MA35_MUX(0x6, "NAND_DATA6"),
65
+
MA35_MUX(0x7, "EBI_AD6"),
66
+
MA35_MUX(0x9, "EBI_ADR6")),
67
+
MA35_PIN(7, PA7, 0x80, 0x1c,
68
+
MA35_MUX(0x0, "GPA7"),
69
+
MA35_MUX(0x2, "UART3_TXD"),
70
+
MA35_MUX(0x6, "NAND_DATA7"),
71
+
MA35_MUX(0x7, "EBI_AD7"),
72
+
MA35_MUX(0x9, "EBI_ADR7")),
73
+
MA35_PIN(8, PA8, 0x84, 0x0,
74
+
MA35_MUX(0x0, "GPA8"),
75
+
MA35_MUX(0x2, "UART5_nCTS"),
76
+
MA35_MUX(0x3, "UART4_RXD"),
77
+
MA35_MUX(0x6, "NAND_RDY0"),
78
+
MA35_MUX(0x7, "EBI_AD8"),
79
+
MA35_MUX(0x9, "EBI_ADR8")),
80
+
MA35_PIN(9, PA9, 0x84, 0x4,
81
+
MA35_MUX(0x0, "GPA9"),
82
+
MA35_MUX(0x2, "UART5_nRTS"),
83
+
MA35_MUX(0x3, "UART4_TXD"),
84
+
MA35_MUX(0x6, "NAND_nRE"),
85
+
MA35_MUX(0x7, "EBI_AD9"),
86
+
MA35_MUX(0x9, "EBI_ADR9")),
87
+
MA35_PIN(10, PA10, 0x84, 0x8,
88
+
MA35_MUX(0x0, "GPA10"),
89
+
MA35_MUX(0x2, "UART5_RXD"),
90
+
MA35_MUX(0x6, "NAND_nWE"),
91
+
MA35_MUX(0x7, "EBI_AD10"),
92
+
MA35_MUX(0x9, "EBI_ADR10")),
93
+
MA35_PIN(11, PA11, 0x84, 0xc,
94
+
MA35_MUX(0x0, "GPA11"),
95
+
MA35_MUX(0x2, "UART5_TXD"),
96
+
MA35_MUX(0x6, "NAND_CLE"),
97
+
MA35_MUX(0x7, "EBI_AD11"),
98
+
MA35_MUX(0x9, "EBI_ADR11")),
99
+
MA35_PIN(12, PA12, 0x84, 0x10,
100
+
MA35_MUX(0x0, "GPA12"),
101
+
MA35_MUX(0x2, "UART7_nCTS"),
102
+
MA35_MUX(0x3, "UART8_RXD"),
103
+
MA35_MUX(0x6, "NAND_ALE"),
104
+
MA35_MUX(0x7, "EBI_AD12"),
105
+
MA35_MUX(0x9, "EBI_ADR12")),
106
+
MA35_PIN(13, PA13, 0x84, 0x14,
107
+
MA35_MUX(0x0, "GPA13"),
108
+
MA35_MUX(0x2, "UART7_nRTS"),
109
+
MA35_MUX(0x3, "UART8_TXD"),
110
+
MA35_MUX(0x6, "NAND_nCS0"),
111
+
MA35_MUX(0x7, "EBI_AD13"),
112
+
MA35_MUX(0x9, "EBI_ADR13")),
113
+
MA35_PIN(14, PA14, 0x84, 0x18,
114
+
MA35_MUX(0x0, "GPA14"),
115
+
MA35_MUX(0x2, "UART7_RXD"),
116
+
MA35_MUX(0x3, "CAN3_RXD"),
117
+
MA35_MUX(0x6, "NAND_nWP"),
118
+
MA35_MUX(0x7, "EBI_AD14"),
119
+
MA35_MUX(0x9, "EBI_ADR14")),
120
+
MA35_PIN(15, PA15, 0x84, 0x1c,
121
+
MA35_MUX(0x0, "GPA15"),
122
+
MA35_MUX(0x1, "EPWM0_CH2"),
123
+
MA35_MUX(0x2, "UART9_nCTS"),
124
+
MA35_MUX(0x3, "UART6_RXD"),
125
+
MA35_MUX(0x4, "I2C4_SDA"),
126
+
MA35_MUX(0x5, "CAN2_RXD"),
127
+
MA35_MUX(0x7, "EBI_ALE"),
128
+
MA35_MUX(0x9, "QEI0_A"),
129
+
MA35_MUX(0xb, "TM1"),
130
+
MA35_MUX(0xe, "RGMII0_PPS"),
131
+
MA35_MUX(0xf, "RMII0_PPS")),
132
+
MA35_PIN(16, PB0, 0x88, 0x0,
133
+
MA35_MUX(0x0, "GPB0"),
134
+
MA35_MUX(0x8, "EADC0_CH0")),
135
+
MA35_PIN(17, PB1, 0x88, 0x4,
136
+
MA35_MUX(0x0, "GPB1"),
137
+
MA35_MUX(0x8, "EADC0_CH1")),
138
+
MA35_PIN(18, PB2, 0x88, 0x8,
139
+
MA35_MUX(0x0, "GPB2"),
140
+
MA35_MUX(0x8, "EADC0_CH2")),
141
+
MA35_PIN(19, PB3, 0x88, 0xc,
142
+
MA35_MUX(0x0, "GPB3"),
143
+
MA35_MUX(0x8, "EADC0_CH3")),
144
+
MA35_PIN(20, PB4, 0x88, 0x10,
145
+
MA35_MUX(0x0, "GPB4"),
146
+
MA35_MUX(0x8, "EADC0_CH4")),
147
+
MA35_PIN(21, PB5, 0x88, 0x14,
148
+
MA35_MUX(0x0, "GPB5"),
149
+
MA35_MUX(0x8, "EADC0_CH5")),
150
+
MA35_PIN(22, PB6, 0x88, 0x18,
151
+
MA35_MUX(0x0, "GPB6"),
152
+
MA35_MUX(0x8, "EADC0_CH6")),
153
+
MA35_PIN(23, PB7, 0x88, 0x1c,
154
+
MA35_MUX(0x0, "GPB7"),
155
+
MA35_MUX(0x8, "EADC0_CH7")),
156
+
MA35_PIN(24, PB8, 0x8c, 0x0,
157
+
MA35_MUX(0x0, "GPB8"),
158
+
MA35_MUX(0x1, "EPWM2_BRAKE0"),
159
+
MA35_MUX(0x2, "UART2_nCTS"),
160
+
MA35_MUX(0x3, "UART1_RXD"),
161
+
MA35_MUX(0x4, "I2C2_SDA"),
162
+
MA35_MUX(0x5, "SPI0_SS1"),
163
+
MA35_MUX(0x6, "SPI0_I2SMCLK"),
164
+
MA35_MUX(0x8, "ADC0_CH0"),
165
+
MA35_MUX(0x9, "EBI_nCS0"),
166
+
MA35_MUX(0xb, "TM4"),
167
+
MA35_MUX(0xe, "QEI2_INDEX"),
168
+
MA35_MUX(0xf, "KPI_ROW6")),
169
+
MA35_PIN(25, PB9, 0x8c, 0x4,
170
+
MA35_MUX(0x0, "GPB9"),
171
+
MA35_MUX(0x1, "EPWM2_CH4"),
172
+
MA35_MUX(0x2, "UART2_nRTS"),
173
+
MA35_MUX(0x3, "UART1_TXD"),
174
+
MA35_MUX(0x4, "I2C2_SCL"),
175
+
MA35_MUX(0x5, "SPI0_CLK"),
176
+
MA35_MUX(0x6, "I2S0_MCLK"),
177
+
MA35_MUX(0x7, "CCAP1_HSYNC"),
178
+
MA35_MUX(0x8, "ADC0_CH1"),
179
+
MA35_MUX(0x9, "EBI_ALE"),
180
+
MA35_MUX(0xa, "EBI_AD13"),
181
+
MA35_MUX(0xb, "TM0_EXT"),
182
+
MA35_MUX(0xc, "I2S1_MCLK"),
183
+
MA35_MUX(0xd, "SC0_nCD"),
184
+
MA35_MUX(0xe, "QEI2_A"),
185
+
MA35_MUX(0xf, "KPI_ROW7")),
186
+
MA35_PIN(26, PB10, 0x8c, 0x8,
187
+
MA35_MUX(0x0, "GPB10"),
188
+
MA35_MUX(0x1, "EPWM2_CH5"),
189
+
MA35_MUX(0x2, "UART2_RXD"),
190
+
MA35_MUX(0x3, "CAN0_RXD"),
191
+
MA35_MUX(0x5, "SPI0_MOSI"),
192
+
MA35_MUX(0x6, "EBI_MCLK"),
193
+
MA35_MUX(0x7, "CCAP1_VSYNC"),
194
+
MA35_MUX(0x8, "ADC0_CH2"),
195
+
MA35_MUX(0x9, "EBI_ADR15"),
196
+
MA35_MUX(0xa, "EBI_AD14"),
197
+
MA35_MUX(0xb, "TM5"),
198
+
MA35_MUX(0xc, "I2C1_SDA"),
199
+
MA35_MUX(0xd, "INT1"),
200
+
MA35_MUX(0xe, "QEI2_B")),
201
+
MA35_PIN(27, PB11, 0x8c, 0xc,
202
+
MA35_MUX(0x0, "GPB11"),
203
+
MA35_MUX(0x1, "EPWM2_BRAKE1"),
204
+
MA35_MUX(0x2, "UART2_TXD"),
205
+
MA35_MUX(0x3, "CAN0_TXD"),
206
+
MA35_MUX(0x5, "SPI0_MISO"),
207
+
MA35_MUX(0x6, "I2S1_MCLK"),
208
+
MA35_MUX(0x7, "CCAP1_SFIELD"),
209
+
MA35_MUX(0x8, "ADC0_CH3"),
210
+
MA35_MUX(0x9, "EBI_nCS2"),
211
+
MA35_MUX(0xa, "EBI_ALE"),
212
+
MA35_MUX(0xb, "TM5_EXT"),
213
+
MA35_MUX(0xc, "I2C1_SCL"),
214
+
MA35_MUX(0xd, "INT2"),
215
+
MA35_MUX(0xe, "QEI2_INDEX")),
216
+
MA35_PIN(28, PB12, 0x8c, 0x10,
217
+
MA35_MUX(0x0, "GPB12"),
218
+
MA35_MUX(0x1, "EPWM2_CH0"),
219
+
MA35_MUX(0x2, "UART4_nCTS"),
220
+
MA35_MUX(0x3, "UART3_RXD"),
221
+
MA35_MUX(0x4, "I2C3_SDA"),
222
+
MA35_MUX(0x5, "CAN2_RXD"),
223
+
MA35_MUX(0x6, "I2S1_LRCK"),
224
+
MA35_MUX(0x8, "ADC0_CH4"),
225
+
MA35_MUX(0x9, "EBI_ADR16"),
226
+
MA35_MUX(0xe, "ECAP2_IC0")),
227
+
MA35_PIN(29, PB13, 0x8c, 0x14,
228
+
MA35_MUX(0x0, "GPB13"),
229
+
MA35_MUX(0x1, "EPWM2_CH1"),
230
+
MA35_MUX(0x2, "UART4_nRTS"),
231
+
MA35_MUX(0x3, "UART3_TXD"),
232
+
MA35_MUX(0x4, "I2C3_SCL"),
233
+
MA35_MUX(0x5, "CAN2_TXD"),
234
+
MA35_MUX(0x6, "I2S1_BCLK"),
235
+
MA35_MUX(0x8, "ADC0_CH5"),
236
+
MA35_MUX(0x9, "EBI_ADR17"),
237
+
MA35_MUX(0xe, "ECAP2_IC1")),
238
+
MA35_PIN(30, PB14, 0x8c, 0x18,
239
+
MA35_MUX(0x0, "GPB14"),
240
+
MA35_MUX(0x1, "EPWM2_CH2"),
241
+
MA35_MUX(0x2, "UART4_RXD"),
242
+
MA35_MUX(0x3, "CAN1_RXD"),
243
+
MA35_MUX(0x5, "I2C4_SDA"),
244
+
MA35_MUX(0x6, "I2S1_DI"),
245
+
MA35_MUX(0x8, "ADC0_CH6"),
246
+
MA35_MUX(0x9, "EBI_ADR18"),
247
+
MA35_MUX(0xe, "ECAP2_IC2")),
248
+
MA35_PIN(31, PB15, 0x8c, 0x1c,
249
+
MA35_MUX(0x0, "GPB15"),
250
+
MA35_MUX(0x1, "EPWM2_CH3"),
251
+
MA35_MUX(0x2, "UART4_TXD"),
252
+
MA35_MUX(0x3, "CAN1_TXD"),
253
+
MA35_MUX(0x5, "I2C4_SCL"),
254
+
MA35_MUX(0x6, "I2S1_DO"),
255
+
MA35_MUX(0x8, "ADC0_CH7"),
256
+
MA35_MUX(0x9, "EBI_ADR19")),
257
+
MA35_PIN(32, PC0, 0x90, 0x0,
258
+
MA35_MUX(0x0, "GPC0"),
259
+
MA35_MUX(0x4, "I2C4_SDA"),
260
+
MA35_MUX(0x6, "SD0_CMD/eMMC0_CMD")),
261
+
MA35_PIN(33, PC1, 0x90, 0x4,
262
+
MA35_MUX(0x0, "GPC1"),
263
+
MA35_MUX(0x4, "I2C4_SCL"),
264
+
MA35_MUX(0x6, "SD0_CLK/eMMC0_CLK")),
265
+
MA35_PIN(34, PC2, 0x90, 0x8,
266
+
MA35_MUX(0x0, "GPC2"),
267
+
MA35_MUX(0x3, "CAN0_RXD"),
268
+
MA35_MUX(0x6, "SD0_DAT0/eMMC0_DAT0")),
269
+
MA35_PIN(35, PC3, 0x90, 0xc,
270
+
MA35_MUX(0x0, "GPC3"),
271
+
MA35_MUX(0x3, "CAN0_TXD"),
272
+
MA35_MUX(0x6, "SD0_DAT1/eMMC0_DAT1")),
273
+
MA35_PIN(36, PC4, 0x90, 0x10,
274
+
MA35_MUX(0x0, "GPC4"),
275
+
MA35_MUX(0x4, "I2C5_SDA"),
276
+
MA35_MUX(0x6, "SD0_DAT2/eMMC0_DAT2")),
277
+
MA35_PIN(37, PC5, 0x90, 0x14,
278
+
MA35_MUX(0x0, "GPC5"),
279
+
MA35_MUX(0x4, "I2C5_SCL"),
280
+
MA35_MUX(0x6, "SD0_DAT3/eMMC0_DAT3")),
281
+
MA35_PIN(38, PC6, 0x90, 0x18,
282
+
MA35_MUX(0x0, "GPC6"),
283
+
MA35_MUX(0x3, "CAN1_RXD"),
284
+
MA35_MUX(0x6, "SD0_nCD")),
285
+
MA35_PIN(39, PC7, 0x90, 0x1c,
286
+
MA35_MUX(0x0, "GPC7"),
287
+
MA35_MUX(0x3, "CAN1_TXD"),
288
+
MA35_MUX(0x6, "SD0_WP")),
289
+
MA35_PIN(40, PC12, 0x94, 0x10,
290
+
MA35_MUX(0x0, "GPC12"),
291
+
MA35_MUX(0x2, "UART12_nCTS"),
292
+
MA35_MUX(0x3, "UART11_RXD"),
293
+
MA35_MUX(0x6, "LCM_DATA16")),
294
+
MA35_PIN(41, PC13, 0x94, 0x14,
295
+
MA35_MUX(0x0, "GPC13"),
296
+
MA35_MUX(0x2, "UART12_nRTS"),
297
+
MA35_MUX(0x3, "UART11_TXD"),
298
+
MA35_MUX(0x6, "LCM_DATA17")),
299
+
MA35_PIN(42, PC14, 0x94, 0x18,
300
+
MA35_MUX(0x0, "GPC14"),
301
+
MA35_MUX(0x2, "UART12_RXD"),
302
+
MA35_MUX(0x6, "LCM_DATA18")),
303
+
MA35_PIN(43, PC15, 0x94, 0x1c,
304
+
MA35_MUX(0x0, "GPC15"),
305
+
MA35_MUX(0x2, "UART12_TXD"),
306
+
MA35_MUX(0x6, "LCM_DATA19"),
307
+
MA35_MUX(0x7, "LCM_MPU_TE"),
308
+
MA35_MUX(0x8, "LCM_MPU_VSYNC")),
309
+
MA35_PIN(44, PD0, 0x98, 0x0,
310
+
MA35_MUX(0x0, "GPD0"),
311
+
MA35_MUX(0x2, "UART3_nCTS"),
312
+
MA35_MUX(0x3, "UART4_RXD"),
313
+
MA35_MUX(0x5, "QSPI0_SS0")),
314
+
MA35_PIN(45, PD1, 0x98, 0x4,
315
+
MA35_MUX(0x0, "GPD1"),
316
+
MA35_MUX(0x2, "UART3_nRTS"),
317
+
MA35_MUX(0x3, "UART4_TXD"),
318
+
MA35_MUX(0x5, "QSPI0_CLK")),
319
+
MA35_PIN(46, PD2, 0x98, 0x8,
320
+
MA35_MUX(0x0, "GPD2"),
321
+
MA35_MUX(0x2, "UART3_RXD"),
322
+
MA35_MUX(0x5, "QSPI0_MOSI0")),
323
+
MA35_PIN(47, PD3, 0x98, 0xc,
324
+
MA35_MUX(0x0, "GPD3"),
325
+
MA35_MUX(0x2, "UART3_TXD"),
326
+
MA35_MUX(0x5, "QSPI0_MISO0")),
327
+
MA35_PIN(48, PD4, 0x98, 0x10,
328
+
MA35_MUX(0x0, "GPD4"),
329
+
MA35_MUX(0x2, "UART1_nCTS"),
330
+
MA35_MUX(0x3, "UART2_RXD"),
331
+
MA35_MUX(0x4, "I2C2_SDA"),
332
+
MA35_MUX(0x5, "QSPI0_MOSI1")),
333
+
MA35_PIN(49, PD5, 0x98, 0x14,
334
+
MA35_MUX(0x0, "GPD5"),
335
+
MA35_MUX(0x2, "UART1_nRTS"),
336
+
MA35_MUX(0x3, "UART2_TXD"),
337
+
MA35_MUX(0x4, "I2C2_SCL"),
338
+
MA35_MUX(0x5, "QSPI0_MISO1")),
339
+
MA35_PIN(50, PD6, 0x98, 0x18,
340
+
MA35_MUX(0x0, "GPD6"),
341
+
MA35_MUX(0x1, "EPWM0_SYNC_IN"),
342
+
MA35_MUX(0x2, "UART1_RXD"),
343
+
MA35_MUX(0x5, "QSPI1_MOSI1"),
344
+
MA35_MUX(0x6, "I2C0_SDA"),
345
+
MA35_MUX(0x7, "I2S0_MCLK"),
346
+
MA35_MUX(0x8, "EPWM0_CH0"),
347
+
MA35_MUX(0x9, "EBI_AD5"),
348
+
MA35_MUX(0xa, "SPI3_SS1"),
349
+
MA35_MUX(0xb, "TRACE_CLK")),
350
+
MA35_PIN(51, PD7, 0x98, 0x1c,
351
+
MA35_MUX(0x0, "GPD7"),
352
+
MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
353
+
MA35_MUX(0x2, "UART1_TXD"),
354
+
MA35_MUX(0x5, "QSPI1_MISO1"),
355
+
MA35_MUX(0x6, "I2C0_SCL"),
356
+
MA35_MUX(0x7, "I2S1_MCLK"),
357
+
MA35_MUX(0x8, "EPWM0_CH1"),
358
+
MA35_MUX(0x9, "EBI_AD6"),
359
+
MA35_MUX(0xa, "SC1_nCD"),
360
+
MA35_MUX(0xb, "EADC0_ST")),
361
+
MA35_PIN(52, PD8, 0x9c, 0x0,
362
+
MA35_MUX(0x0, "GPD8"),
363
+
MA35_MUX(0x1, "EPWM0_BRAKE0"),
364
+
MA35_MUX(0x2, "UART16_nCTS"),
365
+
MA35_MUX(0x3, "UART15_RXD"),
366
+
MA35_MUX(0x5, "QSPI1_SS0"),
367
+
MA35_MUX(0x7, "I2S1_LRCK"),
368
+
MA35_MUX(0x8, "EPWM0_CH2"),
369
+
MA35_MUX(0x9, "EBI_AD7"),
370
+
MA35_MUX(0xa, "SC1_CLK"),
371
+
MA35_MUX(0xb, "TM0")),
372
+
MA35_PIN(53, PD9, 0x9c, 0x4,
373
+
MA35_MUX(0x0, "GPD9"),
374
+
MA35_MUX(0x1, "EPWM0_BRAKE1"),
375
+
MA35_MUX(0x2, "UART16_nRTS"),
376
+
MA35_MUX(0x3, "UART15_TXD"),
377
+
MA35_MUX(0x5, "QSPI1_CLK"),
378
+
MA35_MUX(0x7, "I2S1_BCLK"),
379
+
MA35_MUX(0x8, "EPWM0_CH3"),
380
+
MA35_MUX(0x9, "EBI_AD8"),
381
+
MA35_MUX(0xa, "SC1_DAT"),
382
+
MA35_MUX(0xb, "TM0_EXT")),
383
+
MA35_PIN(54, PD10, 0x9c, 0x8,
384
+
MA35_MUX(0x0, "GPD10"),
385
+
MA35_MUX(0x1, "EPWM1_BRAKE0"),
386
+
MA35_MUX(0x2, "UART16_RXD"),
387
+
MA35_MUX(0x5, "QSPI1_MOSI0"),
388
+
MA35_MUX(0x7, "I2S1_DI"),
389
+
MA35_MUX(0x8, "EPWM0_CH4"),
390
+
MA35_MUX(0x9, "EBI_AD9"),
391
+
MA35_MUX(0xa, "SC1_RST"),
392
+
MA35_MUX(0xb, "TM2")),
393
+
MA35_PIN(55, PD11, 0x9c, 0xc,
394
+
MA35_MUX(0x0, "GPD11"),
395
+
MA35_MUX(0x1, "EPWM1_BRAKE1"),
396
+
MA35_MUX(0x2, "UART16_TXD"),
397
+
MA35_MUX(0x5, "QSPI1_MISO0"),
398
+
MA35_MUX(0x7, "I2S1_DO"),
399
+
MA35_MUX(0x8, "EPWM0_CH5"),
400
+
MA35_MUX(0x9, "EBI_AD10"),
401
+
MA35_MUX(0xa, "SC1_PWR"),
402
+
MA35_MUX(0xb, "TM2_EXT")),
403
+
MA35_PIN(56, PD12, 0x9c, 0x10,
404
+
MA35_MUX(0x0, "GPD12"),
405
+
MA35_MUX(0x1, "EPWM0_BRAKE0"),
406
+
MA35_MUX(0x2, "UART11_TXD"),
407
+
MA35_MUX(0x3, "UART10_RXD"),
408
+
MA35_MUX(0x4, "I2C4_SDA"),
409
+
MA35_MUX(0x6, "TRACE_DATA0"),
410
+
MA35_MUX(0x7, "EBI_nCS1"),
411
+
MA35_MUX(0x8, "EBI_AD4"),
412
+
MA35_MUX(0x9, "QEI0_INDEX"),
413
+
MA35_MUX(0xb, "TM5"),
414
+
MA35_MUX(0xc, "I2S1_LRCK"),
415
+
MA35_MUX(0xd, "INT1")),
416
+
MA35_PIN(57, PD13, 0x9c, 0x14,
417
+
MA35_MUX(0x0, "GPD13"),
418
+
MA35_MUX(0x1, "EPWM0_BRAKE1"),
419
+
MA35_MUX(0x2, "UART11_RXD"),
420
+
MA35_MUX(0x3, "UART10_TXD"),
421
+
MA35_MUX(0x4, "I2C4_SCL"),
422
+
MA35_MUX(0x6, "TRACE_DATA1"),
423
+
MA35_MUX(0x7, "EBI_nCS2"),
424
+
MA35_MUX(0x8, "EBI_AD5"),
425
+
MA35_MUX(0x9, "ECAP0_IC0"),
426
+
MA35_MUX(0xb, "TM5_EXT"),
427
+
MA35_MUX(0xc, "I2S1_BCLK")),
428
+
MA35_PIN(58, PD14, 0x9c, 0x18,
429
+
MA35_MUX(0x0, "GPD14"),
430
+
MA35_MUX(0x1, "EPWM0_SYNC_IN"),
431
+
MA35_MUX(0x2, "UART11_nCTS"),
432
+
MA35_MUX(0x3, "CAN3_RXD"),
433
+
MA35_MUX(0x6, "TRACE_DATA2"),
434
+
MA35_MUX(0x7, "EBI_MCLK"),
435
+
MA35_MUX(0x8, "EBI_AD6"),
436
+
MA35_MUX(0x9, "ECAP0_IC1"),
437
+
MA35_MUX(0xb, "TM6"),
438
+
MA35_MUX(0xc, "I2S1_DI"),
439
+
MA35_MUX(0xd, "INT3")),
440
+
MA35_PIN(59, PD15, 0x9c, 0x1c,
441
+
MA35_MUX(0x0, "GPD15"),
442
+
MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
443
+
MA35_MUX(0x2, "UART11_nRTS"),
444
+
MA35_MUX(0x3, "CAN3_TXD"),
445
+
MA35_MUX(0x6, "TRACE_DATA3"),
446
+
MA35_MUX(0x7, "EBI_ALE"),
447
+
MA35_MUX(0x8, "EBI_AD7"),
448
+
MA35_MUX(0x9, "ECAP0_IC2"),
449
+
MA35_MUX(0xb, "TM6_EXT"),
450
+
MA35_MUX(0xc, "I2S1_DO")),
451
+
MA35_PIN(60, PE0, 0xa0, 0x0,
452
+
MA35_MUX(0x0, "GPE0"),
453
+
MA35_MUX(0x2, "UART9_nCTS"),
454
+
MA35_MUX(0x3, "UART8_RXD"),
455
+
MA35_MUX(0x7, "CCAP1_DATA0"),
456
+
MA35_MUX(0x8, "RGMII0_MDC"),
457
+
MA35_MUX(0x9, "RMII0_MDC")),
458
+
MA35_PIN(61, PE1, 0xa0, 0x4,
459
+
MA35_MUX(0x0, "GPE1"),
460
+
MA35_MUX(0x2, "UART9_nRTS"),
461
+
MA35_MUX(0x3, "UART8_TXD"),
462
+
MA35_MUX(0x7, "CCAP1_DATA1"),
463
+
MA35_MUX(0x8, "RGMII0_MDIO"),
464
+
MA35_MUX(0x9, "RMII0_MDIO")),
465
+
MA35_PIN(62, PE2, 0xa0, 0x8,
466
+
MA35_MUX(0x0, "GPE2"),
467
+
MA35_MUX(0x2, "UART9_RXD"),
468
+
MA35_MUX(0x7, "CCAP1_DATA2"),
469
+
MA35_MUX(0x8, "RGMII0_TXCTL"),
470
+
MA35_MUX(0x9, "RMII0_TXEN")),
471
+
MA35_PIN(63, PE3, 0xa0, 0xc,
472
+
MA35_MUX(0x0, "GPE3"),
473
+
MA35_MUX(0x2, "UART9_TXD"),
474
+
MA35_MUX(0x7, "CCAP1_DATA3"),
475
+
MA35_MUX(0x8, "RGMII0_TXD0"),
476
+
MA35_MUX(0x9, "RMII0_TXD0")),
477
+
MA35_PIN(64, PE4, 0xa0, 0x10,
478
+
MA35_MUX(0x0, "GPE4"),
479
+
MA35_MUX(0x2, "UART4_nCTS"),
480
+
MA35_MUX(0x3, "UART3_RXD"),
481
+
MA35_MUX(0x7, "CCAP1_DATA4"),
482
+
MA35_MUX(0x8, "RGMII0_TXD1"),
483
+
MA35_MUX(0x9, "RMII0_TXD1")),
484
+
MA35_PIN(65, PE5, 0xa0, 0x14,
485
+
MA35_MUX(0x0, "GPE5"),
486
+
MA35_MUX(0x2, "UART4_nRTS"),
487
+
MA35_MUX(0x3, "UART3_TXD"),
488
+
MA35_MUX(0x7, "CCAP1_DATA5"),
489
+
MA35_MUX(0x8, "RGMII0_RXCLK"),
490
+
MA35_MUX(0x9, "RMII0_REFCLK")),
491
+
MA35_PIN(66, PE6, 0xa0, 0x18,
492
+
MA35_MUX(0x0, "GPE6"),
493
+
MA35_MUX(0x2, "UART4_RXD"),
494
+
MA35_MUX(0x7, "CCAP1_DATA6"),
495
+
MA35_MUX(0x8, "RGMII0_RXCTL"),
496
+
MA35_MUX(0x9, "RMII0_CRSDV")),
497
+
MA35_PIN(67, PE7, 0xa0, 0x1c,
498
+
MA35_MUX(0x0, "GPE7"),
499
+
MA35_MUX(0x2, "UART4_TXD"),
500
+
MA35_MUX(0x7, "CCAP1_DATA7"),
501
+
MA35_MUX(0x8, "RGMII0_RXD0"),
502
+
MA35_MUX(0x9, "RMII0_RXD0")),
503
+
MA35_PIN(68, PE8, 0xa4, 0x0,
504
+
MA35_MUX(0x0, "GPE8"),
505
+
MA35_MUX(0x2, "UART13_nCTS"),
506
+
MA35_MUX(0x3, "UART12_RXD"),
507
+
MA35_MUX(0x7, "CCAP1_SCLK"),
508
+
MA35_MUX(0x8, "RGMII0_RXD1"),
509
+
MA35_MUX(0x9, "RMII0_RXD1")),
510
+
MA35_PIN(69, PE9, 0xa4, 0x4,
511
+
MA35_MUX(0x0, "GPE9"),
512
+
MA35_MUX(0x2, "UART13_nRTS"),
513
+
MA35_MUX(0x3, "UART12_TXD"),
514
+
MA35_MUX(0x7, "CCAP1_PIXCLK"),
515
+
MA35_MUX(0x8, "RGMII0_RXD2"),
516
+
MA35_MUX(0x9, "RMII0_RXERR")),
517
+
MA35_PIN(70, PE10, 0xa4, 0x8,
518
+
MA35_MUX(0x0, "GPE10"),
519
+
MA35_MUX(0x2, "UART15_nCTS"),
520
+
MA35_MUX(0x3, "UART14_RXD"),
521
+
MA35_MUX(0x5, "SPI1_SS0"),
522
+
MA35_MUX(0x7, "CCAP1_HSYNC"),
523
+
MA35_MUX(0x8, "RGMII0_RXD3")),
524
+
MA35_PIN(71, PE11, 0xa4, 0xc,
525
+
MA35_MUX(0x0, "GPE11"),
526
+
MA35_MUX(0x2, "UART15_nRTS"),
527
+
MA35_MUX(0x3, "UART14_TXD"),
528
+
MA35_MUX(0x5, "SPI1_CLK"),
529
+
MA35_MUX(0x7, "CCAP1_VSYNC"),
530
+
MA35_MUX(0x8, "RGMII0_TXCLK")),
531
+
MA35_PIN(72, PE12, 0xa4, 0x10,
532
+
MA35_MUX(0x0, "GPE12"),
533
+
MA35_MUX(0x2, "UART15_RXD"),
534
+
MA35_MUX(0x5, "SPI1_MOSI"),
535
+
MA35_MUX(0x7, "CCAP1_DATA8"),
536
+
MA35_MUX(0x8, "RGMII0_TXD2")),
537
+
MA35_PIN(73, PE13, 0xa4, 0x14,
538
+
MA35_MUX(0x0, "GPE13"),
539
+
MA35_MUX(0x2, "UART15_TXD"),
540
+
MA35_MUX(0x5, "SPI1_MISO"),
541
+
MA35_MUX(0x7, "CCAP1_DATA9"),
542
+
MA35_MUX(0x8, "RGMII0_TXD3")),
543
+
MA35_PIN(74, PE14, 0xa4, 0x18,
544
+
MA35_MUX(0x0, "GPE14"),
545
+
MA35_MUX(0x1, "UART0_TXD")),
546
+
MA35_PIN(75, PE15, 0xa4, 0x1c,
547
+
MA35_MUX(0x0, "GPE15"),
548
+
MA35_MUX(0x1, "UART0_RXD")),
549
+
MA35_PIN(76, PF0, 0xa8, 0x0,
550
+
MA35_MUX(0x0, "GPF0"),
551
+
MA35_MUX(0x2, "UART2_nCTS"),
552
+
MA35_MUX(0x3, "UART1_RXD"),
553
+
MA35_MUX(0x6, "RGMII0_RXD3"),
554
+
MA35_MUX(0x8, "RGMII1_MDC"),
555
+
MA35_MUX(0x9, "RMII1_MDC"),
556
+
MA35_MUX(0xe, "KPI_COL0")),
557
+
MA35_PIN(77, PF1, 0xa8, 0x4,
558
+
MA35_MUX(0x0, "GPF1"),
559
+
MA35_MUX(0x2, "UART2_nRTS"),
560
+
MA35_MUX(0x3, "UART1_TXD"),
561
+
MA35_MUX(0x6, "RGMII0_TXCLK"),
562
+
MA35_MUX(0x8, "RGMII1_MDIO"),
563
+
MA35_MUX(0x9, "RMII1_MDIO"),
564
+
MA35_MUX(0xe, "KPI_COL1")),
565
+
MA35_PIN(78, PF2, 0xa8, 0x8,
566
+
MA35_MUX(0x0, "GPF2"),
567
+
MA35_MUX(0x2, "UART2_RXD"),
568
+
MA35_MUX(0x6, "RGMII0_TXD2"),
569
+
MA35_MUX(0x8, "RGMII1_TXCTL"),
570
+
MA35_MUX(0x9, "RMII1_TXEN"),
571
+
MA35_MUX(0xe, "KPI_COL2")),
572
+
MA35_PIN(79, PF3, 0xa8, 0xc,
573
+
MA35_MUX(0x0, "GPF3"),
574
+
MA35_MUX(0x2, "UART2_TXD"),
575
+
MA35_MUX(0x6, "RGMII0_TXD3"),
576
+
MA35_MUX(0x8, "RGMII1_TXD0"),
577
+
MA35_MUX(0x9, "RMII1_TXD0"),
578
+
MA35_MUX(0xe, "KPI_COL3")),
579
+
MA35_PIN(80, PF4, 0xa8, 0x10,
580
+
MA35_MUX(0x0, "GPF4"),
581
+
MA35_MUX(0x2, "UART11_nCTS"),
582
+
MA35_MUX(0x3, "UART10_RXD"),
583
+
MA35_MUX(0x4, "I2S0_LRCK"),
584
+
MA35_MUX(0x5, "SPI1_SS0"),
585
+
MA35_MUX(0x8, "RGMII1_TXD1"),
586
+
MA35_MUX(0x9, "RMII1_TXD1"),
587
+
MA35_MUX(0xd, "CAN2_RXD"),
588
+
MA35_MUX(0xe, "KPI_ROW0")),
589
+
MA35_PIN(81, PF5, 0xa8, 0x14,
590
+
MA35_MUX(0x0, "GPF5"),
591
+
MA35_MUX(0x2, "UART11_nRTS"),
592
+
MA35_MUX(0x3, "UART10_TXD"),
593
+
MA35_MUX(0x4, "I2S0_BCLK"),
594
+
MA35_MUX(0x5, "SPI1_CLK"),
595
+
MA35_MUX(0x8, "RGMII1_RXCLK"),
596
+
MA35_MUX(0x9, "RMII1_REFCLK"),
597
+
MA35_MUX(0xd, "CAN2_TXD"),
598
+
MA35_MUX(0xe, "KPI_ROW1")),
599
+
MA35_PIN(82, PF6, 0xa8, 0x18,
600
+
MA35_MUX(0x0, "GPF6"),
601
+
MA35_MUX(0x2, "UART11_RXD"),
602
+
MA35_MUX(0x4, "I2S0_DI"),
603
+
MA35_MUX(0x5, "SPI1_MOSI"),
604
+
MA35_MUX(0x8, "RGMII1_RXCTL"),
605
+
MA35_MUX(0x9, "RMII1_CRSDV"),
606
+
MA35_MUX(0xa, "I2C4_SDA"),
607
+
MA35_MUX(0xd, "SC0_CLK"),
608
+
MA35_MUX(0xe, "KPI_ROW2")),
609
+
MA35_PIN(83, PF7, 0xa8, 0x1c,
610
+
MA35_MUX(0x0, "GPF7"),
611
+
MA35_MUX(0x2, "UART11_TXD"),
612
+
MA35_MUX(0x4, "I2S0_DO"),
613
+
MA35_MUX(0x5, "SPI1_MISO"),
614
+
MA35_MUX(0x8, "RGMII1_RXD0"),
615
+
MA35_MUX(0x9, "RMII1_RXD0"),
616
+
MA35_MUX(0xa, "I2C4_SCL"),
617
+
MA35_MUX(0xd, "SC0_DAT"),
618
+
MA35_MUX(0xe, "KPI_ROW3")),
619
+
MA35_PIN(84, PF8, 0xac, 0x0,
620
+
MA35_MUX(0x0, "GPF8"),
621
+
MA35_MUX(0x2, "UART13_RXD"),
622
+
MA35_MUX(0x4, "I2C5_SDA"),
623
+
MA35_MUX(0x5, "SPI0_SS0"),
624
+
MA35_MUX(0x8, "RGMII1_RXD1"),
625
+
MA35_MUX(0x9, "RMII1_RXD1"),
626
+
MA35_MUX(0xd, "SC0_RST"),
627
+
MA35_MUX(0xe, "KPI_COL4")),
628
+
MA35_PIN(85, PF9, 0xac, 0x4,
629
+
MA35_MUX(0x0, "GPF9"),
630
+
MA35_MUX(0x2, "UART13_TXD"),
631
+
MA35_MUX(0x4, "I2C5_SCL"),
632
+
MA35_MUX(0x5, "SPI0_SS1"),
633
+
MA35_MUX(0x8, "RGMII1_RXD2"),
634
+
MA35_MUX(0x9, "RMII1_RXERR"),
635
+
MA35_MUX(0xd, "SC0_PWR"),
636
+
MA35_MUX(0xe, "KPI_COL5")),
637
+
MA35_PIN(86, PF10, 0xac, 0x8,
638
+
MA35_MUX(0x0, "GPF10"),
639
+
MA35_MUX(0x2, "UART13_nCTS"),
640
+
MA35_MUX(0x5, "I2S0_LRCK"),
641
+
MA35_MUX(0x6, "SPI1_SS0"),
642
+
MA35_MUX(0x8, "RGMII1_RXD3"),
643
+
MA35_MUX(0x9, "SC0_CLK"),
644
+
MA35_MUX(0xe, "KPI_COL6")),
645
+
MA35_PIN(87, PF11, 0xac, 0xc,
646
+
MA35_MUX(0x0, "GPF11"),
647
+
MA35_MUX(0x2, "UART13_nRTS"),
648
+
MA35_MUX(0x5, "I2S0_BCLK"),
649
+
MA35_MUX(0x6, "SPI1_CLK"),
650
+
MA35_MUX(0x8, "RGMII1_TXCLK"),
651
+
MA35_MUX(0x9, "SC0_DAT"),
652
+
MA35_MUX(0xe, "KPI_COL7")),
653
+
MA35_PIN(88, PF12, 0xac, 0x10,
654
+
MA35_MUX(0x0, "GPF12"),
655
+
MA35_MUX(0x5, "I2S0_DI"),
656
+
MA35_MUX(0x6, "SPI1_MOSI"),
657
+
MA35_MUX(0x8, "RGMII1_TXD2"),
658
+
MA35_MUX(0x9, "SC0_RST"),
659
+
MA35_MUX(0xe, "KPI_ROW4")),
660
+
MA35_PIN(89, PF13, 0xac, 0x14,
661
+
MA35_MUX(0x0, "GPF13"),
662
+
MA35_MUX(0x5, "I2S0_DO"),
663
+
MA35_MUX(0x6, "SPI1_MISO"),
664
+
MA35_MUX(0x8, "RGMII1_TXD3"),
665
+
MA35_MUX(0x9, "SC0_PWR"),
666
+
MA35_MUX(0xe, "KPI_ROW5")),
667
+
MA35_PIN(90, PF14, 0xac, 0x18,
668
+
MA35_MUX(0x0, "GPF14"),
669
+
MA35_MUX(0x1, "EPWM2_BRAKE0"),
670
+
MA35_MUX(0x2, "EADC0_ST"),
671
+
MA35_MUX(0x3, "RGMII1_PPS"),
672
+
MA35_MUX(0x4, "RMII1_PPS"),
673
+
MA35_MUX(0x5, "SPI0_I2SMCLK"),
674
+
MA35_MUX(0x6, "SPI1_I2SMCLK"),
675
+
MA35_MUX(0x7, "CCAP1_SFIELD"),
676
+
MA35_MUX(0x8, "RGMII0_PPS"),
677
+
MA35_MUX(0x9, "RMII0_PPS"),
678
+
MA35_MUX(0xb, "TM0"),
679
+
MA35_MUX(0xc, "INT0"),
680
+
MA35_MUX(0xd, "SPI1_SS1"),
681
+
MA35_MUX(0xe, "QEI2_INDEX"),
682
+
MA35_MUX(0xf, "I2S0_MCLK")),
683
+
MA35_PIN(91, PF15, 0xac, 0x1c,
684
+
MA35_MUX(0x0, "GPF15"),
685
+
MA35_MUX(0x1, "HSUSB0_VBUSVLD")),
686
+
MA35_PIN(92, PG0, 0xb0, 0x0,
687
+
MA35_MUX(0x0, "GPG0"),
688
+
MA35_MUX(0x1, "EPWM0_CH0"),
689
+
MA35_MUX(0x2, "UART7_TXD"),
690
+
MA35_MUX(0x3, "CAN3_TXD"),
691
+
MA35_MUX(0x5, "SPI0_SS0"),
692
+
MA35_MUX(0x6, "EADC0_ST"),
693
+
MA35_MUX(0x7, "EBI_AD15"),
694
+
MA35_MUX(0x9, "I2S1_MCLK"),
695
+
MA35_MUX(0xa, "QEI0_INDEX"),
696
+
MA35_MUX(0xb, "TM1"),
697
+
MA35_MUX(0xc, "CLKO"),
698
+
MA35_MUX(0xd, "INT0"),
699
+
MA35_MUX(0xf, "EBI_ADR15")),
700
+
MA35_PIN(93, PG1, 0xb0, 0x4,
701
+
MA35_MUX(0x0, "GPG1"),
702
+
MA35_MUX(0x1, "EPWM0_CH3"),
703
+
MA35_MUX(0x2, "UART9_nRTS"),
704
+
MA35_MUX(0x3, "UART6_TXD"),
705
+
MA35_MUX(0x4, "I2C4_SCL"),
706
+
MA35_MUX(0x5, "CAN2_TXD"),
707
+
MA35_MUX(0x7, "EBI_nCS0"),
708
+
MA35_MUX(0x9, "QEI0_B"),
709
+
MA35_MUX(0xb, "TM1_EXT"),
710
+
MA35_MUX(0xe, "RGMII1_PPS"),
711
+
MA35_MUX(0xf, "RMII1_PPS")),
712
+
MA35_PIN(94, PG2, 0xb0, 0x8,
713
+
MA35_MUX(0x0, "GPG2"),
714
+
MA35_MUX(0x1, "EPWM0_CH4"),
715
+
MA35_MUX(0x2, "UART9_RXD"),
716
+
MA35_MUX(0x3, "CAN0_RXD"),
717
+
MA35_MUX(0x5, "SPI0_SS1"),
718
+
MA35_MUX(0x7, "EBI_ADR16"),
719
+
MA35_MUX(0x8, "EBI_nCS2"),
720
+
MA35_MUX(0xa, "QEI0_A"),
721
+
MA35_MUX(0xb, "TM3"),
722
+
MA35_MUX(0xd, "INT1")),
723
+
MA35_PIN(95, PG3, 0xb0, 0xc,
724
+
MA35_MUX(0x0, "GPG3"),
725
+
MA35_MUX(0x1, "EPWM0_CH5"),
726
+
MA35_MUX(0x2, "UART9_TXD"),
727
+
MA35_MUX(0x3, "CAN0_TXD"),
728
+
MA35_MUX(0x5, "SPI0_I2SMCLK"),
729
+
MA35_MUX(0x7, "EBI_ADR17"),
730
+
MA35_MUX(0x8, "EBI_nCS1"),
731
+
MA35_MUX(0x9, "EBI_MCLK"),
732
+
MA35_MUX(0xa, "QEI0_B"),
733
+
MA35_MUX(0xb, "TM3_EXT"),
734
+
MA35_MUX(0xc, "I2S1_MCLK")),
735
+
MA35_PIN(96, PG4, 0xb0, 0x10,
736
+
MA35_MUX(0x0, "GPG4"),
737
+
MA35_MUX(0x1, "EPWM1_CH0"),
738
+
MA35_MUX(0x2, "UART5_nCTS"),
739
+
MA35_MUX(0x3, "UART6_RXD"),
740
+
MA35_MUX(0x5, "SPI3_SS0"),
741
+
MA35_MUX(0x6, "QEI1_INDEX"),
742
+
MA35_MUX(0x7, "EBI_ADR18"),
743
+
MA35_MUX(0x8, "EBI_nCS0"),
744
+
MA35_MUX(0x9, "I2S1_DO"),
745
+
MA35_MUX(0xa, "SC1_CLK"),
746
+
MA35_MUX(0xb, "TM4"),
747
+
MA35_MUX(0xd, "INT2"),
748
+
MA35_MUX(0xe, "ECAP1_IC2")),
749
+
MA35_PIN(97, PG5, 0xb0, 0x14,
750
+
MA35_MUX(0x0, "GPG5"),
751
+
MA35_MUX(0x1, "EPWM1_CH1"),
752
+
MA35_MUX(0x2, "UART5_nRTS"),
753
+
MA35_MUX(0x3, "UART6_TXD"),
754
+
MA35_MUX(0x5, "SPI3_CLK"),
755
+
MA35_MUX(0x6, "ECAP0_IC0"),
756
+
MA35_MUX(0x7, "EBI_ADR19"),
757
+
MA35_MUX(0x8, "EBI_ALE"),
758
+
MA35_MUX(0x9, "I2S1_DI"),
759
+
MA35_MUX(0xa, "SC1_DAT"),
760
+
MA35_MUX(0xb, "TM4_EXT")),
761
+
MA35_PIN(98, PG6, 0xb0, 0x18,
762
+
MA35_MUX(0x0, "GPG6"),
763
+
MA35_MUX(0x1, "EPWM1_CH2"),
764
+
MA35_MUX(0x2, "UART5_RXD"),
765
+
MA35_MUX(0x3, "CAN1_RXD"),
766
+
MA35_MUX(0x5, "SPI3_MOSI"),
767
+
MA35_MUX(0x6, "ECAP0_IC1"),
768
+
MA35_MUX(0x7, "EBI_nRD"),
769
+
MA35_MUX(0x9, "I2S1_BCLK"),
770
+
MA35_MUX(0xa, "SC1_RST"),
771
+
MA35_MUX(0xb, "TM7"),
772
+
MA35_MUX(0xd, "INT3")),
773
+
MA35_PIN(99, PG7, 0xb0, 0x1c,
774
+
MA35_MUX(0x0, "GPG7"),
775
+
MA35_MUX(0x1, "EPWM1_CH3"),
776
+
MA35_MUX(0x2, "UART5_TXD"),
777
+
MA35_MUX(0x3, "CAN1_TXD"),
778
+
MA35_MUX(0x5, "SPI3_MISO"),
779
+
MA35_MUX(0x6, "ECAP0_IC2"),
780
+
MA35_MUX(0x7, "EBI_nWR"),
781
+
MA35_MUX(0x9, "I2S1_LRCK"),
782
+
MA35_MUX(0xa, "SC1_PWR"),
783
+
MA35_MUX(0xb, "TM7_EXT")),
784
+
MA35_PIN(100, PG8, 0xb4, 0x0,
785
+
MA35_MUX(0x0, "GPG8"),
786
+
MA35_MUX(0x1, "EPWM1_CH4"),
787
+
MA35_MUX(0x2, "UART12_RXD"),
788
+
MA35_MUX(0x3, "CAN3_RXD"),
789
+
MA35_MUX(0x5, "SPI2_SS0"),
790
+
MA35_MUX(0x6, "LCM_VSYNC"),
791
+
MA35_MUX(0x7, "I2C3_SDA"),
792
+
MA35_MUX(0xc, "EBI_AD7"),
793
+
MA35_MUX(0xd, "EBI_nCS0")),
794
+
MA35_PIN(101, PG9, 0xb4, 0x4,
795
+
MA35_MUX(0x0, "GPG9"),
796
+
MA35_MUX(0x1, "EPWM1_CH5"),
797
+
MA35_MUX(0x2, "UART12_TXD"),
798
+
MA35_MUX(0x3, "CAN3_TXD"),
799
+
MA35_MUX(0x5, "SPI2_CLK"),
800
+
MA35_MUX(0x6, "LCM_HSYNC"),
801
+
MA35_MUX(0x7, "I2C3_SCL"),
802
+
MA35_MUX(0xc, "EBI_AD8"),
803
+
MA35_MUX(0xd, "EBI_nCS1")),
804
+
MA35_PIN(102, PG10, 0xb4, 0x8,
805
+
MA35_MUX(0x0, "GPG10"),
806
+
MA35_MUX(0x2, "UART12_nRTS"),
807
+
MA35_MUX(0x3, "UART13_TXD"),
808
+
MA35_MUX(0x5, "SPI2_MOSI"),
809
+
MA35_MUX(0x6, "LCM_CLK"),
810
+
MA35_MUX(0xc, "EBI_AD9"),
811
+
MA35_MUX(0xd, "EBI_nWRH")),
812
+
MA35_PIN(103, PG11, 0xb4, 0xc,
813
+
MA35_MUX(0x0, "GPG11"),
814
+
MA35_MUX(0x3, "JTAG_TDO"),
815
+
MA35_MUX(0x5, "I2S0_MCLK"),
816
+
MA35_MUX(0x6, "NAND_RDY1"),
817
+
MA35_MUX(0x7, "EBI_nWRH"),
818
+
MA35_MUX(0x8, "EBI_nCS1"),
819
+
MA35_MUX(0xa, "EBI_AD0")),
820
+
MA35_PIN(104, PG12, 0xb4, 0x10,
821
+
MA35_MUX(0x0, "GPG12"),
822
+
MA35_MUX(0x3, "JTAG_TCK/SW_CLK"),
823
+
MA35_MUX(0x5, "I2S0_LRCK"),
824
+
MA35_MUX(0x7, "EBI_nWRL"),
825
+
MA35_MUX(0xa, "EBI_AD1")),
826
+
MA35_PIN(105, PG13, 0xb4, 0x14,
827
+
MA35_MUX(0x0, "GPG13"),
828
+
MA35_MUX(0x3, "JTAG_TMS/SW_DIO"),
829
+
MA35_MUX(0x5, "I2S0_BCLK"),
830
+
MA35_MUX(0x7, "EBI_MCLK"),
831
+
MA35_MUX(0xa, "EBI_AD2")),
832
+
MA35_PIN(106, PG14, 0xb4, 0x18,
833
+
MA35_MUX(0x0, "GPG14"),
834
+
MA35_MUX(0x3, "JTAG_TDI"),
835
+
MA35_MUX(0x5, "I2S0_DI"),
836
+
MA35_MUX(0x6, "NAND_nCS1"),
837
+
MA35_MUX(0x7, "EBI_ALE"),
838
+
MA35_MUX(0xa, "EBI_AD3")),
839
+
MA35_PIN(107, PG15, 0xb4, 0x1c,
840
+
MA35_MUX(0x0, "GPG15"),
841
+
MA35_MUX(0x3, "JTAG_nTRST"),
842
+
MA35_MUX(0x5, "I2S0_DO"),
843
+
MA35_MUX(0x7, "EBI_nCS0"),
844
+
MA35_MUX(0xa, "EBI_AD4")),
845
+
MA35_PIN(108, PH0, 0xb8, 0x0,
846
+
MA35_MUX(0x0, "GPH0"),
847
+
MA35_MUX(0x2, "UART8_nCTS"),
848
+
MA35_MUX(0x3, "UART7_RXD"),
849
+
MA35_MUX(0x6, "LCM_DATA8")),
850
+
MA35_PIN(109, PH1, 0xb8, 0x4,
851
+
MA35_MUX(0x0, "GPH1"),
852
+
MA35_MUX(0x2, "UART8_nRTS"),
853
+
MA35_MUX(0x3, "UART7_TXD"),
854
+
MA35_MUX(0x6, "LCM_DATA9")),
855
+
MA35_PIN(110, PH2, 0xb8, 0x8,
856
+
MA35_MUX(0x0, "GPH2"),
857
+
MA35_MUX(0x2, "UART8_RXD"),
858
+
MA35_MUX(0x6, "LCM_DATA10")),
859
+
MA35_PIN(111, PH3, 0xb8, 0xc,
860
+
MA35_MUX(0x0, "GPH3"),
861
+
MA35_MUX(0x2, "UART8_TXD"),
862
+
MA35_MUX(0x6, "LCM_DATA11")),
863
+
MA35_PIN(112, PH4, 0xb8, 0x10,
864
+
MA35_MUX(0x0, "GPH4"),
865
+
MA35_MUX(0x2, "UART10_nCTS"),
866
+
MA35_MUX(0x3, "UART9_RXD"),
867
+
MA35_MUX(0x6, "LCM_DATA12")),
868
+
MA35_PIN(113, PH5, 0xb8, 0x14,
869
+
MA35_MUX(0x0, "GPH5"),
870
+
MA35_MUX(0x2, "UART10_nRTS"),
871
+
MA35_MUX(0x3, "UART9_TXD"),
872
+
MA35_MUX(0x6, "LCM_DATA13")),
873
+
MA35_PIN(114, PH6, 0xb8, 0x18,
874
+
MA35_MUX(0x0, "GPH6"),
875
+
MA35_MUX(0x2, "UART10_RXD"),
876
+
MA35_MUX(0x6, "LCM_DATA14")),
877
+
MA35_PIN(115, PH7, 0xb8, 0x1c,
878
+
MA35_MUX(0x0, "GPH7"),
879
+
MA35_MUX(0x2, "UART10_TXD"),
880
+
MA35_MUX(0x6, "LCM_DATA15")),
881
+
MA35_PIN(116, PH8, 0xbc, 0x0,
882
+
MA35_MUX(0x0, "GPH8"),
883
+
MA35_MUX(0x6, "TAMPER0")),
884
+
MA35_PIN(117, PH9, 0xbc, 0x4,
885
+
MA35_MUX(0x0, "GPH9"),
886
+
MA35_MUX(0x4, "CLK_32KOUT"),
887
+
MA35_MUX(0x6, "TAMPER1")),
888
+
MA35_PIN(118, PH12, 0xbc, 0x10,
889
+
MA35_MUX(0x0, "GPH12"),
890
+
MA35_MUX(0x2, "UART14_nCTS"),
891
+
MA35_MUX(0x3, "UART13_RXD"),
892
+
MA35_MUX(0x6, "LCM_DATA20")),
893
+
MA35_PIN(119, PH13, 0xbc, 0x14,
894
+
MA35_MUX(0x0, "GPH13"),
895
+
MA35_MUX(0x2, "UART14_nRTS"),
896
+
MA35_MUX(0x3, "UART13_TXD"),
897
+
MA35_MUX(0x6, "LCM_DATA21")),
898
+
MA35_PIN(120, PH14, 0xbc, 0x18,
899
+
MA35_MUX(0x0, "GPH14"),
900
+
MA35_MUX(0x2, "UART14_RXD"),
901
+
MA35_MUX(0x6, "LCM_DATA22")),
902
+
MA35_PIN(121, PH15, 0xbc, 0x1c,
903
+
MA35_MUX(0x0, "GPH15"),
904
+
MA35_MUX(0x2, "UART14_TXD"),
905
+
MA35_MUX(0x6, "LCM_DATA23")),
906
+
MA35_PIN(122, PI0, 0xc0, 0x0,
907
+
MA35_MUX(0x0, "GPI0"),
908
+
MA35_MUX(0x1, "EPWM0_CH0"),
909
+
MA35_MUX(0x2, "UART12_nCTS"),
910
+
MA35_MUX(0x3, "UART11_RXD"),
911
+
MA35_MUX(0x4, "I2C2_SDA"),
912
+
MA35_MUX(0x5, "SPI3_SS0"),
913
+
MA35_MUX(0x7, "SC0_nCD"),
914
+
MA35_MUX(0x8, "EBI_ADR0"),
915
+
MA35_MUX(0xb, "TM0"),
916
+
MA35_MUX(0xc, "ECAP1_IC0")),
917
+
MA35_PIN(123, PI1, 0xc0, 0x4,
918
+
MA35_MUX(0x0, "GPI1"),
919
+
MA35_MUX(0x1, "EPWM0_CH1"),
920
+
MA35_MUX(0x2, "UART12_nRTS"),
921
+
MA35_MUX(0x3, "UART11_TXD"),
922
+
MA35_MUX(0x4, "I2C2_SCL"),
923
+
MA35_MUX(0x5, "SPI3_CLK"),
924
+
MA35_MUX(0x7, "SC0_CLK"),
925
+
MA35_MUX(0x8, "EBI_ADR1"),
926
+
MA35_MUX(0xb, "TM0_EXT"),
927
+
MA35_MUX(0xc, "ECAP1_IC1")),
928
+
MA35_PIN(124, PI2, 0xc0, 0x8,
929
+
MA35_MUX(0x0, "GPI2"),
930
+
MA35_MUX(0x1, "EPWM0_CH2"),
931
+
MA35_MUX(0x2, "UART12_RXD"),
932
+
MA35_MUX(0x3, "CAN0_RXD"),
933
+
MA35_MUX(0x5, "SPI3_MOSI"),
934
+
MA35_MUX(0x7, "SC0_DAT"),
935
+
MA35_MUX(0x8, "EBI_ADR2"),
936
+
MA35_MUX(0xb, "TM1"),
937
+
MA35_MUX(0xc, "ECAP1_IC2")),
938
+
MA35_PIN(125, PI3, 0xc0, 0xc,
939
+
MA35_MUX(0x0, "GPI3"),
940
+
MA35_MUX(0x1, "EPWM0_CH3"),
941
+
MA35_MUX(0x2, "UART12_TXD"),
942
+
MA35_MUX(0x3, "CAN0_TXD"),
943
+
MA35_MUX(0x5, "SPI3_MISO"),
944
+
MA35_MUX(0x7, "SC0_RST"),
945
+
MA35_MUX(0x8, "EBI_ADR3"),
946
+
MA35_MUX(0xb, "TM1_EXT")),
947
+
MA35_PIN(126, PI4, 0xc0, 0x10,
948
+
MA35_MUX(0x0, "GPI4"),
949
+
MA35_MUX(0x1, "EPWM0_CH4"),
950
+
MA35_MUX(0x2, "UART14_nCTS"),
951
+
MA35_MUX(0x3, "UART13_RXD"),
952
+
MA35_MUX(0x4, "I2C3_SDA"),
953
+
MA35_MUX(0x5, "SPI2_SS1"),
954
+
MA35_MUX(0x6, "I2S1_LRCK"),
955
+
MA35_MUX(0x8, "EBI_ADR4"),
956
+
MA35_MUX(0xd, "INT0")),
957
+
MA35_PIN(127, PI5, 0xc0, 0x14,
958
+
MA35_MUX(0x0, "GPI5"),
959
+
MA35_MUX(0x1, "EPWM0_CH5"),
960
+
MA35_MUX(0x2, "UART14_nRTS"),
961
+
MA35_MUX(0x3, "UART13_TXD"),
962
+
MA35_MUX(0x4, "I2C3_SCL"),
963
+
MA35_MUX(0x6, "I2S1_BCLK"),
964
+
MA35_MUX(0x8, "EBI_ADR5"),
965
+
MA35_MUX(0xd, "INT1")),
966
+
MA35_PIN(128, PI6, 0xc0, 0x18,
967
+
MA35_MUX(0x0, "GPI6"),
968
+
MA35_MUX(0x1, "EPWM0_BRAKE0"),
969
+
MA35_MUX(0x2, "UART14_RXD"),
970
+
MA35_MUX(0x3, "CAN1_RXD"),
971
+
MA35_MUX(0x6, "I2S1_DI"),
972
+
MA35_MUX(0x8, "EBI_ADR6"),
973
+
MA35_MUX(0xc, "QEI1_INDEX"),
974
+
MA35_MUX(0xd, "INT2")),
975
+
MA35_PIN(129, PI7, 0xc0, 0x1c,
976
+
MA35_MUX(0x0, "GPI7"),
977
+
MA35_MUX(0x1, "EPWM0_BRAKE1"),
978
+
MA35_MUX(0x2, "UART14_TXD"),
979
+
MA35_MUX(0x3, "CAN1_TXD"),
980
+
MA35_MUX(0x6, "I2S1_DO"),
981
+
MA35_MUX(0x8, "EBI_ADR7"),
982
+
MA35_MUX(0xc, "ECAP0_IC0"),
983
+
MA35_MUX(0xd, "INT3")),
984
+
MA35_PIN(130, PI8, 0xc4, 0x0,
985
+
MA35_MUX(0x0, "GPI8"),
986
+
MA35_MUX(0x2, "UART4_nCTS"),
987
+
MA35_MUX(0x3, "UART3_RXD"),
988
+
MA35_MUX(0x6, "LCM_DATA0"),
989
+
MA35_MUX(0xc, "EBI_AD11")),
990
+
MA35_PIN(131, PI9, 0xc4, 0x4,
991
+
MA35_MUX(0x0, "GPI9"),
992
+
MA35_MUX(0x2, "UART4_nRTS"),
993
+
MA35_MUX(0x3, "UART3_TXD"),
994
+
MA35_MUX(0x6, "LCM_DATA1"),
995
+
MA35_MUX(0xc, "EBI_AD12")),
996
+
MA35_PIN(132, PI10, 0xc4, 0x8,
997
+
MA35_MUX(0x0, "GPI10"),
998
+
MA35_MUX(0x2, "UART4_RXD"),
999
+
MA35_MUX(0x6, "LCM_DATA2"),
1000
+
MA35_MUX(0xc, "EBI_AD13")),
1001
+
MA35_PIN(133, PI11, 0xC4, 0xc,
1002
+
MA35_MUX(0x0, "GPI11"),
1003
+
MA35_MUX(0x2, "UART4_TXD"),
1004
+
MA35_MUX(0x6, "LCM_DATA3"),
1005
+
MA35_MUX(0xc, "EBI_AD14")),
1006
+
MA35_PIN(134, PI12, 0xc4, 0x10,
1007
+
MA35_MUX(0x0, "GPI12"),
1008
+
MA35_MUX(0x2, "UART6_nCTS"),
1009
+
MA35_MUX(0x3, "UART5_RXD"),
1010
+
MA35_MUX(0x6, "LCM_DATA4")),
1011
+
MA35_PIN(135, PI13, 0xc4, 0x14,
1012
+
MA35_MUX(0x0, "GPI13"),
1013
+
MA35_MUX(0x2, "UART6_nRTS"),
1014
+
MA35_MUX(0x3, "UART5_TXD"),
1015
+
MA35_MUX(0x6, "LCM_DATA5")),
1016
+
MA35_PIN(136, PI14, 0xc4, 0x18,
1017
+
MA35_MUX(0x0, "GPI14"),
1018
+
MA35_MUX(0x2, "UART6_RXD"),
1019
+
MA35_MUX(0x6, "LCM_DATA6")),
1020
+
MA35_PIN(137, PI15, 0xc4, 0x1c,
1021
+
MA35_MUX(0x0, "GPI15"),
1022
+
MA35_MUX(0x2, "UART6_TXD"),
1023
+
MA35_MUX(0x6, "LCM_DATA7")),
1024
+
MA35_PIN(138, PJ0, 0xc8, 0x0,
1025
+
MA35_MUX(0x0, "GPJ0"),
1026
+
MA35_MUX(0x1, "EPWM1_BRAKE0"),
1027
+
MA35_MUX(0x2, "UART8_nCTS"),
1028
+
MA35_MUX(0x3, "UART7_RXD"),
1029
+
MA35_MUX(0x4, "I2C2_SDA"),
1030
+
MA35_MUX(0x5, "SPI2_SS0"),
1031
+
MA35_MUX(0x6, "eMMC1_DAT4"),
1032
+
MA35_MUX(0x7, "I2S0_LRCK"),
1033
+
MA35_MUX(0x8, "SC0_CLK"),
1034
+
MA35_MUX(0x9, "EBI_AD11"),
1035
+
MA35_MUX(0xa, "EBI_ADR16"),
1036
+
MA35_MUX(0xb, "EBI_nCS0"),
1037
+
MA35_MUX(0xc, "EBI_AD7")),
1038
+
MA35_PIN(139, PJ1, 0xc8, 0x4,
1039
+
MA35_MUX(0x0, "GPJ1"),
1040
+
MA35_MUX(0x1, "EPWM1_BRAKE1"),
1041
+
MA35_MUX(0x2, "UART8_nRTS"),
1042
+
MA35_MUX(0x3, "UART7_TXD"),
1043
+
MA35_MUX(0x4, "I2C2_SCL"),
1044
+
MA35_MUX(0x5, "SPI2_CLK"),
1045
+
MA35_MUX(0x6, "eMMC1_DAT5"),
1046
+
MA35_MUX(0x7, "I2S0_BCLK"),
1047
+
MA35_MUX(0x8, "SC0_DAT"),
1048
+
MA35_MUX(0x9, "EBI_AD12"),
1049
+
MA35_MUX(0xa, "EBI_ADR17"),
1050
+
MA35_MUX(0xb, "EBI_nCS1"),
1051
+
MA35_MUX(0xc, "EBI_AD8")),
1052
+
MA35_PIN(140, PJ2, 0xc8, 0x8,
1053
+
MA35_MUX(0x0, "GPJ2"),
1054
+
MA35_MUX(0x1, "EPWM1_CH4"),
1055
+
MA35_MUX(0x2, "UART8_RXD"),
1056
+
MA35_MUX(0x3, "CAN1_RXD"),
1057
+
MA35_MUX(0x5, "SPI2_MOSI"),
1058
+
MA35_MUX(0x6, "eMMC1_DAT6"),
1059
+
MA35_MUX(0x7, "I2S0_DI"),
1060
+
MA35_MUX(0x8, "SC0_RST"),
1061
+
MA35_MUX(0x9, "EBI_AD13"),
1062
+
MA35_MUX(0xa, "EBI_ADR18"),
1063
+
MA35_MUX(0xb, "EBI_nWRH"),
1064
+
MA35_MUX(0xc, "EBI_AD9")),
1065
+
MA35_PIN(141, PJ3, 0xc8, 0xc,
1066
+
MA35_MUX(0x0, "GPJ3"),
1067
+
MA35_MUX(0x1, "EPWM1_CH5"),
1068
+
MA35_MUX(0x2, "UART8_TXD"),
1069
+
MA35_MUX(0x3, "CAN1_TXD"),
1070
+
MA35_MUX(0x5, "SPI2_MISO"),
1071
+
MA35_MUX(0x6, "eMMC1_DAT7"),
1072
+
MA35_MUX(0x7, "I2S0_DO"),
1073
+
MA35_MUX(0x8, "SC0_PWR"),
1074
+
MA35_MUX(0x9, "EBI_AD14"),
1075
+
MA35_MUX(0xa, "EBI_ADR19"),
1076
+
MA35_MUX(0xb, "EBI_nWRL"),
1077
+
MA35_MUX(0xc, "EBI_AD10")),
1078
+
MA35_PIN(142, PJ4, 0xc8, 0x10,
1079
+
MA35_MUX(0x0, "GPJ4"),
1080
+
MA35_MUX(0x4, "I2C3_SDA"),
1081
+
MA35_MUX(0x6, "SD1_WP")),
1082
+
MA35_PIN(143, PJ5, 0xc8, 0x14,
1083
+
MA35_MUX(0x0, "GPJ5"),
1084
+
MA35_MUX(0x4, "I2C3_SCL"),
1085
+
MA35_MUX(0x6, "SD1_nCD")),
1086
+
MA35_PIN(144, PJ6, 0xc8, 0x18,
1087
+
MA35_MUX(0x0, "GPJ6"),
1088
+
MA35_MUX(0x3, "CAN3_RXD"),
1089
+
MA35_MUX(0x6, "SD1_CMD/eMMC1_CMD")),
1090
+
MA35_PIN(145, PJ7, 0xc8, 0x1c,
1091
+
MA35_MUX(0x0, "GPJ7"),
1092
+
MA35_MUX(0x3, "CAN3_TXD"),
1093
+
MA35_MUX(0x6, "SD1_CLK/eMMC1_CLK")),
1094
+
MA35_PIN(146, PJ8, 0xcc, 0x0,
1095
+
MA35_MUX(0x0, "GPJ8"),
1096
+
MA35_MUX(0x4, "I2C4_SDA"),
1097
+
MA35_MUX(0x6, "SD1_DAT0/eMMC1_DAT0")),
1098
+
MA35_PIN(147, PJ9, 0xcc, 0x4,
1099
+
MA35_MUX(0x0, "GPJ9"),
1100
+
MA35_MUX(0x4, "I2C4_SCL"),
1101
+
MA35_MUX(0x6, "SD1_DAT1/eMMC1_DAT1")),
1102
+
MA35_PIN(148, PJ10, 0xcc, 0x8,
1103
+
MA35_MUX(0x0, "GPJ10"),
1104
+
MA35_MUX(0x3, "CAN0_RXD"),
1105
+
MA35_MUX(0x6, "SD1_DAT2/eMMC1_DAT2")),
1106
+
MA35_PIN(149, PJ11, 0xcc, 0xc,
1107
+
MA35_MUX(0x0, "GPJ11"),
1108
+
MA35_MUX(0x3, "CAN0_TXD"),
1109
+
MA35_MUX(0x6, "SD1_DAT3/eMMC1_DAT3")),
1110
+
MA35_PIN(150, PJ12, 0xcc, 0x10,
1111
+
MA35_MUX(0x0, "GPJ12"),
1112
+
MA35_MUX(0x1, "EPWM1_CH2"),
1113
+
MA35_MUX(0x2, "UART2_nCTS"),
1114
+
MA35_MUX(0x3, "UART1_RXD"),
1115
+
MA35_MUX(0x4, "I2C5_SDA"),
1116
+
MA35_MUX(0x5, "SPI3_SS0"),
1117
+
MA35_MUX(0x7, "SC1_CLK"),
1118
+
MA35_MUX(0x8, "EBI_ADR12"),
1119
+
MA35_MUX(0xb, "TM2"),
1120
+
MA35_MUX(0xc, "QEI0_INDEX")),
1121
+
MA35_PIN(151, PJ13, 0xcc, 0x14,
1122
+
MA35_MUX(0x0, "GPJ13"),
1123
+
MA35_MUX(0x1, "EPWM1_CH3"),
1124
+
MA35_MUX(0x2, "UART2_nRTS"),
1125
+
MA35_MUX(0x3, "UART1_TXD"),
1126
+
MA35_MUX(0x4, "I2C5_SCL"),
1127
+
MA35_MUX(0x5, "SPI3_MOSI"),
1128
+
MA35_MUX(0x7, "SC1_DAT"),
1129
+
MA35_MUX(0x8, "EBI_ADR13"),
1130
+
MA35_MUX(0xb, "TM2_EXT")),
1131
+
MA35_PIN(152, PJ14, 0xcc, 0x18,
1132
+
MA35_MUX(0x0, "GPJ14"),
1133
+
MA35_MUX(0x1, "EPWM1_CH4"),
1134
+
MA35_MUX(0x2, "UART2_RXD"),
1135
+
MA35_MUX(0x3, "CAN3_RXD"),
1136
+
MA35_MUX(0x5, "SPI3_MISO"),
1137
+
MA35_MUX(0x7, "SC1_RST"),
1138
+
MA35_MUX(0x8, "EBI_ADR14"),
1139
+
MA35_MUX(0xb, "TM3")),
1140
+
MA35_PIN(153, PJ15, 0xcc, 0x1c,
1141
+
MA35_MUX(0x0, "GPJ15"),
1142
+
MA35_MUX(0x1, "EPWM1_CH5"),
1143
+
MA35_MUX(0x2, "UART2_TXD"),
1144
+
MA35_MUX(0x3, "CAN3_TXD"),
1145
+
MA35_MUX(0x5, "SPI3_CLK"),
1146
+
MA35_MUX(0x6, "EADC0_ST"),
1147
+
MA35_MUX(0x7, "SC1_PWR"),
1148
+
MA35_MUX(0x8, "EBI_ADR15"),
1149
+
MA35_MUX(0xb, "TM3_EXT"),
1150
+
MA35_MUX(0xd, "INT1")),
1151
+
MA35_PIN(154, PK0, 0xd0, 0x0,
1152
+
MA35_MUX(0x0, "GPK0"),
1153
+
MA35_MUX(0x1, "EPWM0_SYNC_IN"),
1154
+
MA35_MUX(0x2, "UART16_nCTS"),
1155
+
MA35_MUX(0x3, "UART15_RXD"),
1156
+
MA35_MUX(0x4, "I2C4_SDA"),
1157
+
MA35_MUX(0x6, "I2S1_MCLK"),
1158
+
MA35_MUX(0x8, "EBI_ADR8"),
1159
+
MA35_MUX(0xb, "TM7"),
1160
+
MA35_MUX(0xc, "ECAP0_IC1")),
1161
+
MA35_PIN(155, PK1, 0xd0, 0x4,
1162
+
MA35_MUX(0x0, "GPK1"),
1163
+
MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
1164
+
MA35_MUX(0x2, "UART16_nRTS"),
1165
+
MA35_MUX(0x3, "UART15_TXD"),
1166
+
MA35_MUX(0x4, "I2C4_SCL"),
1167
+
MA35_MUX(0x6, "EADC0_ST"),
1168
+
MA35_MUX(0x8, "EBI_ADR9"),
1169
+
MA35_MUX(0xb, "TM7_EXT"),
1170
+
MA35_MUX(0xc, "ECAP0_IC2")),
1171
+
MA35_PIN(156, PK2, 0xd0, 0x8,
1172
+
MA35_MUX(0x0, "GPK2"),
1173
+
MA35_MUX(0x1, "EPWM1_CH0"),
1174
+
MA35_MUX(0x2, "UART16_RXD"),
1175
+
MA35_MUX(0x3, "CAN2_RXD"),
1176
+
MA35_MUX(0x5, "SPI3_I2SMCLK"),
1177
+
MA35_MUX(0x7, "SC0_PWR"),
1178
+
MA35_MUX(0x8, "EBI_ADR10"),
1179
+
MA35_MUX(0xc, "QEI0_A")),
1180
+
MA35_PIN(157, PK3, 0xd0, 0xc,
1181
+
MA35_MUX(0x0, "GPK3"),
1182
+
MA35_MUX(0x1, "EPWM1_CH1"),
1183
+
MA35_MUX(0x2, "UART16_TXD"),
1184
+
MA35_MUX(0x3, "CAN2_TXD"),
1185
+
MA35_MUX(0x5, "SPI3_SS1"),
1186
+
MA35_MUX(0x7, "SC1_nCD"),
1187
+
MA35_MUX(0x8, "EBI_ADR11"),
1188
+
MA35_MUX(0xc, "QEI0_B")),
1189
+
MA35_PIN(158, PK4, 0xd0, 0x10,
1190
+
MA35_MUX(0x0, "GPK4"),
1191
+
MA35_MUX(0x2, "UART12_nCTS"),
1192
+
MA35_MUX(0x3, "UART13_RXD"),
1193
+
MA35_MUX(0x5, "SPI2_MISO"),
1194
+
MA35_MUX(0x6, "LCM_DEN"),
1195
+
MA35_MUX(0xc, "EBI_AD10"),
1196
+
MA35_MUX(0xd, "EBI_nWRL")),
1197
+
MA35_PIN(159, PK5, 0xd0, 0x14,
1198
+
MA35_MUX(0x0, "GPK5"),
1199
+
MA35_MUX(0x1, "EPWM1_CH1"),
1200
+
MA35_MUX(0x2, "UART12_nRTS"),
1201
+
MA35_MUX(0x3, "UART13_TXD"),
1202
+
MA35_MUX(0x4, "I2C4_SCL"),
1203
+
MA35_MUX(0x5, "SPI2_CLK"),
1204
+
MA35_MUX(0x7, "I2S1_DI"),
1205
+
MA35_MUX(0x8, "SC0_DAT"),
1206
+
MA35_MUX(0x9, "EADC0_ST"),
1207
+
MA35_MUX(0xb, "TM8_EXT"),
1208
+
MA35_MUX(0xd, "INT1")),
1209
+
MA35_PIN(160, PK6, 0xd0, 0x18,
1210
+
MA35_MUX(0x0, "GPK6"),
1211
+
MA35_MUX(0x1, "EPWM1_CH2"),
1212
+
MA35_MUX(0x2, "UART12_RXD"),
1213
+
MA35_MUX(0x3, "CAN0_RXD"),
1214
+
MA35_MUX(0x5, "SPI2_MOSI"),
1215
+
MA35_MUX(0x7, "I2S1_BCLK"),
1216
+
MA35_MUX(0x8, "SC0_RST"),
1217
+
MA35_MUX(0xb, "TM6"),
1218
+
MA35_MUX(0xd, "INT2")),
1219
+
MA35_PIN(161, PK7, 0xd0, 0x1c,
1220
+
MA35_MUX(0x0, "GPK7"),
1221
+
MA35_MUX(0x1, "EPWM1_CH3"),
1222
+
MA35_MUX(0x2, "UART12_TXD"),
1223
+
MA35_MUX(0x3, "CAN0_TXD"),
1224
+
MA35_MUX(0x5, "SPI2_MISO"),
1225
+
MA35_MUX(0x7, "I2S1_LRCK"),
1226
+
MA35_MUX(0x8, "SC0_PWR"),
1227
+
MA35_MUX(0x9, "CLKO"),
1228
+
MA35_MUX(0xb, "TM6_EXT"),
1229
+
MA35_MUX(0xd, "INT3")),
1230
+
MA35_PIN(162, PK8, 0xd4, 0x0,
1231
+
MA35_MUX(0x0, "GPK8"),
1232
+
MA35_MUX(0x1, "EPWM1_CH0"),
1233
+
MA35_MUX(0x4, "I2C3_SDA"),
1234
+
MA35_MUX(0x5, "SPI3_CLK"),
1235
+
MA35_MUX(0x7, "EADC0_ST"),
1236
+
MA35_MUX(0x8, "EBI_AD15"),
1237
+
MA35_MUX(0x9, "EBI_MCLK"),
1238
+
MA35_MUX(0xa, "EBI_ADR15"),
1239
+
MA35_MUX(0xb, "TM8"),
1240
+
MA35_MUX(0xc, "QEI1_INDEX")),
1241
+
MA35_PIN(163, PK9, 0xd4, 0x4,
1242
+
MA35_MUX(0x0, "GPK9"),
1243
+
MA35_MUX(0x4, "I2C3_SCL"),
1244
+
MA35_MUX(0x6, "CCAP0_SCLK"),
1245
+
MA35_MUX(0x8, "EBI_AD0"),
1246
+
MA35_MUX(0xa, "EBI_ADR0")),
1247
+
MA35_PIN(164, PK10, 0xd4, 0x8,
1248
+
MA35_MUX(0x0, "GPK10"),
1249
+
MA35_MUX(0x3, "CAN1_RXD"),
1250
+
MA35_MUX(0x6, "CCAP0_PIXCLK"),
1251
+
MA35_MUX(0x8, "EBI_AD1"),
1252
+
MA35_MUX(0xa, "EBI_ADR1")),
1253
+
MA35_PIN(165, PK11, 0xd4, 0xc,
1254
+
MA35_MUX(0x0, "GPK11"),
1255
+
MA35_MUX(0x3, "CAN1_TXD"),
1256
+
MA35_MUX(0x6, "CCAP0_HSYNC"),
1257
+
MA35_MUX(0x8, "EBI_AD2"),
1258
+
MA35_MUX(0xa, "EBI_ADR2")),
1259
+
MA35_PIN(166, PK12, 0xd4, 0x10,
1260
+
MA35_MUX(0x0, "GPK12"),
1261
+
MA35_MUX(0x1, "EPWM2_CH0"),
1262
+
MA35_MUX(0x2, "UART1_nCTS"),
1263
+
MA35_MUX(0x3, "UART13_RXD"),
1264
+
MA35_MUX(0x4, "I2C4_SDA"),
1265
+
MA35_MUX(0x5, "I2S0_LRCK"),
1266
+
MA35_MUX(0x6, "SPI1_SS0"),
1267
+
MA35_MUX(0x8, "SC0_CLK"),
1268
+
MA35_MUX(0xb, "TM10"),
1269
+
MA35_MUX(0xd, "INT2")),
1270
+
MA35_PIN(167, PK13, 0xd4, 0x14,
1271
+
MA35_MUX(0x0, "GPK13"),
1272
+
MA35_MUX(0x1, "EPWM2_CH1"),
1273
+
MA35_MUX(0x2, "UART1_nRTS"),
1274
+
MA35_MUX(0x3, "UART13_TXD"),
1275
+
MA35_MUX(0x4, "I2C4_SCL"),
1276
+
MA35_MUX(0x5, "I2S0_BCLK"),
1277
+
MA35_MUX(0x6, "SPI1_CLK"),
1278
+
MA35_MUX(0x8, "SC0_DAT"),
1279
+
MA35_MUX(0xb, "TM10_EXT")),
1280
+
MA35_PIN(168, PK14, 0xd4, 0x18,
1281
+
MA35_MUX(0x0, "GPK14"),
1282
+
MA35_MUX(0x1, "EPWM2_CH2"),
1283
+
MA35_MUX(0x2, "UART1_RXD"),
1284
+
MA35_MUX(0x3, "CAN3_RXD"),
1285
+
MA35_MUX(0x5, "I2S0_DI"),
1286
+
MA35_MUX(0x6, "SPI1_MOSI"),
1287
+
MA35_MUX(0x8, "SC0_RST"),
1288
+
MA35_MUX(0xa, "I2C5_SDA"),
1289
+
MA35_MUX(0xb, "TM11"),
1290
+
MA35_MUX(0xd, "INT3")),
1291
+
MA35_PIN(169, PK15, 0xd4, 0x1c,
1292
+
MA35_MUX(0x0, "GPK15"),
1293
+
MA35_MUX(0x1, "EPWM2_CH3"),
1294
+
MA35_MUX(0x2, "UART1_TXD"),
1295
+
MA35_MUX(0x3, "CAN3_TXD"),
1296
+
MA35_MUX(0x5, "I2S0_DO"),
1297
+
MA35_MUX(0x6, "SPI1_MISO"),
1298
+
MA35_MUX(0x8, "SC0_PWR"),
1299
+
MA35_MUX(0xa, "I2C5_SCL"),
1300
+
MA35_MUX(0xb, "TM11_EXT")),
1301
+
MA35_PIN(170, PL0, 0xd8, 0x0,
1302
+
MA35_MUX(0x0, "GPL0"),
1303
+
MA35_MUX(0x1, "EPWM1_CH0"),
1304
+
MA35_MUX(0x2, "UART11_nCTS"),
1305
+
MA35_MUX(0x3, "UART10_RXD"),
1306
+
MA35_MUX(0x4, "I2C3_SDA"),
1307
+
MA35_MUX(0x5, "SPI2_MOSI"),
1308
+
MA35_MUX(0x6, "QSPI1_MOSI1"),
1309
+
MA35_MUX(0x7, "I2S0_LRCK"),
1310
+
MA35_MUX(0x8, "EBI_AD11"),
1311
+
MA35_MUX(0x9, "SC1_CLK"),
1312
+
MA35_MUX(0xb, "TM5"),
1313
+
MA35_MUX(0xc, "QEI1_A")),
1314
+
MA35_PIN(171, PL1, 0xd8, 0x4,
1315
+
MA35_MUX(0x0, "GPL1"),
1316
+
MA35_MUX(0x1, "EPWM1_CH1"),
1317
+
MA35_MUX(0x2, "UART11_nRTS"),
1318
+
MA35_MUX(0x3, "UART10_TXD"),
1319
+
MA35_MUX(0x4, "I2C3_SCL"),
1320
+
MA35_MUX(0x5, "SPI2_MISO"),
1321
+
MA35_MUX(0x6, "QSPI1_MISO1"),
1322
+
MA35_MUX(0x7, "I2S0_BCLK"),
1323
+
MA35_MUX(0x8, "EBI_AD12"),
1324
+
MA35_MUX(0x9, "SC1_DAT"),
1325
+
MA35_MUX(0xb, "TM5_EXT"),
1326
+
MA35_MUX(0xc, "QEI1_B")),
1327
+
MA35_PIN(172, PL2, 0xd8, 0x8,
1328
+
MA35_MUX(0x0, "GPL2"),
1329
+
MA35_MUX(0x1, "EPWM1_CH2"),
1330
+
MA35_MUX(0x2, "UART11_RXD"),
1331
+
MA35_MUX(0x3, "CAN3_RXD"),
1332
+
MA35_MUX(0x5, "SPI2_SS0"),
1333
+
MA35_MUX(0x6, "QSPI1_SS1"),
1334
+
MA35_MUX(0x7, "I2S0_DI"),
1335
+
MA35_MUX(0x8, "EBI_AD13"),
1336
+
MA35_MUX(0x9, "SC1_RST"),
1337
+
MA35_MUX(0xb, "TM7"),
1338
+
MA35_MUX(0xc, "QEI1_INDEX")),
1339
+
MA35_PIN(173, PL3, 0xd8, 0xc,
1340
+
MA35_MUX(0x0, "GPL3"),
1341
+
MA35_MUX(0x1, "EPWM1_CH3"),
1342
+
MA35_MUX(0x2, "UART11_TXD"),
1343
+
MA35_MUX(0x3, "CAN3_TXD"),
1344
+
MA35_MUX(0x5, "SPI2_CLK"),
1345
+
MA35_MUX(0x6, "QSPI1_CLK"),
1346
+
MA35_MUX(0x7, "I2S0_DO"),
1347
+
MA35_MUX(0x8, "EBI_AD14"),
1348
+
MA35_MUX(0x9, "SC1_PWR"),
1349
+
MA35_MUX(0xb, "TM7_EXT"),
1350
+
MA35_MUX(0xc, "ECAP0_IC0")),
1351
+
MA35_PIN(174, PL4, 0xd8, 0x10,
1352
+
MA35_MUX(0x0, "GPL4"),
1353
+
MA35_MUX(0x1, "EPWM1_CH4"),
1354
+
MA35_MUX(0x2, "UART2_nCTS"),
1355
+
MA35_MUX(0x3, "UART1_RXD"),
1356
+
MA35_MUX(0x4, "I2C4_SDA"),
1357
+
MA35_MUX(0x5, "SPI3_MOSI"),
1358
+
MA35_MUX(0x6, "QSPI1_MOSI0"),
1359
+
MA35_MUX(0x7, "I2S0_MCLK"),
1360
+
MA35_MUX(0x8, "EBI_nRD"),
1361
+
MA35_MUX(0x9, "SC1_nCD"),
1362
+
MA35_MUX(0xb, "TM9"),
1363
+
MA35_MUX(0xc, "ECAP0_IC1")),
1364
+
MA35_PIN(175, PL5, 0xd8, 0x14,
1365
+
MA35_MUX(0x0, "GPL5"),
1366
+
MA35_MUX(0x1, "EPWM1_CH5"),
1367
+
MA35_MUX(0x2, "UART2_nRTS"),
1368
+
MA35_MUX(0x3, "UART1_TXD"),
1369
+
MA35_MUX(0x4, "I2C4_SCL"),
1370
+
MA35_MUX(0x5, "SPI3_MISO"),
1371
+
MA35_MUX(0x6, "QSPI1_MISO0"),
1372
+
MA35_MUX(0x7, "I2S1_MCLK"),
1373
+
MA35_MUX(0x8, "EBI_nWR"),
1374
+
MA35_MUX(0x9, "SC0_nCD"),
1375
+
MA35_MUX(0xb, "TM9_EXT"),
1376
+
MA35_MUX(0xc, "ECAP0_IC2")),
1377
+
MA35_PIN(176, PL6, 0xd8, 0x18,
1378
+
MA35_MUX(0x0, "GPL6"),
1379
+
MA35_MUX(0x1, "EPWM0_CH0"),
1380
+
MA35_MUX(0x2, "UART2_RXD"),
1381
+
MA35_MUX(0x3, "CAN0_RXD"),
1382
+
MA35_MUX(0x6, "QSPI1_MOSI1"),
1383
+
MA35_MUX(0x7, "TRACE_CLK"),
1384
+
MA35_MUX(0x8, "EBI_AD5"),
1385
+
MA35_MUX(0xb, "TM3"),
1386
+
MA35_MUX(0xc, "ECAP1_IC0"),
1387
+
MA35_MUX(0xd, "INT0")),
1388
+
MA35_PIN(177, PL7, 0xd8, 0x1c,
1389
+
MA35_MUX(0x0, "GPL7"),
1390
+
MA35_MUX(0x1, "EPWM0_CH1"),
1391
+
MA35_MUX(0x2, "UART2_TXD"),
1392
+
MA35_MUX(0x3, "CAN0_TXD"),
1393
+
MA35_MUX(0x6, "QSPI1_MISO1"),
1394
+
MA35_MUX(0x8, "EBI_AD6"),
1395
+
MA35_MUX(0xb, "TM3_EXT"),
1396
+
MA35_MUX(0xc, "ECAP1_IC1"),
1397
+
MA35_MUX(0xd, "INT1")),
1398
+
MA35_PIN(178, PL8, 0xdc, 0x0,
1399
+
MA35_MUX(0x0, "GPL8"),
1400
+
MA35_MUX(0x1, "EPWM0_CH2"),
1401
+
MA35_MUX(0x2, "UART14_nCTS"),
1402
+
MA35_MUX(0x3, "UART13_RXD"),
1403
+
MA35_MUX(0x4, "I2C5_SDA"),
1404
+
MA35_MUX(0x5, "SPI3_SS0"),
1405
+
MA35_MUX(0x6, "EPWM0_CH4"),
1406
+
MA35_MUX(0x7, "I2S1_LRCK"),
1407
+
MA35_MUX(0x8, "EBI_AD7"),
1408
+
MA35_MUX(0x9, "SC0_CLK"),
1409
+
MA35_MUX(0xb, "TM4"),
1410
+
MA35_MUX(0xc, "ECAP1_IC2"),
1411
+
MA35_MUX(0xd, "INT2")),
1412
+
MA35_PIN(179, PL9, 0xdc, 0x4,
1413
+
MA35_MUX(0x0, "GPL9"),
1414
+
MA35_MUX(0x1, "EPWM0_CH3"),
1415
+
MA35_MUX(0x2, "UART14_nRTS"),
1416
+
MA35_MUX(0x3, "UART13_TXD"),
1417
+
MA35_MUX(0x4, "I2C5_SCL"),
1418
+
MA35_MUX(0x5, "SPI3_CLK"),
1419
+
MA35_MUX(0x6, "EPWM1_CH4"),
1420
+
MA35_MUX(0x7, "I2S1_BCLK"),
1421
+
MA35_MUX(0x8, "EBI_AD8"),
1422
+
MA35_MUX(0x9, "SC0_DAT"),
1423
+
MA35_MUX(0xb, "TM4_EXT"),
1424
+
MA35_MUX(0xc, "QEI0_A"),
1425
+
MA35_MUX(0xd, "INT3")),
1426
+
MA35_PIN(180, PL10, 0xdc, 0x8,
1427
+
MA35_MUX(0x0, "GPL10"),
1428
+
MA35_MUX(0x1, "EPWM0_CH4"),
1429
+
MA35_MUX(0x2, "UART14_RXD"),
1430
+
MA35_MUX(0x3, "CAN3_RXD"),
1431
+
MA35_MUX(0x5, "SPI3_MOSI"),
1432
+
MA35_MUX(0x6, "EPWM0_CH5"),
1433
+
MA35_MUX(0x7, "I2S1_DI"),
1434
+
MA35_MUX(0x8, "EBI_AD9"),
1435
+
MA35_MUX(0x9, "SC0_RST"),
1436
+
MA35_MUX(0xb, "EBI_nWRH"),
1437
+
MA35_MUX(0xc, "QEI0_B")),
1438
+
MA35_PIN(181, PL11, 0xdc, 0xc,
1439
+
MA35_MUX(0x0, "GPL11"),
1440
+
MA35_MUX(0x1, "EPWM0_CH5"),
1441
+
MA35_MUX(0x2, "UART14_TXD"),
1442
+
MA35_MUX(0x3, "CAN3_TXD"),
1443
+
MA35_MUX(0x5, "SPI3_MISO"),
1444
+
MA35_MUX(0x6, "EPWM1_CH5"),
1445
+
MA35_MUX(0x7, "I2S1_DO"),
1446
+
MA35_MUX(0x8, "EBI_AD10"),
1447
+
MA35_MUX(0x9, "SC0_PWR"),
1448
+
MA35_MUX(0xb, "EBI_nWRL"),
1449
+
MA35_MUX(0xc, "QEI0_INDEX")),
1450
+
MA35_PIN(182, PL12, 0xdc, 0x10,
1451
+
MA35_MUX(0x0, "GPL12"),
1452
+
MA35_MUX(0x1, "EPWM0_SYNC_IN"),
1453
+
MA35_MUX(0x2, "UART7_nCTS"),
1454
+
MA35_MUX(0x3, "ECAP1_IC0"),
1455
+
MA35_MUX(0x4, "UART14_RXD"),
1456
+
MA35_MUX(0x5, "SPI0_SS0"),
1457
+
MA35_MUX(0x6, "I2S1_LRCK"),
1458
+
MA35_MUX(0x7, "SC1_CLK"),
1459
+
MA35_MUX(0x8, "EBI_AD0"),
1460
+
MA35_MUX(0x9, "HSUSBH_PWREN"),
1461
+
MA35_MUX(0xa, "I2C2_SDA"),
1462
+
MA35_MUX(0xb, "TM0"),
1463
+
MA35_MUX(0xc, "EPWM0_CH2"),
1464
+
MA35_MUX(0xd, "EBI_AD11"),
1465
+
MA35_MUX(0xe, "RGMII0_PPS"),
1466
+
MA35_MUX(0xf, "RMII0_PPS")),
1467
+
MA35_PIN(183, PL13, 0xdc, 0x14,
1468
+
MA35_MUX(0x0, "GPL13"),
1469
+
MA35_MUX(0x1, "EPWM0_SYNC_OUT"),
1470
+
MA35_MUX(0x2, "UART7_nRTS"),
1471
+
MA35_MUX(0x3, "ECAP1_IC1"),
1472
+
MA35_MUX(0x4, "UART14_TXD"),
1473
+
MA35_MUX(0x5, "SPI0_CLK"),
1474
+
MA35_MUX(0x6, "I2S1_BCLK"),
1475
+
MA35_MUX(0x7, "SC1_DAT"),
1476
+
MA35_MUX(0x8, "EBI_AD1"),
1477
+
MA35_MUX(0x9, "HSUSBH_OVC"),
1478
+
MA35_MUX(0xa, "I2C2_SCL"),
1479
+
MA35_MUX(0xb, "TM0_EXT"),
1480
+
MA35_MUX(0xc, "EPWM0_CH3"),
1481
+
MA35_MUX(0xd, "EBI_AD12"),
1482
+
MA35_MUX(0xe, "RGMII1_PPS"),
1483
+
MA35_MUX(0xf, "RMII1_PPS")),
1484
+
MA35_PIN(184, PL14, 0xdc, 0x18,
1485
+
MA35_MUX(0x0, "GPL14"),
1486
+
MA35_MUX(0x1, "EPWM0_CH2"),
1487
+
MA35_MUX(0x2, "UART7_RXD"),
1488
+
MA35_MUX(0x4, "CAN1_RXD"),
1489
+
MA35_MUX(0x5, "SPI0_MOSI"),
1490
+
MA35_MUX(0x6, "I2S1_DI"),
1491
+
MA35_MUX(0x7, "SC1_RST"),
1492
+
MA35_MUX(0x8, "EBI_AD2"),
1493
+
MA35_MUX(0xb, "TM2"),
1494
+
MA35_MUX(0xc, "INT0"),
1495
+
MA35_MUX(0xd, "EBI_AD13")),
1496
+
MA35_PIN(185, PL15, 0xdc, 0x1c,
1497
+
MA35_MUX(0x0, "GPL15"),
1498
+
MA35_MUX(0x1, "EPWM0_CH1"),
1499
+
MA35_MUX(0x2, "UART7_TXD"),
1500
+
MA35_MUX(0x3, "TRACE_CLK"),
1501
+
MA35_MUX(0x4, "CAN1_TXD"),
1502
+
MA35_MUX(0x5, "SPI0_MISO"),
1503
+
MA35_MUX(0x6, "I2S1_DO"),
1504
+
MA35_MUX(0x7, "SC1_PWR"),
1505
+
MA35_MUX(0x8, "EBI_AD3"),
1506
+
MA35_MUX(0xb, "TM2_EXT"),
1507
+
MA35_MUX(0xc, "INT2"),
1508
+
MA35_MUX(0xd, "EBI_AD14")),
1509
+
MA35_PIN(186, PM0, 0xe0, 0x0,
1510
+
MA35_MUX(0x0, "GPM0"),
1511
+
MA35_MUX(0x4, "I2C4_SDA"),
1512
+
MA35_MUX(0x6, "CCAP0_VSYNC"),
1513
+
MA35_MUX(0x8, "EBI_AD3"),
1514
+
MA35_MUX(0xa, "EBI_ADR3")),
1515
+
MA35_PIN(187, PM1, 0xe0, 0x4,
1516
+
MA35_MUX(0x0, "GPM1"),
1517
+
MA35_MUX(0x4, "I2C4_SCL"),
1518
+
MA35_MUX(0x5, "SPI3_I2SMCLK"),
1519
+
MA35_MUX(0x6, "CCAP0_SFIELD"),
1520
+
MA35_MUX(0x8, "EBI_AD4"),
1521
+
MA35_MUX(0xa, "EBI_ADR4")),
1522
+
MA35_PIN(188, PM2, 0xe0, 0x8,
1523
+
MA35_MUX(0x0, "GPM2"),
1524
+
MA35_MUX(0x3, "CAN3_RXD"),
1525
+
MA35_MUX(0x6, "CCAP0_DATA0"),
1526
+
MA35_MUX(0x8, "EBI_AD5"),
1527
+
MA35_MUX(0xa, "EBI_ADR5")),
1528
+
MA35_PIN(189, PM3, 0xe0, 0xc,
1529
+
MA35_MUX(0x0, "GPM3"),
1530
+
MA35_MUX(0x3, "CAN3_TXD"),
1531
+
MA35_MUX(0x6, "CCAP0_DATA1"),
1532
+
MA35_MUX(0x8, "EBI_AD6"),
1533
+
MA35_MUX(0xa, "EBI_ADR6")),
1534
+
MA35_PIN(190, PM4, 0xe0, 0x10,
1535
+
MA35_MUX(0x0, "GPM4"),
1536
+
MA35_MUX(0x4, "I2C5_SDA"),
1537
+
MA35_MUX(0x6, "CCAP0_DATA2"),
1538
+
MA35_MUX(0x8, "EBI_AD7"),
1539
+
MA35_MUX(0xa, "EBI_ADR7")),
1540
+
MA35_PIN(191, PM5, 0xe0, 0x14,
1541
+
MA35_MUX(0x0, "GPM5"),
1542
+
MA35_MUX(0x4, "I2C5_SCL"),
1543
+
MA35_MUX(0x6, "CCAP0_DATA3"),
1544
+
MA35_MUX(0x8, "EBI_AD8"),
1545
+
MA35_MUX(0xa, "EBI_ADR8")),
1546
+
MA35_PIN(192, PM6, 0xe0, 0x18,
1547
+
MA35_MUX(0x0, "GPM6"),
1548
+
MA35_MUX(0x3, "CAN0_RXD"),
1549
+
MA35_MUX(0x6, "CCAP0_DATA4"),
1550
+
MA35_MUX(0x8, "EBI_AD9"),
1551
+
MA35_MUX(0xa, "EBI_ADR9")),
1552
+
MA35_PIN(193, PM7, 0xe0, 0x1c,
1553
+
MA35_MUX(0x0, "GPM7"),
1554
+
MA35_MUX(0x3, "CAN0_TXD"),
1555
+
MA35_MUX(0x6, "CCAP0_DATA5"),
1556
+
MA35_MUX(0x8, "EBI_AD10"),
1557
+
MA35_MUX(0xa, "EBI_ADR10")),
1558
+
MA35_PIN(194, PM8, 0xe4, 0x0,
1559
+
MA35_MUX(0x0, "GPM8"),
1560
+
MA35_MUX(0x4, "I2C0_SDA"),
1561
+
MA35_MUX(0x6, "CCAP0_DATA6"),
1562
+
MA35_MUX(0x8, "EBI_AD11"),
1563
+
MA35_MUX(0xa, "EBI_ADR11")),
1564
+
MA35_PIN(195, PM9, 0xe4, 0x4,
1565
+
MA35_MUX(0x0, "GPM9"),
1566
+
MA35_MUX(0x4, "I2C0_SCL"),
1567
+
MA35_MUX(0x6, "CCAP0_DATA7"),
1568
+
MA35_MUX(0x8, "EBI_AD12"),
1569
+
MA35_MUX(0xa, "EBI_ADR12")),
1570
+
MA35_PIN(196, PM10, 0xe4, 0x8,
1571
+
MA35_MUX(0x0, "GPM10"),
1572
+
MA35_MUX(0x1, "EPWM1_CH2"),
1573
+
MA35_MUX(0x3, "CAN2_RXD"),
1574
+
MA35_MUX(0x5, "SPI3_SS0"),
1575
+
MA35_MUX(0x6, "CCAP0_DATA8"),
1576
+
MA35_MUX(0x7, "SPI2_I2SMCLK"),
1577
+
MA35_MUX(0x8, "EBI_AD13"),
1578
+
MA35_MUX(0xa, "EBI_ADR13")),
1579
+
MA35_PIN(197, PM11, 0xe4, 0xc,
1580
+
MA35_MUX(0x0, "GPM11"),
1581
+
MA35_MUX(0x1, "EPWM1_CH3"),
1582
+
MA35_MUX(0x3, "CAN2_TXD"),
1583
+
MA35_MUX(0x5, "SPI3_SS1"),
1584
+
MA35_MUX(0x6, "CCAP0_DATA9"),
1585
+
MA35_MUX(0x7, "SPI2_SS1"),
1586
+
MA35_MUX(0x8, "EBI_AD14"),
1587
+
MA35_MUX(0xa, "EBI_ADR14")),
1588
+
MA35_PIN(198, PM12, 0xe4, 0x10,
1589
+
MA35_MUX(0x0, "GPM12"),
1590
+
MA35_MUX(0x1, "EPWM1_CH4"),
1591
+
MA35_MUX(0x2, "UART10_nCTS"),
1592
+
MA35_MUX(0x3, "TRACE_DATA0"),
1593
+
MA35_MUX(0x4, "UART11_RXD"),
1594
+
MA35_MUX(0x5, "I2C2_SDA"),
1595
+
MA35_MUX(0x7, "SC1_nCD"),
1596
+
MA35_MUX(0x8, "EBI_AD8"),
1597
+
MA35_MUX(0x9, "I2S1_MCLK"),
1598
+
MA35_MUX(0xb, "TM8")),
1599
+
MA35_PIN(199, PM13, 0xe4, 0x14,
1600
+
MA35_MUX(0x0, "GPM13"),
1601
+
MA35_MUX(0x1, "EPWM1_CH5"),
1602
+
MA35_MUX(0x2, "UART10_nRTS"),
1603
+
MA35_MUX(0x3, "TRACE_DATA1"),
1604
+
MA35_MUX(0x4, "UART11_TXD"),
1605
+
MA35_MUX(0x5, "I2C2_SCL"),
1606
+
MA35_MUX(0x8, "EBI_AD9"),
1607
+
MA35_MUX(0x9, "ECAP1_IC0"),
1608
+
MA35_MUX(0xb, "TM8_EXT")),
1609
+
MA35_PIN(200, PM14, 0xe4, 0x18,
1610
+
MA35_MUX(0x0, "GPM14"),
1611
+
MA35_MUX(0x1, "EPWM1_BRAKE0"),
1612
+
MA35_MUX(0x2, "UART10_RXD"),
1613
+
MA35_MUX(0x3, "TRACE_DATA2"),
1614
+
MA35_MUX(0x4, "CAN2_RXD"),
1615
+
MA35_MUX(0x6, "I2C3_SDA"),
1616
+
MA35_MUX(0x8, "EBI_AD10"),
1617
+
MA35_MUX(0x9, "ECAP1_IC1"),
1618
+
MA35_MUX(0xb, "TM10"),
1619
+
MA35_MUX(0xd, "INT1")),
1620
+
MA35_PIN(201, PM15, 0xe4, 0x1c,
1621
+
MA35_MUX(0x0, "GPM15"),
1622
+
MA35_MUX(0x1, "EPWM1_BRAKE1"),
1623
+
MA35_MUX(0x2, "UART10_TXD"),
1624
+
MA35_MUX(0x3, "TRACE_DATA3"),
1625
+
MA35_MUX(0x4, "CAN2_TXD"),
1626
+
MA35_MUX(0x6, "I2C3_SCL"),
1627
+
MA35_MUX(0x8, "EBI_AD11"),
1628
+
MA35_MUX(0x9, "ECAP1_IC2"),
1629
+
MA35_MUX(0xb, "TM10_EXT"),
1630
+
MA35_MUX(0xd, "INT2")),
1631
+
MA35_PIN(202, PN0, 0xe8, 0x0,
1632
+
MA35_MUX(0x0, "GPN0"),
1633
+
MA35_MUX(0x4, "I2C2_SDA"),
1634
+
MA35_MUX(0x6, "CCAP1_DATA0")),
1635
+
MA35_PIN(203, PN1, 0xe8, 0x4,
1636
+
MA35_MUX(0x0, "GPN1"),
1637
+
MA35_MUX(0x4, "I2C2_SCL"),
1638
+
MA35_MUX(0x6, "CCAP1_DATA1")),
1639
+
MA35_PIN(204, PN2, 0xe8, 0x8,
1640
+
MA35_MUX(0x0, "GPN2"),
1641
+
MA35_MUX(0x3, "CAN0_RXD"),
1642
+
MA35_MUX(0x6, "CCAP1_DATA2")),
1643
+
MA35_PIN(205, PN3, 0xe8, 0xc,
1644
+
MA35_MUX(0x0, "GPN3"),
1645
+
MA35_MUX(0x3, "CAN0_TXD"),
1646
+
MA35_MUX(0x6, "CCAP1_DATA3")),
1647
+
MA35_PIN(206, PN4, 0xe8, 0x10,
1648
+
MA35_MUX(0x0, "GPN4"),
1649
+
MA35_MUX(0x4, "I2C1_SDA"),
1650
+
MA35_MUX(0x6, "CCAP1_DATA4")),
1651
+
MA35_PIN(207, PN5, 0xe8, 0x14,
1652
+
MA35_MUX(0x0, "GPN5"),
1653
+
MA35_MUX(0x4, "I2C1_SCL"),
1654
+
MA35_MUX(0x6, "CCAP1_DATA5")),
1655
+
MA35_PIN(208, PN6, 0xe8, 0x18,
1656
+
MA35_MUX(0x0, "GPN6"),
1657
+
MA35_MUX(0x3, "CAN1_RXD"),
1658
+
MA35_MUX(0x6, "CCAP1_DATA6")),
1659
+
MA35_PIN(209, PN7, 0xe8, 0x1c,
1660
+
MA35_MUX(0x0, "GPN7"),
1661
+
MA35_MUX(0x3, "CAN1_TXD"),
1662
+
MA35_MUX(0x6, "CCAP1_DATA7")),
1663
+
MA35_PIN(210, PN10, 0xec, 0x8,
1664
+
MA35_MUX(0x0, "GPN10"),
1665
+
MA35_MUX(0x3, "CAN2_RXD"),
1666
+
MA35_MUX(0x6, "CCAP1_SCLK")),
1667
+
MA35_PIN(211, PN11, 0xec, 0xc,
1668
+
MA35_MUX(0x0, "GPN11"),
1669
+
MA35_MUX(0x3, "CAN2_TXD"),
1670
+
MA35_MUX(0x6, "CCAP1_PIXCLK")),
1671
+
MA35_PIN(212, PN12, 0xec, 0x10,
1672
+
MA35_MUX(0x0, "GPN12"),
1673
+
MA35_MUX(0x2, "UART6_nCTS"),
1674
+
MA35_MUX(0x3, "UART12_RXD"),
1675
+
MA35_MUX(0x4, "I2C5_SDA"),
1676
+
MA35_MUX(0x6, "CCAP1_HSYNC")),
1677
+
MA35_PIN(213, PN13, 0xec, 0x14,
1678
+
MA35_MUX(0x0, "GPN13"),
1679
+
MA35_MUX(0x2, "UART6_nRTS"),
1680
+
MA35_MUX(0x3, "UART12_TXD"),
1681
+
MA35_MUX(0x4, "I2C5_SCL"),
1682
+
MA35_MUX(0x6, "CCAP1_VSYNC")),
1683
+
MA35_PIN(214, PN14, 0xec, 0x18,
1684
+
MA35_MUX(0x0, "GPN14"),
1685
+
MA35_MUX(0x2, "UART6_RXD"),
1686
+
MA35_MUX(0x3, "CAN3_RXD"),
1687
+
MA35_MUX(0x5, "SPI1_SS1"),
1688
+
MA35_MUX(0x6, "CCAP1_SFIELD"),
1689
+
MA35_MUX(0x7, "SPI1_I2SMCLK")),
1690
+
MA35_PIN(215, PN15, 0xec, 0x1c,
1691
+
MA35_MUX(0x0, "GPN15"),
1692
+
MA35_MUX(0x1, "EPWM2_CH4"),
1693
+
MA35_MUX(0x2, "UART6_TXD"),
1694
+
MA35_MUX(0x3, "CAN3_TXD"),
1695
+
MA35_MUX(0x5, "I2S0_MCLK"),
1696
+
MA35_MUX(0x6, "SPI1_SS1"),
1697
+
MA35_MUX(0x7, "SPI1_I2SMCLK"),
1698
+
MA35_MUX(0x8, "SC0_nCD"),
1699
+
MA35_MUX(0x9, "EADC0_ST"),
1700
+
MA35_MUX(0xa, "CLKO"),
1701
+
MA35_MUX(0xb, "TM6")),
1702
+
MA35_PIN(216, PN8, 0xec, 0x0,
1703
+
MA35_MUX(0x0, "GPN8"),
1704
+
MA35_MUX(0x1, "EPWM2_CH4"),
1705
+
MA35_MUX(0x4, "I2C0_SDA"),
1706
+
MA35_MUX(0x5, "SPI2_I2SMCLK"),
1707
+
MA35_MUX(0x6, "CCAP1_DATA8")),
1708
+
MA35_PIN(217, PN9, 0xec, 0x4,
1709
+
MA35_MUX(0x0, "GPN9"),
1710
+
MA35_MUX(0x1, "EPWM2_CH5"),
1711
+
MA35_MUX(0x4, "I2C0_SCL"),
1712
+
MA35_MUX(0x5, "SPI1_I2SMCLK"),
1713
+
MA35_MUX(0x6, "CCAP1_DATA9")),
1714
+
MA35_PIN(218, PN10, 0xec, 0x8,
1715
+
MA35_MUX(0x0, "GPN10"),
1716
+
MA35_MUX(0x3, "CAN2_RXD"),
1717
+
MA35_MUX(0x4, "USBHL2_DM"),
1718
+
MA35_MUX(0x6, "CCAP1_SCLK")),
1719
+
MA35_PIN(219, PN11, 0xec, 0xc,
1720
+
MA35_MUX(0x0, "GPN11"),
1721
+
MA35_MUX(0x3, "CAN2_TXD"),
1722
+
MA35_MUX(0x4, "USBHL2_DP"),
1723
+
MA35_MUX(0x6, "CCAP1_PIXCLK")),
1724
+
MA35_PIN(220, PN12, 0xec, 0x10,
1725
+
MA35_MUX(0x0, "GPN12"),
1726
+
MA35_MUX(0x2, "UART6_nCTS"),
1727
+
MA35_MUX(0x3, "UART12_RXD"),
1728
+
MA35_MUX(0x4, "I2C5_SDA"),
1729
+
MA35_MUX(0x6, "CCAP1_HSYNC")),
1730
+
MA35_PIN(221, PN13, 0xec, 0x14,
1731
+
MA35_MUX(0x0, "GPN13"),
1732
+
MA35_MUX(0x2, "UART6_nRTS"),
1733
+
MA35_MUX(0x3, "UART12_TXD"),
1734
+
MA35_MUX(0x4, "I2C5_SCL"),
1735
+
MA35_MUX(0x6, "CCAP1_VSYNC")),
1736
+
MA35_PIN(222, PN14, 0xec, 0x18,
1737
+
MA35_MUX(0x0, "GPN14"),
1738
+
MA35_MUX(0x2, "UART6_RXD"),
1739
+
MA35_MUX(0x3, "CAN3_RXD"),
1740
+
MA35_MUX(0x4, "USBHL3_DM"),
1741
+
MA35_MUX(0x5, "SPI1_SS1"),
1742
+
MA35_MUX(0x6, "CCAP1_SFIELD"),
1743
+
MA35_MUX(0x7, "SPI1_I2SMCLK")),
1744
+
MA35_PIN(223, PN15, 0xec, 0x1c,
1745
+
MA35_MUX(0x0, "GPN15"),
1746
+
MA35_MUX(0x1, "EPWM2_CH4"),
1747
+
MA35_MUX(0x2, "UART6_TXD"),
1748
+
MA35_MUX(0x3, "CAN3_TXD"),
1749
+
MA35_MUX(0x4, "USBHL3_DP"),
1750
+
MA35_MUX(0x5, "I2S0_MCLK"),
1751
+
MA35_MUX(0x6, "SPI1_SS1"),
1752
+
MA35_MUX(0x7, "SPI1_I2SMCLK"),
1753
+
MA35_MUX(0x8, "SC0_nCD"),
1754
+
MA35_MUX(0x9, "EADC0_ST"),
1755
+
MA35_MUX(0xa, "CLKO"),
1756
+
MA35_MUX(0xb, "TM6")),
1757
+
};
1758
+
1759
+
static int ma35d1_get_pin_num(int offset, int shift)
1760
+
{
1761
+
return (offset - 0x80) * 2 + shift / 4;
1762
+
}
1763
+
1764
+
static struct ma35_pinctrl_soc_info ma35d1_pinctrl_info = {
1765
+
.pins = ma35d1_pins,
1766
+
.npins = ARRAY_SIZE(ma35d1_pins),
1767
+
.get_pin_num = ma35d1_get_pin_num,
1768
+
};
1769
+
1770
+
static DEFINE_NOIRQ_DEV_PM_OPS(ma35_pinctrl_pm_ops, ma35_pinctrl_suspend, ma35_pinctrl_resume);
1771
+
1772
+
static int ma35d1_pinctrl_probe(struct platform_device *pdev)
1773
+
{
1774
+
return ma35_pinctrl_probe(pdev, &ma35d1_pinctrl_info);
1775
+
}
1776
+
1777
+
static const struct of_device_id ma35d1_pinctrl_of_match[] = {
1778
+
{ .compatible = "nuvoton,ma35d1-pinctrl" },
1779
+
{ },
1780
+
};
1781
+
1782
+
static struct platform_driver ma35d1_pinctrl_driver = {
1783
+
.probe = ma35d1_pinctrl_probe,
1784
+
.driver = {
1785
+
.name = "ma35d1-pinctrl",
1786
+
.pm = pm_sleep_ptr(&ma35_pinctrl_pm_ops),
1787
+
.of_match_table = ma35d1_pinctrl_of_match,
1788
+
},
1789
+
};
1790
+
1791
+
static int __init ma35d1_pinctrl_init(void)
1792
+
{
1793
+
return platform_driver_register(&ma35d1_pinctrl_driver);
1794
+
}
1795
+
arch_initcall(ma35d1_pinctrl_init);
1796
+
1797
+
MODULE_AUTHOR("schung@nuvoton.com");
1798
+
MODULE_DESCRIPTION("Nuvoton MA35D1 pinctrl driver");
1799
+
MODULE_LICENSE("GPL");
+10
-21
drivers/pinctrl/nxp/pinctrl-s32cc.c
+10
-21
drivers/pinctrl/nxp/pinctrl-s32cc.c
···
268
268
unsigned int *num_maps)
269
269
{
270
270
unsigned int reserved_maps;
271
-
struct device_node *np;
272
-
int ret = 0;
271
+
int ret;
273
272
274
273
reserved_maps = 0;
275
274
*map = NULL;
276
275
*num_maps = 0;
277
276
278
-
for_each_available_child_of_node(np_config, np) {
277
+
for_each_available_child_of_node_scoped(np_config, np) {
279
278
ret = s32_dt_group_node_to_map(pctldev, np, map,
280
279
&reserved_maps, num_maps,
281
280
np_config->name);
282
281
if (ret < 0) {
283
-
of_node_put(np);
284
-
break;
282
+
pinctrl_utils_free_map(pctldev, *map, *num_maps);
283
+
return ret;
285
284
}
286
285
}
287
286
288
-
if (ret)
289
-
pinctrl_utils_free_map(pctldev, *map, *num_maps);
290
-
291
-
return ret;
292
-
287
+
return 0;
293
288
}
294
289
295
290
static const struct pinctrl_ops s32_pctrl_ops = {
···
781
786
struct s32_pinctrl_soc_info *info,
782
787
u32 index)
783
788
{
784
-
struct device_node *child;
785
789
struct pinfunction *func;
786
790
struct s32_pin_group *grp;
787
791
const char **groups;
···
804
810
if (!groups)
805
811
return -ENOMEM;
806
812
807
-
for_each_child_of_node(np, child) {
813
+
for_each_child_of_node_scoped(np, child) {
808
814
groups[i] = child->name;
809
815
grp = &info->groups[info->grp_index++];
810
816
ret = s32_pinctrl_parse_groups(child, grp, info);
811
-
if (ret) {
812
-
of_node_put(child);
817
+
if (ret)
813
818
return ret;
814
-
}
815
819
i++;
816
820
}
817
821
···
823
831
{
824
832
struct s32_pinctrl_soc_info *info = ipctl->info;
825
833
struct device_node *np = pdev->dev.of_node;
826
-
struct device_node *child;
827
834
struct resource *res;
828
835
struct regmap *map;
829
836
void __iomem *base;
···
880
889
return -ENOMEM;
881
890
882
891
info->ngroups = 0;
883
-
for_each_child_of_node(np, child)
892
+
for_each_child_of_node_scoped(np, child)
884
893
info->ngroups += of_get_child_count(child);
885
894
886
895
info->groups = devm_kcalloc(&pdev->dev, info->ngroups,
···
889
898
return -ENOMEM;
890
899
891
900
i = 0;
892
-
for_each_child_of_node(np, child) {
901
+
for_each_child_of_node_scoped(np, child) {
893
902
ret = s32_pinctrl_parse_functions(child, info, i++);
894
-
if (ret) {
895
-
of_node_put(child);
903
+
if (ret)
896
904
return ret;
897
-
}
898
905
}
899
906
900
907
return 0;
+2
-5
drivers/pinctrl/pinconf-generic.c
+2
-5
drivers/pinctrl/pinconf-generic.c
···
382
382
unsigned int *num_maps, enum pinctrl_map_type type)
383
383
{
384
384
unsigned int reserved_maps;
385
-
struct device_node *np;
386
385
int ret;
387
386
388
387
reserved_maps = 0;
···
393
394
if (ret < 0)
394
395
goto exit;
395
396
396
-
for_each_available_child_of_node(np_config, np) {
397
+
for_each_available_child_of_node_scoped(np_config, np) {
397
398
ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map,
398
399
&reserved_maps, num_maps, type);
399
-
if (ret < 0) {
400
-
of_node_put(np);
400
+
if (ret < 0)
401
401
goto exit;
402
-
}
403
402
}
404
403
return 0;
405
404
+2
-5
drivers/pinctrl/pinctrl-at91-pio4.c
+2
-5
drivers/pinctrl/pinctrl-at91-pio4.c
···
632
632
struct pinctrl_map **map,
633
633
unsigned int *num_maps)
634
634
{
635
-
struct device_node *np;
636
635
unsigned int reserved_maps;
637
636
int ret;
638
637
···
647
648
ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
648
649
&reserved_maps, num_maps);
649
650
if (ret) {
650
-
for_each_child_of_node(np_config, np) {
651
+
for_each_child_of_node_scoped(np_config, np) {
651
652
ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
652
653
&reserved_maps, num_maps);
653
-
if (ret < 0) {
654
-
of_node_put(np);
654
+
if (ret < 0)
655
655
break;
656
-
}
657
656
}
658
657
}
659
658
+4
-10
drivers/pinctrl/pinctrl-at91.c
+4
-10
drivers/pinctrl/pinctrl-at91.c
···
1244
1244
static int at91_pinctrl_parse_functions(struct device_node *np,
1245
1245
struct at91_pinctrl *info, u32 index)
1246
1246
{
1247
-
struct device_node *child;
1248
1247
struct at91_pmx_func *func;
1249
1248
struct at91_pin_group *grp;
1250
1249
int ret;
···
1266
1267
if (!func->groups)
1267
1268
return -ENOMEM;
1268
1269
1269
-
for_each_child_of_node(np, child) {
1270
+
for_each_child_of_node_scoped(np, child) {
1270
1271
func->groups[i] = child->name;
1271
1272
grp = &info->groups[grp_index++];
1272
1273
ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1273
-
if (ret) {
1274
-
of_node_put(child);
1274
+
if (ret)
1275
1275
return ret;
1276
-
}
1277
1276
}
1278
1277
1279
1278
return 0;
···
1293
1296
int i, j, ngpio_chips_enabled = 0;
1294
1297
uint32_t *tmp;
1295
1298
struct device_node *np = dev->of_node;
1296
-
struct device_node *child;
1297
1299
1298
1300
if (!np)
1299
1301
return -ENODEV;
···
1345
1349
1346
1350
i = 0;
1347
1351
1348
-
for_each_child_of_node(np, child) {
1352
+
for_each_child_of_node_scoped(np, child) {
1349
1353
if (of_device_is_compatible(child, gpio_compat))
1350
1354
continue;
1351
1355
ret = at91_pinctrl_parse_functions(child, info, i++);
1352
-
if (ret) {
1353
-
of_node_put(child);
1356
+
if (ret)
1354
1357
return dev_err_probe(dev, ret, "failed to parse function\n");
1355
-
}
1356
1358
}
1357
1359
1358
1360
return 0;
+66
-146
drivers/pinctrl/pinctrl-cy8c95x0.c
+66
-146
drivers/pinctrl/pinctrl-cy8c95x0.c
···
9
9
10
10
#include <linux/acpi.h>
11
11
#include <linux/bitmap.h>
12
+
#include <linux/cleanup.h>
12
13
#include <linux/dmi.h>
13
14
#include <linux/gpio/driver.h>
14
15
#include <linux/gpio/consumer.h>
···
59
58
60
59
#define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x))
61
60
62
-
#define CY8C95X0_MUX_REGMAP_TO_PORT(x) ((x) / MUXED_STRIDE)
63
-
#define CY8C95X0_MUX_REGMAP_TO_REG(x) (((x) % MUXED_STRIDE) + CY8C95X0_INTMASK)
64
-
#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) ((x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE)
61
+
#define MAX_BANK 8
62
+
#define BANK_SZ 8
63
+
#define MAX_LINE (MAX_BANK * BANK_SZ)
64
+
#define MUXED_STRIDE (CY8C95X0_DRV_HIZ - CY8C95X0_INTMASK)
65
+
#define CY8C95X0_GPIO_MASK GENMASK(7, 0)
66
+
#define CY8C95X0_VIRTUAL (CY8C95X0_COMMAND + 1)
67
+
#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \
68
+
(CY8C95X0_VIRTUAL + (x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE)
65
69
66
70
static const struct i2c_device_id cy8c95x0_id[] = {
67
71
{ "cy8c9520", 20, },
···
126
120
{}
127
121
};
128
122
129
-
#define MAX_BANK 8
130
-
#define BANK_SZ 8
131
-
#define MAX_LINE (MAX_BANK * BANK_SZ)
132
-
#define MUXED_STRIDE 16
133
-
#define CY8C95X0_GPIO_MASK GENMASK(7, 0)
134
-
135
123
/**
136
124
* struct cy8c95x0_pinctrl - driver data
137
125
* @regmap: Device's regmap. Only direct access registers.
138
-
* @muxed_regmap: Regmap for all muxed registers.
139
126
* @irq_lock: IRQ bus lock
140
-
* @i2c_lock: Mutex for the device internal mux register
127
+
* @i2c_lock: Mutex to hold while using the regmap
141
128
* @irq_mask: I/O bits affected by interrupts
142
129
* @irq_trig_raise: I/O bits affected by raising voltage level
143
130
* @irq_trig_fall: I/O bits affected by falling voltage level
···
151
152
*/
152
153
struct cy8c95x0_pinctrl {
153
154
struct regmap *regmap;
154
-
struct regmap *muxed_regmap;
155
155
struct mutex irq_lock;
156
156
struct mutex i2c_lock;
157
157
DECLARE_BITMAP(irq_mask, MAX_LINE);
···
329
331
330
332
static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
331
333
{
334
+
if (reg >= CY8C95X0_VIRTUAL)
335
+
return true;
336
+
332
337
switch (reg) {
333
338
case 0x24 ... 0x27:
334
339
return false;
···
342
341
343
342
static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg)
344
343
{
344
+
if (reg >= CY8C95X0_VIRTUAL)
345
+
return true;
346
+
345
347
switch (reg) {
346
348
case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7):
347
349
return false;
···
437
433
}
438
434
}
439
435
440
-
static const struct reg_default cy8c95x0_reg_defaults[] = {
441
-
{ CY8C95X0_OUTPUT_(0), GENMASK(7, 0) },
442
-
{ CY8C95X0_OUTPUT_(1), GENMASK(7, 0) },
443
-
{ CY8C95X0_OUTPUT_(2), GENMASK(7, 0) },
444
-
{ CY8C95X0_OUTPUT_(3), GENMASK(7, 0) },
445
-
{ CY8C95X0_OUTPUT_(4), GENMASK(7, 0) },
446
-
{ CY8C95X0_OUTPUT_(5), GENMASK(7, 0) },
447
-
{ CY8C95X0_OUTPUT_(6), GENMASK(7, 0) },
448
-
{ CY8C95X0_OUTPUT_(7), GENMASK(7, 0) },
449
-
{ CY8C95X0_PORTSEL, 0 },
450
-
{ CY8C95X0_PWMSEL, 0 },
436
+
static const struct regmap_range_cfg cy8c95x0_ranges[] = {
437
+
{
438
+
.range_min = CY8C95X0_VIRTUAL,
439
+
.range_max = 0, /* Updated at runtime */
440
+
.selector_reg = CY8C95X0_PORTSEL,
441
+
.selector_mask = 0x07,
442
+
.selector_shift = 0x0,
443
+
.window_start = CY8C95X0_INTMASK,
444
+
.window_len = MUXED_STRIDE,
445
+
}
451
446
};
452
447
453
-
static int
454
-
cy8c95x0_mux_reg_read(void *context, unsigned int off, unsigned int *val)
455
-
{
456
-
struct cy8c95x0_pinctrl *chip = context;
457
-
u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
458
-
int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
459
-
460
-
mutex_lock(&chip->i2c_lock);
461
-
/* Select the correct bank */
462
-
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
463
-
if (ret < 0)
464
-
goto out;
465
-
466
-
/*
467
-
* Read the register through direct access regmap. The target range
468
-
* is marked volatile.
469
-
*/
470
-
ret = regmap_read(chip->regmap, reg, val);
471
-
out:
472
-
mutex_unlock(&chip->i2c_lock);
473
-
474
-
return ret;
475
-
}
476
-
477
-
static int
478
-
cy8c95x0_mux_reg_write(void *context, unsigned int off, unsigned int val)
479
-
{
480
-
struct cy8c95x0_pinctrl *chip = context;
481
-
u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
482
-
int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
483
-
484
-
mutex_lock(&chip->i2c_lock);
485
-
/* Select the correct bank */
486
-
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
487
-
if (ret < 0)
488
-
goto out;
489
-
490
-
/*
491
-
* Write the register through direct access regmap. The target range
492
-
* is marked volatile.
493
-
*/
494
-
ret = regmap_write(chip->regmap, reg, val);
495
-
out:
496
-
mutex_unlock(&chip->i2c_lock);
497
-
498
-
return ret;
499
-
}
500
-
501
-
static bool cy8c95x0_mux_accessible_register(struct device *dev, unsigned int off)
502
-
{
503
-
struct i2c_client *i2c = to_i2c_client(dev);
504
-
struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(i2c);
505
-
u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
506
-
u8 reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
507
-
508
-
if (port >= chip->nport)
509
-
return false;
510
-
511
-
return cy8c95x0_muxed_register(reg);
512
-
}
513
-
514
-
static struct regmap_bus cy8c95x0_regmap_bus = {
515
-
.reg_read = cy8c95x0_mux_reg_read,
516
-
.reg_write = cy8c95x0_mux_reg_write,
517
-
};
518
-
519
-
/* Regmap for muxed registers CY8C95X0_INTMASK - CY8C95X0_DRV_HIZ */
520
-
static const struct regmap_config cy8c95x0_muxed_regmap = {
521
-
.name = "muxed",
448
+
static const struct regmap_config cy8c9520_i2c_regmap = {
522
449
.reg_bits = 8,
523
450
.val_bits = 8,
524
-
.cache_type = REGCACHE_FLAT,
525
-
.use_single_read = true,
526
-
.use_single_write = true,
527
-
.max_register = MUXED_STRIDE * BANK_SZ,
528
-
.num_reg_defaults_raw = MUXED_STRIDE * BANK_SZ,
529
-
.readable_reg = cy8c95x0_mux_accessible_register,
530
-
.writeable_reg = cy8c95x0_mux_accessible_register,
531
-
};
532
-
533
-
/* Direct access regmap */
534
-
static const struct regmap_config cy8c95x0_i2c_regmap = {
535
-
.name = "direct",
536
-
.reg_bits = 8,
537
-
.val_bits = 8,
538
-
539
-
.reg_defaults = cy8c95x0_reg_defaults,
540
-
.num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults),
541
451
542
452
.readable_reg = cy8c95x0_readable_register,
543
453
.writeable_reg = cy8c95x0_writeable_register,
544
454
.volatile_reg = cy8c95x0_volatile_register,
545
455
.precious_reg = cy8c95x0_precious_register,
546
456
547
-
.cache_type = REGCACHE_FLAT,
548
-
.max_register = CY8C95X0_COMMAND,
457
+
.cache_type = REGCACHE_MAPLE,
458
+
.ranges = NULL, /* Updated at runtime */
459
+
.num_ranges = 1,
460
+
.max_register = 0, /* Updated at runtime */
461
+
.num_reg_defaults_raw = 0, /* Updated at runtime */
462
+
.use_single_read = true, /* Workaround for regcache bug */
463
+
.disable_locking = true,
549
464
};
550
465
551
466
static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip,
···
475
552
bool *change, bool async,
476
553
bool force)
477
554
{
478
-
struct regmap *regmap;
479
-
int ret, off, i, read_val;
555
+
int ret, off, i;
480
556
481
557
/* Caller should never modify PORTSEL directly */
482
558
if (reg == CY8C95X0_PORTSEL)
483
559
return -EINVAL;
484
560
485
-
/* Registers behind the PORTSEL mux have their own regmap */
561
+
/* Registers behind the PORTSEL mux have their own range in regmap */
486
562
if (cy8c95x0_muxed_register(reg)) {
487
-
regmap = chip->muxed_regmap;
488
563
off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
489
564
} else {
490
-
regmap = chip->regmap;
491
565
/* Quick path direct access registers honor the port argument */
492
566
if (cy8c95x0_quick_path_register(reg))
493
567
off = reg + port;
494
568
else
495
569
off = reg;
496
570
}
571
+
guard(mutex)(&chip->i2c_lock);
497
572
498
-
ret = regmap_update_bits_base(regmap, off, mask, val, change, async, force);
573
+
ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force);
499
574
if (ret < 0)
500
575
return ret;
501
576
502
-
/* Update the cache when a WC bit is written */
577
+
/* Mimic what hardware does and update the cache when a WC bit is written.
578
+
* Allows to mark the registers as non-volatile and reduces I/O cycles.
579
+
*/
503
580
if (cy8c95x0_wc_register(reg) && (mask & val)) {
581
+
/* Writing a 1 clears set bits in the other drive mode registers */
582
+
regcache_cache_only(chip->regmap, true);
504
583
for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) {
505
584
if (i == reg)
506
585
continue;
586
+
507
587
off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port);
508
-
509
-
ret = regmap_read(regmap, off, &read_val);
510
-
if (ret < 0)
511
-
continue;
512
-
513
-
if (!(read_val & mask & val))
514
-
continue;
515
-
516
-
regcache_cache_only(regmap, true);
517
-
regmap_update_bits(regmap, off, mask & val, 0);
518
-
regcache_cache_only(regmap, false);
588
+
regmap_clear_bits(chip->regmap, off, mask & val);
519
589
}
590
+
regcache_cache_only(chip->regmap, false);
520
591
}
521
592
522
593
return ret;
···
583
666
static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg,
584
667
unsigned int port, unsigned int *read_val)
585
668
{
586
-
struct regmap *regmap;
587
-
int off;
669
+
int off, ret;
588
670
589
-
/* Registers behind the PORTSEL mux have their own regmap */
671
+
/* Registers behind the PORTSEL mux have their own range in regmap */
590
672
if (cy8c95x0_muxed_register(reg)) {
591
-
regmap = chip->muxed_regmap;
592
673
off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port);
593
674
} else {
594
-
regmap = chip->regmap;
595
675
/* Quick path direct access registers honor the port argument */
596
676
if (cy8c95x0_quick_path_register(reg))
597
677
off = reg + port;
598
678
else
599
679
off = reg;
600
680
}
681
+
guard(mutex)(&chip->i2c_lock);
601
682
602
-
return regmap_read(regmap, off, read_val);
683
+
ret = regmap_read(chip->regmap, off, read_val);
684
+
685
+
return ret;
603
686
}
604
687
605
688
static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
···
1428
1511
static int cy8c95x0_probe(struct i2c_client *client)
1429
1512
{
1430
1513
struct cy8c95x0_pinctrl *chip;
1514
+
struct regmap_config regmap_conf;
1515
+
struct regmap_range_cfg regmap_range_conf;
1431
1516
struct regulator *reg;
1432
1517
int ret;
1433
1518
···
1449
1530
chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
1450
1531
chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
1451
1532
1533
+
memcpy(®map_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf));
1534
+
1452
1535
switch (chip->tpin) {
1453
1536
case 20:
1454
1537
strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE);
1538
+
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE;
1455
1539
break;
1456
1540
case 40:
1457
1541
strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE);
1542
+
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE;
1458
1543
break;
1459
1544
case 60:
1460
1545
strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE);
1546
+
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE;
1461
1547
break;
1462
1548
default:
1463
1549
return -ENODEV;
···
1495
1571
gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET");
1496
1572
}
1497
1573
1498
-
/* Generic regmap for direct access registers */
1499
-
chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap);
1574
+
/* Regmap for direct and paged registers */
1575
+
memcpy(®map_conf, &cy8c9520_i2c_regmap, sizeof(regmap_conf));
1576
+
regmap_conf.ranges = ®map_range_conf;
1577
+
regmap_conf.max_register = regmap_range_conf.range_max;
1578
+
regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max;
1579
+
1580
+
chip->regmap = devm_regmap_init_i2c(client, ®map_conf);
1500
1581
if (IS_ERR(chip->regmap)) {
1501
1582
ret = PTR_ERR(chip->regmap);
1502
-
goto err_exit;
1503
-
}
1504
-
1505
-
/* Port specific regmap behind PORTSEL mux */
1506
-
chip->muxed_regmap = devm_regmap_init(&client->dev, &cy8c95x0_regmap_bus,
1507
-
chip, &cy8c95x0_muxed_regmap);
1508
-
if (IS_ERR(chip->muxed_regmap)) {
1509
-
ret = dev_err_probe(&client->dev, PTR_ERR(chip->muxed_regmap),
1510
-
"Failed to register muxed regmap\n");
1511
1583
goto err_exit;
1512
1584
}
1513
1585
+18
-27
drivers/pinctrl/pinctrl-equilibrium.c
+18
-27
drivers/pinctrl/pinctrl-equilibrium.c
···
566
566
.pin_config_config_dbg_show = pinconf_generic_dump_config,
567
567
};
568
568
569
-
static bool is_func_exist(struct eqbr_pmx_func *funcs, const char *name,
570
-
unsigned int nr_funcs, unsigned int *idx)
569
+
static bool is_func_exist(struct pinfunction *funcs, const char *name,
570
+
unsigned int nr_funcs, unsigned int *idx)
571
571
{
572
572
int i;
573
573
···
584
584
return false;
585
585
}
586
586
587
-
static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs,
587
+
static int funcs_utils(struct device *dev, struct pinfunction *funcs,
588
588
unsigned int *nr_funcs, funcs_util_ops op)
589
589
{
590
590
struct device_node *node = dev->of_node;
591
-
struct device_node *np;
592
591
struct property *prop;
593
592
const char *fn_name;
593
+
const char **groups;
594
594
unsigned int fid;
595
595
int i, j;
596
596
597
597
i = 0;
598
-
for_each_child_of_node(node, np) {
598
+
for_each_child_of_node_scoped(node, np) {
599
599
prop = of_find_property(np, "groups", NULL);
600
600
if (!prop)
601
601
continue;
···
620
620
621
621
case OP_COUNT_NR_FUNC_GRPS:
622
622
if (is_func_exist(funcs, fn_name, *nr_funcs, &fid))
623
-
funcs[fid].nr_groups++;
623
+
funcs[fid].ngroups++;
624
624
break;
625
625
626
626
case OP_ADD_FUNC_GRPS:
627
627
if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) {
628
-
for (j = 0; j < funcs[fid].nr_groups; j++)
629
-
if (!funcs[fid].groups[j])
628
+
groups = (const char **)funcs[fid].groups;
629
+
for (j = 0; j < funcs[fid].ngroups; j++)
630
+
if (!groups[j])
630
631
break;
631
-
funcs[fid].groups[j] = prop->value;
632
+
groups[j] = prop->value;
632
633
}
633
634
break;
634
635
635
636
default:
636
-
of_node_put(np);
637
637
return -EINVAL;
638
638
}
639
639
i++;
···
645
645
static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata)
646
646
{
647
647
struct device *dev = drvdata->dev;
648
-
struct eqbr_pmx_func *funcs = NULL;
648
+
struct pinfunction *funcs = NULL;
649
649
unsigned int nr_funcs = 0;
650
650
int i, ret;
651
651
···
666
666
return ret;
667
667
668
668
for (i = 0; i < nr_funcs; i++) {
669
-
if (!funcs[i].nr_groups)
669
+
if (!funcs[i].ngroups)
670
670
continue;
671
-
funcs[i].groups = devm_kcalloc(dev, funcs[i].nr_groups,
671
+
funcs[i].groups = devm_kcalloc(dev, funcs[i].ngroups,
672
672
sizeof(*(funcs[i].groups)),
673
673
GFP_KERNEL);
674
674
if (!funcs[i].groups)
···
688
688
ret = pinmux_generic_add_function(drvdata->pctl_dev,
689
689
funcs[i].name,
690
690
funcs[i].groups,
691
-
funcs[i].nr_groups,
691
+
funcs[i].ngroups,
692
692
drvdata);
693
693
if (ret < 0) {
694
694
dev_err(dev, "Failed to register function %s\n",
···
706
706
struct device_node *node = dev->of_node;
707
707
unsigned int *pins, *pinmux, pin_id, pinmux_id;
708
708
struct pingroup group, *grp = &group;
709
-
struct device_node *np;
710
709
struct property *prop;
711
710
int j, err;
712
711
713
-
for_each_child_of_node(node, np) {
712
+
for_each_child_of_node_scoped(node, np) {
714
713
prop = of_find_property(np, "groups", NULL);
715
714
if (!prop)
716
715
continue;
···
717
718
err = of_property_count_u32_elems(np, "pins");
718
719
if (err < 0) {
719
720
dev_err(dev, "No pins in the group: %s\n", prop->name);
720
-
of_node_put(np);
721
721
return err;
722
722
}
723
723
grp->npins = err;
724
724
grp->name = prop->value;
725
725
pins = devm_kcalloc(dev, grp->npins, sizeof(*pins), GFP_KERNEL);
726
-
if (!pins) {
727
-
of_node_put(np);
726
+
if (!pins)
728
727
return -ENOMEM;
729
-
}
728
+
730
729
grp->pins = pins;
731
730
732
731
pinmux = devm_kcalloc(dev, grp->npins, sizeof(*pinmux), GFP_KERNEL);
733
-
if (!pinmux) {
734
-
of_node_put(np);
732
+
if (!pinmux)
735
733
return -ENOMEM;
736
-
}
737
734
738
735
for (j = 0; j < grp->npins; j++) {
739
736
if (of_property_read_u32_index(np, "pins", j, &pin_id)) {
740
737
dev_err(dev, "Group %s: Read intel pins id failed\n",
741
738
grp->name);
742
-
of_node_put(np);
743
739
return -EINVAL;
744
740
}
745
741
if (pin_id >= drvdata->pctl_desc.npins) {
746
742
dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",
747
743
grp->name, j, pin_id);
748
-
of_node_put(np);
749
744
return -EINVAL;
750
745
}
751
746
pins[j] = pin_id;
752
747
if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
753
748
dev_err(dev, "Group %s: Read intel pinmux id failed\n",
754
749
grp->name);
755
-
of_node_put(np);
756
750
return -EINVAL;
757
751
}
758
752
pinmux[j] = pinmux_id;
···
756
764
pinmux);
757
765
if (err < 0) {
758
766
dev_err(dev, "Failed to register group %s\n", grp->name);
759
-
of_node_put(np);
760
767
return err;
761
768
}
762
769
memset(&group, 0, sizeof(group));
-12
drivers/pinctrl/pinctrl-equilibrium.h
-12
drivers/pinctrl/pinctrl-equilibrium.h
···
68
68
};
69
69
70
70
/**
71
-
* struct eqbr_pmx_func: represent a pin function.
72
-
* @name: name of the pin function, used to lookup the function.
73
-
* @groups: one or more names of pin groups that provide this function.
74
-
* @nr_groups: number of groups included in @groups.
75
-
*/
76
-
struct eqbr_pmx_func {
77
-
const char *name;
78
-
const char **groups;
79
-
unsigned int nr_groups;
80
-
};
81
-
82
-
/**
83
71
* struct eqbr_pin_bank: represent a pin bank.
84
72
* @membase: base address of the pin bank register.
85
73
* @id: bank id, to idenify the unique bank.
+356
-351
drivers/pinctrl/pinctrl-ingenic.c
+356
-351
drivers/pinctrl/pinctrl-ingenic.c
···
94
94
.data = (void *)func, \
95
95
}
96
96
97
+
#define INGENIC_PIN_FUNCTION(_name_, id) \
98
+
{ \
99
+
.func = PINCTRL_PINFUNCTION(_name_, id##_groups, ARRAY_SIZE(id##_groups)), \
100
+
.data = NULL, \
101
+
}
102
+
97
103
enum jz_version {
98
104
ID_JZ4730,
99
105
ID_JZ4740,
···
244
238
static const char *jz4730_pwm1_groups[] = { "pwm1", };
245
239
246
240
static const struct function_desc jz4730_functions[] = {
247
-
{ "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), },
248
-
{ "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), },
249
-
{ "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), },
250
-
{ "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), },
251
-
{ "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), },
252
-
{ "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), },
253
-
{ "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), },
254
-
{ "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), },
255
-
{ "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), },
241
+
INGENIC_PIN_FUNCTION("mmc", jz4730_mmc),
242
+
INGENIC_PIN_FUNCTION("uart0", jz4730_uart0),
243
+
INGENIC_PIN_FUNCTION("uart1", jz4730_uart1),
244
+
INGENIC_PIN_FUNCTION("uart2", jz4730_uart2),
245
+
INGENIC_PIN_FUNCTION("uart3", jz4730_uart3),
246
+
INGENIC_PIN_FUNCTION("lcd", jz4730_lcd),
247
+
INGENIC_PIN_FUNCTION("nand", jz4730_nand),
248
+
INGENIC_PIN_FUNCTION("pwm0", jz4730_pwm0),
249
+
INGENIC_PIN_FUNCTION("pwm1", jz4730_pwm1),
256
250
};
257
251
258
252
static const struct ingenic_chip_info jz4730_chip_info = {
···
349
343
static const char *jz4740_pwm7_groups[] = { "pwm7", };
350
344
351
345
static const struct function_desc jz4740_functions[] = {
352
-
{ "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
353
-
{ "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
354
-
{ "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
355
-
{ "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
356
-
{ "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
357
-
{ "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
358
-
{ "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
359
-
{ "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
360
-
{ "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
361
-
{ "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
362
-
{ "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
363
-
{ "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
364
-
{ "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
346
+
INGENIC_PIN_FUNCTION("mmc", jz4740_mmc),
347
+
INGENIC_PIN_FUNCTION("uart0", jz4740_uart0),
348
+
INGENIC_PIN_FUNCTION("uart1", jz4740_uart1),
349
+
INGENIC_PIN_FUNCTION("lcd", jz4740_lcd),
350
+
INGENIC_PIN_FUNCTION("nand", jz4740_nand),
351
+
INGENIC_PIN_FUNCTION("pwm0", jz4740_pwm0),
352
+
INGENIC_PIN_FUNCTION("pwm1", jz4740_pwm1),
353
+
INGENIC_PIN_FUNCTION("pwm2", jz4740_pwm2),
354
+
INGENIC_PIN_FUNCTION("pwm3", jz4740_pwm3),
355
+
INGENIC_PIN_FUNCTION("pwm4", jz4740_pwm4),
356
+
INGENIC_PIN_FUNCTION("pwm5", jz4740_pwm5),
357
+
INGENIC_PIN_FUNCTION("pwm6", jz4740_pwm6),
358
+
INGENIC_PIN_FUNCTION("pwm7", jz4740_pwm7),
365
359
};
366
360
367
361
static const struct ingenic_chip_info jz4740_chip_info = {
···
453
447
static const char *jz4725b_pwm5_groups[] = { "pwm5", };
454
448
455
449
static const struct function_desc jz4725b_functions[] = {
456
-
{ "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
457
-
{ "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
458
-
{ "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
459
-
{ "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
460
-
{ "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
461
-
{ "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
462
-
{ "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
463
-
{ "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
464
-
{ "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
465
-
{ "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
466
-
{ "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
450
+
INGENIC_PIN_FUNCTION("mmc0", jz4725b_mmc0),
451
+
INGENIC_PIN_FUNCTION("mmc1", jz4725b_mmc1),
452
+
INGENIC_PIN_FUNCTION("uart", jz4725b_uart),
453
+
INGENIC_PIN_FUNCTION("nand", jz4725b_nand),
454
+
INGENIC_PIN_FUNCTION("pwm0", jz4725b_pwm0),
455
+
INGENIC_PIN_FUNCTION("pwm1", jz4725b_pwm1),
456
+
INGENIC_PIN_FUNCTION("pwm2", jz4725b_pwm2),
457
+
INGENIC_PIN_FUNCTION("pwm3", jz4725b_pwm3),
458
+
INGENIC_PIN_FUNCTION("pwm4", jz4725b_pwm4),
459
+
INGENIC_PIN_FUNCTION("pwm5", jz4725b_pwm5),
460
+
INGENIC_PIN_FUNCTION("lcd", jz4725b_lcd),
467
461
};
468
462
469
463
static const struct ingenic_chip_info jz4725b_chip_info = {
···
585
579
static const char *jz4750_pwm5_groups[] = { "pwm5", };
586
580
587
581
static const struct function_desc jz4750_functions[] = {
588
-
{ "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), },
589
-
{ "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), },
590
-
{ "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), },
591
-
{ "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), },
592
-
{ "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), },
593
-
{ "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), },
594
-
{ "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), },
595
-
{ "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), },
596
-
{ "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), },
597
-
{ "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), },
598
-
{ "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), },
599
-
{ "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), },
600
-
{ "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), },
601
-
{ "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), },
602
-
{ "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), },
603
-
{ "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), },
582
+
INGENIC_PIN_FUNCTION("uart0", jz4750_uart0),
583
+
INGENIC_PIN_FUNCTION("uart1", jz4750_uart1),
584
+
INGENIC_PIN_FUNCTION("uart2", jz4750_uart2),
585
+
INGENIC_PIN_FUNCTION("uart3", jz4750_uart3),
586
+
INGENIC_PIN_FUNCTION("mmc0", jz4750_mmc0),
587
+
INGENIC_PIN_FUNCTION("mmc1", jz4750_mmc1),
588
+
INGENIC_PIN_FUNCTION("i2c", jz4750_i2c),
589
+
INGENIC_PIN_FUNCTION("cim", jz4750_cim),
590
+
INGENIC_PIN_FUNCTION("lcd", jz4750_lcd),
591
+
INGENIC_PIN_FUNCTION("nand", jz4750_nand),
592
+
INGENIC_PIN_FUNCTION("pwm0", jz4750_pwm0),
593
+
INGENIC_PIN_FUNCTION("pwm1", jz4750_pwm1),
594
+
INGENIC_PIN_FUNCTION("pwm2", jz4750_pwm2),
595
+
INGENIC_PIN_FUNCTION("pwm3", jz4750_pwm3),
596
+
INGENIC_PIN_FUNCTION("pwm4", jz4750_pwm4),
597
+
INGENIC_PIN_FUNCTION("pwm5", jz4750_pwm5),
604
598
};
605
599
606
600
static const struct ingenic_chip_info jz4750_chip_info = {
···
750
744
static const char *jz4755_pwm5_groups[] = { "pwm5", };
751
745
752
746
static const struct function_desc jz4755_functions[] = {
753
-
{ "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), },
754
-
{ "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), },
755
-
{ "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), },
756
-
{ "ssi", jz4755_ssi_groups, ARRAY_SIZE(jz4755_ssi_groups), },
757
-
{ "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), },
758
-
{ "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), },
759
-
{ "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), },
760
-
{ "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), },
761
-
{ "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), },
762
-
{ "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), },
763
-
{ "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), },
764
-
{ "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), },
765
-
{ "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), },
766
-
{ "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), },
767
-
{ "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), },
768
-
{ "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), },
747
+
INGENIC_PIN_FUNCTION("uart0", jz4755_uart0),
748
+
INGENIC_PIN_FUNCTION("uart1", jz4755_uart1),
749
+
INGENIC_PIN_FUNCTION("uart2", jz4755_uart2),
750
+
INGENIC_PIN_FUNCTION("ssi", jz4755_ssi),
751
+
INGENIC_PIN_FUNCTION("mmc0", jz4755_mmc0),
752
+
INGENIC_PIN_FUNCTION("mmc1", jz4755_mmc1),
753
+
INGENIC_PIN_FUNCTION("i2c", jz4755_i2c),
754
+
INGENIC_PIN_FUNCTION("cim", jz4755_cim),
755
+
INGENIC_PIN_FUNCTION("lcd", jz4755_lcd),
756
+
INGENIC_PIN_FUNCTION("nand", jz4755_nand),
757
+
INGENIC_PIN_FUNCTION("pwm0", jz4755_pwm0),
758
+
INGENIC_PIN_FUNCTION("pwm1", jz4755_pwm1),
759
+
INGENIC_PIN_FUNCTION("pwm2", jz4755_pwm2),
760
+
INGENIC_PIN_FUNCTION("pwm3", jz4755_pwm3),
761
+
INGENIC_PIN_FUNCTION("pwm4", jz4755_pwm4),
762
+
INGENIC_PIN_FUNCTION("pwm5", jz4755_pwm5),
769
763
};
770
764
771
765
static const struct ingenic_chip_info jz4755_chip_info = {
···
1085
1079
static const char *jz4760_otg_groups[] = { "otg-vbus", };
1086
1080
1087
1081
static const struct function_desc jz4760_functions[] = {
1088
-
{ "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
1089
-
{ "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
1090
-
{ "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
1091
-
{ "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
1092
-
{ "ssi0", jz4760_ssi0_groups, ARRAY_SIZE(jz4760_ssi0_groups), },
1093
-
{ "ssi1", jz4760_ssi1_groups, ARRAY_SIZE(jz4760_ssi1_groups), },
1094
-
{ "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
1095
-
{ "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
1096
-
{ "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
1097
-
{ "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
1098
-
{ "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
1099
-
{ "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
1100
-
{ "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
1101
-
{ "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
1102
-
{ "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
1103
-
{ "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
1104
-
{ "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
1105
-
{ "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
1106
-
{ "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
1107
-
{ "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
1108
-
{ "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
1109
-
{ "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
1110
-
{ "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
1111
-
{ "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
1112
-
{ "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
1113
-
{ "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
1114
-
{ "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
1115
-
{ "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
1116
-
{ "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
1082
+
INGENIC_PIN_FUNCTION("uart0", jz4760_uart0),
1083
+
INGENIC_PIN_FUNCTION("uart1", jz4760_uart1),
1084
+
INGENIC_PIN_FUNCTION("uart2", jz4760_uart2),
1085
+
INGENIC_PIN_FUNCTION("uart3", jz4760_uart3),
1086
+
INGENIC_PIN_FUNCTION("ssi0", jz4760_ssi0),
1087
+
INGENIC_PIN_FUNCTION("ssi1", jz4760_ssi1),
1088
+
INGENIC_PIN_FUNCTION("mmc0", jz4760_mmc0),
1089
+
INGENIC_PIN_FUNCTION("mmc1", jz4760_mmc1),
1090
+
INGENIC_PIN_FUNCTION("mmc2", jz4760_mmc2),
1091
+
INGENIC_PIN_FUNCTION("nemc", jz4760_nemc),
1092
+
INGENIC_PIN_FUNCTION("nemc-cs1", jz4760_cs1),
1093
+
INGENIC_PIN_FUNCTION("nemc-cs2", jz4760_cs2),
1094
+
INGENIC_PIN_FUNCTION("nemc-cs3", jz4760_cs3),
1095
+
INGENIC_PIN_FUNCTION("nemc-cs4", jz4760_cs4),
1096
+
INGENIC_PIN_FUNCTION("nemc-cs5", jz4760_cs5),
1097
+
INGENIC_PIN_FUNCTION("nemc-cs6", jz4760_cs6),
1098
+
INGENIC_PIN_FUNCTION("i2c0", jz4760_i2c0),
1099
+
INGENIC_PIN_FUNCTION("i2c1", jz4760_i2c1),
1100
+
INGENIC_PIN_FUNCTION("cim", jz4760_cim),
1101
+
INGENIC_PIN_FUNCTION("lcd", jz4760_lcd),
1102
+
INGENIC_PIN_FUNCTION("pwm0", jz4760_pwm0),
1103
+
INGENIC_PIN_FUNCTION("pwm1", jz4760_pwm1),
1104
+
INGENIC_PIN_FUNCTION("pwm2", jz4760_pwm2),
1105
+
INGENIC_PIN_FUNCTION("pwm3", jz4760_pwm3),
1106
+
INGENIC_PIN_FUNCTION("pwm4", jz4760_pwm4),
1107
+
INGENIC_PIN_FUNCTION("pwm5", jz4760_pwm5),
1108
+
INGENIC_PIN_FUNCTION("pwm6", jz4760_pwm6),
1109
+
INGENIC_PIN_FUNCTION("pwm7", jz4760_pwm7),
1110
+
INGENIC_PIN_FUNCTION("otg", jz4760_otg),
1117
1111
};
1118
1112
1119
1113
static const struct ingenic_chip_info jz4760_chip_info = {
···
1423
1417
static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
1424
1418
1425
1419
static const struct function_desc jz4770_functions[] = {
1426
-
{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
1427
-
{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
1428
-
{ "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
1429
-
{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
1430
-
{ "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), },
1431
-
{ "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), },
1432
-
{ "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
1433
-
{ "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
1434
-
{ "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
1435
-
{ "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
1436
-
{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1437
-
{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1438
-
{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1439
-
{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1440
-
{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1441
-
{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1442
-
{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1443
-
{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1444
-
{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1445
-
{ "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
1446
-
{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1447
-
{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1448
-
{ "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1449
-
{ "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1450
-
{ "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1451
-
{ "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1452
-
{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1453
-
{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1454
-
{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
1455
-
{ "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
1456
-
{ "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
1420
+
INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),
1421
+
INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),
1422
+
INGENIC_PIN_FUNCTION("uart2", jz4770_uart2),
1423
+
INGENIC_PIN_FUNCTION("uart3", jz4770_uart3),
1424
+
INGENIC_PIN_FUNCTION("ssi0", jz4770_ssi0),
1425
+
INGENIC_PIN_FUNCTION("ssi1", jz4770_ssi1),
1426
+
INGENIC_PIN_FUNCTION("mmc0", jz4770_mmc0),
1427
+
INGENIC_PIN_FUNCTION("mmc1", jz4770_mmc1),
1428
+
INGENIC_PIN_FUNCTION("mmc2", jz4770_mmc2),
1429
+
INGENIC_PIN_FUNCTION("nemc", jz4770_nemc),
1430
+
INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
1431
+
INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
1432
+
INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
1433
+
INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
1434
+
INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
1435
+
INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
1436
+
INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0),
1437
+
INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1),
1438
+
INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2),
1439
+
INGENIC_PIN_FUNCTION("cim", jz4770_cim),
1440
+
INGENIC_PIN_FUNCTION("lcd", jz4770_lcd),
1441
+
INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0),
1442
+
INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1),
1443
+
INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2),
1444
+
INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3),
1445
+
INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4),
1446
+
INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5),
1447
+
INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6),
1448
+
INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7),
1449
+
INGENIC_PIN_FUNCTION("mac", jz4770_mac),
1450
+
INGENIC_PIN_FUNCTION("otg", jz4760_otg),
1457
1451
};
1458
1452
1459
1453
static const struct ingenic_chip_info jz4770_chip_info = {
···
1702
1696
static const char *jz4775_otg_groups[] = { "otg-vbus", };
1703
1697
1704
1698
static const struct function_desc jz4775_functions[] = {
1705
-
{ "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), },
1706
-
{ "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), },
1707
-
{ "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), },
1708
-
{ "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), },
1709
-
{ "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), },
1710
-
{ "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), },
1711
-
{ "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), },
1712
-
{ "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), },
1713
-
{ "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), },
1714
-
{ "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), },
1715
-
{ "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), },
1716
-
{ "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), },
1717
-
{ "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), },
1718
-
{ "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), },
1719
-
{ "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), },
1720
-
{ "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), },
1721
-
{ "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), },
1722
-
{ "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), },
1723
-
{ "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), },
1724
-
{ "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), },
1725
-
{ "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), },
1726
-
{ "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), },
1727
-
{ "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), },
1728
-
{ "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), },
1729
-
{ "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), },
1699
+
INGENIC_PIN_FUNCTION("uart0", jz4775_uart0),
1700
+
INGENIC_PIN_FUNCTION("uart1", jz4775_uart1),
1701
+
INGENIC_PIN_FUNCTION("uart2", jz4775_uart2),
1702
+
INGENIC_PIN_FUNCTION("uart3", jz4775_uart3),
1703
+
INGENIC_PIN_FUNCTION("ssi", jz4775_ssi),
1704
+
INGENIC_PIN_FUNCTION("mmc0", jz4775_mmc0),
1705
+
INGENIC_PIN_FUNCTION("mmc1", jz4775_mmc1),
1706
+
INGENIC_PIN_FUNCTION("mmc2", jz4775_mmc2),
1707
+
INGENIC_PIN_FUNCTION("nemc", jz4775_nemc),
1708
+
INGENIC_PIN_FUNCTION("nemc-cs1", jz4775_cs1),
1709
+
INGENIC_PIN_FUNCTION("nemc-cs2", jz4775_cs2),
1710
+
INGENIC_PIN_FUNCTION("nemc-cs3", jz4775_cs3),
1711
+
INGENIC_PIN_FUNCTION("i2c0", jz4775_i2c0),
1712
+
INGENIC_PIN_FUNCTION("i2c1", jz4775_i2c1),
1713
+
INGENIC_PIN_FUNCTION("i2c2", jz4775_i2c2),
1714
+
INGENIC_PIN_FUNCTION("i2s", jz4775_i2s),
1715
+
INGENIC_PIN_FUNCTION("dmic", jz4775_dmic),
1716
+
INGENIC_PIN_FUNCTION("cim", jz4775_cim),
1717
+
INGENIC_PIN_FUNCTION("lcd", jz4775_lcd),
1718
+
INGENIC_PIN_FUNCTION("pwm0", jz4775_pwm0),
1719
+
INGENIC_PIN_FUNCTION("pwm1", jz4775_pwm1),
1720
+
INGENIC_PIN_FUNCTION("pwm2", jz4775_pwm2),
1721
+
INGENIC_PIN_FUNCTION("pwm3", jz4775_pwm3),
1722
+
INGENIC_PIN_FUNCTION("mac", jz4775_mac),
1723
+
INGENIC_PIN_FUNCTION("otg", jz4775_otg),
1730
1724
};
1731
1725
1732
1726
static const struct ingenic_chip_info jz4775_chip_info = {
···
1955
1949
static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1956
1950
1957
1951
static const struct function_desc jz4780_functions[] = {
1958
-
{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
1959
-
{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
1960
-
{ "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
1961
-
{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
1962
-
{ "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
1963
-
{ "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), },
1964
-
{ "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), },
1965
-
{ "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
1966
-
{ "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
1967
-
{ "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
1968
-
{ "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
1969
-
{ "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1970
-
{ "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1971
-
{ "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1972
-
{ "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1973
-
{ "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1974
-
{ "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1975
-
{ "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1976
-
{ "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1977
-
{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1978
-
{ "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
1979
-
{ "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
1980
-
{ "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), },
1981
-
{ "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), },
1982
-
{ "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
1983
-
{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1984
-
{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1985
-
{ "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1986
-
{ "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1987
-
{ "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1988
-
{ "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1989
-
{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1990
-
{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1991
-
{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
1992
-
{ "hdmi-ddc", jz4780_hdmi_ddc_groups,
1993
-
ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
1952
+
INGENIC_PIN_FUNCTION("uart0", jz4770_uart0),
1953
+
INGENIC_PIN_FUNCTION("uart1", jz4770_uart1),
1954
+
INGENIC_PIN_FUNCTION("uart2", jz4780_uart2),
1955
+
INGENIC_PIN_FUNCTION("uart3", jz4770_uart3),
1956
+
INGENIC_PIN_FUNCTION("uart4", jz4780_uart4),
1957
+
INGENIC_PIN_FUNCTION("ssi0", jz4780_ssi0),
1958
+
INGENIC_PIN_FUNCTION("ssi1", jz4780_ssi1),
1959
+
INGENIC_PIN_FUNCTION("mmc0", jz4780_mmc0),
1960
+
INGENIC_PIN_FUNCTION("mmc1", jz4780_mmc1),
1961
+
INGENIC_PIN_FUNCTION("mmc2", jz4780_mmc2),
1962
+
INGENIC_PIN_FUNCTION("nemc", jz4780_nemc),
1963
+
INGENIC_PIN_FUNCTION("nemc-cs1", jz4770_cs1),
1964
+
INGENIC_PIN_FUNCTION("nemc-cs2", jz4770_cs2),
1965
+
INGENIC_PIN_FUNCTION("nemc-cs3", jz4770_cs3),
1966
+
INGENIC_PIN_FUNCTION("nemc-cs4", jz4770_cs4),
1967
+
INGENIC_PIN_FUNCTION("nemc-cs5", jz4770_cs5),
1968
+
INGENIC_PIN_FUNCTION("nemc-cs6", jz4770_cs6),
1969
+
INGENIC_PIN_FUNCTION("i2c0", jz4770_i2c0),
1970
+
INGENIC_PIN_FUNCTION("i2c1", jz4770_i2c1),
1971
+
INGENIC_PIN_FUNCTION("i2c2", jz4770_i2c2),
1972
+
INGENIC_PIN_FUNCTION("i2c3", jz4780_i2c3),
1973
+
INGENIC_PIN_FUNCTION("i2c4", jz4780_i2c4),
1974
+
INGENIC_PIN_FUNCTION("i2s", jz4780_i2s),
1975
+
INGENIC_PIN_FUNCTION("dmic", jz4780_dmic),
1976
+
INGENIC_PIN_FUNCTION("cim", jz4780_cim),
1977
+
INGENIC_PIN_FUNCTION("lcd", jz4770_lcd),
1978
+
INGENIC_PIN_FUNCTION("pwm0", jz4770_pwm0),
1979
+
INGENIC_PIN_FUNCTION("pwm1", jz4770_pwm1),
1980
+
INGENIC_PIN_FUNCTION("pwm2", jz4770_pwm2),
1981
+
INGENIC_PIN_FUNCTION("pwm3", jz4770_pwm3),
1982
+
INGENIC_PIN_FUNCTION("pwm4", jz4770_pwm4),
1983
+
INGENIC_PIN_FUNCTION("pwm5", jz4770_pwm5),
1984
+
INGENIC_PIN_FUNCTION("pwm6", jz4770_pwm6),
1985
+
INGENIC_PIN_FUNCTION("pwm7", jz4770_pwm7),
1986
+
INGENIC_PIN_FUNCTION("hdmi-ddc", jz4780_hdmi_ddc),
1994
1987
};
1995
1988
1996
1989
static const struct ingenic_chip_info jz4780_chip_info = {
···
2190
2185
static const char *x1000_mac_groups[] = { "mac", };
2191
2186
2192
2187
static const struct function_desc x1000_functions[] = {
2193
-
{ "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
2194
-
{ "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
2195
-
{ "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
2196
-
{ "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
2197
-
{ "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
2198
-
{ "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
2199
-
{ "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
2200
-
{ "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
2201
-
{ "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
2202
-
{ "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
2203
-
{ "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
2204
-
{ "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
2205
-
{ "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
2206
-
{ "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), },
2207
-
{ "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), },
2208
-
{ "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
2209
-
{ "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
2210
-
{ "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
2211
-
{ "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
2212
-
{ "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
2213
-
{ "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
2214
-
{ "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
2215
-
{ "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
2188
+
INGENIC_PIN_FUNCTION("uart0", x1000_uart0),
2189
+
INGENIC_PIN_FUNCTION("uart1", x1000_uart1),
2190
+
INGENIC_PIN_FUNCTION("uart2", x1000_uart2),
2191
+
INGENIC_PIN_FUNCTION("sfc", x1000_sfc),
2192
+
INGENIC_PIN_FUNCTION("ssi", x1000_ssi),
2193
+
INGENIC_PIN_FUNCTION("mmc0", x1000_mmc0),
2194
+
INGENIC_PIN_FUNCTION("mmc1", x1000_mmc1),
2195
+
INGENIC_PIN_FUNCTION("emc", x1000_emc),
2196
+
INGENIC_PIN_FUNCTION("emc-cs1", x1000_cs1),
2197
+
INGENIC_PIN_FUNCTION("emc-cs2", x1000_cs2),
2198
+
INGENIC_PIN_FUNCTION("i2c0", x1000_i2c0),
2199
+
INGENIC_PIN_FUNCTION("i2c1", x1000_i2c1),
2200
+
INGENIC_PIN_FUNCTION("i2c2", x1000_i2c2),
2201
+
INGENIC_PIN_FUNCTION("i2s", x1000_i2s),
2202
+
INGENIC_PIN_FUNCTION("dmic", x1000_dmic),
2203
+
INGENIC_PIN_FUNCTION("cim", x1000_cim),
2204
+
INGENIC_PIN_FUNCTION("lcd", x1000_lcd),
2205
+
INGENIC_PIN_FUNCTION("pwm0", x1000_pwm0),
2206
+
INGENIC_PIN_FUNCTION("pwm1", x1000_pwm1),
2207
+
INGENIC_PIN_FUNCTION("pwm2", x1000_pwm2),
2208
+
INGENIC_PIN_FUNCTION("pwm3", x1000_pwm3),
2209
+
INGENIC_PIN_FUNCTION("pwm4", x1000_pwm4),
2210
+
INGENIC_PIN_FUNCTION("mac", x1000_mac),
2216
2211
};
2217
2212
2218
2213
static const struct regmap_range x1000_access_ranges[] = {
···
2320
2315
static const char *x1500_pwm4_groups[] = { "pwm4", };
2321
2316
2322
2317
static const struct function_desc x1500_functions[] = {
2323
-
{ "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
2324
-
{ "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
2325
-
{ "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
2326
-
{ "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
2327
-
{ "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
2328
-
{ "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
2329
-
{ "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
2330
-
{ "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
2331
-
{ "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), },
2332
-
{ "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), },
2333
-
{ "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
2334
-
{ "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
2335
-
{ "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
2336
-
{ "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
2337
-
{ "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
2338
-
{ "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
2318
+
INGENIC_PIN_FUNCTION("uart0", x1500_uart0),
2319
+
INGENIC_PIN_FUNCTION("uart1", x1500_uart1),
2320
+
INGENIC_PIN_FUNCTION("uart2", x1500_uart2),
2321
+
INGENIC_PIN_FUNCTION("sfc", x1000_sfc),
2322
+
INGENIC_PIN_FUNCTION("mmc", x1500_mmc),
2323
+
INGENIC_PIN_FUNCTION("i2c0", x1500_i2c0),
2324
+
INGENIC_PIN_FUNCTION("i2c1", x1500_i2c1),
2325
+
INGENIC_PIN_FUNCTION("i2c2", x1500_i2c2),
2326
+
INGENIC_PIN_FUNCTION("i2s", x1500_i2s),
2327
+
INGENIC_PIN_FUNCTION("dmic", x1500_dmic),
2328
+
INGENIC_PIN_FUNCTION("cim", x1500_cim),
2329
+
INGENIC_PIN_FUNCTION("pwm0", x1500_pwm0),
2330
+
INGENIC_PIN_FUNCTION("pwm1", x1500_pwm1),
2331
+
INGENIC_PIN_FUNCTION("pwm2", x1500_pwm2),
2332
+
INGENIC_PIN_FUNCTION("pwm3", x1500_pwm3),
2333
+
INGENIC_PIN_FUNCTION("pwm4", x1500_pwm4),
2339
2334
};
2340
2335
2341
2336
static const struct ingenic_chip_info x1500_chip_info = {
···
2531
2526
static const char *x1830_mac_groups[] = { "mac", };
2532
2527
2533
2528
static const struct function_desc x1830_functions[] = {
2534
-
{ "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
2535
-
{ "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
2536
-
{ "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
2537
-
{ "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
2538
-
{ "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
2539
-
{ "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
2540
-
{ "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
2541
-
{ "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
2542
-
{ "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
2543
-
{ "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
2544
-
{ "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), },
2545
-
{ "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), },
2546
-
{ "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
2547
-
{ "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
2548
-
{ "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
2549
-
{ "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
2550
-
{ "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
2551
-
{ "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2552
-
{ "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2553
-
{ "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2554
-
{ "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2555
-
{ "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
2529
+
INGENIC_PIN_FUNCTION("uart0", x1830_uart0),
2530
+
INGENIC_PIN_FUNCTION("uart1", x1830_uart1),
2531
+
INGENIC_PIN_FUNCTION("sfc", x1830_sfc),
2532
+
INGENIC_PIN_FUNCTION("ssi0", x1830_ssi0),
2533
+
INGENIC_PIN_FUNCTION("ssi1", x1830_ssi1),
2534
+
INGENIC_PIN_FUNCTION("mmc0", x1830_mmc0),
2535
+
INGENIC_PIN_FUNCTION("mmc1", x1830_mmc1),
2536
+
INGENIC_PIN_FUNCTION("i2c0", x1830_i2c0),
2537
+
INGENIC_PIN_FUNCTION("i2c1", x1830_i2c1),
2538
+
INGENIC_PIN_FUNCTION("i2c2", x1830_i2c2),
2539
+
INGENIC_PIN_FUNCTION("i2s", x1830_i2s),
2540
+
INGENIC_PIN_FUNCTION("dmic", x1830_dmic),
2541
+
INGENIC_PIN_FUNCTION("lcd", x1830_lcd),
2542
+
INGENIC_PIN_FUNCTION("pwm0", x1830_pwm0),
2543
+
INGENIC_PIN_FUNCTION("pwm1", x1830_pwm1),
2544
+
INGENIC_PIN_FUNCTION("pwm2", x1830_pwm2),
2545
+
INGENIC_PIN_FUNCTION("pwm3", x1830_pwm3),
2546
+
INGENIC_PIN_FUNCTION("pwm4", x1830_pwm4),
2547
+
INGENIC_PIN_FUNCTION("pwm5", x1830_pwm5),
2548
+
INGENIC_PIN_FUNCTION("pwm6", x1830_pwm6),
2549
+
INGENIC_PIN_FUNCTION("pwm7", x1830_pwm7),
2550
+
INGENIC_PIN_FUNCTION("mac", x1830_mac),
2556
2551
};
2557
2552
2558
2553
static const struct regmap_range x1830_access_ranges[] = {
···
2977
2972
static const char *x2000_otg_groups[] = { "otg-vbus", };
2978
2973
2979
2974
static const struct function_desc x2000_functions[] = {
2980
-
{ "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
2981
-
{ "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
2982
-
{ "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
2983
-
{ "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
2984
-
{ "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
2985
-
{ "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
2986
-
{ "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
2987
-
{ "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
2988
-
{ "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
2989
-
{ "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
2990
-
{ "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
2991
-
{ "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
2992
-
{ "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
2993
-
{ "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
2994
-
{ "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
2995
-
{ "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
2996
-
{ "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
2997
-
{ "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
2998
-
{ "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
2999
-
{ "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
3000
-
{ "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
3001
-
{ "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
3002
-
{ "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
3003
-
{ "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
3004
-
{ "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
3005
-
{ "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
3006
-
{ "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
3007
-
{ "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
3008
-
{ "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
3009
-
{ "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
3010
-
{ "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
3011
-
{ "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
3012
-
{ "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
3013
-
{ "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
3014
-
{ "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
3015
-
{ "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
3016
-
{ "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
3017
-
{ "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
3018
-
{ "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
3019
-
{ "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
3020
-
{ "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
3021
-
{ "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
3022
-
{ "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
3023
-
{ "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
3024
-
{ "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
3025
-
{ "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
3026
-
{ "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
3027
-
{ "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), },
3028
-
{ "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), },
3029
-
{ "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), },
2975
+
INGENIC_PIN_FUNCTION("uart0", x2000_uart0),
2976
+
INGENIC_PIN_FUNCTION("uart1", x2000_uart1),
2977
+
INGENIC_PIN_FUNCTION("uart2", x2000_uart2),
2978
+
INGENIC_PIN_FUNCTION("uart3", x2000_uart3),
2979
+
INGENIC_PIN_FUNCTION("uart4", x2000_uart4),
2980
+
INGENIC_PIN_FUNCTION("uart5", x2000_uart5),
2981
+
INGENIC_PIN_FUNCTION("uart6", x2000_uart6),
2982
+
INGENIC_PIN_FUNCTION("uart7", x2000_uart7),
2983
+
INGENIC_PIN_FUNCTION("uart8", x2000_uart8),
2984
+
INGENIC_PIN_FUNCTION("uart9", x2000_uart9),
2985
+
INGENIC_PIN_FUNCTION("sfc", x2000_sfc),
2986
+
INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0),
2987
+
INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1),
2988
+
INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0),
2989
+
INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1),
2990
+
INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2),
2991
+
INGENIC_PIN_FUNCTION("emc", x2000_emc),
2992
+
INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
2993
+
INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
2994
+
INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0),
2995
+
INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1),
2996
+
INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2),
2997
+
INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3),
2998
+
INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4),
2999
+
INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5),
3000
+
INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1),
3001
+
INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2),
3002
+
INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3),
3003
+
INGENIC_PIN_FUNCTION("dmic", x2000_dmic),
3004
+
INGENIC_PIN_FUNCTION("cim", x2000_cim),
3005
+
INGENIC_PIN_FUNCTION("lcd", x2000_lcd),
3006
+
INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0),
3007
+
INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1),
3008
+
INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2),
3009
+
INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3),
3010
+
INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4),
3011
+
INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5),
3012
+
INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6),
3013
+
INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7),
3014
+
INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8),
3015
+
INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9),
3016
+
INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10),
3017
+
INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11),
3018
+
INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12),
3019
+
INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13),
3020
+
INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14),
3021
+
INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15),
3022
+
INGENIC_PIN_FUNCTION("mac0", x2000_mac0),
3023
+
INGENIC_PIN_FUNCTION("mac1", x2000_mac1),
3024
+
INGENIC_PIN_FUNCTION("otg", x2000_otg),
3030
3025
};
3031
3026
3032
3027
static const struct regmap_range x2000_access_ranges[] = {
···
3201
3196
static const char *x2100_mac_groups[] = { "mac", };
3202
3197
3203
3198
static const struct function_desc x2100_functions[] = {
3204
-
{ "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
3205
-
{ "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
3206
-
{ "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
3207
-
{ "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
3208
-
{ "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
3209
-
{ "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
3210
-
{ "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
3211
-
{ "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
3212
-
{ "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
3213
-
{ "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
3214
-
{ "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
3215
-
{ "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
3216
-
{ "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
3217
-
{ "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
3218
-
{ "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
3219
-
{ "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
3220
-
{ "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
3221
-
{ "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
3222
-
{ "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
3223
-
{ "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
3224
-
{ "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
3225
-
{ "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
3226
-
{ "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
3227
-
{ "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
3228
-
{ "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
3229
-
{ "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
3230
-
{ "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
3231
-
{ "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
3232
-
{ "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
3233
-
{ "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
3234
-
{ "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
3235
-
{ "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
3236
-
{ "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
3237
-
{ "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
3238
-
{ "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
3239
-
{ "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
3240
-
{ "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
3241
-
{ "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
3242
-
{ "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
3243
-
{ "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
3244
-
{ "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
3245
-
{ "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
3246
-
{ "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
3247
-
{ "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
3248
-
{ "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
3249
-
{ "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
3250
-
{ "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
3251
-
{ "mac", x2100_mac_groups, ARRAY_SIZE(x2100_mac_groups), },
3199
+
INGENIC_PIN_FUNCTION("uart0", x2000_uart0),
3200
+
INGENIC_PIN_FUNCTION("uart1", x2000_uart1),
3201
+
INGENIC_PIN_FUNCTION("uart2", x2000_uart2),
3202
+
INGENIC_PIN_FUNCTION("uart3", x2000_uart3),
3203
+
INGENIC_PIN_FUNCTION("uart4", x2000_uart4),
3204
+
INGENIC_PIN_FUNCTION("uart5", x2000_uart5),
3205
+
INGENIC_PIN_FUNCTION("uart6", x2000_uart6),
3206
+
INGENIC_PIN_FUNCTION("uart7", x2000_uart7),
3207
+
INGENIC_PIN_FUNCTION("uart8", x2000_uart8),
3208
+
INGENIC_PIN_FUNCTION("uart9", x2000_uart9),
3209
+
INGENIC_PIN_FUNCTION("sfc", x2000_sfc),
3210
+
INGENIC_PIN_FUNCTION("ssi0", x2000_ssi0),
3211
+
INGENIC_PIN_FUNCTION("ssi1", x2000_ssi1),
3212
+
INGENIC_PIN_FUNCTION("mmc0", x2000_mmc0),
3213
+
INGENIC_PIN_FUNCTION("mmc1", x2000_mmc1),
3214
+
INGENIC_PIN_FUNCTION("mmc2", x2000_mmc2),
3215
+
INGENIC_PIN_FUNCTION("emc", x2000_emc),
3216
+
INGENIC_PIN_FUNCTION("emc-cs1", x2000_cs1),
3217
+
INGENIC_PIN_FUNCTION("emc-cs2", x2000_cs2),
3218
+
INGENIC_PIN_FUNCTION("i2c0", x2000_i2c0),
3219
+
INGENIC_PIN_FUNCTION("i2c1", x2000_i2c1),
3220
+
INGENIC_PIN_FUNCTION("i2c2", x2000_i2c2),
3221
+
INGENIC_PIN_FUNCTION("i2c3", x2000_i2c3),
3222
+
INGENIC_PIN_FUNCTION("i2c4", x2000_i2c4),
3223
+
INGENIC_PIN_FUNCTION("i2c5", x2000_i2c5),
3224
+
INGENIC_PIN_FUNCTION("i2s1", x2000_i2s1),
3225
+
INGENIC_PIN_FUNCTION("i2s2", x2000_i2s2),
3226
+
INGENIC_PIN_FUNCTION("i2s3", x2000_i2s3),
3227
+
INGENIC_PIN_FUNCTION("dmic", x2000_dmic),
3228
+
INGENIC_PIN_FUNCTION("cim", x2000_cim),
3229
+
INGENIC_PIN_FUNCTION("lcd", x2000_lcd),
3230
+
INGENIC_PIN_FUNCTION("pwm0", x2000_pwm0),
3231
+
INGENIC_PIN_FUNCTION("pwm1", x2000_pwm1),
3232
+
INGENIC_PIN_FUNCTION("pwm2", x2000_pwm2),
3233
+
INGENIC_PIN_FUNCTION("pwm3", x2000_pwm3),
3234
+
INGENIC_PIN_FUNCTION("pwm4", x2000_pwm4),
3235
+
INGENIC_PIN_FUNCTION("pwm5", x2000_pwm5),
3236
+
INGENIC_PIN_FUNCTION("pwm6", x2000_pwm6),
3237
+
INGENIC_PIN_FUNCTION("pwm7", x2000_pwm7),
3238
+
INGENIC_PIN_FUNCTION("pwm8", x2000_pwm8),
3239
+
INGENIC_PIN_FUNCTION("pwm9", x2000_pwm9),
3240
+
INGENIC_PIN_FUNCTION("pwm10", x2000_pwm10),
3241
+
INGENIC_PIN_FUNCTION("pwm11", x2000_pwm11),
3242
+
INGENIC_PIN_FUNCTION("pwm12", x2000_pwm12),
3243
+
INGENIC_PIN_FUNCTION("pwm13", x2000_pwm13),
3244
+
INGENIC_PIN_FUNCTION("pwm14", x2000_pwm14),
3245
+
INGENIC_PIN_FUNCTION("pwm15", x2000_pwm15),
3246
+
INGENIC_PIN_FUNCTION("mac", x2100_mac),
3252
3247
};
3253
3248
3254
3249
static const struct ingenic_chip_info x2100_chip_info = {
···
3767
3762
return -EINVAL;
3768
3763
3769
3764
dev_dbg(pctldev->dev, "enable function %s group %s\n",
3770
-
func->name, grp->grp.name);
3765
+
func->func.name, grp->grp.name);
3771
3766
3772
3767
mode = (uintptr_t)grp->data;
3773
3768
if (mode <= 3) {
···
4315
4310
}
4316
4311
4317
4312
for (i = 0; i < chip_info->num_functions; i++) {
4318
-
const struct function_desc *func = &chip_info->functions[i];
4313
+
const struct function_desc *function = &chip_info->functions[i];
4314
+
const struct pinfunction *func = &function->func;
4319
4315
4320
4316
err = pinmux_generic_add_function(jzpc->pctl, func->name,
4321
-
func->group_names, func->num_group_names,
4322
-
func->data);
4317
+
func->groups, func->ngroups,
4318
+
function->data);
4323
4319
if (err < 0) {
4324
-
dev_err(dev, "Failed to register function %s\n",
4325
-
func->name);
4320
+
dev_err(dev, "Failed to register function %s\n", func->name);
4326
4321
return err;
4327
4322
}
4328
4323
}
+2
-5
drivers/pinctrl/pinctrl-k210.c
+2
-5
drivers/pinctrl/pinctrl-k210.c
···
849
849
unsigned int *num_maps)
850
850
{
851
851
unsigned int reserved_maps;
852
-
struct device_node *np;
853
852
int ret;
854
853
855
854
reserved_maps = 0;
···
860
861
if (ret < 0)
861
862
goto err;
862
863
863
-
for_each_available_child_of_node(np_config, np) {
864
+
for_each_available_child_of_node_scoped(np_config, np) {
864
865
ret = k210_pinctrl_dt_subnode_to_map(pctldev, np, map,
865
866
&reserved_maps, num_maps);
866
-
if (ret < 0) {
867
-
of_node_put(np);
867
+
if (ret < 0)
868
868
goto err;
869
-
}
870
869
}
871
870
return 0;
872
871
+12
-12
drivers/pinctrl/pinctrl-keembay.c
+12
-12
drivers/pinctrl/pinctrl-keembay.c
···
1566
1566
unsigned int grp_idx = 0;
1567
1567
int j;
1568
1568
1569
-
group_names = devm_kcalloc(kpc->dev, func->num_group_names,
1569
+
group_names = devm_kcalloc(kpc->dev, func->func.ngroups,
1570
1570
sizeof(*group_names), GFP_KERNEL);
1571
1571
if (!group_names)
1572
1572
return -ENOMEM;
···
1576
1576
struct keembay_mux_desc *mux;
1577
1577
1578
1578
for (mux = pdesc->drv_data; mux->name; mux++) {
1579
-
if (!strcmp(mux->name, func->name))
1579
+
if (!strcmp(mux->name, func->func.name))
1580
1580
group_names[grp_idx++] = pdesc->name;
1581
1581
}
1582
1582
}
1583
1583
1584
-
func->group_names = group_names;
1584
+
func->func.groups = group_names;
1585
1585
}
1586
1586
1587
1587
/* Add all functions */
1588
1588
for (i = 0; i < kpc->nfuncs; i++) {
1589
1589
pinmux_generic_add_function(kpc->pctrl,
1590
-
functions[i].name,
1591
-
functions[i].group_names,
1592
-
functions[i].num_group_names,
1590
+
functions[i].func.name,
1591
+
functions[i].func.groups,
1592
+
functions[i].func.ngroups,
1593
1593
functions[i].data);
1594
1594
}
1595
1595
···
1619
1619
struct function_desc *fdesc;
1620
1620
1621
1621
/* Check if we already have function for this mux */
1622
-
for (fdesc = keembay_funcs; fdesc->name; fdesc++) {
1623
-
if (!strcmp(mux->name, fdesc->name)) {
1624
-
fdesc->num_group_names++;
1622
+
for (fdesc = keembay_funcs; fdesc->func.name; fdesc++) {
1623
+
if (!strcmp(mux->name, fdesc->func.name)) {
1624
+
fdesc->func.ngroups++;
1625
1625
break;
1626
1626
}
1627
1627
}
1628
1628
1629
1629
/* Setup new function for this mux we didn't see before */
1630
-
if (!fdesc->name) {
1631
-
fdesc->name = mux->name;
1632
-
fdesc->num_group_names = 1;
1630
+
if (!fdesc->func.name) {
1631
+
fdesc->func.name = mux->name;
1632
+
fdesc->func.ngroups = 1;
1633
1633
fdesc->data = &mux->mode;
1634
1634
kpc->nfuncs++;
1635
1635
}
+1
drivers/pinctrl/pinctrl-mcp23s08.c
+1
drivers/pinctrl/pinctrl-mcp23s08.c
+1
drivers/pinctrl/pinctrl-mcp23s08_i2c.c
+1
drivers/pinctrl/pinctrl-mcp23s08_i2c.c
+1
drivers/pinctrl/pinctrl-mcp23s08_spi.c
+1
drivers/pinctrl/pinctrl-mcp23s08_spi.c
+6
-6
drivers/pinctrl/pinctrl-mlxbf3.c
+6
-6
drivers/pinctrl/pinctrl-mlxbf3.c
···
259
259
return PTR_ERR(priv->fw_ctrl_set0);
260
260
261
261
priv->fw_ctrl_clr0 = devm_platform_ioremap_resource(pdev, 1);
262
-
if (IS_ERR(priv->fw_ctrl_set0))
263
-
return PTR_ERR(priv->fw_ctrl_set0);
262
+
if (IS_ERR(priv->fw_ctrl_clr0))
263
+
return PTR_ERR(priv->fw_ctrl_clr0);
264
264
265
265
priv->fw_ctrl_set1 = devm_platform_ioremap_resource(pdev, 2);
266
-
if (IS_ERR(priv->fw_ctrl_set0))
267
-
return PTR_ERR(priv->fw_ctrl_set0);
266
+
if (IS_ERR(priv->fw_ctrl_set1))
267
+
return PTR_ERR(priv->fw_ctrl_set1);
268
268
269
269
priv->fw_ctrl_clr1 = devm_platform_ioremap_resource(pdev, 3);
270
-
if (IS_ERR(priv->fw_ctrl_set0))
271
-
return PTR_ERR(priv->fw_ctrl_set0);
270
+
if (IS_ERR(priv->fw_ctrl_clr1))
271
+
return PTR_ERR(priv->fw_ctrl_clr1);
272
272
273
273
ret = devm_pinctrl_register_and_init(dev,
274
274
&mlxbf3_pin_desc,
+5
-23
drivers/pinctrl/pinctrl-rockchip.c
+5
-23
drivers/pinctrl/pinctrl-rockchip.c
···
915
915
RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
916
916
RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
917
917
RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
918
-
RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
919
-
RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
920
-
RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
918
+
RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */
919
+
RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */
921
920
RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
922
921
RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
923
922
RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
···
925
926
RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
926
927
RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
927
928
RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
928
-
RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
929
-
RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
930
-
RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
931
-
RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
932
-
RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
933
-
RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
934
-
RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
935
-
RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
936
-
RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
937
-
RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
938
-
RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
939
-
RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
940
929
};
941
930
942
931
static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
···
3094
3107
u32 index)
3095
3108
{
3096
3109
struct device *dev = info->dev;
3097
-
struct device_node *child;
3098
3110
struct rockchip_pmx_func *func;
3099
3111
struct rockchip_pin_group *grp;
3100
3112
int ret;
···
3114
3128
if (!func->groups)
3115
3129
return -ENOMEM;
3116
3130
3117
-
for_each_child_of_node(np, child) {
3131
+
for_each_child_of_node_scoped(np, child) {
3118
3132
func->groups[i] = child->name;
3119
3133
grp = &info->groups[grp_index++];
3120
3134
ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
3121
-
if (ret) {
3122
-
of_node_put(child);
3135
+
if (ret)
3123
3136
return ret;
3124
-
}
3125
3137
}
3126
3138
3127
3139
return 0;
···
3130
3146
{
3131
3147
struct device *dev = &pdev->dev;
3132
3148
struct device_node *np = dev->of_node;
3133
-
struct device_node *child;
3134
3149
int ret;
3135
3150
int i;
3136
3151
···
3148
3165
3149
3166
i = 0;
3150
3167
3151
-
for_each_child_of_node(np, child) {
3168
+
for_each_child_of_node_scoped(np, child) {
3152
3169
if (of_match_node(rockchip_bank_match, child))
3153
3170
continue;
3154
3171
3155
3172
ret = rockchip_pinctrl_parse_functions(child, info, i++);
3156
3173
if (ret) {
3157
3174
dev_err(dev, "failed to parse function\n");
3158
-
of_node_put(child);
3159
3175
return ret;
3160
3176
}
3161
3177
}
+9
drivers/pinctrl/pinctrl-scmi.c
+9
drivers/pinctrl/pinctrl-scmi.c
···
11
11
#include <linux/errno.h>
12
12
#include <linux/module.h>
13
13
#include <linux/mod_devicetable.h>
14
+
#include <linux/of.h>
14
15
#include <linux/scmi_protocol.h>
15
16
#include <linux/slab.h>
16
17
#include <linux/types.h>
···
505
504
return 0;
506
505
}
507
506
507
+
static const char * const scmi_pinctrl_blocklist[] = {
508
+
"fsl,imx95",
509
+
NULL
510
+
};
511
+
508
512
static int scmi_pinctrl_probe(struct scmi_device *sdev)
509
513
{
510
514
int ret;
···
520
514
521
515
if (!sdev->handle)
522
516
return -EINVAL;
517
+
518
+
if (of_machine_compatible_match(scmi_pinctrl_blocklist))
519
+
return -ENODEV;
523
520
524
521
handle = sdev->handle;
525
522
+4
-3
drivers/pinctrl/pinctrl-single.c
+4
-3
drivers/pinctrl/pinctrl-single.c
···
1329
1329
static void pcs_free_resources(struct pcs_device *pcs)
1330
1330
{
1331
1331
pcs_irq_free(pcs);
1332
-
pinctrl_unregister(pcs->pctl);
1333
1332
1334
1333
#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1335
1334
if (pcs->missing_nr_pinctrl_cells)
···
1878
1879
if (ret < 0)
1879
1880
goto free;
1880
1881
1881
-
ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1882
+
ret = devm_pinctrl_register_and_init(pcs->dev, &pcs->desc, pcs, &pcs->pctl);
1882
1883
if (ret) {
1883
1884
dev_err(pcs->dev, "could not register single pinctrl driver\n");
1884
1885
goto free;
···
1911
1912
1912
1913
dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1913
1914
1914
-
return pinctrl_enable(pcs->pctl);
1915
+
if (pinctrl_enable(pcs->pctl))
1916
+
goto free;
1915
1917
1918
+
return 0;
1916
1919
free:
1917
1920
pcs_free_resources(pcs);
1918
1921
+11
-26
drivers/pinctrl/pinctrl-st.c
+11
-26
drivers/pinctrl/pinctrl-st.c
···
1195
1195
struct property *pp;
1196
1196
struct device *dev = info->dev;
1197
1197
struct st_pinconf *conf;
1198
-
struct device_node *pins;
1198
+
struct device_node *pins __free(device_node) = NULL;
1199
1199
phandle bank;
1200
1200
unsigned int offset;
1201
-
int i = 0, npins = 0, nr_props, ret = 0;
1201
+
int i = 0, npins = 0, nr_props;
1202
1202
1203
1203
pins = of_get_child_by_name(np, "st,pins");
1204
1204
if (!pins)
···
1213
1213
npins++;
1214
1214
} else {
1215
1215
pr_warn("Invalid st,pins in %pOFn node\n", np);
1216
-
ret = -EINVAL;
1217
-
goto out_put_node;
1216
+
return -EINVAL;
1218
1217
}
1219
1218
}
1220
1219
···
1222
1223
grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL);
1223
1224
grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL);
1224
1225
1225
-
if (!grp->pins || !grp->pin_conf) {
1226
-
ret = -ENOMEM;
1227
-
goto out_put_node;
1228
-
}
1226
+
if (!grp->pins || !grp->pin_conf)
1227
+
return -ENOMEM;
1229
1228
1230
1229
/* <bank offset mux direction rt_type rt_delay rt_clk> */
1231
1230
for_each_property_of_node(pins, pp) {
···
1257
1260
i++;
1258
1261
}
1259
1262
1260
-
out_put_node:
1261
-
of_node_put(pins);
1262
-
1263
-
return ret;
1263
+
return 0;
1264
1264
}
1265
1265
1266
1266
static int st_pctl_parse_functions(struct device_node *np,
1267
1267
struct st_pinctrl *info, u32 index, int *grp_index)
1268
1268
{
1269
1269
struct device *dev = info->dev;
1270
-
struct device_node *child;
1271
1270
struct st_pmx_func *func;
1272
1271
struct st_pctl_group *grp;
1273
1272
int ret, i;
···
1278
1285
return -ENOMEM;
1279
1286
1280
1287
i = 0;
1281
-
for_each_child_of_node(np, child) {
1288
+
for_each_child_of_node_scoped(np, child) {
1282
1289
func->groups[i] = child->name;
1283
1290
grp = &info->groups[*grp_index];
1284
1291
*grp_index += 1;
1285
1292
ret = st_pctl_dt_parse_groups(child, grp, info, i++);
1286
-
if (ret) {
1287
-
of_node_put(child);
1293
+
if (ret)
1288
1294
return ret;
1289
-
}
1290
1295
}
1291
1296
dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups);
1292
1297
···
1592
1601
int i = 0, j = 0, k = 0, bank;
1593
1602
struct pinctrl_pin_desc *pdesc;
1594
1603
struct device_node *np = dev->of_node;
1595
-
struct device_node *child;
1596
1604
int grp_index = 0;
1597
1605
int irq = 0;
1598
1606
···
1636
1646
pctl_desc->pins = pdesc;
1637
1647
1638
1648
bank = 0;
1639
-
for_each_child_of_node(np, child) {
1649
+
for_each_child_of_node_scoped(np, child) {
1640
1650
if (of_property_read_bool(child, "gpio-controller")) {
1641
1651
const char *bank_name = NULL;
1642
1652
char **pin_names;
1643
1653
1644
1654
ret = st_gpiolib_register_bank(info, bank, child);
1645
-
if (ret) {
1646
-
of_node_put(child);
1655
+
if (ret)
1647
1656
return ret;
1648
-
}
1649
1657
1650
1658
k = info->banks[bank].range.pin_base;
1651
1659
bank_name = info->banks[bank].range.name;
1652
1660
1653
1661
pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK);
1654
-
if (IS_ERR(pin_names)) {
1655
-
of_node_put(child);
1662
+
if (IS_ERR(pin_names))
1656
1663
return PTR_ERR(pin_names);
1657
-
}
1658
1664
1659
1665
for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
1660
1666
pdesc->number = k;
···
1664
1678
i++, &grp_index);
1665
1679
if (ret) {
1666
1680
dev_err(dev, "No functions found.\n");
1667
-
of_node_put(child);
1668
1681
return ret;
1669
1682
}
1670
1683
}
+1
drivers/pinctrl/pinctrl-tb10x.c
+1
drivers/pinctrl/pinctrl-tb10x.c
+2
-2
drivers/pinctrl/pinctrl-tps6594.c
+2
-2
drivers/pinctrl/pinctrl-tps6594.c
···
237
237
u8 remap;
238
238
};
239
239
240
-
struct muxval_remap tps65224_muxval_remap[] = {
240
+
static struct muxval_remap tps65224_muxval_remap[] = {
241
241
{5, TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION, TPS65224_PINCTRL_WKUP_FUNCTION_GPIO5},
242
242
{5, TPS65224_PINCTRL_SYNCCLKIN_FUNCTION, TPS65224_PINCTRL_SYNCCLKIN_FUNCTION_GPIO5},
243
243
{5, TPS65224_PINCTRL_NSLEEP2_FUNCTION, TPS65224_PINCTRL_NSLEEP2_FUNCTION_GPIO5},
244
244
};
245
245
246
-
struct muxval_remap tps6594_muxval_remap[] = {
246
+
static struct muxval_remap tps6594_muxval_remap[] = {
247
247
{8, TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION, TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION_GPIO8},
248
248
{8, TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION, TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION_GPIO8},
249
249
{9, TPS6594_PINCTRL_CLK32KOUT_FUNCTION, TPS6594_PINCTRL_CLK32KOUT_FUNCTION_GPIO9},
+55
-30
drivers/pinctrl/pinctrl-zynqmp.c
+55
-30
drivers/pinctrl/pinctrl-zynqmp.c
···
10
10
11
11
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
12
12
13
+
#include <linux/bitmap.h>
13
14
#include <linux/init.h>
14
15
#include <linux/module.h>
15
16
#include <linux/of_address.h>
···
98
97
{
99
98
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
100
99
101
-
return pctrl->ngroups;
100
+
return pctrl->ngroups + zynqmp_desc.npins;
102
101
}
103
102
104
103
static const char *zynqmp_pctrl_get_group_name(struct pinctrl_dev *pctldev,
···
106
105
{
107
106
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
108
107
109
-
return pctrl->groups[selector].name;
108
+
if (selector < pctrl->ngroups)
109
+
return pctrl->groups[selector].name;
110
+
111
+
return zynqmp_desc.pins[selector - pctrl->ngroups].name;
110
112
}
111
113
112
114
static int zynqmp_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
···
119
115
{
120
116
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
121
117
122
-
*pins = pctrl->groups[selector].pins;
123
-
*npins = pctrl->groups[selector].npins;
118
+
if (selector < pctrl->ngroups) {
119
+
*pins = pctrl->groups[selector].pins;
120
+
*npins = pctrl->groups[selector].npins;
121
+
} else {
122
+
*pins = &zynqmp_desc.pins[selector - pctrl->ngroups].number;
123
+
*npins = 1;
124
+
}
124
125
125
126
return 0;
126
127
}
···
206
197
unsigned int function,
207
198
unsigned int group)
208
199
{
209
-
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
210
-
const struct zynqmp_pctrl_group *pgrp = &pctrl->groups[group];
200
+
const unsigned int *pins;
201
+
unsigned int npins;
211
202
int ret, i;
212
203
213
-
for (i = 0; i < pgrp->npins; i++) {
214
-
unsigned int pin = pgrp->pins[i];
215
-
216
-
ret = zynqmp_pm_pinctrl_set_function(pin, function);
204
+
zynqmp_pctrl_get_group_pins(pctldev, group, &pins, &npins);
205
+
for (i = 0; i < npins; i++) {
206
+
ret = zynqmp_pm_pinctrl_set_function(pins[i], function);
217
207
if (ret) {
218
208
dev_err(pctldev->dev, "set mux failed for pin %u\n",
219
-
pin);
209
+
pins[i]);
220
210
return ret;
221
211
}
222
212
}
···
475
467
unsigned long *configs,
476
468
unsigned int num_configs)
477
469
{
470
+
const unsigned int *pins;
471
+
unsigned int npins;
478
472
int i, ret;
479
-
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
480
-
const struct zynqmp_pctrl_group *pgrp = &pctrl->groups[selector];
481
473
482
-
for (i = 0; i < pgrp->npins; i++) {
483
-
ret = zynqmp_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
474
+
zynqmp_pctrl_get_group_pins(pctldev, selector, &pins, &npins);
475
+
for (i = 0; i < npins; i++) {
476
+
ret = zynqmp_pinconf_cfg_set(pctldev, pins[i], configs,
484
477
num_configs);
485
478
if (ret)
486
479
return ret;
···
569
560
{
570
561
u16 resp[NUM_GROUPS_PER_RESP] = {0};
571
562
const char **fgroups;
572
-
int ret, index, i;
563
+
int ret, index, i, pin;
564
+
unsigned int npins;
565
+
unsigned long *used_pins __free(bitmap) =
566
+
bitmap_zalloc(zynqmp_desc.npins, GFP_KERNEL);
573
567
574
-
fgroups = devm_kcalloc(dev, func->ngroups, sizeof(*fgroups), GFP_KERNEL);
575
-
if (!fgroups)
568
+
if (!used_pins)
576
569
return -ENOMEM;
577
570
578
571
for (index = 0; index < func->ngroups; index += NUM_GROUPS_PER_RESP) {
···
589
578
if (resp[i] == RESERVED_GROUP)
590
579
continue;
591
580
592
-
fgroups[index + i] = devm_kasprintf(dev, GFP_KERNEL,
593
-
"%s_%d_grp",
594
-
func->name,
595
-
index + i);
596
-
if (!fgroups[index + i])
597
-
return -ENOMEM;
598
-
599
581
groups[resp[i]].name = devm_kasprintf(dev, GFP_KERNEL,
600
582
"%s_%d_grp",
601
583
func->name,
602
584
index + i);
603
585
if (!groups[resp[i]].name)
604
586
return -ENOMEM;
587
+
588
+
for (pin = 0; pin < groups[resp[i]].npins; pin++)
589
+
__set_bit(groups[resp[i]].pins[pin], used_pins);
605
590
}
606
591
}
607
592
done:
593
+
npins = bitmap_weight(used_pins, zynqmp_desc.npins);
594
+
fgroups = devm_kcalloc(dev, size_add(func->ngroups, npins),
595
+
sizeof(*fgroups), GFP_KERNEL);
596
+
if (!fgroups)
597
+
return -ENOMEM;
598
+
599
+
for (i = 0; i < func->ngroups; i++) {
600
+
fgroups[i] = devm_kasprintf(dev, GFP_KERNEL, "%s_%d_grp",
601
+
func->name, i);
602
+
if (!fgroups[i])
603
+
return -ENOMEM;
604
+
}
605
+
606
+
pin = 0;
607
+
for_each_set_bit(pin, used_pins, zynqmp_desc.npins)
608
+
fgroups[i++] = zynqmp_desc.pins[pin].name;
609
+
608
610
func->groups = fgroups;
611
+
func->ngroups += npins;
609
612
610
613
return 0;
611
614
}
···
743
718
int ret;
744
719
745
720
for (pin = 0; pin < zynqmp_desc.npins; pin++) {
746
-
ret = zynqmp_pinctrl_create_pin_groups(dev, groups, pin);
721
+
ret = zynqmp_pinctrl_create_pin_groups(dev, groups, zynqmp_desc.pins[pin].number);
747
722
if (ret)
748
723
return ret;
749
724
}
···
797
772
if (!groups)
798
773
return -ENOMEM;
799
774
775
+
ret = zynqmp_pinctrl_prepare_group_pins(dev, groups, pctrl->ngroups);
776
+
if (ret)
777
+
return ret;
778
+
800
779
for (i = 0; i < pctrl->nfuncs; i++) {
801
780
ret = zynqmp_pinctrl_prepare_func_groups(dev, i, &funcs[i],
802
781
groups);
803
782
if (ret)
804
783
return ret;
805
784
}
806
-
807
-
ret = zynqmp_pinctrl_prepare_group_pins(dev, groups, pctrl->ngroups);
808
-
if (ret)
809
-
return ret;
810
785
811
786
pctrl->funcs = funcs;
812
787
pctrl->groups = groups;
+8
-11
drivers/pinctrl/pinmux.c
+8
-11
drivers/pinctrl/pinmux.c
···
796
796
if (!function)
797
797
return NULL;
798
798
799
-
return function->name;
799
+
return function->func.name;
800
800
}
801
801
EXPORT_SYMBOL_GPL(pinmux_generic_get_function_name);
802
802
···
805
805
* @pctldev: pin controller device
806
806
* @selector: function number
807
807
* @groups: array of pin groups
808
-
* @num_groups: number of pin groups
808
+
* @ngroups: number of pin groups
809
809
*/
810
810
int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev,
811
811
unsigned int selector,
812
812
const char * const **groups,
813
-
unsigned int * const num_groups)
813
+
unsigned int * const ngroups)
814
814
{
815
815
struct function_desc *function;
816
816
···
821
821
__func__, selector);
822
822
return -EINVAL;
823
823
}
824
-
*groups = function->group_names;
825
-
*num_groups = function->num_group_names;
824
+
*groups = function->func.groups;
825
+
*ngroups = function->func.ngroups;
826
826
827
827
return 0;
828
828
}
···
852
852
* @pctldev: pin controller device
853
853
* @name: name of the function
854
854
* @groups: array of pin groups
855
-
* @num_groups: number of pin groups
855
+
* @ngroups: number of pin groups
856
856
* @data: pin controller driver specific data
857
857
*/
858
858
int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
859
859
const char *name,
860
860
const char * const *groups,
861
-
const unsigned int num_groups,
861
+
const unsigned int ngroups,
862
862
void *data)
863
863
{
864
864
struct function_desc *function;
···
877
877
if (!function)
878
878
return -ENOMEM;
879
879
880
-
function->name = name;
881
-
function->group_names = groups;
882
-
function->num_group_names = num_groups;
883
-
function->data = data;
880
+
*function = PINCTRL_FUNCTION_DESC(name, groups, ngroups, data);
884
881
885
882
error = radix_tree_insert(&pctldev->pin_function_tree, selector, function);
886
883
if (error)
+11
-8
drivers/pinctrl/pinmux.h
+11
-8
drivers/pinctrl/pinmux.h
···
133
133
134
134
/**
135
135
* struct function_desc - generic function descriptor
136
-
* @name: name of the function
137
-
* @group_names: array of pin group names
138
-
* @num_group_names: number of pin group names
136
+
* @func: generic data of the pin function (name and groups of pins)
139
137
* @data: pin controller driver specific data
140
138
*/
141
139
struct function_desc {
142
-
const char *name;
143
-
const char * const *group_names;
144
-
int num_group_names;
140
+
struct pinfunction func;
145
141
void *data;
146
142
};
143
+
144
+
/* Convenient macro to define a generic pin function descriptor */
145
+
#define PINCTRL_FUNCTION_DESC(_name, _grps, _num_grps, _data) \
146
+
(struct function_desc) { \
147
+
.func = PINCTRL_PINFUNCTION(_name, _grps, _num_grps), \
148
+
.data = _data, \
149
+
}
147
150
148
151
int pinmux_generic_get_function_count(struct pinctrl_dev *pctldev);
149
152
···
157
154
int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev,
158
155
unsigned int selector,
159
156
const char * const **groups,
160
-
unsigned int * const num_groups);
157
+
unsigned int * const ngroups);
161
158
162
159
struct function_desc *pinmux_generic_get_function(struct pinctrl_dev *pctldev,
163
160
unsigned int selector);
···
165
162
int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
166
163
const char *name,
167
164
const char * const *groups,
168
-
unsigned int const num_groups,
165
+
unsigned int const ngroups,
169
166
void *data);
170
167
171
168
int pinmux_generic_remove_function(struct pinctrl_dev *pctldev,
+9
drivers/pinctrl/qcom/Kconfig
+9
drivers/pinctrl/qcom/Kconfig
···
68
68
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
69
69
(Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
70
70
71
+
config PINCTRL_SM4250_LPASS_LPI
72
+
tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver"
73
+
depends on ARM64 || COMPILE_TEST
74
+
depends on PINCTRL_LPASS_LPI
75
+
help
76
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
77
+
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
78
+
(Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform.
79
+
71
80
config PINCTRL_SM6115_LPASS_LPI
72
81
tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver"
73
82
depends on ARM64 || COMPILE_TEST
+1
drivers/pinctrl/qcom/Makefile
+1
drivers/pinctrl/qcom/Makefile
···
43
43
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
44
44
obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
45
45
obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o
46
+
obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o
46
47
obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o
47
48
obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
48
49
obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o
+1
-1
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+1
-1
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+19
drivers/pinctrl/qcom/pinctrl-sdm670.c
+19
drivers/pinctrl/qcom/pinctrl-sdm670.c
···
1290
1290
58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74, 104, -1
1291
1291
};
1292
1292
1293
+
static const struct msm_gpio_wakeirq_map sdm670_pdc_map[] = {
1294
+
{ 1, 30 }, { 3, 31 }, { 5, 32 }, { 10, 33 }, { 11, 34 },
1295
+
{ 20, 35 }, { 22, 36 }, { 24, 37 }, { 26, 38 }, { 30, 39 },
1296
+
{ 31, 117 }, { 32, 41 }, { 34, 42 }, { 36, 43 }, { 37, 44 },
1297
+
{ 38, 45 }, { 39, 46 }, { 40, 47 }, { 41, 115 }, { 43, 49 },
1298
+
{ 44, 50 }, { 46, 51 }, { 48, 52 }, { 49, 118 }, { 52, 54 },
1299
+
{ 53, 55 }, { 54, 56 }, { 56, 57 }, { 57, 58 }, { 66, 66 },
1300
+
{ 68, 67 }, { 77, 70 }, { 78, 71 }, { 79, 72 }, { 80, 73 },
1301
+
{ 84, 74 }, { 85, 75 }, { 86, 76 }, { 88, 77 }, { 89, 116 },
1302
+
{ 91, 79 }, { 92, 80 }, { 95, 81 }, { 96, 82 }, { 97, 83 },
1303
+
{ 101, 84 }, { 103, 85 }, { 115, 90 }, { 116, 91 }, { 117, 92 },
1304
+
{ 118, 93 }, { 119, 94 }, { 120, 95 }, { 121, 96 }, { 122, 97 },
1305
+
{ 123, 98 }, { 124, 99 }, { 125, 100 }, { 127, 102 }, { 128, 103 },
1306
+
{ 129, 104 }, { 130, 105 }, { 132, 106 }, { 133, 107 }, { 145, 108 },
1307
+
};
1308
+
1293
1309
static const struct msm_pinctrl_soc_data sdm670_pinctrl = {
1294
1310
.pins = sdm670_pins,
1295
1311
.npins = ARRAY_SIZE(sdm670_pins),
···
1315
1299
.ngroups = ARRAY_SIZE(sdm670_groups),
1316
1300
.ngpios = 151,
1317
1301
.reserved_gpios = sdm670_reserved_gpios,
1302
+
.wakeirq_map = sdm670_pdc_map,
1303
+
.nwakeirq_map = ARRAY_SIZE(sdm670_pdc_map),
1304
+
.wakeirq_dual_edge_errata = true,
1318
1305
};
1319
1306
1320
1307
static int sdm670_pinctrl_probe(struct platform_device *pdev)
+236
drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
+236
drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2020, 2023 Linaro Ltd.
5
+
*/
6
+
7
+
#include <linux/gpio/driver.h>
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
11
+
#include "pinctrl-lpass-lpi.h"
12
+
13
+
enum lpass_lpi_functions {
14
+
LPI_MUX_dmic01_clk,
15
+
LPI_MUX_dmic01_data,
16
+
LPI_MUX_dmic23_clk,
17
+
LPI_MUX_dmic23_data,
18
+
LPI_MUX_dmic4_clk,
19
+
LPI_MUX_dmic4_data,
20
+
LPI_MUX_ext_mclk0_a,
21
+
LPI_MUX_ext_mclk0_b,
22
+
LPI_MUX_ext_mclk1_a,
23
+
LPI_MUX_ext_mclk1_b,
24
+
LPI_MUX_ext_mclk1_c,
25
+
LPI_MUX_i2s1_clk,
26
+
LPI_MUX_i2s1_data,
27
+
LPI_MUX_i2s1_ws,
28
+
LPI_MUX_i2s2_clk,
29
+
LPI_MUX_i2s2_data,
30
+
LPI_MUX_i2s2_ws,
31
+
LPI_MUX_i2s3_clk,
32
+
LPI_MUX_i2s3_data,
33
+
LPI_MUX_i2s3_ws,
34
+
LPI_MUX_qup_io_00,
35
+
LPI_MUX_qup_io_01,
36
+
LPI_MUX_qup_io_05,
37
+
LPI_MUX_qup_io_10,
38
+
LPI_MUX_qup_io_11,
39
+
LPI_MUX_qup_io_25,
40
+
LPI_MUX_qup_io_21,
41
+
LPI_MUX_qup_io_26,
42
+
LPI_MUX_qup_io_31,
43
+
LPI_MUX_qup_io_36,
44
+
LPI_MUX_qua_mi2s_data,
45
+
LPI_MUX_qua_mi2s_sclk,
46
+
LPI_MUX_qua_mi2s_ws,
47
+
LPI_MUX_slim_clk,
48
+
LPI_MUX_slim_data,
49
+
LPI_MUX_sync_out,
50
+
LPI_MUX_swr_rx_clk,
51
+
LPI_MUX_swr_rx_data,
52
+
LPI_MUX_swr_tx_clk,
53
+
LPI_MUX_swr_tx_data,
54
+
LPI_MUX_swr_wsa_clk,
55
+
LPI_MUX_swr_wsa_data,
56
+
LPI_MUX_gpio,
57
+
LPI_MUX__,
58
+
};
59
+
60
+
static const struct pinctrl_pin_desc sm4250_lpi_pins[] = {
61
+
PINCTRL_PIN(0, "gpio0"),
62
+
PINCTRL_PIN(1, "gpio1"),
63
+
PINCTRL_PIN(2, "gpio2"),
64
+
PINCTRL_PIN(3, "gpio3"),
65
+
PINCTRL_PIN(4, "gpio4"),
66
+
PINCTRL_PIN(5, "gpio5"),
67
+
PINCTRL_PIN(6, "gpio6"),
68
+
PINCTRL_PIN(7, "gpio7"),
69
+
PINCTRL_PIN(8, "gpio8"),
70
+
PINCTRL_PIN(9, "gpio9"),
71
+
PINCTRL_PIN(10, "gpio10"),
72
+
PINCTRL_PIN(11, "gpio11"),
73
+
PINCTRL_PIN(12, "gpio12"),
74
+
PINCTRL_PIN(13, "gpio13"),
75
+
PINCTRL_PIN(14, "gpio14"),
76
+
PINCTRL_PIN(15, "gpio15"),
77
+
PINCTRL_PIN(16, "gpio16"),
78
+
PINCTRL_PIN(17, "gpio17"),
79
+
PINCTRL_PIN(18, "gpio18"),
80
+
PINCTRL_PIN(19, "gpio19"),
81
+
PINCTRL_PIN(20, "gpio20"),
82
+
PINCTRL_PIN(21, "gpio21"),
83
+
PINCTRL_PIN(22, "gpio22"),
84
+
PINCTRL_PIN(23, "gpio23"),
85
+
PINCTRL_PIN(24, "gpio24"),
86
+
PINCTRL_PIN(25, "gpio25"),
87
+
PINCTRL_PIN(26, "gpio26"),
88
+
};
89
+
90
+
static const char * const dmic01_clk_groups[] = { "gpio6" };
91
+
static const char * const dmic01_data_groups[] = { "gpio7" };
92
+
static const char * const dmic23_clk_groups[] = { "gpio8" };
93
+
static const char * const dmic23_data_groups[] = { "gpio9" };
94
+
static const char * const dmic4_clk_groups[] = { "gpio10" };
95
+
static const char * const dmic4_data_groups[] = { "gpio11" };
96
+
static const char * const ext_mclk0_a_groups[] = { "gpio13" };
97
+
static const char * const ext_mclk0_b_groups[] = { "gpio5" };
98
+
static const char * const ext_mclk1_a_groups[] = { "gpio18" };
99
+
static const char * const ext_mclk1_b_groups[] = { "gpio9" };
100
+
static const char * const ext_mclk1_c_groups[] = { "gpio17" };
101
+
static const char * const slim_clk_groups[] = { "gpio14" };
102
+
static const char * const slim_data_groups[] = { "gpio15" };
103
+
static const char * const i2s1_clk_groups[] = { "gpio6" };
104
+
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
105
+
static const char * const i2s1_ws_groups[] = { "gpio7" };
106
+
static const char * const i2s2_clk_groups[] = { "gpio10" };
107
+
static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
108
+
static const char * const i2s2_ws_groups[] = { "gpio11" };
109
+
static const char * const i2s3_clk_groups[] = { "gpio14" };
110
+
static const char * const i2s3_data_groups[] = { "gpio16", "gpio17" };
111
+
static const char * const i2s3_ws_groups[] = { "gpio15" };
112
+
static const char * const qup_io_00_groups[] = { "gpio19" };
113
+
static const char * const qup_io_01_groups[] = { "gpio21" };
114
+
static const char * const qup_io_05_groups[] = { "gpio23" };
115
+
static const char * const qup_io_10_groups[] = { "gpio20" };
116
+
static const char * const qup_io_11_groups[] = { "gpio22" };
117
+
static const char * const qup_io_25_groups[] = { "gpio23" };
118
+
static const char * const qup_io_21_groups[] = { "gpio25" };
119
+
static const char * const qup_io_26_groups[] = { "gpio25" };
120
+
static const char * const qup_io_31_groups[] = { "gpio26" };
121
+
static const char * const qup_io_36_groups[] = { "gpio26" };
122
+
static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
123
+
static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
124
+
static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
125
+
static const char * const sync_out_groups[] = { "gpio19", "gpio20", "gpio21", "gpio22",
126
+
"gpio23", "gpio24", "gpio25", "gpio26"};
127
+
static const char * const swr_rx_clk_groups[] = { "gpio3" };
128
+
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
129
+
static const char * const swr_tx_clk_groups[] = { "gpio0" };
130
+
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2" };
131
+
static const char * const swr_wsa_clk_groups[] = { "gpio10" };
132
+
static const char * const swr_wsa_data_groups[] = { "gpio11" };
133
+
134
+
135
+
static const struct lpi_pingroup sm4250_groups[] = {
136
+
LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
137
+
LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
138
+
LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
139
+
LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
140
+
LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
141
+
LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk0_b, qua_mi2s_data, _),
142
+
LPI_PINGROUP(6, LPI_NO_SLEW, dmic01_clk, i2s1_clk, _, _),
143
+
LPI_PINGROUP(7, LPI_NO_SLEW, dmic01_data, i2s1_ws, _, _),
144
+
LPI_PINGROUP(8, LPI_NO_SLEW, dmic23_clk, i2s1_data, _, _),
145
+
LPI_PINGROUP(9, LPI_NO_SLEW, dmic23_data, i2s1_data, ext_mclk1_b, _),
146
+
LPI_PINGROUP(10, 16, i2s2_clk, swr_wsa_clk, dmic4_clk, _),
147
+
LPI_PINGROUP(11, 18, i2s2_ws, swr_wsa_data, dmic4_data, _),
148
+
LPI_PINGROUP(12, LPI_NO_SLEW, dmic23_clk, i2s2_data, _, _),
149
+
LPI_PINGROUP(13, LPI_NO_SLEW, dmic23_data, i2s2_data, ext_mclk0_a, _),
150
+
LPI_PINGROUP(14, LPI_NO_SLEW, i2s3_clk, slim_clk, _, _),
151
+
LPI_PINGROUP(15, LPI_NO_SLEW, i2s3_ws, slim_data, _, _),
152
+
LPI_PINGROUP(16, LPI_NO_SLEW, i2s3_data, _, _, _),
153
+
LPI_PINGROUP(17, LPI_NO_SLEW, i2s3_data, ext_mclk1_c, _, _),
154
+
LPI_PINGROUP(18, 20, ext_mclk1_a, swr_rx_data, _, _),
155
+
LPI_PINGROUP(19, LPI_NO_SLEW, qup_io_00, sync_out, _, _),
156
+
LPI_PINGROUP(20, LPI_NO_SLEW, qup_io_10, sync_out, _, _),
157
+
LPI_PINGROUP(21, LPI_NO_SLEW, qup_io_01, sync_out, _, _),
158
+
LPI_PINGROUP(22, LPI_NO_SLEW, qup_io_11, sync_out, _, _),
159
+
LPI_PINGROUP(23, LPI_NO_SLEW, qup_io_25, qup_io_05, sync_out, _),
160
+
LPI_PINGROUP(25, LPI_NO_SLEW, qup_io_26, qup_io_21, sync_out, _),
161
+
LPI_PINGROUP(26, LPI_NO_SLEW, qup_io_36, qup_io_31, sync_out, _),
162
+
};
163
+
164
+
static const struct lpi_function sm4250_functions[] = {
165
+
LPI_FUNCTION(dmic01_clk),
166
+
LPI_FUNCTION(dmic01_data),
167
+
LPI_FUNCTION(dmic23_clk),
168
+
LPI_FUNCTION(dmic23_data),
169
+
LPI_FUNCTION(dmic4_clk),
170
+
LPI_FUNCTION(dmic4_data),
171
+
LPI_FUNCTION(ext_mclk0_a),
172
+
LPI_FUNCTION(ext_mclk0_b),
173
+
LPI_FUNCTION(ext_mclk1_a),
174
+
LPI_FUNCTION(ext_mclk1_b),
175
+
LPI_FUNCTION(ext_mclk1_c),
176
+
LPI_FUNCTION(i2s1_clk),
177
+
LPI_FUNCTION(i2s1_data),
178
+
LPI_FUNCTION(i2s1_ws),
179
+
LPI_FUNCTION(i2s2_clk),
180
+
LPI_FUNCTION(i2s2_data),
181
+
LPI_FUNCTION(i2s2_ws),
182
+
LPI_FUNCTION(i2s3_clk),
183
+
LPI_FUNCTION(i2s3_data),
184
+
LPI_FUNCTION(i2s3_ws),
185
+
LPI_FUNCTION(qup_io_00),
186
+
LPI_FUNCTION(qup_io_01),
187
+
LPI_FUNCTION(qup_io_05),
188
+
LPI_FUNCTION(qup_io_10),
189
+
LPI_FUNCTION(qup_io_11),
190
+
LPI_FUNCTION(qup_io_25),
191
+
LPI_FUNCTION(qup_io_21),
192
+
LPI_FUNCTION(qup_io_26),
193
+
LPI_FUNCTION(qup_io_31),
194
+
LPI_FUNCTION(qup_io_36),
195
+
LPI_FUNCTION(qua_mi2s_data),
196
+
LPI_FUNCTION(qua_mi2s_sclk),
197
+
LPI_FUNCTION(qua_mi2s_ws),
198
+
LPI_FUNCTION(slim_clk),
199
+
LPI_FUNCTION(slim_data),
200
+
LPI_FUNCTION(sync_out),
201
+
LPI_FUNCTION(swr_rx_clk),
202
+
LPI_FUNCTION(swr_rx_data),
203
+
LPI_FUNCTION(swr_tx_clk),
204
+
LPI_FUNCTION(swr_tx_data),
205
+
LPI_FUNCTION(swr_wsa_clk),
206
+
LPI_FUNCTION(swr_wsa_data),
207
+
};
208
+
209
+
static const struct lpi_pinctrl_variant_data sm4250_lpi_data = {
210
+
.pins = sm4250_lpi_pins,
211
+
.npins = ARRAY_SIZE(sm4250_lpi_pins),
212
+
.groups = sm4250_groups,
213
+
.ngroups = ARRAY_SIZE(sm4250_groups),
214
+
.functions = sm4250_functions,
215
+
.nfunctions = ARRAY_SIZE(sm4250_functions),
216
+
};
217
+
218
+
static const struct of_device_id lpi_pinctrl_of_match[] = {
219
+
{ .compatible = "qcom,sm4250-lpass-lpi-pinctrl", .data = &sm4250_lpi_data },
220
+
{ }
221
+
};
222
+
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
223
+
224
+
static struct platform_driver lpi_pinctrl_driver = {
225
+
.driver = {
226
+
.name = "qcom-sm4250-lpass-lpi-pinctrl",
227
+
.of_match_table = lpi_pinctrl_of_match,
228
+
},
229
+
.probe = lpi_pinctrl_probe,
230
+
.remove_new = lpi_pinctrl_remove,
231
+
};
232
+
233
+
module_platform_driver(lpi_pinctrl_driver);
234
+
MODULE_DESCRIPTION("QTI SM4250 LPI GPIO pin control driver");
235
+
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
236
+
MODULE_LICENSE("GPL");
+1
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+1
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
···
1234
1234
{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1235
1235
{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1236
1236
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1237
+
{ .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 },
1237
1238
{ .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 },
1238
1239
{ .compatible = "qcom,pmi632-gpio", .data = (void *) 8 },
1239
1240
{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
+464
-370
drivers/pinctrl/renesas/pfc-r8a779g0.c
+464
-370
drivers/pinctrl/renesas/pfc-r8a779g0.c
···
68
68
#define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
69
69
#define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
70
70
#define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
71
-
#define GPSR0_6 F_(IRQ0, IP0SR0_27_24)
72
-
#define GPSR0_5 F_(IRQ1, IP0SR0_23_20)
73
-
#define GPSR0_4 F_(IRQ2, IP0SR0_19_16)
74
-
#define GPSR0_3 F_(IRQ3, IP0SR0_15_12)
71
+
#define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24)
72
+
#define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20)
73
+
#define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16)
74
+
#define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12)
75
75
#define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
76
76
#define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
77
77
#define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
78
78
79
79
/* GPSR1 */
80
-
#define GPSR1_28 F_(HTX3, IP3SR1_19_16)
81
-
#define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12)
82
-
#define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8)
83
-
#define GPSR1_25 F_(HSCK3, IP3SR1_7_4)
84
-
#define GPSR1_24 F_(HRX3, IP3SR1_3_0)
80
+
#define GPSR1_28 F_(HTX3_A, IP3SR1_19_16)
81
+
#define GPSR1_27 F_(HCTS3_N_A, IP3SR1_15_12)
82
+
#define GPSR1_26 F_(HRTS3_N_A, IP3SR1_11_8)
83
+
#define GPSR1_25 F_(HSCK3_A, IP3SR1_7_4)
84
+
#define GPSR1_24 F_(HRX3_A, IP3SR1_3_0)
85
85
#define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
86
86
#define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
87
87
#define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
···
119
119
#define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)
120
120
#define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)
121
121
#define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)
122
-
#define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0)
123
-
#define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)
122
+
#define GPSR2_8 F_(TPU0TO0_A, IP1SR2_3_0)
123
+
#define GPSR2_7 F_(TPU0TO1_A, IP0SR2_31_28)
124
124
#define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
125
-
#define GPSR2_5 F_(FXR_TXENB_N, IP0SR2_23_20)
125
+
#define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20)
126
126
#define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
127
127
#define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)
128
128
#define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)
129
-
#define GPSR2_1 F_(FXR_TXENA_N, IP0SR2_7_4)
129
+
#define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4)
130
130
#define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)
131
131
132
132
/* GPSR3 */
···
275
275
276
276
/* SR0 */
277
277
/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
278
-
#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278
+
#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279
279
#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280
280
#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281
-
#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282
-
#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283
-
#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284
-
#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281
+
#define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282
+
#define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283
+
#define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284
+
#define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285
285
#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286
286
287
287
/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
···
290
290
#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291
291
#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292
292
#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293
-
#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294
-
#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295
-
#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293
+
#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294
+
#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295
+
#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296
296
297
297
/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
298
-
#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299
-
#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300
-
#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298
+
#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299
+
#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300
+
#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301
301
302
302
/* SR1 */
303
303
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
304
-
#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305
-
#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306
-
#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307
-
#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308
-
#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304
+
#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305
+
#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306
+
#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307
+
#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308
+
#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309
309
#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310
-
#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311
-
#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310
+
#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311
+
#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312
312
313
313
/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
314
-
#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) FM(CTS1_N_X) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315
-
#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) FM(RTS1_N_X) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316
-
#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314
+
#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315
+
#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316
+
#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317
317
#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318
318
#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319
-
#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320
-
#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321
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#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319
+
#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320
+
#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321
+
#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325
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#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326
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#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327
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#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328
-
#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329
-
#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326
+
#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327
+
#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328
+
#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329
+
#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330
330
#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331
-
#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331
+
#define IP2SR1_31_28 F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
334
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#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335
-
#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336
-
#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337
-
#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338
-
#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334
+
#define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335
+
#define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336
+
#define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337
+
#define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338
+
#define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339
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340
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/* SR2 */
341
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/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
342
-
#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343
-
#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344
-
#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345
-
#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342
+
#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343
+
#define IP0SR2_7_4 FM(FXR_TXENA_N_A) FM(CANFD1_RX) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344
+
#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX_A) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345
+
#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX_A) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346
346
#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347
-
#define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347
+
#define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348
348
#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349
-
#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349
+
#define IP0SR2_31_28 FM(TPU0TO1_A) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350
350
351
351
/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
352
-
#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353
-
#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354
-
#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352
+
#define IP1SR2_3_0 FM(TPU0TO0_A) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353
+
#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354
+
#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355
355
#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356
-
#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357
-
#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358
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#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356
+
#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357
+
#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358
+
#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359
359
#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360
360
361
361
/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
···
381
381
#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382
382
#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383
383
#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384
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#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385
-
#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384
+
#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385
+
#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386
386
#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387
387
388
388
/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
···
718
718
719
719
/* IP0SR0 */
720
720
PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B),
721
-
PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_A),
721
+
PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_B),
722
722
723
723
PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
724
724
725
725
PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),
726
726
727
-
PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3),
727
+
PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A),
728
728
PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),
729
729
730
-
PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2),
730
+
PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A),
731
731
PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),
732
732
733
-
PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1),
733
+
PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A),
734
734
PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),
735
735
736
-
PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0),
736
+
PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A),
737
737
PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),
738
738
739
739
PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),
···
750
750
PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD),
751
751
752
752
PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),
753
-
PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1),
754
-
PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_A),
753
+
PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1_A),
754
+
PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_B),
755
755
756
756
PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
757
-
PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1),
758
-
PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1),
757
+
PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A),
758
+
PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A),
759
759
760
760
PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),
761
-
PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1),
762
-
PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1),
761
+
PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A),
762
+
PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A),
763
763
764
764
/* IP2SR0 */
765
765
PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),
766
-
PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N),
767
-
PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N),
766
+
PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A),
767
+
PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A),
768
768
769
769
PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),
770
-
PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N),
771
-
PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N),
770
+
PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A),
771
+
PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A),
772
772
773
773
PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),
774
-
PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1),
775
-
PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1),
774
+
PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A),
775
+
PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A),
776
776
777
777
/* IP0SR1 */
778
778
PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
779
-
PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A),
780
-
PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3),
779
+
PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B),
780
+
PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B),
781
781
782
782
PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
783
-
PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_A),
784
-
PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3),
783
+
PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B),
784
+
PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B),
785
785
786
786
PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
787
-
PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_A),
788
-
PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N),
787
+
PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B),
788
+
PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B),
789
789
790
790
PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
791
-
PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A),
792
-
PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N),
791
+
PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B),
792
+
PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B),
793
793
794
794
PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
795
-
PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
796
-
PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3),
795
+
PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B),
796
+
PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B),
797
797
798
798
PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
799
799
800
800
PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
801
-
PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_X),
802
-
PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_X),
801
+
PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B),
802
+
PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B),
803
803
804
804
PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
805
-
PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_X),
806
-
PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_X),
805
+
PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B),
806
+
PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B),
807
807
808
808
/* IP1SR1 */
809
809
PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
810
-
PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_X),
811
-
PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_X),
810
+
PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B),
811
+
PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B),
812
812
PINMUX_IPSR_GPSR(IP1SR1_3_0, CANFD5_TX_B),
813
813
814
814
PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
815
-
PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_X),
816
-
PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_X),
815
+
PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B),
816
+
PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B),
817
817
PINMUX_IPSR_GPSR(IP1SR1_7_4, CANFD5_RX_B),
818
818
819
819
PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
820
-
PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_X),
821
-
PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_X),
820
+
PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B),
821
+
PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B),
822
822
823
823
PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
824
824
···
827
827
828
828
PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
829
829
PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
830
-
PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8_A),
830
+
PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8),
831
831
832
832
PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
833
833
PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
834
-
PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9_A),
834
+
PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9),
835
835
836
836
PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
837
837
PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
838
-
PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A),
838
+
PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),
839
839
840
840
/* IP2SR1 */
841
841
PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
···
845
845
PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A),
846
846
847
847
PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK),
848
-
PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3),
848
+
PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3_B),
849
849
850
850
PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS),
851
-
PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4),
851
+
PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4_B),
852
852
853
853
PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),
854
-
PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_A),
854
+
PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_B),
855
855
856
856
PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),
857
-
PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_A),
857
+
PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_B),
858
858
859
859
PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
860
860
PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_A),
861
861
862
-
PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2),
862
+
PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2_A),
863
863
PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
864
864
PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),
865
865
866
866
/* IP3SR1 */
867
-
PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
867
+
PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A),
868
868
PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
869
869
PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
870
870
871
-
PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
871
+
PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A),
872
872
PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),
873
873
PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
874
-
PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_A),
874
+
PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B),
875
875
876
-
PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
876
+
PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A),
877
877
PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),
878
878
PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
879
-
PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_A),
879
+
PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B),
880
880
881
-
PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
881
+
PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A),
882
882
PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
883
883
PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
884
884
885
-
PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
885
+
PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A),
886
886
PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
887
887
PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
888
888
889
889
/* IP0SR2 */
890
890
PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
891
891
PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
892
-
PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_A),
892
+
PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B),
893
893
894
-
PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N),
894
+
PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A),
895
895
PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
896
-
PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_A),
896
+
PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B),
897
897
898
898
PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
899
-
PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX),
899
+
PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX_A),
900
900
PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5),
901
901
902
902
PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),
903
-
PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX),
903
+
PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX_A),
904
904
PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B),
905
905
906
906
PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),
907
907
908
-
PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N),
908
+
PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A),
909
909
910
910
PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),
911
911
912
-
PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1),
912
+
PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A),
913
913
PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),
914
-
PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_B),
914
+
PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C),
915
915
916
916
/* IP1SR2 */
917
-
PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0),
917
+
PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A),
918
918
PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX),
919
-
PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_A),
919
+
PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B),
920
920
921
921
PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
922
-
PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_X),
922
+
PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B),
923
923
924
924
PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),
925
-
PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_X),
925
+
PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B),
926
926
927
927
PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
928
928
PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
929
929
930
930
PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
931
-
PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2),
932
-
PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_A),
931
+
PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A),
932
+
PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C),
933
933
934
934
PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
935
-
PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3),
935
+
PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A),
936
936
PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),
937
-
PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A),
937
+
PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C),
938
938
939
939
PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
940
-
PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B),
940
+
PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),
941
941
942
942
PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
943
943
PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),
···
979
979
PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),
980
980
PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),
981
981
PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A),
982
-
PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_X),
982
+
PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_A),
983
983
984
984
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
985
985
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),
986
986
PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_N_A),
987
-
PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_X),
987
+
PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_A),
988
988
989
989
PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
990
990
···
1531
1531
};
1532
1532
1533
1533
/* - CANFD5 ----------------------------------------------------------------- */
1534
-
static const unsigned int canfd5_data_pins[] = {
1535
-
/* CANFD5_TX, CANFD5_RX */
1534
+
static const unsigned int canfd5_data_a_pins[] = {
1535
+
/* CANFD5_TX_A, CANFD5_RX_A */
1536
1536
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1537
1537
};
1538
-
static const unsigned int canfd5_data_mux[] = {
1539
-
CANFD5_TX_MARK, CANFD5_RX_MARK,
1538
+
static const unsigned int canfd5_data_a_mux[] = {
1539
+
CANFD5_TX_A_MARK, CANFD5_RX_A_MARK,
1540
1540
};
1541
1541
1542
-
/* - CANFD5_B ----------------------------------------------------------------- */
1543
1542
static const unsigned int canfd5_data_b_pins[] = {
1544
1543
/* CANFD5_TX_B, CANFD5_RX_B */
1545
1544
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
···
1598
1599
};
1599
1600
1600
1601
/* - HSCIF1 ----------------------------------------------------------------- */
1601
-
static const unsigned int hscif1_data_pins[] = {
1602
-
/* HRX1, HTX1 */
1602
+
static const unsigned int hscif1_data_a_pins[] = {
1603
+
/* HRX1_A, HTX1_A */
1603
1604
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1604
1605
};
1605
-
static const unsigned int hscif1_data_mux[] = {
1606
-
HRX1_MARK, HTX1_MARK,
1606
+
static const unsigned int hscif1_data_a_mux[] = {
1607
+
HRX1_A_MARK, HTX1_A_MARK,
1607
1608
};
1608
-
static const unsigned int hscif1_clk_pins[] = {
1609
-
/* HSCK1 */
1609
+
static const unsigned int hscif1_clk_a_pins[] = {
1610
+
/* HSCK1_A */
1610
1611
RCAR_GP_PIN(0, 18),
1611
1612
};
1612
-
static const unsigned int hscif1_clk_mux[] = {
1613
-
HSCK1_MARK,
1613
+
static const unsigned int hscif1_clk_a_mux[] = {
1614
+
HSCK1_A_MARK,
1614
1615
};
1615
-
static const unsigned int hscif1_ctrl_pins[] = {
1616
-
/* HRTS1_N, HCTS1_N */
1616
+
static const unsigned int hscif1_ctrl_a_pins[] = {
1617
+
/* HRTS1_N_A, HCTS1_N_A */
1617
1618
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1618
1619
};
1619
-
static const unsigned int hscif1_ctrl_mux[] = {
1620
-
HRTS1_N_MARK, HCTS1_N_MARK,
1620
+
static const unsigned int hscif1_ctrl_a_mux[] = {
1621
+
HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1621
1622
};
1622
1623
1623
-
/* - HSCIF1_X---------------------------------------------------------------- */
1624
-
static const unsigned int hscif1_data_x_pins[] = {
1625
-
/* HRX1_X, HTX1_X */
1624
+
static const unsigned int hscif1_data_b_pins[] = {
1625
+
/* HRX1_B, HTX1_B */
1626
1626
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1627
1627
};
1628
-
static const unsigned int hscif1_data_x_mux[] = {
1629
-
HRX1_X_MARK, HTX1_X_MARK,
1628
+
static const unsigned int hscif1_data_b_mux[] = {
1629
+
HRX1_B_MARK, HTX1_B_MARK,
1630
1630
};
1631
-
static const unsigned int hscif1_clk_x_pins[] = {
1632
-
/* HSCK1_X */
1631
+
static const unsigned int hscif1_clk_b_pins[] = {
1632
+
/* HSCK1_B */
1633
1633
RCAR_GP_PIN(1, 10),
1634
1634
};
1635
-
static const unsigned int hscif1_clk_x_mux[] = {
1636
-
HSCK1_X_MARK,
1635
+
static const unsigned int hscif1_clk_b_mux[] = {
1636
+
HSCK1_B_MARK,
1637
1637
};
1638
-
static const unsigned int hscif1_ctrl_x_pins[] = {
1639
-
/* HRTS1_N_X, HCTS1_N_X */
1638
+
static const unsigned int hscif1_ctrl_b_pins[] = {
1639
+
/* HRTS1_N_B, HCTS1_N_B */
1640
1640
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1641
1641
};
1642
-
static const unsigned int hscif1_ctrl_x_mux[] = {
1643
-
HRTS1_N_X_MARK, HCTS1_N_X_MARK,
1642
+
static const unsigned int hscif1_ctrl_b_mux[] = {
1643
+
HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1644
1644
};
1645
1645
1646
1646
/* - HSCIF2 ----------------------------------------------------------------- */
···
1666
1668
};
1667
1669
1668
1670
/* - HSCIF3 ----------------------------------------------------------------- */
1669
-
static const unsigned int hscif3_data_pins[] = {
1670
-
/* HRX3, HTX3 */
1671
-
RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1672
-
};
1673
-
static const unsigned int hscif3_data_mux[] = {
1674
-
HRX3_MARK, HTX3_MARK,
1675
-
};
1676
-
static const unsigned int hscif3_clk_pins[] = {
1677
-
/* HSCK3 */
1678
-
RCAR_GP_PIN(1, 25),
1679
-
};
1680
-
static const unsigned int hscif3_clk_mux[] = {
1681
-
HSCK3_MARK,
1682
-
};
1683
-
static const unsigned int hscif3_ctrl_pins[] = {
1684
-
/* HRTS3_N, HCTS3_N */
1685
-
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1686
-
};
1687
-
static const unsigned int hscif3_ctrl_mux[] = {
1688
-
HRTS3_N_MARK, HCTS3_N_MARK,
1689
-
};
1690
-
1691
-
/* - HSCIF3_A ----------------------------------------------------------------- */
1692
1671
static const unsigned int hscif3_data_a_pins[] = {
1693
1672
/* HRX3_A, HTX3_A */
1694
-
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1673
+
RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1695
1674
};
1696
1675
static const unsigned int hscif3_data_a_mux[] = {
1697
1676
HRX3_A_MARK, HTX3_A_MARK,
1698
1677
};
1699
1678
static const unsigned int hscif3_clk_a_pins[] = {
1700
1679
/* HSCK3_A */
1701
-
RCAR_GP_PIN(1, 3),
1680
+
RCAR_GP_PIN(1, 25),
1702
1681
};
1703
1682
static const unsigned int hscif3_clk_a_mux[] = {
1704
1683
HSCK3_A_MARK,
1705
1684
};
1706
1685
static const unsigned int hscif3_ctrl_a_pins[] = {
1707
1686
/* HRTS3_N_A, HCTS3_N_A */
1708
-
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1687
+
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1709
1688
};
1710
1689
static const unsigned int hscif3_ctrl_a_mux[] = {
1711
1690
HRTS3_N_A_MARK, HCTS3_N_A_MARK,
1691
+
};
1692
+
1693
+
static const unsigned int hscif3_data_b_pins[] = {
1694
+
/* HRX3_B, HTX3_B */
1695
+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1696
+
};
1697
+
static const unsigned int hscif3_data_b_mux[] = {
1698
+
HRX3_B_MARK, HTX3_B_MARK,
1699
+
};
1700
+
static const unsigned int hscif3_clk_b_pins[] = {
1701
+
/* HSCK3_B */
1702
+
RCAR_GP_PIN(1, 3),
1703
+
};
1704
+
static const unsigned int hscif3_clk_b_mux[] = {
1705
+
HSCK3_B_MARK,
1706
+
};
1707
+
static const unsigned int hscif3_ctrl_b_pins[] = {
1708
+
/* HRTS3_N_B, HCTS3_N_B */
1709
+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1710
+
};
1711
+
static const unsigned int hscif3_ctrl_b_mux[] = {
1712
+
HRTS3_N_B_MARK, HCTS3_N_B_MARK,
1712
1713
};
1713
1714
1714
1715
/* - I2C0 ------------------------------------------------------------------- */
···
1762
1765
};
1763
1766
static const unsigned int i2c5_mux[] = {
1764
1767
SDA5_MARK, SCL5_MARK,
1768
+
};
1769
+
1770
+
/* - INTC-EX ---------------------------------------------------------------- */
1771
+
static const unsigned int intc_ex_irq0_a_pins[] = {
1772
+
/* IRQ0_A */
1773
+
RCAR_GP_PIN(0, 6),
1774
+
};
1775
+
static const unsigned int intc_ex_irq0_a_mux[] = {
1776
+
IRQ0_A_MARK,
1777
+
};
1778
+
static const unsigned int intc_ex_irq0_b_pins[] = {
1779
+
/* IRQ0_B */
1780
+
RCAR_GP_PIN(1, 20),
1781
+
};
1782
+
static const unsigned int intc_ex_irq0_b_mux[] = {
1783
+
IRQ0_B_MARK,
1784
+
};
1785
+
1786
+
static const unsigned int intc_ex_irq1_a_pins[] = {
1787
+
/* IRQ1_A */
1788
+
RCAR_GP_PIN(0, 5),
1789
+
};
1790
+
static const unsigned int intc_ex_irq1_a_mux[] = {
1791
+
IRQ1_A_MARK,
1792
+
};
1793
+
static const unsigned int intc_ex_irq1_b_pins[] = {
1794
+
/* IRQ1_B */
1795
+
RCAR_GP_PIN(1, 21),
1796
+
};
1797
+
static const unsigned int intc_ex_irq1_b_mux[] = {
1798
+
IRQ1_B_MARK,
1799
+
};
1800
+
1801
+
static const unsigned int intc_ex_irq2_a_pins[] = {
1802
+
/* IRQ2_A */
1803
+
RCAR_GP_PIN(0, 4),
1804
+
};
1805
+
static const unsigned int intc_ex_irq2_a_mux[] = {
1806
+
IRQ2_A_MARK,
1807
+
};
1808
+
static const unsigned int intc_ex_irq2_b_pins[] = {
1809
+
/* IRQ2_B */
1810
+
RCAR_GP_PIN(0, 13),
1811
+
};
1812
+
static const unsigned int intc_ex_irq2_b_mux[] = {
1813
+
IRQ2_B_MARK,
1814
+
};
1815
+
1816
+
static const unsigned int intc_ex_irq3_a_pins[] = {
1817
+
/* IRQ3_A */
1818
+
RCAR_GP_PIN(0, 3),
1819
+
};
1820
+
static const unsigned int intc_ex_irq3_a_mux[] = {
1821
+
IRQ3_A_MARK,
1822
+
};
1823
+
static const unsigned int intc_ex_irq3_b_pins[] = {
1824
+
/* IRQ3_B */
1825
+
RCAR_GP_PIN(1, 23),
1826
+
};
1827
+
static const unsigned int intc_ex_irq3_b_mux[] = {
1828
+
IRQ3_B_MARK,
1829
+
};
1830
+
1831
+
static const unsigned int intc_ex_irq4_a_pins[] = {
1832
+
/* IRQ4_A */
1833
+
RCAR_GP_PIN(1, 17),
1834
+
};
1835
+
static const unsigned int intc_ex_irq4_a_mux[] = {
1836
+
IRQ4_A_MARK,
1837
+
};
1838
+
static const unsigned int intc_ex_irq4_b_pins[] = {
1839
+
/* IRQ4_B */
1840
+
RCAR_GP_PIN(2, 3),
1841
+
};
1842
+
static const unsigned int intc_ex_irq4_b_mux[] = {
1843
+
IRQ4_B_MARK,
1844
+
};
1845
+
1846
+
static const unsigned int intc_ex_irq5_pins[] = {
1847
+
/* IRQ5 */
1848
+
RCAR_GP_PIN(2, 2),
1849
+
};
1850
+
static const unsigned int intc_ex_irq5_mux[] = {
1851
+
IRQ5_MARK,
1765
1852
};
1766
1853
1767
1854
/* - MMC -------------------------------------------------------------------- */
···
2174
2093
PCIE1_CLKREQ_N_MARK,
2175
2094
};
2176
2095
2177
-
/* - PWM0_A ------------------------------------------------------------------- */
2178
-
static const unsigned int pwm0_a_pins[] = {
2179
-
/* PWM0_A */
2096
+
/* - PWM0 ------------------------------------------------------------------- */
2097
+
static const unsigned int pwm0_pins[] = {
2098
+
/* PWM0 */
2180
2099
RCAR_GP_PIN(1, 15),
2181
2100
};
2182
-
static const unsigned int pwm0_a_mux[] = {
2183
-
PWM0_A_MARK,
2101
+
static const unsigned int pwm0_mux[] = {
2102
+
PWM0_MARK,
2184
2103
};
2185
2104
2186
-
/* - PWM1_A ------------------------------------------------------------------- */
2105
+
/* - PWM1 ------------------------------------------------------------------- */
2187
2106
static const unsigned int pwm1_a_pins[] = {
2188
2107
/* PWM1_A */
2189
2108
RCAR_GP_PIN(3, 13),
···
2192
2111
PWM1_A_MARK,
2193
2112
};
2194
2113
2195
-
/* - PWM1_B ------------------------------------------------------------------- */
2196
2114
static const unsigned int pwm1_b_pins[] = {
2197
2115
/* PWM1_B */
2198
2116
RCAR_GP_PIN(2, 13),
···
2200
2120
PWM1_B_MARK,
2201
2121
};
2202
2122
2203
-
/* - PWM2_B ------------------------------------------------------------------- */
2204
-
static const unsigned int pwm2_b_pins[] = {
2205
-
/* PWM2_B */
2123
+
/* - PWM2 ------------------------------------------------------------------- */
2124
+
static const unsigned int pwm2_pins[] = {
2125
+
/* PWM2 */
2206
2126
RCAR_GP_PIN(2, 14),
2207
2127
};
2208
-
static const unsigned int pwm2_b_mux[] = {
2209
-
PWM2_B_MARK,
2128
+
static const unsigned int pwm2_mux[] = {
2129
+
PWM2_MARK,
2210
2130
};
2211
2131
2212
-
/* - PWM3_A ------------------------------------------------------------------- */
2132
+
/* - PWM3 ------------------------------------------------------------------- */
2213
2133
static const unsigned int pwm3_a_pins[] = {
2214
2134
/* PWM3_A */
2215
2135
RCAR_GP_PIN(1, 22),
···
2218
2138
PWM3_A_MARK,
2219
2139
};
2220
2140
2221
-
/* - PWM3_B ------------------------------------------------------------------- */
2222
2141
static const unsigned int pwm3_b_pins[] = {
2223
2142
/* PWM3_B */
2224
2143
RCAR_GP_PIN(2, 15),
···
2262
2183
PWM7_MARK,
2263
2184
};
2264
2185
2265
-
/* - PWM8_A ------------------------------------------------------------------- */
2266
-
static const unsigned int pwm8_a_pins[] = {
2267
-
/* PWM8_A */
2186
+
/* - PWM8 ------------------------------------------------------------------- */
2187
+
static const unsigned int pwm8_pins[] = {
2188
+
/* PWM8 */
2268
2189
RCAR_GP_PIN(1, 13),
2269
2190
};
2270
-
static const unsigned int pwm8_a_mux[] = {
2271
-
PWM8_A_MARK,
2191
+
static const unsigned int pwm8_mux[] = {
2192
+
PWM8_MARK,
2272
2193
};
2273
2194
2274
-
/* - PWM9_A ------------------------------------------------------------------- */
2275
-
static const unsigned int pwm9_a_pins[] = {
2276
-
/* PWM9_A */
2195
+
/* - PWM9 ------------------------------------------------------------------- */
2196
+
static const unsigned int pwm9_pins[] = {
2197
+
/* PWM9 */
2277
2198
RCAR_GP_PIN(1, 14),
2278
2199
};
2279
-
static const unsigned int pwm9_a_mux[] = {
2280
-
PWM9_A_MARK,
2200
+
static const unsigned int pwm9_mux[] = {
2201
+
PWM9_MARK,
2281
2202
};
2282
2203
2283
2204
/* - QSPI0 ------------------------------------------------------------------ */
···
2340
2261
};
2341
2262
2342
2263
/* - SCIF1 ------------------------------------------------------------------ */
2343
-
static const unsigned int scif1_data_pins[] = {
2344
-
/* RX1, TX1 */
2264
+
static const unsigned int scif1_data_a_pins[] = {
2265
+
/* RX1_A, TX1_A */
2345
2266
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2346
2267
};
2347
-
static const unsigned int scif1_data_mux[] = {
2348
-
RX1_MARK, TX1_MARK,
2268
+
static const unsigned int scif1_data_a_mux[] = {
2269
+
RX1_A_MARK, TX1_A_MARK,
2349
2270
};
2350
-
static const unsigned int scif1_clk_pins[] = {
2351
-
/* SCK1 */
2271
+
static const unsigned int scif1_clk_a_pins[] = {
2272
+
/* SCK1_A */
2352
2273
RCAR_GP_PIN(0, 18),
2353
2274
};
2354
-
static const unsigned int scif1_clk_mux[] = {
2355
-
SCK1_MARK,
2275
+
static const unsigned int scif1_clk_a_mux[] = {
2276
+
SCK1_A_MARK,
2356
2277
};
2357
-
static const unsigned int scif1_ctrl_pins[] = {
2358
-
/* RTS1_N, CTS1_N */
2278
+
static const unsigned int scif1_ctrl_a_pins[] = {
2279
+
/* RTS1_N_A, CTS1_N_A */
2359
2280
RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2360
2281
};
2361
-
static const unsigned int scif1_ctrl_mux[] = {
2362
-
RTS1_N_MARK, CTS1_N_MARK,
2282
+
static const unsigned int scif1_ctrl_a_mux[] = {
2283
+
RTS1_N_A_MARK, CTS1_N_A_MARK,
2363
2284
};
2364
2285
2365
-
/* - SCIF1_X ------------------------------------------------------------------ */
2366
-
static const unsigned int scif1_data_x_pins[] = {
2367
-
/* RX1_X, TX1_X */
2286
+
static const unsigned int scif1_data_b_pins[] = {
2287
+
/* RX1_B, TX1_B */
2368
2288
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2369
2289
};
2370
-
static const unsigned int scif1_data_x_mux[] = {
2371
-
RX1_X_MARK, TX1_X_MARK,
2290
+
static const unsigned int scif1_data_b_mux[] = {
2291
+
RX1_B_MARK, TX1_B_MARK,
2372
2292
};
2373
-
static const unsigned int scif1_clk_x_pins[] = {
2374
-
/* SCK1_X */
2293
+
static const unsigned int scif1_clk_b_pins[] = {
2294
+
/* SCK1_B */
2375
2295
RCAR_GP_PIN(1, 10),
2376
2296
};
2377
-
static const unsigned int scif1_clk_x_mux[] = {
2378
-
SCK1_X_MARK,
2297
+
static const unsigned int scif1_clk_b_mux[] = {
2298
+
SCK1_B_MARK,
2379
2299
};
2380
-
static const unsigned int scif1_ctrl_x_pins[] = {
2381
-
/* RTS1_N_X, CTS1_N_X */
2300
+
static const unsigned int scif1_ctrl_b_pins[] = {
2301
+
/* RTS1_N_B, CTS1_N_B */
2382
2302
RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2383
2303
};
2384
-
static const unsigned int scif1_ctrl_x_mux[] = {
2385
-
RTS1_N_X_MARK, CTS1_N_X_MARK,
2304
+
static const unsigned int scif1_ctrl_b_mux[] = {
2305
+
RTS1_N_B_MARK, CTS1_N_B_MARK,
2386
2306
};
2387
2307
2388
2308
/* - SCIF3 ------------------------------------------------------------------ */
2389
-
static const unsigned int scif3_data_pins[] = {
2390
-
/* RX3, TX3 */
2391
-
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2392
-
};
2393
-
static const unsigned int scif3_data_mux[] = {
2394
-
RX3_MARK, TX3_MARK,
2395
-
};
2396
-
static const unsigned int scif3_clk_pins[] = {
2397
-
/* SCK3 */
2398
-
RCAR_GP_PIN(1, 4),
2399
-
};
2400
-
static const unsigned int scif3_clk_mux[] = {
2401
-
SCK3_MARK,
2402
-
};
2403
-
static const unsigned int scif3_ctrl_pins[] = {
2404
-
/* RTS3_N, CTS3_N */
2405
-
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2406
-
};
2407
-
static const unsigned int scif3_ctrl_mux[] = {
2408
-
RTS3_N_MARK, CTS3_N_MARK,
2409
-
};
2410
-
2411
-
/* - SCIF3_A ------------------------------------------------------------------ */
2412
2309
static const unsigned int scif3_data_a_pins[] = {
2413
2310
/* RX3_A, TX3_A */
2414
2311
RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
···
2405
2350
};
2406
2351
static const unsigned int scif3_ctrl_a_mux[] = {
2407
2352
RTS3_N_A_MARK, CTS3_N_A_MARK,
2353
+
};
2354
+
2355
+
static const unsigned int scif3_data_b_pins[] = {
2356
+
/* RX3_B, TX3_B */
2357
+
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2358
+
};
2359
+
static const unsigned int scif3_data_b_mux[] = {
2360
+
RX3_B_MARK, TX3_B_MARK,
2361
+
};
2362
+
static const unsigned int scif3_clk_b_pins[] = {
2363
+
/* SCK3_B */
2364
+
RCAR_GP_PIN(1, 4),
2365
+
};
2366
+
static const unsigned int scif3_clk_b_mux[] = {
2367
+
SCK3_B_MARK,
2368
+
};
2369
+
static const unsigned int scif3_ctrl_b_pins[] = {
2370
+
/* RTS3_N_B, CTS3_N_B */
2371
+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2372
+
};
2373
+
static const unsigned int scif3_ctrl_b_mux[] = {
2374
+
RTS3_N_B_MARK, CTS3_N_B_MARK,
2408
2375
};
2409
2376
2410
2377
/* - SCIF4 ------------------------------------------------------------------ */
···
2485
2408
SSI_SCK_MARK, SSI_WS_MARK,
2486
2409
};
2487
2410
2488
-
/* - TPU ------------------------------------------------------------------- */
2489
-
static const unsigned int tpu_to0_pins[] = {
2490
-
/* TPU0TO0 */
2491
-
RCAR_GP_PIN(2, 8),
2492
-
};
2493
-
static const unsigned int tpu_to0_mux[] = {
2494
-
TPU0TO0_MARK,
2495
-
};
2496
-
static const unsigned int tpu_to1_pins[] = {
2497
-
/* TPU0TO1 */
2498
-
RCAR_GP_PIN(2, 7),
2499
-
};
2500
-
static const unsigned int tpu_to1_mux[] = {
2501
-
TPU0TO1_MARK,
2502
-
};
2503
-
static const unsigned int tpu_to2_pins[] = {
2504
-
/* TPU0TO2 */
2505
-
RCAR_GP_PIN(2, 12),
2506
-
};
2507
-
static const unsigned int tpu_to2_mux[] = {
2508
-
TPU0TO2_MARK,
2509
-
};
2510
-
static const unsigned int tpu_to3_pins[] = {
2511
-
/* TPU0TO3 */
2512
-
RCAR_GP_PIN(2, 13),
2513
-
};
2514
-
static const unsigned int tpu_to3_mux[] = {
2515
-
TPU0TO3_MARK,
2516
-
};
2517
-
2518
-
/* - TPU_A ------------------------------------------------------------------- */
2411
+
/* - TPU -------------------------------------------------------------------- */
2519
2412
static const unsigned int tpu_to0_a_pins[] = {
2520
2413
/* TPU0TO0_A */
2521
-
RCAR_GP_PIN(1, 25),
2414
+
RCAR_GP_PIN(2, 8),
2522
2415
};
2523
2416
static const unsigned int tpu_to0_a_mux[] = {
2524
2417
TPU0TO0_A_MARK,
2525
2418
};
2526
2419
static const unsigned int tpu_to1_a_pins[] = {
2527
2420
/* TPU0TO1_A */
2528
-
RCAR_GP_PIN(1, 26),
2421
+
RCAR_GP_PIN(2, 7),
2529
2422
};
2530
2423
static const unsigned int tpu_to1_a_mux[] = {
2531
2424
TPU0TO1_A_MARK,
2532
2425
};
2533
2426
static const unsigned int tpu_to2_a_pins[] = {
2534
2427
/* TPU0TO2_A */
2535
-
RCAR_GP_PIN(2, 0),
2428
+
RCAR_GP_PIN(2, 12),
2536
2429
};
2537
2430
static const unsigned int tpu_to2_a_mux[] = {
2538
2431
TPU0TO2_A_MARK,
2539
2432
};
2540
2433
static const unsigned int tpu_to3_a_pins[] = {
2541
2434
/* TPU0TO3_A */
2542
-
RCAR_GP_PIN(2, 1),
2435
+
RCAR_GP_PIN(2, 13),
2543
2436
};
2544
2437
static const unsigned int tpu_to3_a_mux[] = {
2545
2438
TPU0TO3_A_MARK,
2439
+
};
2440
+
2441
+
static const unsigned int tpu_to0_b_pins[] = {
2442
+
/* TPU0TO0_B */
2443
+
RCAR_GP_PIN(1, 25),
2444
+
};
2445
+
static const unsigned int tpu_to0_b_mux[] = {
2446
+
TPU0TO0_B_MARK,
2447
+
};
2448
+
static const unsigned int tpu_to1_b_pins[] = {
2449
+
/* TPU0TO1_B */
2450
+
RCAR_GP_PIN(1, 26),
2451
+
};
2452
+
static const unsigned int tpu_to1_b_mux[] = {
2453
+
TPU0TO1_B_MARK,
2454
+
};
2455
+
static const unsigned int tpu_to2_b_pins[] = {
2456
+
/* TPU0TO2_B */
2457
+
RCAR_GP_PIN(2, 0),
2458
+
};
2459
+
static const unsigned int tpu_to2_b_mux[] = {
2460
+
TPU0TO2_B_MARK,
2461
+
};
2462
+
static const unsigned int tpu_to3_b_pins[] = {
2463
+
/* TPU0TO3_B */
2464
+
RCAR_GP_PIN(2, 1),
2465
+
};
2466
+
static const unsigned int tpu_to3_b_mux[] = {
2467
+
TPU0TO3_B_MARK,
2546
2468
};
2547
2469
2548
2470
/* - TSN0 ------------------------------------------------ */
···
2654
2578
SH_PFC_PIN_GROUP(canfd2_data),
2655
2579
SH_PFC_PIN_GROUP(canfd3_data),
2656
2580
SH_PFC_PIN_GROUP(canfd4_data),
2657
-
SH_PFC_PIN_GROUP(canfd5_data), /* suffix might be updated */
2658
-
SH_PFC_PIN_GROUP(canfd5_data_b), /* suffix might be updated */
2581
+
SH_PFC_PIN_GROUP(canfd5_data_a),
2582
+
SH_PFC_PIN_GROUP(canfd5_data_b),
2659
2583
SH_PFC_PIN_GROUP(canfd6_data),
2660
2584
SH_PFC_PIN_GROUP(canfd7_data),
2661
2585
SH_PFC_PIN_GROUP(can_clk),
···
2663
2587
SH_PFC_PIN_GROUP(hscif0_data),
2664
2588
SH_PFC_PIN_GROUP(hscif0_clk),
2665
2589
SH_PFC_PIN_GROUP(hscif0_ctrl),
2666
-
SH_PFC_PIN_GROUP(hscif1_data), /* suffix might be updated */
2667
-
SH_PFC_PIN_GROUP(hscif1_clk), /* suffix might be updated */
2668
-
SH_PFC_PIN_GROUP(hscif1_ctrl), /* suffix might be updated */
2669
-
SH_PFC_PIN_GROUP(hscif1_data_x), /* suffix might be updated */
2670
-
SH_PFC_PIN_GROUP(hscif1_clk_x), /* suffix might be updated */
2671
-
SH_PFC_PIN_GROUP(hscif1_ctrl_x), /* suffix might be updated */
2590
+
SH_PFC_PIN_GROUP(hscif1_data_a),
2591
+
SH_PFC_PIN_GROUP(hscif1_clk_a),
2592
+
SH_PFC_PIN_GROUP(hscif1_ctrl_a),
2593
+
SH_PFC_PIN_GROUP(hscif1_data_b),
2594
+
SH_PFC_PIN_GROUP(hscif1_clk_b),
2595
+
SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2672
2596
SH_PFC_PIN_GROUP(hscif2_data),
2673
2597
SH_PFC_PIN_GROUP(hscif2_clk),
2674
2598
SH_PFC_PIN_GROUP(hscif2_ctrl),
2675
-
SH_PFC_PIN_GROUP(hscif3_data), /* suffix might be updated */
2676
-
SH_PFC_PIN_GROUP(hscif3_clk), /* suffix might be updated */
2677
-
SH_PFC_PIN_GROUP(hscif3_ctrl), /* suffix might be updated */
2678
-
SH_PFC_PIN_GROUP(hscif3_data_a), /* suffix might be updated */
2679
-
SH_PFC_PIN_GROUP(hscif3_clk_a), /* suffix might be updated */
2680
-
SH_PFC_PIN_GROUP(hscif3_ctrl_a), /* suffix might be updated */
2599
+
SH_PFC_PIN_GROUP(hscif3_data_a),
2600
+
SH_PFC_PIN_GROUP(hscif3_clk_a),
2601
+
SH_PFC_PIN_GROUP(hscif3_ctrl_a),
2602
+
SH_PFC_PIN_GROUP(hscif3_data_b),
2603
+
SH_PFC_PIN_GROUP(hscif3_clk_b),
2604
+
SH_PFC_PIN_GROUP(hscif3_ctrl_b),
2681
2605
2682
2606
SH_PFC_PIN_GROUP(i2c0),
2683
2607
SH_PFC_PIN_GROUP(i2c1),
···
2685
2609
SH_PFC_PIN_GROUP(i2c3),
2686
2610
SH_PFC_PIN_GROUP(i2c4),
2687
2611
SH_PFC_PIN_GROUP(i2c5),
2612
+
2613
+
SH_PFC_PIN_GROUP(intc_ex_irq0_a),
2614
+
SH_PFC_PIN_GROUP(intc_ex_irq0_b),
2615
+
SH_PFC_PIN_GROUP(intc_ex_irq1_a),
2616
+
SH_PFC_PIN_GROUP(intc_ex_irq1_b),
2617
+
SH_PFC_PIN_GROUP(intc_ex_irq2_a),
2618
+
SH_PFC_PIN_GROUP(intc_ex_irq2_b),
2619
+
SH_PFC_PIN_GROUP(intc_ex_irq3_a),
2620
+
SH_PFC_PIN_GROUP(intc_ex_irq3_b),
2621
+
SH_PFC_PIN_GROUP(intc_ex_irq4_a),
2622
+
SH_PFC_PIN_GROUP(intc_ex_irq4_b),
2623
+
SH_PFC_PIN_GROUP(intc_ex_irq5),
2688
2624
2689
2625
BUS_DATA_PIN_GROUP(mmc_data, 1),
2690
2626
BUS_DATA_PIN_GROUP(mmc_data, 4),
···
2751
2663
SH_PFC_PIN_GROUP(pcie0_clkreq_n),
2752
2664
SH_PFC_PIN_GROUP(pcie1_clkreq_n),
2753
2665
2754
-
SH_PFC_PIN_GROUP(pwm0_a), /* suffix might be updated */
2666
+
SH_PFC_PIN_GROUP(pwm0),
2755
2667
SH_PFC_PIN_GROUP(pwm1_a),
2756
2668
SH_PFC_PIN_GROUP(pwm1_b),
2757
-
SH_PFC_PIN_GROUP(pwm2_b), /* suffix might be updated */
2669
+
SH_PFC_PIN_GROUP(pwm2),
2758
2670
SH_PFC_PIN_GROUP(pwm3_a),
2759
2671
SH_PFC_PIN_GROUP(pwm3_b),
2760
2672
SH_PFC_PIN_GROUP(pwm4),
2761
2673
SH_PFC_PIN_GROUP(pwm5),
2762
2674
SH_PFC_PIN_GROUP(pwm6),
2763
2675
SH_PFC_PIN_GROUP(pwm7),
2764
-
SH_PFC_PIN_GROUP(pwm8_a), /* suffix might be updated */
2765
-
SH_PFC_PIN_GROUP(pwm9_a), /* suffix might be updated */
2676
+
SH_PFC_PIN_GROUP(pwm8),
2677
+
SH_PFC_PIN_GROUP(pwm9),
2766
2678
2767
2679
SH_PFC_PIN_GROUP(qspi0_ctrl),
2768
2680
BUS_DATA_PIN_GROUP(qspi0_data, 2),
···
2774
2686
SH_PFC_PIN_GROUP(scif0_data),
2775
2687
SH_PFC_PIN_GROUP(scif0_clk),
2776
2688
SH_PFC_PIN_GROUP(scif0_ctrl),
2777
-
SH_PFC_PIN_GROUP(scif1_data), /* suffix might be updated */
2778
-
SH_PFC_PIN_GROUP(scif1_clk), /* suffix might be updated */
2779
-
SH_PFC_PIN_GROUP(scif1_ctrl), /* suffix might be updated */
2780
-
SH_PFC_PIN_GROUP(scif1_data_x), /* suffix might be updated */
2781
-
SH_PFC_PIN_GROUP(scif1_clk_x), /* suffix might be updated */
2782
-
SH_PFC_PIN_GROUP(scif1_ctrl_x), /* suffix might be updated */
2783
-
SH_PFC_PIN_GROUP(scif3_data), /* suffix might be updated */
2784
-
SH_PFC_PIN_GROUP(scif3_clk), /* suffix might be updated */
2785
-
SH_PFC_PIN_GROUP(scif3_ctrl), /* suffix might be updated */
2786
-
SH_PFC_PIN_GROUP(scif3_data_a), /* suffix might be updated */
2787
-
SH_PFC_PIN_GROUP(scif3_clk_a), /* suffix might be updated */
2788
-
SH_PFC_PIN_GROUP(scif3_ctrl_a), /* suffix might be updated */
2689
+
SH_PFC_PIN_GROUP(scif1_data_a),
2690
+
SH_PFC_PIN_GROUP(scif1_clk_a),
2691
+
SH_PFC_PIN_GROUP(scif1_ctrl_a),
2692
+
SH_PFC_PIN_GROUP(scif1_data_b),
2693
+
SH_PFC_PIN_GROUP(scif1_clk_b),
2694
+
SH_PFC_PIN_GROUP(scif1_ctrl_b),
2695
+
SH_PFC_PIN_GROUP(scif3_data_a),
2696
+
SH_PFC_PIN_GROUP(scif3_clk_a),
2697
+
SH_PFC_PIN_GROUP(scif3_ctrl_a),
2698
+
SH_PFC_PIN_GROUP(scif3_data_b),
2699
+
SH_PFC_PIN_GROUP(scif3_clk_b),
2700
+
SH_PFC_PIN_GROUP(scif3_ctrl_b),
2789
2701
SH_PFC_PIN_GROUP(scif4_data),
2790
2702
SH_PFC_PIN_GROUP(scif4_clk),
2791
2703
SH_PFC_PIN_GROUP(scif4_ctrl),
···
2795
2707
SH_PFC_PIN_GROUP(ssi_data),
2796
2708
SH_PFC_PIN_GROUP(ssi_ctrl),
2797
2709
2798
-
SH_PFC_PIN_GROUP(tpu_to0), /* suffix might be updated */
2799
-
SH_PFC_PIN_GROUP(tpu_to0_a), /* suffix might be updated */
2800
-
SH_PFC_PIN_GROUP(tpu_to1), /* suffix might be updated */
2801
-
SH_PFC_PIN_GROUP(tpu_to1_a), /* suffix might be updated */
2802
-
SH_PFC_PIN_GROUP(tpu_to2), /* suffix might be updated */
2803
-
SH_PFC_PIN_GROUP(tpu_to2_a), /* suffix might be updated */
2804
-
SH_PFC_PIN_GROUP(tpu_to3), /* suffix might be updated */
2805
-
SH_PFC_PIN_GROUP(tpu_to3_a), /* suffix might be updated */
2710
+
SH_PFC_PIN_GROUP(tpu_to0_a),
2711
+
SH_PFC_PIN_GROUP(tpu_to0_b),
2712
+
SH_PFC_PIN_GROUP(tpu_to1_a),
2713
+
SH_PFC_PIN_GROUP(tpu_to1_b),
2714
+
SH_PFC_PIN_GROUP(tpu_to2_a),
2715
+
SH_PFC_PIN_GROUP(tpu_to2_b),
2716
+
SH_PFC_PIN_GROUP(tpu_to3_a),
2717
+
SH_PFC_PIN_GROUP(tpu_to3_b),
2806
2718
2807
2719
SH_PFC_PIN_GROUP(tsn0_link),
2808
2720
SH_PFC_PIN_GROUP(tsn0_phy_int),
···
2876
2788
};
2877
2789
2878
2790
static const char * const canfd5_groups[] = {
2879
-
/* suffix might be updated */
2880
-
"canfd5_data",
2791
+
"canfd5_data_a",
2881
2792
"canfd5_data_b",
2882
2793
};
2883
2794
···
2899
2812
};
2900
2813
2901
2814
static const char * const hscif1_groups[] = {
2902
-
/* suffix might be updated */
2903
-
"hscif1_data",
2904
-
"hscif1_clk",
2905
-
"hscif1_ctrl",
2906
-
"hscif1_data_x",
2907
-
"hscif1_clk_x",
2908
-
"hscif1_ctrl_x",
2815
+
"hscif1_data_a",
2816
+
"hscif1_clk_a",
2817
+
"hscif1_ctrl_a",
2818
+
"hscif1_data_b",
2819
+
"hscif1_clk_b",
2820
+
"hscif1_ctrl_b",
2909
2821
};
2910
2822
2911
2823
static const char * const hscif2_groups[] = {
···
2914
2828
};
2915
2829
2916
2830
static const char * const hscif3_groups[] = {
2917
-
/* suffix might be updated */
2918
-
"hscif3_data",
2919
-
"hscif3_clk",
2920
-
"hscif3_ctrl",
2921
2831
"hscif3_data_a",
2922
2832
"hscif3_clk_a",
2923
2833
"hscif3_ctrl_a",
2834
+
"hscif3_data_b",
2835
+
"hscif3_clk_b",
2836
+
"hscif3_ctrl_b",
2924
2837
};
2925
2838
2926
2839
static const char * const i2c0_groups[] = {
···
2944
2859
2945
2860
static const char * const i2c5_groups[] = {
2946
2861
"i2c5",
2862
+
};
2863
+
2864
+
static const char * const intc_ex_groups[] = {
2865
+
"intc_ex_irq0_a",
2866
+
"intc_ex_irq0_b",
2867
+
"intc_ex_irq1_a",
2868
+
"intc_ex_irq1_b",
2869
+
"intc_ex_irq2_a",
2870
+
"intc_ex_irq2_b",
2871
+
"intc_ex_irq3_a",
2872
+
"intc_ex_irq3_b",
2873
+
"intc_ex_irq4_a",
2874
+
"intc_ex_irq4_b",
2875
+
"intc_ex_irq5",
2947
2876
};
2948
2877
2949
2878
static const char * const mmc_groups[] = {
···
3030
2931
};
3031
2932
3032
2933
static const char * const pwm0_groups[] = {
3033
-
/* suffix might be updated */
3034
-
"pwm0_a",
2934
+
"pwm0",
3035
2935
};
3036
2936
3037
2937
static const char * const pwm1_groups[] = {
···
3039
2941
};
3040
2942
3041
2943
static const char * const pwm2_groups[] = {
3042
-
/* suffix might be updated */
3043
-
"pwm2_b",
2944
+
"pwm2",
3044
2945
};
3045
2946
3046
2947
static const char * const pwm3_groups[] = {
···
3064
2967
};
3065
2968
3066
2969
static const char * const pwm8_groups[] = {
3067
-
/* suffix might be updated */
3068
-
"pwm8_a",
2970
+
"pwm8",
3069
2971
};
3070
2972
3071
2973
static const char * const pwm9_groups[] = {
3072
-
/* suffix might be updated */
3073
-
"pwm9_a",
2974
+
"pwm9",
3074
2975
};
3075
2976
3076
2977
static const char * const qspi0_groups[] = {
···
3090
2995
};
3091
2996
3092
2997
static const char * const scif1_groups[] = {
3093
-
/* suffix might be updated */
3094
-
"scif1_data",
3095
-
"scif1_clk",
3096
-
"scif1_ctrl",
3097
-
"scif1_data_x",
3098
-
"scif1_clk_x",
3099
-
"scif1_ctrl_x",
2998
+
"scif1_data_a",
2999
+
"scif1_clk_a",
3000
+
"scif1_ctrl_a",
3001
+
"scif1_data_b",
3002
+
"scif1_clk_b",
3003
+
"scif1_ctrl_b",
3100
3004
};
3101
3005
3102
3006
static const char * const scif3_groups[] = {
3103
-
/* suffix might be updated */
3104
-
"scif3_data",
3105
-
"scif3_clk",
3106
-
"scif3_ctrl",
3107
3007
"scif3_data_a",
3108
3008
"scif3_clk_a",
3109
3009
"scif3_ctrl_a",
3010
+
"scif3_data_b",
3011
+
"scif3_clk_b",
3012
+
"scif3_ctrl_b",
3110
3013
};
3111
3014
3112
3015
static const char * const scif4_groups[] = {
···
3127
3034
};
3128
3035
3129
3036
static const char * const tpu_groups[] = {
3130
-
/* suffix might be updated */
3131
-
"tpu_to0",
3132
3037
"tpu_to0_a",
3133
-
"tpu_to1",
3038
+
"tpu_to0_b",
3134
3039
"tpu_to1_a",
3135
-
"tpu_to2",
3040
+
"tpu_to1_b",
3136
3041
"tpu_to2_a",
3137
-
"tpu_to3",
3042
+
"tpu_to2_b",
3138
3043
"tpu_to3_a",
3044
+
"tpu_to3_b",
3139
3045
};
3140
3046
3141
3047
static const char * const tsn0_groups[] = {
···
3176
3084
SH_PFC_FUNCTION(i2c3),
3177
3085
SH_PFC_FUNCTION(i2c4),
3178
3086
SH_PFC_FUNCTION(i2c5),
3087
+
3088
+
SH_PFC_FUNCTION(intc_ex),
3179
3089
3180
3090
SH_PFC_FUNCTION(mmc),
3181
3091
+61
-21
drivers/pinctrl/renesas/pfc-r8a779h0.c
+61
-21
drivers/pinctrl/renesas/pfc-r8a779h0.c
···
1236
1236
static const unsigned int avb0_mdio_mux[] = {
1237
1237
AVB0_MDC_MARK, AVB0_MDIO_MARK,
1238
1238
};
1239
+
static const unsigned int avb0_mii_pins[] = {
1240
+
/*
1241
+
* AVB0_MII_TD0, AVB0_MII_TD1, AVB0_MII_TD2,
1242
+
* AVB0_MII_TD3, AVB0_MII_RD0, AVB0_MII_RD1,
1243
+
* AVB0_MII_RD2, AVB0_MII_RD3, AVB0_MII_TXC,
1244
+
* AVB0_MII_TX_EN, AVB0_MII_TX_ER, AVB0_MII_RXC,
1245
+
* AVB0_MII_RX_DV, AVB0_MII_RX_ER, AVB0_MII_CRS,
1246
+
* AVB0_MII_COL
1247
+
*/
1248
+
RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 6),
1249
+
RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1250
+
RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 15),
1251
+
RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 19),
1252
+
RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 1),
1253
+
RCAR_GP_PIN(7, 0),
1254
+
};
1255
+
static const unsigned int avb0_mii_mux[] = {
1256
+
AVB0_MII_TD0_MARK, AVB0_MII_TD1_MARK, AVB0_MII_TD2_MARK,
1257
+
AVB0_MII_TD3_MARK, AVB0_MII_RD0_MARK, AVB0_MII_RD1_MARK,
1258
+
AVB0_MII_RD2_MARK, AVB0_MII_RD3_MARK, AVB0_MII_TXC_MARK,
1259
+
AVB0_MII_TX_EN_MARK, AVB0_MII_TX_ER_MARK, AVB0_MII_RXC_MARK,
1260
+
AVB0_MII_RX_DV_MARK, AVB0_MII_RX_ER_MARK, AVB0_MII_CRS_MARK,
1261
+
AVB0_MII_COL_MARK,
1262
+
};
1239
1263
static const unsigned int avb0_rgmii_pins[] = {
1240
1264
/*
1241
1265
* AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
···
1337
1313
};
1338
1314
static const unsigned int avb1_mdio_mux[] = {
1339
1315
AVB1_MDC_MARK, AVB1_MDIO_MARK,
1316
+
};
1317
+
static const unsigned int avb1_mii_pins[] = {
1318
+
/*
1319
+
* AVB1_MII_TD0, AVB1_MII_TD1, AVB1_MII_TD2,
1320
+
* AVB1_MII_TD3, AVB1_MII_RD0, AVB1_MII_RD1,
1321
+
* AVB1_MII_RD2, AVB1_MII_RD3, AVB1_MII_TXC,
1322
+
* AVB1_MII_TX_EN, AVB1_MII_TX_ER, AVB1_MII_RXC,
1323
+
* AVB1_MII_RX_DV, AVB1_MII_RX_ER, AVB1_MII_CRS,
1324
+
* AVB1_MII_COL
1325
+
*/
1326
+
RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 16),
1327
+
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1328
+
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 6),
1329
+
RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 8),
1330
+
RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11),
1331
+
RCAR_GP_PIN(6, 10),
1332
+
};
1333
+
static const unsigned int avb1_mii_mux[] = {
1334
+
AVB1_MII_TD0_MARK, AVB1_MII_TD1_MARK, AVB1_MII_TD2_MARK,
1335
+
AVB1_MII_TD3_MARK, AVB1_MII_RD0_MARK, AVB1_MII_RD1_MARK,
1336
+
AVB1_MII_RD2_MARK, AVB1_MII_RD3_MARK, AVB1_MII_TXC_MARK,
1337
+
AVB1_MII_TX_EN_MARK, AVB1_MII_TX_ER_MARK, AVB1_MII_RXC_MARK,
1338
+
AVB1_MII_RX_DV_MARK, AVB1_MII_RX_ER_MARK, AVB1_MII_CRS_MARK,
1339
+
AVB1_MII_COL_MARK,
1340
1340
};
1341
1341
static const unsigned int avb1_rgmii_pins[] = {
1342
1342
/*
···
1557
1509
HRTS0_N_MARK, HCTS0_N_MARK,
1558
1510
};
1559
1511
1560
-
/* - HSCIF1_A ----------------------------------------------------------------- */
1512
+
/* - HSCIF1 ------------------------------------------------------------------- */
1561
1513
static const unsigned int hscif1_data_a_pins[] = {
1562
1514
/* HRX1_A, HTX1_A */
1563
1515
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
···
1580
1532
HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1581
1533
};
1582
1534
1583
-
/* - HSCIF1_B ---------------------------------------------------------------- */
1584
1535
static const unsigned int hscif1_data_b_pins[] = {
1585
1536
/* HRX1_B, HTX1_B */
1586
1537
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
···
1625
1578
HRTS2_N_MARK, HCTS2_N_MARK,
1626
1579
};
1627
1580
1628
-
/* - HSCIF3_A ----------------------------------------------------------------- */
1581
+
/* - HSCIF3 ------------------------------------------------------------------- */
1629
1582
static const unsigned int hscif3_data_a_pins[] = {
1630
1583
/* HRX3_A, HTX3_A */
1631
1584
RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
···
1648
1601
HRTS3_N_A_MARK, HCTS3_N_A_MARK,
1649
1602
};
1650
1603
1651
-
/* - HSCIF3_B ----------------------------------------------------------------- */
1652
1604
static const unsigned int hscif3_data_b_pins[] = {
1653
1605
/* HRX3_B, HTX3_B */
1654
1606
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
···
2107
2061
PCIE0_CLKREQ_N_MARK,
2108
2062
};
2109
2063
2110
-
/* - PWM0_A ------------------------------------------------------------------- */
2064
+
/* - PWM0 --------------------------------------------------------------------- */
2111
2065
static const unsigned int pwm0_a_pins[] = {
2112
2066
/* PWM0_A */
2113
2067
RCAR_GP_PIN(1, 15),
···
2116
2070
PWM0_A_MARK,
2117
2071
};
2118
2072
2119
-
/* - PWM0_B ------------------------------------------------------------------- */
2120
2073
static const unsigned int pwm0_b_pins[] = {
2121
2074
/* PWM0_B */
2122
2075
RCAR_GP_PIN(1, 14),
···
2124
2079
PWM0_B_MARK,
2125
2080
};
2126
2081
2127
-
/* - PWM1_A ------------------------------------------------------------------- */
2082
+
/* - PWM1 --------------------------------------------------------------------- */
2128
2083
static const unsigned int pwm1_a_pins[] = {
2129
2084
/* PWM1_A */
2130
2085
RCAR_GP_PIN(3, 13),
···
2133
2088
PWM1_A_MARK,
2134
2089
};
2135
2090
2136
-
/* - PWM1_B ------------------------------------------------------------------- */
2137
2091
static const unsigned int pwm1_b_pins[] = {
2138
2092
/* PWM1_B */
2139
2093
RCAR_GP_PIN(2, 13),
···
2141
2097
PWM1_B_MARK,
2142
2098
};
2143
2099
2144
-
/* - PWM1_C ------------------------------------------------------------------- */
2145
2100
static const unsigned int pwm1_c_pins[] = {
2146
2101
/* PWM1_C */
2147
2102
RCAR_GP_PIN(2, 17),
···
2149
2106
PWM1_C_MARK,
2150
2107
};
2151
2108
2152
-
/* - PWM2_A ------------------------------------------------------------------- */
2109
+
/* - PWM2 --------------------------------------------------------------------- */
2153
2110
static const unsigned int pwm2_a_pins[] = {
2154
2111
/* PWM2_A */
2155
2112
RCAR_GP_PIN(3, 14),
···
2158
2115
PWM2_A_MARK,
2159
2116
};
2160
2117
2161
-
/* - PWM2_B ------------------------------------------------------------------- */
2162
2118
static const unsigned int pwm2_b_pins[] = {
2163
2119
/* PWM2_B */
2164
2120
RCAR_GP_PIN(2, 14),
···
2166
2124
PWM2_B_MARK,
2167
2125
};
2168
2126
2169
-
/* - PWM2_C ------------------------------------------------------------------- */
2170
2127
static const unsigned int pwm2_c_pins[] = {
2171
2128
/* PWM2_C */
2172
2129
RCAR_GP_PIN(2, 19),
···
2174
2133
PWM2_C_MARK,
2175
2134
};
2176
2135
2177
-
/* - PWM3_A ------------------------------------------------------------------- */
2136
+
/* - PWM3 --------------------------------------------------------------------- */
2178
2137
static const unsigned int pwm3_a_pins[] = {
2179
2138
/* PWM3_A */
2180
2139
RCAR_GP_PIN(4, 14),
···
2183
2142
PWM3_A_MARK,
2184
2143
};
2185
2144
2186
-
/* - PWM3_B ------------------------------------------------------------------- */
2187
2145
static const unsigned int pwm3_b_pins[] = {
2188
2146
/* PWM3_B */
2189
2147
RCAR_GP_PIN(2, 15),
···
2191
2151
PWM3_B_MARK,
2192
2152
};
2193
2153
2194
-
/* - PWM3_C ------------------------------------------------------------------- */
2195
2154
static const unsigned int pwm3_c_pins[] = {
2196
2155
/* PWM3_C */
2197
2156
RCAR_GP_PIN(1, 22),
···
2267
2228
RTS0_N_MARK, CTS0_N_MARK,
2268
2229
};
2269
2230
2270
-
/* - SCIF1_A ------------------------------------------------------------------ */
2231
+
/* - SCIF1 -------------------------------------------------------------------- */
2271
2232
static const unsigned int scif1_data_a_pins[] = {
2272
2233
/* RX1_A, TX1_A */
2273
2234
RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
···
2290
2251
RTS1_N_A_MARK, CTS1_N_A_MARK,
2291
2252
};
2292
2253
2293
-
/* - SCIF1_B ------------------------------------------------------------------ */
2294
2254
static const unsigned int scif1_data_b_pins[] = {
2295
2255
/* RX1_B, TX1_B */
2296
2256
RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
···
2312
2274
RTS1_N_B_MARK, CTS1_N_B_MARK,
2313
2275
};
2314
2276
2315
-
/* - SCIF3_A ------------------------------------------------------------------ */
2277
+
/* - SCIF3 -------------------------------------------------------------------- */
2316
2278
static const unsigned int scif3_data_a_pins[] = {
2317
2279
/* RX3_A, TX3_A */
2318
2280
RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
···
2335
2297
RTS3_N_A_MARK, CTS3_N_A_MARK,
2336
2298
};
2337
2299
2338
-
/* - SCIF3_B ------------------------------------------------------------------ */
2339
2300
static const unsigned int scif3_data_b_pins[] = {
2340
2301
/* RX3_B, TX3_B */
2341
2302
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
···
2413
2376
SSI_SCK_MARK, SSI_WS_MARK,
2414
2377
};
2415
2378
2416
-
/* - TPU_A ------------------------------------------------------------------- */
2379
+
/* - TPU --------------------------------------------------------------------- */
2417
2380
static const unsigned int tpu_to0_a_pins[] = {
2418
2381
/* TPU0TO0_A */
2419
2382
RCAR_GP_PIN(2, 8),
···
2443
2406
TPU0TO3_A_MARK,
2444
2407
};
2445
2408
2446
-
/* - TPU_B ------------------------------------------------------------------- */
2447
2409
static const unsigned int tpu_to0_b_pins[] = {
2448
2410
/* TPU0TO0_B */
2449
2411
RCAR_GP_PIN(1, 25),
···
2480
2444
SH_PFC_PIN_GROUP(avb0_magic),
2481
2445
SH_PFC_PIN_GROUP(avb0_phy_int),
2482
2446
SH_PFC_PIN_GROUP(avb0_mdio),
2447
+
SH_PFC_PIN_GROUP(avb0_mii),
2483
2448
SH_PFC_PIN_GROUP(avb0_rgmii),
2484
2449
SH_PFC_PIN_GROUP(avb0_txcrefclk),
2485
2450
SH_PFC_PIN_GROUP(avb0_avtp_pps),
···
2491
2454
SH_PFC_PIN_GROUP(avb1_magic),
2492
2455
SH_PFC_PIN_GROUP(avb1_phy_int),
2493
2456
SH_PFC_PIN_GROUP(avb1_mdio),
2457
+
SH_PFC_PIN_GROUP(avb1_mii),
2494
2458
SH_PFC_PIN_GROUP(avb1_rgmii),
2495
2459
SH_PFC_PIN_GROUP(avb1_txcrefclk),
2496
2460
SH_PFC_PIN_GROUP(avb1_avtp_pps),
···
2666
2628
"avb0_magic",
2667
2629
"avb0_phy_int",
2668
2630
"avb0_mdio",
2631
+
"avb0_mii",
2669
2632
"avb0_rgmii",
2670
2633
"avb0_txcrefclk",
2671
2634
"avb0_avtp_pps",
···
2679
2640
"avb1_magic",
2680
2641
"avb1_phy_int",
2681
2642
"avb1_mdio",
2643
+
"avb1_mii",
2682
2644
"avb1_rgmii",
2683
2645
"avb1_txcrefclk",
2684
2646
"avb1_avtp_pps",
+2
-2
drivers/pinctrl/renesas/pfc-sh73a0.c
+2
-2
drivers/pinctrl/renesas/pfc-sh73a0.c
···
4024
4024
4025
4025
static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
4026
4026
{
4027
-
struct sh_pfc *pfc = reg->reg_data;
4027
+
struct sh_pfc *pfc = rdev_get_drvdata(reg);
4028
4028
void __iomem *addr = pfc->windows[1].virt + 4;
4029
4029
unsigned long flags;
4030
4030
u32 value;
···
4057
4057
4058
4058
static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
4059
4059
{
4060
-
struct sh_pfc *pfc = reg->reg_data;
4060
+
struct sh_pfc *pfc = rdev_get_drvdata(reg);
4061
4061
void __iomem *addr = pfc->windows[1].virt + 4;
4062
4062
unsigned long flags;
4063
4063
u32 value;
+4
-10
drivers/pinctrl/renesas/pinctrl-rza1.c
+4
-10
drivers/pinctrl/renesas/pinctrl-rza1.c
···
852
852
*/
853
853
static int rza1_dt_node_pin_count(struct device_node *np)
854
854
{
855
-
struct device_node *child;
856
855
struct property *of_pins;
857
856
unsigned int npins;
858
857
···
860
861
return of_pins->length / sizeof(u32);
861
862
862
863
npins = 0;
863
-
for_each_child_of_node(np, child) {
864
+
for_each_child_of_node_scoped(np, child) {
864
865
of_pins = of_find_property(child, "pinmux", NULL);
865
-
if (!of_pins) {
866
-
of_node_put(child);
866
+
if (!of_pins)
867
867
return -EINVAL;
868
-
}
869
868
870
869
npins += of_pins->length / sizeof(u32);
871
870
}
···
983
986
struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
984
987
struct rza1_mux_conf *mux_confs, *mux_conf;
985
988
unsigned int *grpins, *grpin;
986
-
struct device_node *child;
987
989
const char *grpname;
988
990
const char **fngrps;
989
991
int ret, npins;
···
1019
1023
1020
1024
ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
1021
1025
if (ret == -ENOENT)
1022
-
for_each_child_of_node(np, child) {
1026
+
for_each_child_of_node_scoped(np, child) {
1023
1027
ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
1024
1028
grpin);
1025
-
if (ret < 0) {
1026
-
of_node_put(child);
1029
+
if (ret < 0)
1027
1030
return ret;
1028
-
}
1029
1031
1030
1032
grpin += ret;
1031
1033
mux_conf += ret;
+700
-225
drivers/pinctrl/renesas/pinctrl-rzg2l.c
+700
-225
drivers/pinctrl/renesas/pinctrl-rzg2l.c
···
57
57
#define PIN_CFG_IOLH_C BIT(13)
58
58
#define PIN_CFG_SOFT_PS BIT(14)
59
59
#define PIN_CFG_OEN BIT(15)
60
-
#define PIN_CFG_VARIABLE BIT(16)
61
-
#define PIN_CFG_NOGPIO_INT BIT(17)
60
+
#define PIN_CFG_NOGPIO_INT BIT(16)
61
+
#define PIN_CFG_NOD BIT(17) /* N-ch Open Drain */
62
+
#define PIN_CFG_SMT BIT(18) /* Schmitt-trigger input control */
63
+
#define PIN_CFG_ELC BIT(19)
64
+
#define PIN_CFG_IOLH_RZV2H BIT(20)
65
+
66
+
#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
67
+
#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
62
68
63
69
#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
64
70
(PIN_CFG_IOLH_##group | \
···
79
73
#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
80
74
PIN_CFG_SOFT_PS)
81
75
76
+
#define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \
77
+
PIN_CFG_NOD | \
78
+
PIN_CFG_SR | \
79
+
PIN_CFG_SMT)
80
+
82
81
#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
83
82
PIN_CFG_FILONOFF | \
84
83
PIN_CFG_FILNUM | \
85
84
PIN_CFG_FILCLKSEL)
86
85
87
-
#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28)
88
-
#define PIN_CFG_PIN_REG_MASK GENMASK(27, 20)
89
-
#define PIN_CFG_MASK GENMASK(19, 0)
86
+
#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)
87
+
#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)
88
+
#define PIN_CFG_MASK GENMASK_ULL(31, 0)
90
89
91
90
/*
92
91
* m indicates the bitmap of supported pins, a is the register index
···
100
89
#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \
101
90
FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \
102
91
FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
92
+
#define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \
93
+
(RZG2L_VARIABLE_CFG | \
94
+
RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0))
103
95
104
96
/*
105
97
* n indicates number of pins in the port, a is the register index
106
98
* and f is pin configuration capabilities supported.
107
99
*/
108
100
#define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
101
+
#define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_VARIABLE_CFG | \
102
+
RZG2L_GPIO_PORT_PACK(n, a, 0))
109
103
104
+
#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56)
105
+
#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53)
110
106
/*
111
-
* BIT(63) indicates dedicated pin, p is the register index while
112
-
* referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
113
-
* (b * 8) and f is the pin configuration capabilities supported.
107
+
* p is the register index while referencing to SR/IEN/IOLH/FILxx
108
+
* registers, b is the register bits (b * 8) and f is the pin
109
+
* configuration capabilities supported.
114
110
*/
115
-
#define RZG2L_SINGLE_PIN BIT_ULL(63)
116
-
#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24)
117
-
#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20)
118
-
119
111
#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
120
112
FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \
121
113
FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \
···
128
114
FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \
129
115
FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg)))
130
116
117
+
#define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52)
118
+
#define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47)
119
+
#define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \
120
+
(FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \
121
+
FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \
122
+
FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))
123
+
131
124
#define P(off) (0x0000 + (off))
132
125
#define PM(off) (0x0100 + (off) * 2)
133
126
#define PMC(off) (0x0200 + (off))
134
127
#define PFC(off) (0x0400 + (off) * 4)
135
128
#define PIN(off) (0x0800 + (off))
136
129
#define IOLH(off) (0x1000 + (off) * 8)
130
+
#define SR(off) (0x1400 + (off) * 8)
137
131
#define IEN(off) (0x1800 + (off) * 8)
132
+
#define PUPD(off) (0x1C00 + (off) * 8)
138
133
#define ISEL(off) (0x2C00 + (off) * 8)
139
134
#define SD_CH(off, ch) ((off) + (ch) * 4)
140
135
#define ETH_POC(off, ch) ((off) + (ch) * 4)
141
136
#define QSPI (0x3008)
142
137
#define ETH_MODE (0x3018)
138
+
#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */
143
139
144
140
#define PVDD_2500 2 /* I/O domain voltage 2.5V */
145
141
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
···
157
133
158
134
#define PWPR_B0WI BIT(7) /* Bit Write Disable */
159
135
#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
136
+
#define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */
137
+
#define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */
160
138
161
139
#define PM_MASK 0x03
162
140
#define PFC_MASK 0x07
163
141
#define IEN_MASK 0x01
164
142
#define IOLH_MASK 0x03
143
+
#define SR_MASK 0x01
144
+
#define PUPD_MASK 0x03
165
145
166
146
#define PM_INPUT 0x1
167
147
#define PM_OUTPUT 0x2
···
176
148
#define RZG2L_TINT_MAX_INTERRUPT 32
177
149
#define RZG2L_TINT_IRQ_START_INDEX 9
178
150
#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
151
+
152
+
/* Custom pinconf parameters */
153
+
#define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1)
154
+
155
+
static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = {
156
+
{ "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },
157
+
};
158
+
159
+
#ifdef CONFIG_DEBUG_FS
160
+
static const struct pin_config_item renesas_rzv2h_conf_items[] = {
161
+
PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true),
162
+
};
163
+
#endif
179
164
180
165
/* Read/write 8 bits register */
181
166
#define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \
···
275
234
u64 config;
276
235
};
277
236
278
-
/**
279
-
* struct rzg2l_variable_pin_cfg - pin data cfg
280
-
* @cfg: port pin configuration
281
-
* @port: port number
282
-
* @pin: port pin
283
-
*/
284
-
struct rzg2l_variable_pin_cfg {
285
-
u32 cfg:20;
286
-
u32 port:5;
287
-
u32 pin:3;
288
-
};
237
+
struct rzg2l_pinctrl;
289
238
290
239
struct rzg2l_pinctrl_data {
291
240
const char * const *port_pins;
···
285
254
unsigned int n_port_pins;
286
255
unsigned int n_dedicated_pins;
287
256
const struct rzg2l_hwcfg *hwcfg;
288
-
const struct rzg2l_variable_pin_cfg *variable_pin_cfg;
257
+
const u64 *variable_pin_cfg;
289
258
unsigned int n_variable_pin_cfg;
259
+
unsigned int num_custom_params;
260
+
const struct pinconf_generic_params *custom_params;
261
+
#ifdef CONFIG_DEBUG_FS
262
+
const struct pin_config_item *custom_conf_items;
263
+
#endif
264
+
void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
265
+
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
266
+
u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
267
+
int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
268
+
int (*hw_to_bias_param)(unsigned int val);
269
+
int (*bias_param_to_hw)(enum pin_config_param param);
290
270
};
291
271
292
272
/**
···
364
322
365
323
static const u16 available_ps[] = { 1800, 2500, 3300 };
366
324
367
-
#ifdef CONFIG_RISCV
368
325
static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
369
326
u64 pincfg,
370
327
unsigned int port,
···
372
331
unsigned int i;
373
332
374
333
for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) {
375
-
if (pctrl->data->variable_pin_cfg[i].port == port &&
376
-
pctrl->data->variable_pin_cfg[i].pin == pin)
377
-
return (pincfg & ~PIN_CFG_VARIABLE) | pctrl->data->variable_pin_cfg[i].cfg;
334
+
u64 cfg = pctrl->data->variable_pin_cfg[i];
335
+
336
+
if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port &&
337
+
FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin)
338
+
return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg);
378
339
}
379
340
380
341
return 0;
381
342
}
382
343
383
-
static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = {
384
-
{
385
-
.port = 20,
386
-
.pin = 0,
387
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
388
-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
389
-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
390
-
},
391
-
{
392
-
.port = 20,
393
-
.pin = 1,
394
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
395
-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
396
-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
397
-
},
398
-
{
399
-
.port = 20,
400
-
.pin = 2,
401
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
402
-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
403
-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
404
-
},
405
-
{
406
-
.port = 20,
407
-
.pin = 3,
408
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
409
-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
410
-
},
411
-
{
412
-
.port = 20,
413
-
.pin = 4,
414
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
415
-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
416
-
},
417
-
{
418
-
.port = 20,
419
-
.pin = 5,
420
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
421
-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
422
-
},
423
-
{
424
-
.port = 20,
425
-
.pin = 6,
426
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
427
-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
428
-
},
429
-
{
430
-
.port = 20,
431
-
.pin = 7,
432
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
433
-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
434
-
},
435
-
{
436
-
.port = 23,
437
-
.pin = 1,
438
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
439
-
PIN_CFG_NOGPIO_INT
440
-
},
441
-
{
442
-
.port = 23,
443
-
.pin = 2,
444
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
445
-
PIN_CFG_NOGPIO_INT,
446
-
},
447
-
{
448
-
.port = 23,
449
-
.pin = 3,
450
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
451
-
PIN_CFG_NOGPIO_INT,
452
-
},
453
-
{
454
-
.port = 23,
455
-
.pin = 4,
456
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
457
-
PIN_CFG_NOGPIO_INT,
458
-
},
459
-
{
460
-
.port = 23,
461
-
.pin = 5,
462
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,
463
-
},
464
-
{
465
-
.port = 24,
466
-
.pin = 0,
467
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,
468
-
},
469
-
{
470
-
.port = 24,
471
-
.pin = 1,
472
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
473
-
PIN_CFG_NOGPIO_INT,
474
-
},
475
-
{
476
-
.port = 24,
477
-
.pin = 2,
478
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
479
-
PIN_CFG_NOGPIO_INT,
480
-
},
481
-
{
482
-
.port = 24,
483
-
.pin = 3,
484
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
485
-
PIN_CFG_NOGPIO_INT,
486
-
},
487
-
{
488
-
.port = 24,
489
-
.pin = 4,
490
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
491
-
PIN_CFG_NOGPIO_INT,
492
-
},
493
-
{
494
-
.port = 24,
495
-
.pin = 5,
496
-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
497
-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
498
-
PIN_CFG_NOGPIO_INT,
499
-
},
344
+
static const u64 r9a09g057_variable_pin_cfg[] = {
345
+
RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS),
346
+
RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
347
+
RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
348
+
RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
349
+
RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
350
+
RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
351
+
};
352
+
353
+
#ifdef CONFIG_RISCV
354
+
static const u64 r9a07g043f_variable_pin_cfg[] = {
355
+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
356
+
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
357
+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
358
+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
359
+
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
360
+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
361
+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
362
+
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
363
+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
364
+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
365
+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
366
+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
367
+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
368
+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
369
+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
370
+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
371
+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
372
+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
373
+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
374
+
RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
375
+
PIN_CFG_NOGPIO_INT),
376
+
RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
377
+
PIN_CFG_NOGPIO_INT),
378
+
RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
379
+
PIN_CFG_NOGPIO_INT),
380
+
RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
381
+
PIN_CFG_NOGPIO_INT),
382
+
RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
383
+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
384
+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
385
+
PIN_CFG_NOGPIO_INT),
386
+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
387
+
PIN_CFG_NOGPIO_INT),
388
+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
389
+
PIN_CFG_NOGPIO_INT),
390
+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
391
+
PIN_CFG_NOGPIO_INT),
392
+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
393
+
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
394
+
PIN_CFG_NOGPIO_INT),
500
395
};
501
396
#endif
397
+
398
+
static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
399
+
{
400
+
writeb(val, pctrl->base + offset);
401
+
}
402
+
403
+
static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
404
+
{
405
+
const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
406
+
u8 pwpr;
407
+
408
+
pwpr = readb(pctrl->base + regs->pwpr);
409
+
writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr);
410
+
writeb(val, pctrl->base + offset);
411
+
writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
412
+
}
502
413
503
414
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
504
415
u8 pin, u8 off, u8 func)
505
416
{
506
-
const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
507
417
unsigned long flags;
508
418
u32 reg;
509
419
···
465
473
reg &= ~(PM_MASK << (pin * 2));
466
474
writew(reg, pctrl->base + PM(off));
467
475
476
+
pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
477
+
468
478
/* Temporarily switch to GPIO mode with PMC register */
469
479
reg = readb(pctrl->base + PMC(off));
470
480
writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
471
-
472
-
/* Set the PWPR register to allow PFC register to write */
473
-
writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
474
-
writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
475
481
476
482
/* Select Pin function mode with PFC register */
477
483
reg = readl(pctrl->base + PFC(off));
478
484
reg &= ~(PFC_MASK << (pin * 4));
479
485
writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
480
486
481
-
/* Set the PWPR register to be write-protected */
482
-
writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
483
-
writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
484
-
485
487
/* Switch to Peripheral pin function with PMC register */
486
488
reg = readb(pctrl->base + PMC(off));
487
489
writeb(reg | BIT(pin), pctrl->base + PMC(off));
490
+
491
+
pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);
488
492
489
493
spin_unlock_irqrestore(&pctrl->lock, flags);
490
494
};
···
587
599
return -EINVAL;
588
600
}
589
601
590
-
ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
602
+
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
591
603
if (ret < 0)
592
604
return ret;
593
605
···
733
745
unsigned int *num_maps)
734
746
{
735
747
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
736
-
struct device_node *child;
737
748
unsigned int index;
738
749
int ret;
739
750
···
740
753
*num_maps = 0;
741
754
index = 0;
742
755
743
-
for_each_child_of_node(np, child) {
756
+
for_each_child_of_node_scoped(np, child) {
744
757
ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map,
745
758
num_maps, &index);
746
-
if (ret < 0) {
747
-
of_node_put(child);
759
+
if (ret < 0)
748
760
goto done;
749
-
}
750
761
}
751
762
752
763
if (*num_maps == 0) {
···
999
1014
return false;
1000
1015
}
1001
1016
1002
-
static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
1017
+
static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1003
1018
{
1004
-
if (!(caps & PIN_CFG_OEN))
1005
-
return false;
1019
+
u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1020
+
u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);
1021
+
u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
1006
1022
1007
-
if (pin > max_pin)
1008
-
return false;
1023
+
if (pin > pctrl->data->hwcfg->oen_max_pin)
1024
+
return -EINVAL;
1009
1025
1010
-
return true;
1011
-
}
1012
-
1013
-
static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
1014
-
{
1015
-
if (pin)
1016
-
pin *= 2;
1017
-
1018
-
if (offset / RZG2L_PINS_PER_PORT == max_port)
1019
-
pin += 1;
1020
-
1021
-
return pin;
1022
-
}
1023
-
1024
-
static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
1025
-
{
1026
-
u8 max_port = pctrl->data->hwcfg->oen_max_port;
1027
-
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
1028
-
u8 bit;
1029
-
1030
-
if (!rzg2l_oen_is_supported(caps, pin, max_pin))
1026
+
/*
1027
+
* We can determine which Ethernet interface we're dealing with from
1028
+
* the caps.
1029
+
*/
1030
+
if (caps & PIN_CFG_IO_VMC_ETH0)
1031
1031
return 0;
1032
+
if (caps & PIN_CFG_IO_VMC_ETH1)
1033
+
return 1;
1032
1034
1033
-
bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
1035
+
return -EINVAL;
1036
+
}
1037
+
1038
+
static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1039
+
{
1040
+
int bit;
1041
+
1042
+
bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1043
+
if (bit < 0)
1044
+
return 0;
1034
1045
1035
1046
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
1036
1047
}
1037
1048
1038
-
static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
1049
+
static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1039
1050
{
1040
-
u8 max_port = pctrl->data->hwcfg->oen_max_port;
1041
-
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
1042
1051
unsigned long flags;
1043
-
u8 val, bit;
1052
+
int bit;
1053
+
u8 val;
1044
1054
1045
-
if (!rzg2l_oen_is_supported(caps, pin, max_pin))
1046
-
return -EINVAL;
1047
-
1048
-
bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
1055
+
bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1056
+
if (bit < 0)
1057
+
return bit;
1049
1058
1050
1059
spin_lock_irqsave(&pctrl->lock, flags);
1051
1060
val = readb(pctrl->base + ETH_MODE);
···
1053
1074
return 0;
1054
1075
}
1055
1076
1077
+
static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1078
+
{
1079
+
u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1080
+
u8 port, pin, bit;
1081
+
1082
+
if (*pin_data & RZG2L_SINGLE_PIN)
1083
+
return -EINVAL;
1084
+
1085
+
port = RZG2L_PIN_ID_TO_PORT(_pin);
1086
+
pin = RZG2L_PIN_ID_TO_PIN(_pin);
1087
+
if (pin > pctrl->data->hwcfg->oen_max_pin)
1088
+
return -EINVAL;
1089
+
1090
+
bit = pin * 2;
1091
+
if (port == pctrl->data->hwcfg->oen_max_port)
1092
+
bit += 1;
1093
+
1094
+
return bit;
1095
+
}
1096
+
1097
+
static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1098
+
{
1099
+
int bit;
1100
+
1101
+
bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1102
+
if (bit < 0)
1103
+
return bit;
1104
+
1105
+
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
1106
+
}
1107
+
1108
+
static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1109
+
{
1110
+
unsigned long flags;
1111
+
int bit;
1112
+
u8 val;
1113
+
1114
+
bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1115
+
if (bit < 0)
1116
+
return bit;
1117
+
1118
+
spin_lock_irqsave(&pctrl->lock, flags);
1119
+
val = readb(pctrl->base + ETH_MODE);
1120
+
if (oen)
1121
+
val &= ~BIT(bit);
1122
+
else
1123
+
val |= BIT(bit);
1124
+
writeb(val, pctrl->base + ETH_MODE);
1125
+
spin_unlock_irqrestore(&pctrl->lock, flags);
1126
+
1127
+
return 0;
1128
+
}
1129
+
1130
+
static int rzg2l_hw_to_bias_param(unsigned int bias)
1131
+
{
1132
+
switch (bias) {
1133
+
case 0:
1134
+
return PIN_CONFIG_BIAS_DISABLE;
1135
+
case 1:
1136
+
return PIN_CONFIG_BIAS_PULL_UP;
1137
+
case 2:
1138
+
return PIN_CONFIG_BIAS_PULL_DOWN;
1139
+
default:
1140
+
break;
1141
+
}
1142
+
1143
+
return -EINVAL;
1144
+
}
1145
+
1146
+
static int rzg2l_bias_param_to_hw(enum pin_config_param param)
1147
+
{
1148
+
switch (param) {
1149
+
case PIN_CONFIG_BIAS_DISABLE:
1150
+
return 0;
1151
+
case PIN_CONFIG_BIAS_PULL_UP:
1152
+
return 1;
1153
+
case PIN_CONFIG_BIAS_PULL_DOWN:
1154
+
return 2;
1155
+
default:
1156
+
break;
1157
+
}
1158
+
1159
+
return -EINVAL;
1160
+
}
1161
+
1162
+
static int rzv2h_hw_to_bias_param(unsigned int bias)
1163
+
{
1164
+
switch (bias) {
1165
+
case 0:
1166
+
case 1:
1167
+
return PIN_CONFIG_BIAS_DISABLE;
1168
+
case 2:
1169
+
return PIN_CONFIG_BIAS_PULL_DOWN;
1170
+
case 3:
1171
+
return PIN_CONFIG_BIAS_PULL_UP;
1172
+
default:
1173
+
break;
1174
+
}
1175
+
1176
+
return -EINVAL;
1177
+
}
1178
+
1179
+
static int rzv2h_bias_param_to_hw(enum pin_config_param param)
1180
+
{
1181
+
switch (param) {
1182
+
case PIN_CONFIG_BIAS_DISABLE:
1183
+
return 0;
1184
+
case PIN_CONFIG_BIAS_PULL_DOWN:
1185
+
return 2;
1186
+
case PIN_CONFIG_BIAS_PULL_UP:
1187
+
return 3;
1188
+
default:
1189
+
break;
1190
+
}
1191
+
1192
+
return -EINVAL;
1193
+
}
1194
+
1195
+
static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1196
+
{
1197
+
static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
1198
+
"XSPI0_RESET0N", "XSPI0_CS0N",
1199
+
"XSPI0_CKN", "XSPI0_CKP" };
1200
+
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];
1201
+
unsigned int i;
1202
+
1203
+
for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
1204
+
if (!strcmp(pin_desc->name, pin_names[i]))
1205
+
return i;
1206
+
}
1207
+
1208
+
/* Should not happen. */
1209
+
return 0;
1210
+
}
1211
+
1212
+
static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1213
+
{
1214
+
u8 bit;
1215
+
1216
+
bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
1217
+
1218
+
return !(readb(pctrl->base + PFC_OEN) & BIT(bit));
1219
+
}
1220
+
1221
+
static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1222
+
{
1223
+
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1224
+
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
1225
+
unsigned long flags;
1226
+
u8 val, bit;
1227
+
u8 pwpr;
1228
+
1229
+
bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
1230
+
spin_lock_irqsave(&pctrl->lock, flags);
1231
+
val = readb(pctrl->base + PFC_OEN);
1232
+
if (oen)
1233
+
val &= ~BIT(bit);
1234
+
else
1235
+
val |= BIT(bit);
1236
+
1237
+
pwpr = readb(pctrl->base + regs->pwpr);
1238
+
writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
1239
+
writeb(val, pctrl->base + PFC_OEN);
1240
+
writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
1241
+
spin_unlock_irqrestore(&pctrl->lock, flags);
1242
+
1243
+
return 0;
1244
+
}
1245
+
1056
1246
static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
1057
1247
unsigned int _pin,
1058
1248
unsigned long *config)
1059
1249
{
1060
1250
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1061
-
enum pin_config_param param = pinconf_to_config_param(*config);
1062
1251
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1063
1252
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
1253
+
u32 param = pinconf_to_config_param(*config);
1064
1254
u64 *pin_data = pin->drv_data;
1065
1255
unsigned int arg = 0;
1066
-
u32 off, cfg;
1256
+
u32 off;
1257
+
u32 cfg;
1067
1258
int ret;
1068
1259
u8 bit;
1069
1260
···
1261
1112
break;
1262
1113
1263
1114
case PIN_CONFIG_OUTPUT_ENABLE:
1264
-
arg = rzg2l_read_oen(pctrl, cfg, _pin, bit);
1115
+
if (!pctrl->data->oen_read || !(cfg & PIN_CFG_OEN))
1116
+
return -EOPNOTSUPP;
1117
+
arg = pctrl->data->oen_read(pctrl, _pin);
1265
1118
if (!arg)
1266
1119
return -EINVAL;
1267
1120
break;
···
1273
1122
if (ret < 0)
1274
1123
return ret;
1275
1124
arg = ret;
1125
+
break;
1126
+
1127
+
case PIN_CONFIG_SLEW_RATE:
1128
+
if (!(cfg & PIN_CFG_SR))
1129
+
return -EINVAL;
1130
+
1131
+
arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK);
1132
+
break;
1133
+
1134
+
case PIN_CONFIG_BIAS_DISABLE:
1135
+
case PIN_CONFIG_BIAS_PULL_UP:
1136
+
case PIN_CONFIG_BIAS_PULL_DOWN:
1137
+
if (!(cfg & PIN_CFG_PUPD))
1138
+
return -EINVAL;
1139
+
1140
+
arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK);
1141
+
ret = pctrl->data->hw_to_bias_param(arg);
1142
+
if (ret < 0)
1143
+
return ret;
1144
+
1145
+
if (ret != param)
1146
+
return -EINVAL;
1147
+
/* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */
1148
+
arg = 1;
1276
1149
break;
1277
1150
1278
1151
case PIN_CONFIG_DRIVE_STRENGTH: {
···
1342
1167
break;
1343
1168
}
1344
1169
1170
+
case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
1171
+
if (!(cfg & PIN_CFG_IOLH_RZV2H))
1172
+
return -EINVAL;
1173
+
1174
+
arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1175
+
break;
1176
+
1345
1177
default:
1346
1178
return -ENOTSUPP;
1347
1179
}
···
1368
1186
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1369
1187
struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
1370
1188
u64 *pin_data = pin->drv_data;
1371
-
enum pin_config_param param;
1372
1189
unsigned int i, arg, index;
1373
-
u32 cfg, off;
1190
+
u32 off, param;
1191
+
u32 cfg;
1374
1192
int ret;
1375
1193
u8 bit;
1376
1194
···
1402
1220
1403
1221
case PIN_CONFIG_OUTPUT_ENABLE:
1404
1222
arg = pinconf_to_config_argument(_configs[i]);
1405
-
ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg);
1223
+
if (!pctrl->data->oen_write || !(cfg & PIN_CFG_OEN))
1224
+
return -EOPNOTSUPP;
1225
+
ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
1406
1226
if (ret)
1407
1227
return ret;
1408
1228
break;
1409
1229
1410
1230
case PIN_CONFIG_POWER_SOURCE:
1411
1231
settings.power_source = pinconf_to_config_argument(_configs[i]);
1232
+
break;
1233
+
1234
+
case PIN_CONFIG_SLEW_RATE:
1235
+
arg = pinconf_to_config_argument(_configs[i]);
1236
+
1237
+
if (!(cfg & PIN_CFG_SR) || arg > 1)
1238
+
return -EINVAL;
1239
+
1240
+
rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg);
1241
+
break;
1242
+
1243
+
case PIN_CONFIG_BIAS_DISABLE:
1244
+
case PIN_CONFIG_BIAS_PULL_UP:
1245
+
case PIN_CONFIG_BIAS_PULL_DOWN:
1246
+
if (!(cfg & PIN_CFG_PUPD))
1247
+
return -EINVAL;
1248
+
1249
+
ret = pctrl->data->bias_param_to_hw(param);
1250
+
if (ret < 0)
1251
+
return ret;
1252
+
1253
+
rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret);
1412
1254
break;
1413
1255
1414
1256
case PIN_CONFIG_DRIVE_STRENGTH:
···
1474
1268
return -EINVAL;
1475
1269
1476
1270
rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
1271
+
break;
1272
+
1273
+
case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
1274
+
if (!(cfg & PIN_CFG_IOLH_RZV2H))
1275
+
return -EINVAL;
1276
+
1277
+
arg = pinconf_to_config_argument(_configs[i]);
1278
+
if (arg > 3)
1279
+
return -EINVAL;
1280
+
rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg);
1477
1281
break;
1478
1282
1479
1283
default:
···
1627
1411
/* Select GPIO mode in PMC Register */
1628
1412
reg8 = readb(pctrl->base + PMC(off));
1629
1413
reg8 &= ~BIT(bit);
1630
-
writeb(reg8, pctrl->base + PMC(off));
1414
+
pctrl->data->pmc_writeb(pctrl, reg8, PMC(off));
1631
1415
1632
1416
spin_unlock_irqrestore(&pctrl->lock, flags);
1633
1417
···
1829
1613
RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
1830
1614
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
1831
1615
RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
1832
-
RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1616
+
RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
1833
1617
RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1834
1618
RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1835
1619
RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
···
1838
1622
RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1839
1623
RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1840
1624
RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1841
-
RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1625
+
RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
1842
1626
RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1843
1627
RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1844
1628
RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
···
1862
1646
1863
1647
static const u64 r9a07g043_gpio_configs[] = {
1864
1648
RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
1865
-
RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1649
+
RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
1866
1650
RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1867
1651
RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1868
1652
RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1869
1653
RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
1870
1654
RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
1871
-
RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1655
+
RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
1872
1656
RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1873
1657
RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1874
1658
RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
···
1885
1669
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1886
1670
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
1887
1671
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
1888
-
RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE), /* P20 */
1672
+
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */
1889
1673
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1890
1674
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */
1891
1675
RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1892
1676
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */
1893
-
RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE), /* P23 */
1894
-
RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE), /* P24 */
1677
+
RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */
1678
+
RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */
1895
1679
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF |
1896
1680
PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
1897
1681
PIN_CFG_NOGPIO_INT), /* P25 */
···
1931
1715
RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
1932
1716
RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
1933
1717
RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
1718
+
};
1719
+
1720
+
static const char * const rzv2h_gpio_names[] = {
1721
+
"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
1722
+
"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
1723
+
"P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
1724
+
"P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
1725
+
"P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
1726
+
"P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
1727
+
"P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
1728
+
"P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
1729
+
"P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
1730
+
"P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97",
1731
+
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
1732
+
"PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
1733
+
};
1734
+
1735
+
static const u64 r9a09g057_gpio_configs[] = {
1736
+
RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
1737
+
RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS), /* P1 */
1738
+
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
1739
+
PIN_CFG_NOD), /* P2 */
1740
+
RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
1741
+
RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
1742
+
RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
1743
+
RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS |
1744
+
PIN_CFG_ELC), /* P6 */
1745
+
RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS), /* P7 */
1746
+
RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS |
1747
+
PIN_CFG_ELC), /* P8 */
1748
+
RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */
1749
+
RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */
1750
+
RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b), /* PB */
1934
1751
};
1935
1752
1936
1753
static const struct {
···
2090
1841
PIN_CFG_IO_VMC_SD1)) },
2091
1842
{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2092
1843
PIN_CFG_IO_VMC_SD1)) },
1844
+
};
1845
+
1846
+
static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
1847
+
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
1848
+
PIN_CFG_FILCLKSEL)) },
1849
+
{ "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1850
+
PIN_CFG_IEN)) },
1851
+
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
1852
+
{ "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1853
+
PIN_CFG_PUPD | PIN_CFG_NOD)) },
1854
+
{ "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1855
+
PIN_CFG_PUPD | PIN_CFG_NOD)) },
1856
+
{ "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1857
+
PIN_CFG_PUPD)) },
1858
+
{ "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1859
+
PIN_CFG_PUPD)) },
1860
+
{ "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1861
+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
1862
+
{ "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1863
+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
1864
+
{ "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1865
+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
1866
+
{ "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1867
+
PIN_CFG_PUPD)) },
1868
+
{ "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1869
+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
1870
+
{ "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
1871
+
{ "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
1872
+
{ "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
1873
+
{ "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1874
+
PIN_CFG_PUPD)) },
1875
+
{ "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1876
+
PIN_CFG_PUPD)) },
1877
+
{ "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1878
+
PIN_CFG_PUPD)) },
1879
+
{ "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1880
+
PIN_CFG_PUPD)) },
1881
+
{ "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1882
+
PIN_CFG_PUPD)) },
1883
+
{ "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1884
+
PIN_CFG_PUPD)) },
1885
+
{ "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1886
+
PIN_CFG_PUPD)) },
1887
+
{ "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1888
+
PIN_CFG_PUPD)) },
1889
+
{ "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
1890
+
{ "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1891
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1892
+
{ "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
1893
+
{ "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1894
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1895
+
{ "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1896
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1897
+
{ "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1898
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1899
+
{ "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1900
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1901
+
{ "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1902
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1903
+
{ "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1904
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1905
+
{ "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1906
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1907
+
{ "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1908
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1909
+
{ "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
1910
+
{ "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1911
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1912
+
{ "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1913
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1914
+
{ "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1915
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1916
+
{ "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1917
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1918
+
{ "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1919
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1920
+
{ "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
1921
+
{ "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
1922
+
{ "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1923
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1924
+
{ "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1925
+
PIN_CFG_PUPD)) },
1926
+
{ "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
1927
+
{ "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1928
+
PIN_CFG_PUPD)) },
1929
+
{ "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1930
+
PIN_CFG_PUPD)) },
1931
+
{ "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
1932
+
{ "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
1933
+
{ "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1934
+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
1935
+
{ "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
1936
+
{ "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
1937
+
{ "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1938
+
PIN_CFG_PUPD)) },
1939
+
{ "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1940
+
PIN_CFG_PUPD)) },
1941
+
{ "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1942
+
PIN_CFG_PUPD)) },
1943
+
{ "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1944
+
PIN_CFG_PUPD)) },
1945
+
{ "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
1946
+
{ "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
1947
+
{ "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
1948
+
{ "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
1949
+
{ "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1950
+
PIN_CFG_IEN | PIN_CFG_PUPD)) },
1951
+
{ "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1952
+
PIN_CFG_PUPD)) },
1953
+
{ "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
1954
+
{ "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1955
+
PIN_CFG_PUPD)) },
1956
+
{ "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1957
+
PIN_CFG_PUPD)) },
1958
+
{ "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
1959
+
{ "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
1960
+
{ "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1961
+
PIN_CFG_PUPD | PIN_CFG_OEN)) },
1962
+
{ "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
1963
+
{ "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
1964
+
{ "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1965
+
PIN_CFG_PUPD)) },
1966
+
{ "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1967
+
PIN_CFG_PUPD)) },
1968
+
{ "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1969
+
PIN_CFG_PUPD)) },
1970
+
{ "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
1971
+
PIN_CFG_PUPD)) },
1972
+
{ "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
1973
+
{ "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
1974
+
{ "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
1975
+
{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
2093
1976
};
2094
1977
2095
1978
static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
···
2661
2280
pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;
2662
2281
pctrl->desc.confops = &rzg2l_pinctrl_confops;
2663
2282
pctrl->desc.owner = THIS_MODULE;
2283
+
if (pctrl->data->num_custom_params) {
2284
+
pctrl->desc.num_custom_params = pctrl->data->num_custom_params;
2285
+
pctrl->desc.custom_params = pctrl->data->custom_params;
2286
+
#ifdef CONFIG_DEBUG_FS
2287
+
pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items;
2288
+
#endif
2289
+
}
2664
2290
2665
2291
pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
2666
2292
if (!pins)
···
2687
2299
if (i && !(i % RZG2L_PINS_PER_PORT))
2688
2300
j++;
2689
2301
pin_data[i] = pctrl->data->port_pin_configs[j];
2690
-
#ifdef CONFIG_RISCV
2691
-
if (pin_data[i] & PIN_CFG_VARIABLE)
2302
+
if (pin_data[i] & RZG2L_VARIABLE_CFG)
2692
2303
pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,
2693
2304
pin_data[i],
2694
2305
j,
2695
2306
i % RZG2L_PINS_PER_PORT);
2696
-
#endif
2697
2307
pins[i].drv_data = &pin_data[i];
2698
2308
}
2699
2309
···
2759
2373
2760
2374
BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
2761
2375
ARRAY_SIZE(rzg2l_gpio_names));
2376
+
2377
+
BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
2378
+
ARRAY_SIZE(rzv2h_gpio_names));
2762
2379
2763
2380
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
2764
2381
if (!pctrl)
···
2851
2462
static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
2852
2463
{
2853
2464
struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache;
2465
+
u32 caps;
2466
+
u32 i;
2854
2467
2855
2468
/*
2856
2469
* Make sure entries in pctrl->data->n_dedicated_pins[] having the same
2857
2470
* port offset are close together.
2858
2471
*/
2859
-
for (u32 i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {
2472
+
for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {
2860
2473
bool has_iolh, has_ien;
2861
2474
u32 off, next_off = 0;
2862
2475
u64 cfg, next_cfg;
···
2910
2519
static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
2911
2520
{
2912
2521
u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
2913
-
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
2914
-
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
2522
+
unsigned long flags;
2915
2523
2916
-
/* Set the PWPR register to allow PFC register to write. */
2917
-
writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
2918
-
writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
2524
+
spin_lock_irqsave(&pctrl->lock, flags);
2525
+
pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
2919
2526
2920
2527
/* Restore port registers. */
2921
2528
for (u32 port = 0; port < nports; port++) {
···
2956
2567
}
2957
2568
}
2958
2569
2959
-
/* Set the PWPR register to be write-protected. */
2960
-
writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
2961
-
writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
2570
+
pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);
2571
+
spin_unlock_irqrestore(&pctrl->lock, flags);
2962
2572
}
2963
2573
2964
2574
static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
···
2971
2583
rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true);
2972
2584
2973
2585
for (u8 i = 0; i < 2; i++) {
2974
-
cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i));
2975
-
cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));
2586
+
if (regs->sd_ch)
2587
+
cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i));
2588
+
if (regs->eth_poc)
2589
+
cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));
2976
2590
}
2977
2591
2978
2592
cache->qspi = readb(pctrl->base + QSPI);
···
3005
2615
writeb(cache->qspi, pctrl->base + QSPI);
3006
2616
writeb(cache->eth_mode, pctrl->base + ETH_MODE);
3007
2617
for (u8 i = 0; i < 2; i++) {
3008
-
writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
3009
-
writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i));
2618
+
if (regs->sd_ch)
2619
+
writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
2620
+
if (regs->eth_poc)
2621
+
writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i));
3010
2622
}
3011
2623
3012
2624
rzg2l_pinctrl_pm_setup_pfc(pctrl);
···
3017
2625
rzg2l_gpio_irq_restore(pctrl);
3018
2626
3019
2627
return 0;
2628
+
}
2629
+
2630
+
static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
2631
+
{
2632
+
const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
2633
+
2634
+
if (lock) {
2635
+
/* Set the PWPR register to be write-protected */
2636
+
writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
2637
+
writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
2638
+
} else {
2639
+
/* Set the PWPR register to allow PFC register to write */
2640
+
writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
2641
+
writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
2642
+
}
2643
+
}
2644
+
2645
+
static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
2646
+
{
2647
+
const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
2648
+
u8 pwpr;
2649
+
2650
+
if (lock) {
2651
+
/* Set the PWPR register to be write-protected */
2652
+
pwpr = readb(pctrl->base + regs->pwpr);
2653
+
writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
2654
+
} else {
2655
+
/* Set the PWPR register to allow PFC and PMC register to write */
2656
+
pwpr = readb(pctrl->base + regs->pwpr);
2657
+
writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr);
2658
+
}
3020
2659
}
3021
2660
3022
2661
static const struct rzg2l_hwcfg rzg2l_hwcfg = {
···
3061
2638
[RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
3062
2639
},
3063
2640
.iolh_groupb_oi = { 100, 66, 50, 33, },
2641
+
.oen_max_pin = 0,
3064
2642
};
3065
2643
3066
2644
static const struct rzg2l_hwcfg rzg3s_hwcfg = {
···
3096
2672
.oen_max_port = 7, /* P7_1 is the maximum OEN port. */
3097
2673
};
3098
2674
2675
+
static const struct rzg2l_hwcfg rzv2h_hwcfg = {
2676
+
.regs = {
2677
+
.pwpr = 0x3c04,
2678
+
},
2679
+
};
2680
+
3099
2681
static struct rzg2l_pinctrl_data r9a07g043_data = {
3100
2682
.port_pins = rzg2l_gpio_names,
3101
2683
.port_pin_configs = r9a07g043_gpio_configs,
···
3114
2684
.variable_pin_cfg = r9a07g043f_variable_pin_cfg,
3115
2685
.n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),
3116
2686
#endif
2687
+
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
2688
+
.pmc_writeb = &rzg2l_pmc_writeb,
2689
+
.oen_read = &rzg2l_read_oen,
2690
+
.oen_write = &rzg2l_write_oen,
2691
+
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
2692
+
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
3117
2693
};
3118
2694
3119
2695
static struct rzg2l_pinctrl_data r9a07g044_data = {
···
3131
2695
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
3132
2696
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
3133
2697
.hwcfg = &rzg2l_hwcfg,
2698
+
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
2699
+
.pmc_writeb = &rzg2l_pmc_writeb,
2700
+
.oen_read = &rzg2l_read_oen,
2701
+
.oen_write = &rzg2l_write_oen,
2702
+
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
2703
+
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
3134
2704
};
3135
2705
3136
2706
static struct rzg2l_pinctrl_data r9a08g045_data = {
···
3147
2705
.n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
3148
2706
.n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
3149
2707
.hwcfg = &rzg3s_hwcfg,
2708
+
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
2709
+
.pmc_writeb = &rzg2l_pmc_writeb,
2710
+
.oen_read = &rzg3s_oen_read,
2711
+
.oen_write = &rzg3s_oen_write,
2712
+
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
2713
+
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
2714
+
};
2715
+
2716
+
static struct rzg2l_pinctrl_data r9a09g057_data = {
2717
+
.port_pins = rzv2h_gpio_names,
2718
+
.port_pin_configs = r9a09g057_gpio_configs,
2719
+
.n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
2720
+
.dedicated_pins = rzv2h_dedicated_pins,
2721
+
.n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
2722
+
.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins),
2723
+
.hwcfg = &rzv2h_hwcfg,
2724
+
.variable_pin_cfg = r9a09g057_variable_pin_cfg,
2725
+
.n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
2726
+
.num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
2727
+
.custom_params = renesas_rzv2h_custom_bindings,
2728
+
#ifdef CONFIG_DEBUG_FS
2729
+
.custom_conf_items = renesas_rzv2h_conf_items,
2730
+
#endif
2731
+
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
2732
+
.pmc_writeb = &rzv2h_pmc_writeb,
2733
+
.oen_read = &rzv2h_oen_read,
2734
+
.oen_write = &rzv2h_oen_write,
2735
+
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
2736
+
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
3150
2737
};
3151
2738
3152
2739
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
···
3190
2719
{
3191
2720
.compatible = "renesas,r9a08g045-pinctrl",
3192
2721
.data = &r9a08g045_data,
2722
+
},
2723
+
{
2724
+
.compatible = "renesas,r9a09g057-pinctrl",
2725
+
.data = &r9a09g057_data,
3193
2726
},
3194
2727
{ /* sentinel */ }
3195
2728
};
+8
-18
drivers/pinctrl/renesas/pinctrl-rzn1.c
+8
-18
drivers/pinctrl/renesas/pinctrl-rzn1.c
···
404
404
struct pinctrl_map **map,
405
405
unsigned int *num_maps)
406
406
{
407
-
struct device_node *child;
408
407
int ret;
409
408
410
409
*map = NULL;
···
413
414
if (ret < 0)
414
415
return ret;
415
416
416
-
for_each_child_of_node(np, child) {
417
+
for_each_child_of_node_scoped(np, child) {
417
418
ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps);
418
-
if (ret < 0) {
419
-
of_node_put(child);
419
+
if (ret < 0)
420
420
return ret;
421
-
}
422
421
}
423
422
424
423
return 0;
···
737
740
738
741
static int rzn1_pinctrl_count_function_groups(struct device_node *np)
739
742
{
740
-
struct device_node *child;
741
743
int count = 0;
742
744
743
745
if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0)
744
746
count++;
745
747
746
-
for_each_child_of_node(np, child) {
748
+
for_each_child_of_node_scoped(np, child) {
747
749
if (of_property_count_u32_elems(child, RZN1_PINS_PROP) > 0)
748
750
count++;
749
751
}
···
756
760
{
757
761
struct rzn1_pmx_func *func;
758
762
struct rzn1_pin_group *grp;
759
-
struct device_node *child;
760
763
unsigned int i = 0;
761
764
int ret;
762
765
···
788
793
ipctl->ngroups++;
789
794
}
790
795
791
-
for_each_child_of_node(np, child) {
796
+
for_each_child_of_node_scoped(np, child) {
792
797
func->groups[i] = child->name;
793
798
grp = &ipctl->groups[ipctl->ngroups];
794
799
grp->func = func->name;
795
800
ret = rzn1_pinctrl_parse_groups(child, grp, ipctl);
796
-
if (ret < 0) {
797
-
of_node_put(child);
801
+
if (ret < 0)
798
802
return ret;
799
-
}
800
803
i++;
801
804
ipctl->ngroups++;
802
805
}
···
809
816
struct rzn1_pinctrl *ipctl)
810
817
{
811
818
struct device_node *np = pdev->dev.of_node;
812
-
struct device_node *child;
813
819
unsigned int maxgroups = 0;
814
820
unsigned int i = 0;
815
821
int nfuncs = 0;
···
826
834
return -ENOMEM;
827
835
828
836
ipctl->ngroups = 0;
829
-
for_each_child_of_node(np, child)
837
+
for_each_child_of_node_scoped(np, child)
830
838
maxgroups += rzn1_pinctrl_count_function_groups(child);
831
839
832
840
ipctl->groups = devm_kmalloc_array(&pdev->dev,
···
836
844
if (!ipctl->groups)
837
845
return -ENOMEM;
838
846
839
-
for_each_child_of_node(np, child) {
847
+
for_each_child_of_node_scoped(np, child) {
840
848
ret = rzn1_pinctrl_parse_functions(child, ipctl, i++);
841
-
if (ret < 0) {
842
-
of_node_put(child);
849
+
if (ret < 0)
843
850
return ret;
844
-
}
845
851
}
846
852
847
853
return 0;
+2
-5
drivers/pinctrl/renesas/pinctrl-rzv2m.c
+2
-5
drivers/pinctrl/renesas/pinctrl-rzv2m.c
···
388
388
unsigned int *num_maps)
389
389
{
390
390
struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
391
-
struct device_node *child;
392
391
unsigned int index;
393
392
int ret;
394
393
···
395
396
*num_maps = 0;
396
397
index = 0;
397
398
398
-
for_each_child_of_node(np, child) {
399
+
for_each_child_of_node_scoped(np, child) {
399
400
ret = rzv2m_dt_subnode_to_map(pctldev, child, np, map,
400
401
num_maps, &index);
401
-
if (ret < 0) {
402
-
of_node_put(child);
402
+
if (ret < 0)
403
403
goto done;
404
-
}
405
404
}
406
405
407
406
if (*num_maps == 0) {
+2
-5
drivers/pinctrl/renesas/pinctrl.c
+2
-5
drivers/pinctrl/renesas/pinctrl.c
···
241
241
{
242
242
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
243
243
struct device *dev = pmx->pfc->dev;
244
-
struct device_node *child;
245
244
unsigned int index;
246
245
int ret;
247
246
···
248
249
*num_maps = 0;
249
250
index = 0;
250
251
251
-
for_each_child_of_node(np, child) {
252
+
for_each_child_of_node_scoped(np, child) {
252
253
ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps,
253
254
&index);
254
-
if (ret < 0) {
255
-
of_node_put(child);
255
+
if (ret < 0)
256
256
goto done;
257
-
}
258
257
}
259
258
260
259
/* If no mapping has been found in child nodes try the config node. */
+4
-9
drivers/pinctrl/spear/pinctrl-spear.c
+4
-9
drivers/pinctrl/spear/pinctrl-spear.c
···
151
151
unsigned *num_maps)
152
152
{
153
153
struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
154
-
struct device_node *np;
155
154
struct property *prop;
156
155
const char *function, *group;
157
156
int ret, index = 0, count = 0;
158
157
159
158
/* calculate number of maps required */
160
-
for_each_child_of_node(np_config, np) {
159
+
for_each_child_of_node_scoped(np_config, np) {
161
160
ret = of_property_read_string(np, "st,function", &function);
162
-
if (ret < 0) {
163
-
of_node_put(np);
161
+
if (ret < 0)
164
162
return ret;
165
-
}
166
163
167
164
ret = of_property_count_strings(np, "st,pins");
168
-
if (ret < 0) {
169
-
of_node_put(np);
165
+
if (ret < 0)
170
166
return ret;
171
-
}
172
167
173
168
count += ret;
174
169
}
···
177
182
if (!*map)
178
183
return -ENOMEM;
179
184
180
-
for_each_child_of_node(np_config, np) {
185
+
for_each_child_of_node_scoped(np_config, np) {
181
186
of_property_read_string(np, "st,function", &function);
182
187
of_property_for_each_string(np, "st,pins", prop, group) {
183
188
(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
+4
-10
drivers/pinctrl/sprd/pinctrl-sprd.c
+4
-10
drivers/pinctrl/sprd/pinctrl-sprd.c
···
934
934
{
935
935
struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
936
936
struct device_node *np = sprd_pctl->dev->of_node;
937
-
struct device_node *child, *sub_child;
938
937
struct sprd_pin_group *grp;
939
938
const char **temp;
940
939
int ret;
···
961
962
temp = info->grp_names;
962
963
grp = info->groups;
963
964
964
-
for_each_child_of_node(np, child) {
965
+
for_each_child_of_node_scoped(np, child) {
965
966
ret = sprd_pinctrl_parse_groups(child, sprd_pctl, grp);
966
-
if (ret) {
967
-
of_node_put(child);
967
+
if (ret)
968
968
return ret;
969
-
}
970
969
971
970
*temp++ = grp->name;
972
971
grp++;
973
972
974
973
if (of_get_child_count(child) > 0) {
975
-
for_each_child_of_node(child, sub_child) {
974
+
for_each_child_of_node_scoped(child, sub_child) {
976
975
ret = sprd_pinctrl_parse_groups(sub_child,
977
976
sprd_pctl, grp);
978
-
if (ret) {
979
-
of_node_put(sub_child);
980
-
of_node_put(child);
977
+
if (ret)
981
978
return ret;
982
-
}
983
979
984
980
*temp++ = grp->name;
985
981
grp++;
+11
-16
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
+11
-16
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
···
480
480
{
481
481
struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
482
482
struct device *dev = sfp->gc.parent;
483
-
struct device_node *child;
484
483
struct pinctrl_map *map;
485
484
const char **pgnames;
486
485
const char *grpname;
···
491
492
492
493
nmaps = 0;
493
494
ngroups = 0;
494
-
for_each_available_child_of_node(np, child) {
495
+
for_each_available_child_of_node_scoped(np, child) {
495
496
int npinmux = of_property_count_u32_elems(child, "pinmux");
496
497
int npins = of_property_count_u32_elems(child, "pins");
497
498
498
499
if (npinmux > 0 && npins > 0) {
499
500
dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n",
500
501
np, child);
501
-
of_node_put(child);
502
502
return -EINVAL;
503
503
}
504
504
if (npinmux == 0 && npins == 0) {
505
505
dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n",
506
506
np, child);
507
-
of_node_put(child);
508
507
return -EINVAL;
509
508
}
510
509
···
524
527
nmaps = 0;
525
528
ngroups = 0;
526
529
mutex_lock(&sfp->mutex);
527
-
for_each_available_child_of_node(np, child) {
530
+
for_each_available_child_of_node_scoped(np, child) {
528
531
int npins;
529
532
int i;
530
533
531
534
grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
532
535
if (!grpname) {
533
536
ret = -ENOMEM;
534
-
goto put_child;
537
+
goto free_map;
535
538
}
536
539
537
540
pgnames[ngroups++] = grpname;
···
540
543
pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
541
544
if (!pins) {
542
545
ret = -ENOMEM;
543
-
goto put_child;
546
+
goto free_map;
544
547
}
545
548
546
549
pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
547
550
if (!pinmux) {
548
551
ret = -ENOMEM;
549
-
goto put_child;
552
+
goto free_map;
550
553
}
551
554
552
555
ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
553
556
if (ret)
554
-
goto put_child;
557
+
goto free_map;
555
558
556
559
for (i = 0; i < npins; i++) {
557
560
unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);
···
567
570
pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
568
571
if (!pins) {
569
572
ret = -ENOMEM;
570
-
goto put_child;
573
+
goto free_map;
571
574
}
572
575
573
576
pinmux = NULL;
···
577
580
578
581
ret = of_property_read_u32_index(child, "pins", i, &v);
579
582
if (ret)
580
-
goto put_child;
583
+
goto free_map;
581
584
pins[i] = v;
582
585
}
583
586
} else {
584
587
ret = -EINVAL;
585
-
goto put_child;
588
+
goto free_map;
586
589
}
587
590
588
591
ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux);
589
592
if (ret < 0) {
590
593
dev_err(dev, "error adding group %s: %d\n", grpname, ret);
591
-
goto put_child;
594
+
goto free_map;
592
595
}
593
596
594
597
ret = pinconf_generic_parse_dt_config(child, pctldev,
···
597
600
if (ret) {
598
601
dev_err(dev, "error parsing pin config of group %s: %d\n",
599
602
grpname, ret);
600
-
goto put_child;
603
+
goto free_map;
601
604
}
602
605
603
606
/* don't create a map if there are no pinconf settings */
···
620
623
mutex_unlock(&sfp->mutex);
621
624
return 0;
622
625
623
-
put_child:
624
-
of_node_put(child);
625
626
free_map:
626
627
pinctrl_utils_free_map(pctldev, map, nmaps);
627
628
mutex_unlock(&sfp->mutex);
+8
-10
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
+8
-10
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
···
150
150
nmaps = 0;
151
151
ngroups = 0;
152
152
mutex_lock(&sfp->mutex);
153
-
for_each_available_child_of_node(np, child) {
153
+
for_each_available_child_of_node_scoped(np, child) {
154
154
int npins = of_property_count_u32_elems(child, "pinmux");
155
155
int *pins;
156
156
u32 *pinmux;
···
161
161
"invalid pinctrl group %pOFn.%pOFn: pinmux not set\n",
162
162
np, child);
163
163
ret = -EINVAL;
164
-
goto put_child;
164
+
goto free_map;
165
165
}
166
166
167
167
grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
168
168
if (!grpname) {
169
169
ret = -ENOMEM;
170
-
goto put_child;
170
+
goto free_map;
171
171
}
172
172
173
173
pgnames[ngroups++] = grpname;
···
175
175
pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
176
176
if (!pins) {
177
177
ret = -ENOMEM;
178
-
goto put_child;
178
+
goto free_map;
179
179
}
180
180
181
181
pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
182
182
if (!pinmux) {
183
183
ret = -ENOMEM;
184
-
goto put_child;
184
+
goto free_map;
185
185
}
186
186
187
187
ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
188
188
if (ret)
189
-
goto put_child;
189
+
goto free_map;
190
190
191
191
for (i = 0; i < npins; i++)
192
192
pins[i] = jh7110_pinmux_pin(pinmux[i]);
···
200
200
pins, npins, pinmux);
201
201
if (ret < 0) {
202
202
dev_err(dev, "error adding group %s: %d\n", grpname, ret);
203
-
goto put_child;
203
+
goto free_map;
204
204
}
205
205
206
206
ret = pinconf_generic_parse_dt_config(child, pctldev,
···
209
209
if (ret) {
210
210
dev_err(dev, "error parsing pin config of group %s: %d\n",
211
211
grpname, ret);
212
-
goto put_child;
212
+
goto free_map;
213
213
}
214
214
215
215
/* don't create a map if there are no pinconf settings */
···
233
233
*num_maps = nmaps;
234
234
return 0;
235
235
236
-
put_child:
237
-
of_node_put(child);
238
236
free_map:
239
237
pinctrl_utils_free_map(pctldev, map, nmaps);
240
238
mutex_unlock(&sfp->mutex);
+1
-3
drivers/pinctrl/stm32/pinctrl-stm32.c
+1
-3
drivers/pinctrl/stm32/pinctrl-stm32.c
···
670
670
struct device_node *np_config,
671
671
struct pinctrl_map **map, unsigned *num_maps)
672
672
{
673
-
struct device_node *np;
674
673
unsigned reserved_maps;
675
674
int ret;
676
675
···
677
678
*num_maps = 0;
678
679
reserved_maps = 0;
679
680
680
-
for_each_child_of_node(np_config, np) {
681
+
for_each_child_of_node_scoped(np_config, np) {
681
682
ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
682
683
&reserved_maps, num_maps);
683
684
if (ret < 0) {
684
685
pinctrl_utils_free_map(pctldev, *map, *num_maps);
685
-
of_node_put(np);
686
686
return ret;
687
687
}
688
688
}
+2
-5
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
+2
-5
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
···
238
238
{
239
239
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
240
240
unsigned int reserved_maps = 0;
241
-
struct device_node *np;
242
241
int err;
243
242
244
243
*num_maps = 0;
245
244
*maps = NULL;
246
245
247
-
for_each_child_of_node(parent, np) {
246
+
for_each_child_of_node_scoped(parent, np) {
248
247
err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
249
248
&reserved_maps,
250
249
num_maps);
251
-
if (err < 0) {
252
-
of_node_put(np);
250
+
if (err < 0)
253
251
return err;
254
-
}
255
252
}
256
253
257
254
return 0;
+1
-3
drivers/pinctrl/tegra/pinctrl-tegra.c
+1
-3
drivers/pinctrl/tegra/pinctrl-tegra.c
···
188
188
unsigned *num_maps)
189
189
{
190
190
unsigned reserved_maps;
191
-
struct device_node *np;
192
191
int ret;
193
192
194
193
reserved_maps = 0;
195
194
*map = NULL;
196
195
*num_maps = 0;
197
196
198
-
for_each_child_of_node(np_config, np) {
197
+
for_each_child_of_node_scoped(np_config, np) {
199
198
ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
200
199
&reserved_maps, num_maps);
201
200
if (ret < 0) {
202
201
pinctrl_utils_free_map(pctldev, *map,
203
202
*num_maps);
204
-
of_node_put(np);
205
203
return ret;
206
204
}
207
205
}
+15
-27
drivers/pinctrl/ti/pinctrl-ti-iodelay.c
+15
-27
drivers/pinctrl/ti/pinctrl-ti-iodelay.c
···
822
822
static int ti_iodelay_probe(struct platform_device *pdev)
823
823
{
824
824
struct device *dev = &pdev->dev;
825
-
struct device_node *np = of_node_get(dev->of_node);
825
+
struct device_node *np __free(device_node) = of_node_get(dev->of_node);
826
826
struct resource *res;
827
827
struct ti_iodelay_device *iod;
828
-
int ret = 0;
828
+
int ret;
829
829
830
830
if (!np) {
831
-
ret = -EINVAL;
832
831
dev_err(dev, "No OF node\n");
833
-
goto exit_out;
832
+
return -EINVAL;
834
833
}
835
834
836
835
iod = devm_kzalloc(dev, sizeof(*iod), GFP_KERNEL);
837
-
if (!iod) {
838
-
ret = -ENOMEM;
839
-
goto exit_out;
840
-
}
836
+
if (!iod)
837
+
return -ENOMEM;
838
+
841
839
iod->dev = dev;
842
840
iod->reg_data = device_get_match_data(dev);
843
841
if (!iod->reg_data) {
844
-
ret = -EINVAL;
845
842
dev_err(dev, "No DATA match\n");
846
-
goto exit_out;
843
+
return -EINVAL;
847
844
}
848
845
849
846
/* So far We can assume there is only 1 bank of registers */
850
847
iod->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
851
-
if (IS_ERR(iod->reg_base)) {
852
-
ret = PTR_ERR(iod->reg_base);
853
-
goto exit_out;
854
-
}
848
+
if (IS_ERR(iod->reg_base))
849
+
return PTR_ERR(iod->reg_base);
850
+
855
851
iod->phys_base = res->start;
856
852
857
853
iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base,
858
854
iod->reg_data->regmap_config);
859
855
if (IS_ERR(iod->regmap)) {
860
856
dev_err(dev, "Regmap MMIO init failed.\n");
861
-
ret = PTR_ERR(iod->regmap);
862
-
goto exit_out;
857
+
return PTR_ERR(iod->regmap);
863
858
}
864
859
865
860
ret = ti_iodelay_pinconf_init_dev(iod);
866
861
if (ret)
867
-
goto exit_out;
862
+
return ret;
868
863
869
864
ret = ti_iodelay_alloc_pins(dev, iod, res->start);
870
865
if (ret)
871
-
goto exit_out;
866
+
return ret;
872
867
873
868
iod->desc.pctlops = &ti_iodelay_pinctrl_ops;
874
869
/* no pinmux ops - we are pinconf */
···
871
876
iod->desc.name = dev_name(dev);
872
877
iod->desc.owner = THIS_MODULE;
873
878
874
-
ret = pinctrl_register_and_init(&iod->desc, dev, iod, &iod->pctl);
879
+
ret = devm_pinctrl_register_and_init(dev, &iod->desc, iod, &iod->pctl);
875
880
if (ret) {
876
881
dev_err(dev, "Failed to register pinctrl\n");
877
-
goto exit_out;
882
+
return ret;
878
883
}
879
884
880
885
platform_set_drvdata(pdev, iod);
881
886
882
887
return pinctrl_enable(iod->pctl);
883
-
884
-
exit_out:
885
-
of_node_put(np);
886
-
return ret;
887
888
}
888
889
889
890
/**
···
889
898
static void ti_iodelay_remove(struct platform_device *pdev)
890
899
{
891
900
struct ti_iodelay_device *iod = platform_get_drvdata(pdev);
892
-
893
-
if (iod->pctl)
894
-
pinctrl_unregister(iod->pctl);
895
901
896
902
ti_iodelay_pinconf_deinit_dev(iod);
897
903