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pinctrl: baytrail: Use dedicated helpers for chained IRQ handlers

Instead of relying on the fact that the parent IRQ chip supports
fasteoi mode and calling the respective callback at the end of
the interrupt handler, surround it with enter and exit helpers
for chained IRQ handlers which will consider all possible cases.

This in particular unifies how GPIO drivers handle IRQ.

Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

+4 -1
+4 -1
drivers/pinctrl/intel/pinctrl-baytrail.c
··· 1355 1355 void __iomem *reg; 1356 1356 unsigned long pending; 1357 1357 1358 + chained_irq_enter(chip, desc); 1359 + 1358 1360 /* check from GPIO controller which pin triggered the interrupt */ 1359 1361 for (base = 0; base < vg->chip.ngpio; base += 32) { 1360 1362 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); ··· 1371 1369 for_each_set_bit(pin, &pending, 32) 1372 1370 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); 1373 1371 } 1374 - chip->irq_eoi(data); 1372 + 1373 + chained_irq_exit(chip, desc); 1375 1374 } 1376 1375 1377 1376 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)