drm/amdgpu: Switch to SOC partition funcs

+4 -27

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

··· 28 28 #include "amdgpu_gfx.h" 29 29 #include "amdgpu_rlc.h" 30 30 #include "amdgpu_ras.h" 31 + #include "amdgpu_xcp.h" 31 32 32 33 /* delay 0.1 second to enable gfx off feature */ 33 34 #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100) ··· 1171 1170 { 1172 1171 struct drm_device *ddev = dev_get_drvdata(dev); 1173 1172 struct amdgpu_device *adev = drm_to_adev(ddev); 1174 - enum amdgpu_gfx_partition mode; 1173 + int mode; 1175 1174 char *partition_mode; 1176 1175 1177 - mode = adev->gfx.funcs->query_partition_mode(adev); 1176 + mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr); 1178 1177 1179 1178 switch (mode) { 1180 1179 case AMDGPU_SPX_PARTITION_MODE: ··· 1255 1254 return -EINVAL; 1256 1255 } 1257 1256 1258 - if (!adev->kfd.init_complete) 1259 - return -EPERM; 1260 - 1261 - mutex_lock(&adev->gfx.partition_mutex); 1262 - 1263 - if (mode == adev->gfx.funcs->query_partition_mode(adev)) 1264 - goto out; 1265 - 1266 - ret = amdgpu_amdkfd_check_and_lock_kfd(adev); 1267 - if (ret) 1268 - goto out; 1269 - 1270 - amdgpu_amdkfd_device_fini_sw(adev); 1271 - 1272 - adev->gfx.funcs->switch_partition_mode(adev, mode); 1273 - 1274 - amdgpu_amdkfd_device_probe(adev); 1275 - amdgpu_amdkfd_device_init(adev); 1276 - /* If KFD init failed, return failure */ 1277 - if (!adev->kfd.init_complete) 1278 - ret = -EIO; 1279 - 1280 - amdgpu_amdkfd_unlock_kfd(adev); 1281 - out: 1282 - mutex_unlock(&adev->gfx.partition_mutex); 1257 + ret = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, mode); 1283 1258 1284 1259 if (ret) 1285 1260 return ret;

-5

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

··· 278 278 (*query_partition_mode)(struct amdgpu_device *adev); 279 279 enum amdgpu_memory_partition 280 280 (*query_mem_partition_mode)(struct amdgpu_device *adev); 281 - 282 281 int (*switch_partition_mode)(struct amdgpu_device *adev, 283 - enum amdgpu_gfx_partition mode); 284 - 285 - int (*switch_gfx_partition_mode)(struct amdgpu_device *adev, 286 282 int num_xccs_per_xcp); 287 283 }; 288 284 ··· 412 416 413 417 bool cp_gfx_shadow; /* for gfx11 */ 414 418 415 - enum amdgpu_gfx_partition partition_mode; 416 419 uint16_t xcc_mask; 417 420 enum amdgpu_memory_partition mem_partition_mode; 418 421 uint32_t num_xcc_per_xcp;

+2 -2

drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c

··· 307 307 goto unlock; 308 308 309 309 num_xcc_per_xcp = __aqua_vanjaram_get_xcc_per_xcp(xcp_mgr, mode); 310 - if (adev->gfx.funcs->switch_gfx_partition_mode) 311 - adev->gfx.funcs->switch_gfx_partition_mode(xcp_mgr->adev, 310 + if (adev->gfx.funcs->switch_partition_mode) 311 + adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev, 312 312 num_xcc_per_xcp); 313 313 314 314 if (adev->nbio.funcs->set_compute_partition_mode)

+9 -50

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

··· 38 38 #include "gc/gc_9_4_3_sh_mask.h" 39 39 40 40 #include "gfx_v9_4_3.h" 41 + #include "amdgpu_xcp.h" 41 42 42 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); ··· 615 614 return mode; 616 615 } 617 616 618 - static enum amdgpu_gfx_partition 619 - gfx_v9_4_3_query_compute_partition(struct amdgpu_device *adev) 620 - { 621 - enum amdgpu_gfx_partition mode = adev->gfx.partition_mode; 622 - 623 - if (adev->nbio.funcs->get_compute_partition_mode) 624 - mode = adev->nbio.funcs->get_compute_partition_mode(adev); 625 - 626 - return mode; 627 - } 628 - 629 617 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 630 - enum amdgpu_gfx_partition mode) 618 + int num_xccs_per_xcp) 631 619 { 620 + int i, num_xcc; 632 621 u32 tmp = 0; 633 - int num_xcc_per_partition, i, num_xcc; 634 622 635 623 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 636 - switch (mode) { 637 - case AMDGPU_SPX_PARTITION_MODE: 638 - num_xcc_per_partition = num_xcc; 639 - break; 640 - case AMDGPU_DPX_PARTITION_MODE: 641 - num_xcc_per_partition = num_xcc / 2; 642 - break; 643 - case AMDGPU_TPX_PARTITION_MODE: 644 - num_xcc_per_partition = num_xcc / 3; 645 - break; 646 - case AMDGPU_QPX_PARTITION_MODE: 647 - num_xcc_per_partition = num_xcc / 4; 648 - break; 649 - case AMDGPU_CPX_PARTITION_MODE: 650 - num_xcc_per_partition = 1; 651 - break; 652 - default: 653 - return -EINVAL; 654 - } 655 - 656 - /* TODO: 657 - * Stop user queues and threads, and make sure GPU is empty of work. 658 - */ 659 624 660 625 for (i = 0; i < num_xcc; i++) { 661 626 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 662 - num_xcc_per_partition); 627 + num_xccs_per_xcp); 663 628 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 664 - i % num_xcc_per_partition); 629 + i % num_xccs_per_xcp); 665 630 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, tmp); 666 631 } 667 632 668 - if (adev->nbio.funcs->set_compute_partition_mode) 669 - adev->nbio.funcs->set_compute_partition_mode(adev, mode); 670 - 671 - adev->gfx.num_xcc_per_xcp = num_xcc_per_partition; 672 - adev->gfx.partition_mode = mode; 633 + adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 673 634 674 635 return 0; 675 636 } ··· 643 680 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 644 681 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 645 682 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 646 - .query_partition_mode = &gfx_v9_4_3_query_compute_partition, 647 683 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 648 684 .query_mem_partition_mode = &gfx_v9_4_3_query_memory_partition, 649 685 }; ··· 1861 1899 return r; 1862 1900 } 1863 1901 1864 - if (adev->gfx.partition_mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 1865 - gfx_v9_4_3_switch_compute_partition(adev, 1866 - amdgpu_user_partt_mode); 1867 - 1868 1902 /* set the virtual and physical id based on partition_mode */ 1869 1903 gfx_v9_4_3_xcc_program_xcc_id(adev, xcc_id); 1870 1904 ··· 1888 1930 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 1889 1931 { 1890 1932 int r, i, num_xcc; 1933 + 1934 + if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr) == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 1935 + amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, amdgpu_user_partt_mode); 1891 1936 1892 1937 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1893 1938 for (i = 0; i < num_xcc; i++) { ··· 2106 2145 int num_xcc; 2107 2146 2108 2147 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2109 - 2110 - adev->gfx.partition_mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 2111 2148 2112 2149 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2113 2150 AMDGPU_MAX_COMPUTE_RINGS);

+5 -3

drivers/gpu/drm/amd/amdkfd/kfd_device.c

··· 34 34 #include "kfd_smi_events.h" 35 35 #include "kfd_migrate.h" 36 36 #include "amdgpu.h" 37 + #include "amdgpu_xcp.h" 37 38 38 39 #define MQD_SIZE_ALIGNED 768 39 40 ··· 593 592 struct kfd_node *node; 594 593 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 595 594 unsigned int max_proc_per_quantum; 596 - int num_xcd; 595 + int num_xcd, partition_mode; 597 596 598 597 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 599 598 KGD_ENGINE_MEC1); ··· 645 644 * If the VMID range changes for GFX9.4.3, then this code MUST be 646 645 * revisited. 647 646 */ 647 + partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr); 648 648 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) && 649 - kfd->adev->gfx.partition_mode == AMDGPU_CPX_PARTITION_MODE && 649 + partition_mode == AMDGPU_CPX_PARTITION_MODE && 650 650 kfd->num_nodes != 1) { 651 651 vmid_num_kfd /= 2; 652 652 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; ··· 763 761 node->start_xcc_id = node->num_xcc_per_node * i; 764 762 765 763 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) && 766 - kfd->adev->gfx.partition_mode == AMDGPU_CPX_PARTITION_MODE && 764 + partition_mode == AMDGPU_CPX_PARTITION_MODE && 767 765 kfd->num_nodes != 1) { 768 766 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 769 767 * 4-9 and second XCD gets VMID range 10-15.

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