tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2021-02-05-1' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"Fixes for rc7, bit bigger than I'd like at this stage, but most of the
i915 stuff and some amdgpu is destined for staging and I'd rather not
hold it up, the i915 changes also pulled in a few precusor code
movement patches to make things cleaner, but nothing seems that
horrible, and I've checked over all of it.

Otherwise there is a nouveau dma-api warning regression, and a ttm
page allocation warning fix, and some fixes for a bridge chip,

ttm:
- fix huge page warning regression

i915:
- Skip vswing programming for TBT
- Power up combo PHY lanes for HDMI
- Fix double YUV range correction on HDR planes
- Fix the MST PBN divider calculation
- Fix LTTPR vswing/pre-emp setting in non-transparent mode
- Move the breadcrumb to the signaler if completed upon cancel
- Close race between enable_breadcrumbs and cancel_breadcrumbs
- Drop lru bumping on display unpinning

amdgpu:
- Fix retry in gem create
- Vangogh fixes
- Fix for display from shared buffers
- Various display fixes

amdkfd:
- Fix regression in buffer free

nouveau:
- fix DMA API warning regression

drm/bridge/lontium-lt9611uxc:
- EDID fixes
- Don't handle hotplug events in IRQ handler"

* tag 'drm-fixes-2021-02-05-1' of git://anongit.freedesktop.org/drm/drm: (29 commits)
drm/nouveau: fix dma syncing warning with debugging on.
drm/amd/display: Decrement refcount of dc_sink before reassignment
drm/amd/display: Free atomic state after drm_atomic_commit
drm/amd/display: Fix dc_sink kref count in emulated_link_detect
drm/amd/display: Release DSC before acquiring
drm/amd/display: Revert "Fix EDID parsing after resume from suspend"
drm/amd/display: Add more Clock Sources to DCN2.1
drm/amd/display: reuse current context instead of recreating one
drm/amd/display: Fix DPCD translation for LTTPR AUX_RD_INTERVAL
drm/amdgpu: enable freesync for A+A configs
drm/amd/pm: fill in the data member of v2 gpu metrics table for vangogh
drm/amdgpu/gfx10: update CGTS_TCC_DISABLE and CGTS_USER_TCC_DISABLE register offsets for VGH
drm/amdkfd: fix null pointer panic while free buffer in kfd
drm/amdgpu: fix the issue that retry constantly once the buffer is oversize
drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode
drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c
drm/i915: Fix the MST PBN divider calculation
drm/dp/mst: Export drm_dp_get_vc_payload_bw()
drm/i915/gem: Drop lru bumping on display unpinning
drm/i915/gt: Close race between enable_breadcrumbs and cancel_breadcrumbs
...

Linus Torvalds 8e91dd93 dd86e7fa

+290 -256
+6 -10
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
··· 26 26 #include <linux/sched/task.h> 27 27 28 28 #include "amdgpu_object.h" 29 + #include "amdgpu_gem.h" 29 30 #include "amdgpu_vm.h" 30 31 #include "amdgpu_amdkfd.h" 31 32 #include "amdgpu_dma_buf.h" ··· 1153 1152 struct sg_table *sg = NULL; 1154 1153 uint64_t user_addr = 0; 1155 1154 struct amdgpu_bo *bo; 1156 - struct amdgpu_bo_param bp; 1155 + struct drm_gem_object *gobj; 1157 1156 u32 domain, alloc_domain; 1158 1157 u64 alloc_flags; 1159 1158 int ret; ··· 1221 1220 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n", 1222 1221 va, size, domain_string(alloc_domain)); 1223 1222 1224 - memset(&bp, 0, sizeof(bp)); 1225 - bp.size = size; 1226 - bp.byte_align = 1; 1227 - bp.domain = alloc_domain; 1228 - bp.flags = alloc_flags; 1229 - bp.type = bo_type; 1230 - bp.resv = NULL; 1231 - ret = amdgpu_bo_create(adev, &bp, &bo); 1223 + ret = amdgpu_gem_object_create(adev, size, 1, alloc_domain, alloc_flags, 1224 + bo_type, NULL, &gobj); 1232 1225 if (ret) { 1233 1226 pr_debug("Failed to create BO on domain %s. ret %d\n", 1234 - domain_string(alloc_domain), ret); 1227 + domain_string(alloc_domain), ret); 1235 1228 goto err_bo_create; 1236 1229 } 1230 + bo = gem_to_amdgpu_bo(gobj); 1237 1231 if (bo_type == ttm_bo_type_sg) { 1238 1232 bo->tbo.sg = sg; 1239 1233 bo->tbo.ttm->sg = sg;
+6 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
··· 926 926 struct drm_file *file_priv, 927 927 const struct drm_mode_fb_cmd2 *mode_cmd) 928 928 { 929 - struct drm_gem_object *obj; 930 929 struct amdgpu_framebuffer *amdgpu_fb; 930 + struct drm_gem_object *obj; 931 + struct amdgpu_bo *bo; 932 + uint32_t domains; 931 933 int ret; 932 934 933 935 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); ··· 940 938 } 941 939 942 940 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 943 - if (obj->import_attach) { 941 + bo = gem_to_amdgpu_bo(obj); 942 + domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); 943 + if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { 944 944 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n"); 945 945 return ERR_PTR(-EINVAL); 946 946 }
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
··· 269 269 resv = vm->root.base.bo->tbo.base.resv; 270 270 } 271 271 272 - retry: 273 272 initial_domain = (u32)(0xffffffff & args->in.domains); 273 + retry: 274 274 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 275 275 initial_domain, 276 276 flags, ttm_bo_type_device, resv, &gobj);
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
··· 897 897 return -EINVAL; 898 898 899 899 /* A shared bo cannot be migrated to VRAM */ 900 - if (bo->prime_shared_count) { 900 + if (bo->prime_shared_count || bo->tbo.base.import_attach) { 901 901 if (domain & AMDGPU_GEM_DOMAIN_GTT) 902 902 domain = AMDGPU_GEM_DOMAIN_GTT; 903 903 else
+16 -2
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 99 99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 100 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 101 101 102 + #define mmCGTS_TCC_DISABLE_Vangogh 0x5006 103 + #define mmCGTS_TCC_DISABLE_Vangogh_BASE_IDX 1 104 + #define mmCGTS_USER_TCC_DISABLE_Vangogh 0x5007 105 + #define mmCGTS_USER_TCC_DISABLE_Vangogh_BASE_IDX 1 102 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 103 107 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 104 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 ··· 4940 4936 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 4941 4937 { 4942 4938 /* TCCs are global (not instanced). */ 4943 - uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4944 - RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4939 + uint32_t tcc_disable; 4940 + 4941 + switch (adev->asic_type) { 4942 + case CHIP_VANGOGH: 4943 + tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_Vangogh) | 4944 + RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_Vangogh); 4945 + break; 4946 + default: 4947 + tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 4948 + RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 4949 + break; 4950 + } 4945 4951 4946 4952 adev->gfx.config.tcc_disabled_mask = 4947 4953 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
+21 -26
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 1833 1833 link->type = dc_connection_none; 1834 1834 prev_sink = link->local_sink; 1835 1835 1836 - if (prev_sink != NULL) 1837 - dc_sink_retain(prev_sink); 1836 + if (prev_sink) 1837 + dc_sink_release(prev_sink); 1838 1838 1839 1839 switch (link->connector_signal) { 1840 1840 case SIGNAL_TYPE_HDMI_TYPE_A: { ··· 1934 1934 dc_commit_updates_for_stream( 1935 1935 dm->dc, bundle->surface_updates, 1936 1936 dc_state->stream_status->plane_count, 1937 - dc_state->streams[k], &bundle->stream_update, dc_state); 1937 + dc_state->streams[k], &bundle->stream_update); 1938 1938 } 1939 1939 1940 1940 cleanup: ··· 1965 1965 1966 1966 stream_update.stream = stream_state; 1967 1967 dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0, 1968 - stream_state, &stream_update, 1969 - stream_state->ctx->dc->current_state); 1968 + stream_state, &stream_update); 1970 1969 mutex_unlock(&adev->dm.dc_lock); 1971 1970 } 1972 1971 ··· 2329 2330 * TODO: check if we still need the S3 mode update workaround. 2330 2331 * If yes, put it here. 2331 2332 */ 2332 - if (aconnector->dc_sink) 2333 + if (aconnector->dc_sink) { 2333 2334 amdgpu_dm_update_freesync_caps(connector, NULL); 2335 + dc_sink_release(aconnector->dc_sink); 2336 + } 2334 2337 2335 2338 aconnector->dc_sink = sink; 2336 2339 dc_sink_retain(aconnector->dc_sink); ··· 2348 2347 2349 2348 drm_connector_update_edid_property(connector, 2350 2349 aconnector->edid); 2351 - drm_add_edid_modes(connector, aconnector->edid); 2352 - 2353 2350 if (aconnector->dc_link->aux_mode) 2354 2351 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 2355 2352 aconnector->edid); ··· 7548 7549 struct drm_crtc *pcrtc, 7549 7550 bool wait_for_vblank) 7550 7551 { 7551 - uint32_t i; 7552 + int i; 7552 7553 uint64_t timestamp_ns; 7553 7554 struct drm_plane *plane; 7554 7555 struct drm_plane_state *old_plane_state, *new_plane_state; ··· 7589 7590 amdgpu_dm_commit_cursors(state); 7590 7591 7591 7592 /* update planes when needed */ 7592 - for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 7593 + for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 7593 7594 struct drm_crtc *crtc = new_plane_state->crtc; 7594 7595 struct drm_crtc_state *new_crtc_state; 7595 7596 struct drm_framebuffer *fb = new_plane_state->fb; ··· 7812 7813 bundle->surface_updates, 7813 7814 planes_count, 7814 7815 acrtc_state->stream, 7815 - &bundle->stream_update, 7816 - dc_state); 7816 + &bundle->stream_update); 7817 7817 7818 7818 /** 7819 7819 * Enable or disable the interrupts on the backend. ··· 8148 8150 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8149 8151 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 8150 8152 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8151 - struct dc_surface_update dummy_updates[MAX_SURFACES]; 8153 + struct dc_surface_update surface_updates[MAX_SURFACES]; 8152 8154 struct dc_stream_update stream_update; 8153 8155 struct dc_info_packet hdr_packet; 8154 8156 struct dc_stream_status *status = NULL; 8155 8157 bool abm_changed, hdr_changed, scaling_changed; 8156 8158 8157 - memset(&dummy_updates, 0, sizeof(dummy_updates)); 8159 + memset(&surface_updates, 0, sizeof(surface_updates)); 8158 8160 memset(&stream_update, 0, sizeof(stream_update)); 8159 8161 8160 8162 if (acrtc) { ··· 8211 8213 * To fix this, DC should permit updating only stream properties. 8212 8214 */ 8213 8215 for (j = 0; j < status->plane_count; j++) 8214 - dummy_updates[j].surface = status->plane_states[0]; 8216 + surface_updates[j].surface = status->plane_states[j]; 8215 8217 8216 8218 8217 8219 mutex_lock(&dm->dc_lock); 8218 8220 dc_commit_updates_for_stream(dm->dc, 8219 - dummy_updates, 8221 + surface_updates, 8220 8222 status->plane_count, 8221 8223 dm_new_crtc_state->stream, 8222 - &stream_update, 8223 - dc_state); 8224 + &stream_update); 8224 8225 mutex_unlock(&dm->dc_lock); 8225 8226 } 8226 8227 ··· 8356 8359 8357 8360 ret = PTR_ERR_OR_ZERO(conn_state); 8358 8361 if (ret) 8359 - goto err; 8362 + goto out; 8360 8363 8361 8364 /* Attach crtc to drm_atomic_state*/ 8362 8365 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 8363 8366 8364 8367 ret = PTR_ERR_OR_ZERO(crtc_state); 8365 8368 if (ret) 8366 - goto err; 8369 + goto out; 8367 8370 8368 8371 /* force a restore */ 8369 8372 crtc_state->mode_changed = true; ··· 8373 8376 8374 8377 ret = PTR_ERR_OR_ZERO(plane_state); 8375 8378 if (ret) 8376 - goto err; 8377 - 8379 + goto out; 8378 8380 8379 8381 /* Call commit internally with the state we just constructed */ 8380 8382 ret = drm_atomic_commit(state); 8381 - if (!ret) 8382 - return 0; 8383 8383 8384 - err: 8385 - DRM_ERROR("Restoring old state failed with %i\n", ret); 8384 + out: 8386 8385 drm_atomic_state_put(state); 8386 + if (ret) 8387 + DRM_ERROR("Restoring old state failed with %i\n", ret); 8387 8388 8388 8389 return ret; 8389 8390 }
+5 -1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
··· 833 833 if (computed_streams[i]) 834 834 continue; 835 835 836 + if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) 837 + return false; 838 + 836 839 mutex_lock(&aconnector->mst_mgr.lock); 837 840 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) { 838 841 mutex_unlock(&aconnector->mst_mgr.lock); ··· 853 850 stream = dc_state->streams[i]; 854 851 855 852 if (stream->timing.flags.DSC == 1) 856 - dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream); 853 + if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) 854 + return false; 857 855 } 858 856 859 857 return true;
+20 -9
drivers/gpu/drm/amd/display/dc/core/dc.c
··· 2679 2679 struct dc_surface_update *srf_updates, 2680 2680 int surface_count, 2681 2681 struct dc_stream_state *stream, 2682 - struct dc_stream_update *stream_update, 2683 - struct dc_state *state) 2682 + struct dc_stream_update *stream_update) 2684 2683 { 2685 2684 const struct dc_stream_status *stream_status; 2686 2685 enum surface_update_type update_type; ··· 2698 2699 2699 2700 2700 2701 if (update_type >= UPDATE_TYPE_FULL) { 2702 + struct dc_plane_state *new_planes[MAX_SURFACES]; 2703 + 2704 + memset(new_planes, 0, sizeof(new_planes)); 2705 + 2706 + for (i = 0; i < surface_count; i++) 2707 + new_planes[i] = srf_updates[i].surface; 2701 2708 2702 2709 /* initialize scratch memory for building context */ 2703 2710 context = dc_create_state(dc); ··· 2712 2707 return; 2713 2708 } 2714 2709 2715 - dc_resource_state_copy_construct(state, context); 2710 + dc_resource_state_copy_construct( 2711 + dc->current_state, context); 2716 2712 2717 - for (i = 0; i < dc->res_pool->pipe_count; i++) { 2718 - struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; 2719 - struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 2720 - 2721 - if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state) 2722 - new_pipe->plane_state->force_full_update = true; 2713 + /*remove old surfaces from context */ 2714 + if (!dc_rem_all_planes_for_stream(dc, stream, context)) { 2715 + DC_ERROR("Failed to remove streams for new validate context!\n"); 2716 + return; 2723 2717 } 2718 + 2719 + /* add surface to context */ 2720 + if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) { 2721 + DC_ERROR("Failed to add streams for new validate context!\n"); 2722 + return; 2723 + } 2724 + 2724 2725 } 2725 2726 2726 2727
+1 -2
drivers/gpu/drm/amd/display/dc/dc_stream.h
··· 283 283 struct dc_surface_update *srf_updates, 284 284 int surface_count, 285 285 struct dc_stream_state *stream, 286 - struct dc_stream_update *stream_update, 287 - struct dc_state *state); 286 + struct dc_stream_update *stream_update); 288 287 /* 289 288 * Log the current stream state. 290 289 */
+10
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
··· 906 906 DCN20_CLK_SRC_PLL0, 907 907 DCN20_CLK_SRC_PLL1, 908 908 DCN20_CLK_SRC_PLL2, 909 + DCN20_CLK_SRC_PLL3, 910 + DCN20_CLK_SRC_PLL4, 909 911 DCN20_CLK_SRC_TOTAL_DCN21 910 912 }; 911 913 ··· 2032 2030 dcn21_clock_source_create(ctx, ctx->dc_bios, 2033 2031 CLOCK_SOURCE_COMBO_PHY_PLL2, 2034 2032 &clk_src_regs[2], false); 2033 + pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 2034 + dcn21_clock_source_create(ctx, ctx->dc_bios, 2035 + CLOCK_SOURCE_COMBO_PHY_PLL3, 2036 + &clk_src_regs[3], false); 2037 + pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 2038 + dcn21_clock_source_create(ctx, ctx->dc_bios, 2039 + CLOCK_SOURCE_COMBO_PHY_PLL4, 2040 + &clk_src_regs[4], false); 2035 2041 2036 2042 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; 2037 2043
+3
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
··· 591 591 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 592 592 gpu_metrics->average_cpu_power = metrics.Power[0]; 593 593 gpu_metrics->average_soc_power = metrics.Power[1]; 594 + gpu_metrics->average_gfx_power = metrics.Power[2]; 594 595 memcpy(&gpu_metrics->average_core_power[0], 595 596 &metrics.CorePower[0], 596 597 sizeof(uint16_t) * 8); 597 598 598 599 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 599 600 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 601 + gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 600 602 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 601 603 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 604 + gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 602 605 603 606 memcpy(&gpu_metrics->current_coreclk[0], 604 607 &metrics.CoreFrequency[0],
+47 -14
drivers/gpu/drm/bridge/lontium-lt9611uxc.c
··· 14 14 #include <linux/regmap.h> 15 15 #include <linux/regulator/consumer.h> 16 16 #include <linux/wait.h> 17 + #include <linux/workqueue.h> 17 18 18 19 #include <sound/hdmi-codec.h> 19 20 ··· 37 36 struct mutex ocm_lock; 38 37 39 38 struct wait_queue_head wq; 39 + struct work_struct work; 40 40 41 41 struct device_node *dsi0_node; 42 42 struct device_node *dsi1_node; ··· 54 52 55 53 bool hpd_supported; 56 54 bool edid_read; 55 + /* can be accessed from different threads, so protect this with ocm_lock */ 56 + bool hdmi_connected; 57 57 uint8_t fw_version; 58 58 }; 59 59 ··· 147 143 if (irq_status) 148 144 regmap_write(lt9611uxc->regmap, 0xb022, 0); 149 145 150 - lt9611uxc_unlock(lt9611uxc); 151 - 152 - if (irq_status & BIT(0)) 146 + if (irq_status & BIT(0)) { 153 147 lt9611uxc->edid_read = !!(hpd_status & BIT(0)); 154 - 155 - if (irq_status & BIT(1)) { 156 - if (lt9611uxc->connector.dev) 157 - drm_kms_helper_hotplug_event(lt9611uxc->connector.dev); 158 - else 159 - drm_bridge_hpd_notify(&lt9611uxc->bridge, !!(hpd_status & BIT(1))); 148 + wake_up_all(&lt9611uxc->wq); 160 149 } 161 150 151 + if (irq_status & BIT(1)) { 152 + lt9611uxc->hdmi_connected = hpd_status & BIT(1); 153 + schedule_work(&lt9611uxc->work); 154 + } 155 + 156 + lt9611uxc_unlock(lt9611uxc); 157 + 162 158 return IRQ_HANDLED; 159 + } 160 + 161 + static void lt9611uxc_hpd_work(struct work_struct *work) 162 + { 163 + struct lt9611uxc *lt9611uxc = container_of(work, struct lt9611uxc, work); 164 + bool connected; 165 + 166 + if (lt9611uxc->connector.dev) 167 + drm_kms_helper_hotplug_event(lt9611uxc->connector.dev); 168 + else { 169 + 170 + mutex_lock(&lt9611uxc->ocm_lock); 171 + connected = lt9611uxc->hdmi_connected; 172 + mutex_unlock(&lt9611uxc->ocm_lock); 173 + 174 + drm_bridge_hpd_notify(&lt9611uxc->bridge, 175 + connected ? 176 + connector_status_connected : 177 + connector_status_disconnected); 178 + } 163 179 } 164 180 165 181 static void lt9611uxc_reset(struct lt9611uxc *lt9611uxc) ··· 469 445 struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge); 470 446 unsigned int reg_val = 0; 471 447 int ret; 472 - int connected = 1; 448 + bool connected = true; 449 + 450 + lt9611uxc_lock(lt9611uxc); 473 451 474 452 if (lt9611uxc->hpd_supported) { 475 - lt9611uxc_lock(lt9611uxc); 476 453 ret = regmap_read(lt9611uxc->regmap, 0xb023, &reg_val); 477 - lt9611uxc_unlock(lt9611uxc); 478 454 479 455 if (ret) 480 456 dev_err(lt9611uxc->dev, "failed to read hpd status: %d\n", ret); 481 457 else 482 458 connected = reg_val & BIT(1); 483 459 } 460 + lt9611uxc->hdmi_connected = connected; 461 + 462 + lt9611uxc_unlock(lt9611uxc); 484 463 485 464 return connected ? connector_status_connected : 486 465 connector_status_disconnected; ··· 492 465 static int lt9611uxc_wait_for_edid(struct lt9611uxc *lt9611uxc) 493 466 { 494 467 return wait_event_interruptible_timeout(lt9611uxc->wq, lt9611uxc->edid_read, 495 - msecs_to_jiffies(100)); 468 + msecs_to_jiffies(500)); 496 469 } 497 470 498 471 static int lt9611uxc_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) ··· 530 503 ret = lt9611uxc_wait_for_edid(lt9611uxc); 531 504 if (ret < 0) { 532 505 dev_err(lt9611uxc->dev, "wait for EDID failed: %d\n", ret); 533 - return ERR_PTR(ret); 506 + return NULL; 507 + } else if (ret == 0) { 508 + dev_err(lt9611uxc->dev, "wait for EDID timeout\n"); 509 + return NULL; 534 510 } 535 511 536 512 return drm_do_get_edid(connector, lt9611uxc_get_edid_block, lt9611uxc); ··· 956 926 lt9611uxc->fw_version = ret; 957 927 958 928 init_waitqueue_head(&lt9611uxc->wq); 929 + INIT_WORK(&lt9611uxc->work, lt9611uxc_hpd_work); 930 + 959 931 ret = devm_request_threaded_irq(dev, client->irq, NULL, 960 932 lt9611uxc_irq_thread_handler, 961 933 IRQF_ONESHOT, "lt9611uxc", lt9611uxc); ··· 994 962 struct lt9611uxc *lt9611uxc = i2c_get_clientdata(client); 995 963 996 964 disable_irq(client->irq); 965 + flush_scheduled_work(); 997 966 lt9611uxc_audio_exit(lt9611uxc); 998 967 drm_bridge_remove(&lt9611uxc->bridge); 999 968
+18 -6
drivers/gpu/drm/drm_dp_mst_topology.c
··· 3629 3629 return 0; 3630 3630 } 3631 3631 3632 - static int drm_dp_get_vc_payload_bw(u8 dp_link_bw, u8 dp_link_count) 3632 + /** 3633 + * drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link 3634 + * @link_rate: link rate in 10kbits/s units 3635 + * @link_lane_count: lane count 3636 + * 3637 + * Calculate the total bandwidth of a MultiStream Transport link. The returned 3638 + * value is in units of PBNs/(timeslots/1 MTP). This value can be used to 3639 + * convert the number of PBNs required for a given stream to the number of 3640 + * timeslots this stream requires in each MTP. 3641 + */ 3642 + int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count) 3633 3643 { 3634 - if (dp_link_bw == 0 || dp_link_count == 0) 3635 - DRM_DEBUG_KMS("invalid link bandwidth in DPCD: %x (link count: %d)\n", 3636 - dp_link_bw, dp_link_count); 3644 + if (link_rate == 0 || link_lane_count == 0) 3645 + DRM_DEBUG_KMS("invalid link rate/lane count: (%d / %d)\n", 3646 + link_rate, link_lane_count); 3637 3647 3638 - return dp_link_bw * dp_link_count / 2; 3648 + /* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */ 3649 + return link_rate * link_lane_count / 54000; 3639 3650 } 3651 + EXPORT_SYMBOL(drm_dp_get_vc_payload_bw); 3640 3652 3641 3653 /** 3642 3654 * drm_dp_read_mst_cap() - check whether or not a sink supports MST ··· 3704 3692 goto out_unlock; 3705 3693 } 3706 3694 3707 - mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1], 3695 + mgr->pbn_div = drm_dp_get_vc_payload_bw(drm_dp_bw_code_to_link_rate(mgr->dpcd[1]), 3708 3696 mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK); 3709 3697 if (mgr->pbn_div == 0) { 3710 3698 ret = -EINVAL;
+27 -16
drivers/gpu/drm/i915/display/intel_ddi.c
··· 2754 2754 int n_entries, ln; 2755 2755 u32 val; 2756 2756 2757 + if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 2758 + return; 2759 + 2757 2760 ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries); 2758 2761 if (level >= n_entries) { 2759 2762 drm_dbg_kms(&dev_priv->drm, ··· 2892 2889 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2893 2890 u32 val, dpcnt_mask, dpcnt_val; 2894 2891 int n_entries, ln; 2892 + 2893 + if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 2894 + return; 2895 2895 2896 2896 ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); 2897 2897 ··· 3537 3531 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3538 3532 } 3539 3533 3534 + static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 3535 + const struct intel_crtc_state *crtc_state) 3536 + { 3537 + struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3538 + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3539 + enum phy phy = intel_port_to_phy(i915, encoder->port); 3540 + 3541 + if (intel_phy_is_combo(i915, phy)) { 3542 + bool lane_reversal = 3543 + dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3544 + 3545 + intel_combo_phy_power_up_lanes(i915, phy, false, 3546 + crtc_state->lane_count, 3547 + lane_reversal); 3548 + } 3549 + } 3550 + 3540 3551 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 3541 3552 struct intel_encoder *encoder, 3542 3553 const struct intel_crtc_state *crtc_state, ··· 3643 3620 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 3644 3621 * the used lanes of the DDI. 3645 3622 */ 3646 - if (intel_phy_is_combo(dev_priv, phy)) { 3647 - bool lane_reversal = 3648 - dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3649 - 3650 - intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3651 - crtc_state->lane_count, 3652 - lane_reversal); 3653 - } 3623 + intel_ddi_power_up_lanes(encoder, crtc_state); 3654 3624 3655 3625 /* 3656 3626 * 7.g Configure and enable DDI_BUF_CTL ··· 3728 3712 else 3729 3713 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3730 3714 3731 - if (intel_phy_is_combo(dev_priv, phy)) { 3732 - bool lane_reversal = 3733 - dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3734 - 3735 - intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3736 - crtc_state->lane_count, 3737 - lane_reversal); 3738 - } 3715 + intel_ddi_power_up_lanes(encoder, crtc_state); 3739 3716 3740 3717 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 3741 3718 if (!is_mst) ··· 4213 4204 4214 4205 intel_de_write(dev_priv, reg, val); 4215 4206 } 4207 + 4208 + intel_ddi_power_up_lanes(encoder, crtc_state); 4216 4209 4217 4210 /* In HDMI/DVI mode, the port width, and swing/emphasis values 4218 4211 * are ignored so nothing special needs to be done besides
+4 -5
drivers/gpu/drm/i915/display/intel_display.c
··· 2309 2309 */ 2310 2310 ret = i915_vma_pin_fence(vma); 2311 2311 if (ret != 0 && INTEL_GEN(dev_priv) < 4) { 2312 - i915_gem_object_unpin_from_display_plane(vma); 2312 + i915_vma_unpin(vma); 2313 2313 vma = ERR_PTR(ret); 2314 2314 goto err; 2315 2315 } ··· 2327 2327 2328 2328 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) 2329 2329 { 2330 - i915_gem_object_lock(vma->obj, NULL); 2331 2330 if (flags & PLANE_HAS_FENCE) 2332 2331 i915_vma_unpin_fence(vma); 2333 - i915_gem_object_unpin_from_display_plane(vma); 2334 - i915_gem_object_unlock(vma->obj); 2335 - 2332 + i915_vma_unpin(vma); 2336 2333 i915_vma_put(vma); 2337 2334 } 2338 2335 ··· 4804 4807 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 4805 4808 } else if (fb->format->is_yuv) { 4806 4809 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE; 4810 + if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 4811 + plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 4807 4812 } 4808 4813 4809 4814 return plane_color_ctl;
+1 -19
drivers/gpu/drm/i915/display/intel_dp.c
··· 4637 4637 intel_de_posting_read(dev_priv, intel_dp->output_reg); 4638 4638 } 4639 4639 4640 - void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 4641 - const struct intel_crtc_state *crtc_state) 4642 - { 4643 - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4644 - u8 train_set = intel_dp->train_set[0]; 4645 - 4646 - drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n", 4647 - train_set & DP_TRAIN_VOLTAGE_SWING_MASK, 4648 - train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : ""); 4649 - drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n", 4650 - (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> 4651 - DP_TRAIN_PRE_EMPHASIS_SHIFT, 4652 - train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? 4653 - " (max)" : ""); 4654 - 4655 - intel_dp->set_signal_levels(intel_dp, crtc_state); 4656 - } 4657 - 4658 4640 void 4659 4641 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 4660 4642 const struct intel_crtc_state *crtc_state, ··· 5685 5703 5686 5704 intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state); 5687 5705 5688 - intel_dp_set_signal_levels(intel_dp, crtc_state); 5706 + intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX); 5689 5707 5690 5708 intel_dp_phy_pattern_update(intel_dp, crtc_state); 5691 5709
-3
drivers/gpu/drm/i915/display/intel_dp.h
··· 96 96 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 97 97 const struct intel_crtc_state *crtc_state, 98 98 u8 dp_train_pat); 99 - void 100 - intel_dp_set_signal_levels(struct intel_dp *intel_dp, 101 - const struct intel_crtc_state *crtc_state); 102 99 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 103 100 u8 *link_bw, u8 *rate_select); 104 101 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
+3 -1
drivers/gpu/drm/i915/display/intel_dp_mst.c
··· 69 69 70 70 slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, 71 71 connector->port, 72 - crtc_state->pbn, 0); 72 + crtc_state->pbn, 73 + drm_dp_get_vc_payload_bw(crtc_state->port_clock, 74 + crtc_state->lane_count)); 73 75 if (slots == -EDEADLK) 74 76 return slots; 75 77 if (slots >= 0)
+2 -2
drivers/gpu/drm/i915/display/intel_overlay.c
··· 359 359 intel_frontbuffer_flip_complete(overlay->i915, 360 360 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 361 361 362 - i915_gem_object_unpin_from_display_plane(vma); 362 + i915_vma_unpin(vma); 363 363 i915_vma_put(vma); 364 364 } 365 365 ··· 860 860 return 0; 861 861 862 862 out_unpin: 863 - i915_gem_object_unpin_from_display_plane(vma); 863 + i915_vma_unpin(vma); 864 864 out_pin_section: 865 865 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 866 866
+10 -55
drivers/gpu/drm/i915/display/intel_sprite.c
··· 618 618 619 619 /* Preoffset values for YUV to RGB Conversion */ 620 620 #define PREOFF_YUV_TO_RGB_HI 0x1800 621 - #define PREOFF_YUV_TO_RGB_ME 0x1F00 621 + #define PREOFF_YUV_TO_RGB_ME 0x0000 622 622 #define PREOFF_YUV_TO_RGB_LO 0x1800 623 623 624 624 #define ROFF(x) (((x) & 0xffff) << 16) 625 625 #define GOFF(x) (((x) & 0xffff) << 0) 626 626 #define BOFF(x) (((x) & 0xffff) << 16) 627 627 628 + /* 629 + * Programs the input color space conversion stage for ICL HDR planes. 630 + * Note that it is assumed that this stage always happens after YUV 631 + * range correction. Thus, the input to this stage is assumed to be 632 + * in full-range YCbCr. 633 + */ 628 634 static void 629 635 icl_program_input_csc(struct intel_plane *plane, 630 636 const struct intel_crtc_state *crtc_state, ··· 678 672 0x0, 0x7800, 0x7F10, 679 673 }, 680 674 }; 681 - 682 - /* Matrix for Limited Range to Full Range Conversion */ 683 - static const u16 input_csc_matrix_lr[][9] = { 684 - /* 685 - * BT.601 Limted range YCbCr -> full range RGB 686 - * The matrix required is : 687 - * [1.164384, 0.000, 1.596027, 688 - * 1.164384, -0.39175, -0.812813, 689 - * 1.164384, 2.017232, 0.0000] 690 - */ 691 - [DRM_COLOR_YCBCR_BT601] = { 692 - 0x7CC8, 0x7950, 0x0, 693 - 0x8D00, 0x7950, 0x9C88, 694 - 0x0, 0x7950, 0x6810, 695 - }, 696 - /* 697 - * BT.709 Limited range YCbCr -> full range RGB 698 - * The matrix required is : 699 - * [1.164384, 0.000, 1.792741, 700 - * 1.164384, -0.213249, -0.532909, 701 - * 1.164384, 2.112402, 0.0000] 702 - */ 703 - [DRM_COLOR_YCBCR_BT709] = { 704 - 0x7E58, 0x7950, 0x0, 705 - 0x8888, 0x7950, 0xADA8, 706 - 0x0, 0x7950, 0x6870, 707 - }, 708 - /* 709 - * BT.2020 Limited range YCbCr -> full range RGB 710 - * The matrix required is : 711 - * [1.164, 0.000, 1.678, 712 - * 1.164, -0.1873, -0.6504, 713 - * 1.164, 2.1417, 0.0000] 714 - */ 715 - [DRM_COLOR_YCBCR_BT2020] = { 716 - 0x7D70, 0x7950, 0x0, 717 - 0x8A68, 0x7950, 0xAC00, 718 - 0x0, 0x7950, 0x6890, 719 - }, 720 - }; 721 - const u16 *csc; 722 - 723 - if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 724 - csc = input_csc_matrix[plane_state->hw.color_encoding]; 725 - else 726 - csc = input_csc_matrix_lr[plane_state->hw.color_encoding]; 675 + const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding]; 727 676 728 677 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), 729 678 ROFF(csc[0]) | GOFF(csc[1])); ··· 695 734 696 735 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), 697 736 PREOFF_YUV_TO_RGB_HI); 698 - if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 699 - intel_de_write_fw(dev_priv, 700 - PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 701 - 0); 702 - else 703 - intel_de_write_fw(dev_priv, 704 - PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 705 - PREOFF_YUV_TO_RGB_ME); 737 + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 738 + PREOFF_YUV_TO_RGB_ME); 706 739 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), 707 740 PREOFF_YUV_TO_RGB_LO); 708 741 intel_de_write_fw(dev_priv,
-45
drivers/gpu/drm/i915/gem/i915_gem_domain.c
··· 387 387 return vma; 388 388 } 389 389 390 - static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) 391 - { 392 - struct drm_i915_private *i915 = to_i915(obj->base.dev); 393 - struct i915_vma *vma; 394 - 395 - if (list_empty(&obj->vma.list)) 396 - return; 397 - 398 - mutex_lock(&i915->ggtt.vm.mutex); 399 - spin_lock(&obj->vma.lock); 400 - for_each_ggtt_vma(vma, obj) { 401 - if (!drm_mm_node_allocated(&vma->node)) 402 - continue; 403 - 404 - GEM_BUG_ON(vma->vm != &i915->ggtt.vm); 405 - list_move_tail(&vma->vm_link, &vma->vm->bound_list); 406 - } 407 - spin_unlock(&obj->vma.lock); 408 - mutex_unlock(&i915->ggtt.vm.mutex); 409 - 410 - if (i915_gem_object_is_shrinkable(obj)) { 411 - unsigned long flags; 412 - 413 - spin_lock_irqsave(&i915->mm.obj_lock, flags); 414 - 415 - if (obj->mm.madv == I915_MADV_WILLNEED && 416 - !atomic_read(&obj->mm.shrink_pin)) 417 - list_move_tail(&obj->mm.link, &i915->mm.shrink_list); 418 - 419 - spin_unlock_irqrestore(&i915->mm.obj_lock, flags); 420 - } 421 - } 422 - 423 - void 424 - i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) 425 - { 426 - /* Bump the LRU to try and avoid premature eviction whilst flipping */ 427 - i915_gem_object_bump_inactive_ggtt(vma->obj); 428 - 429 - i915_vma_unpin(vma); 430 - } 431 - 432 390 /** 433 391 * Moves a single object to the CPU read, and possibly write domain. 434 392 * @obj: object to act on ··· 526 568 err = i915_gem_object_set_to_gtt_domain(obj, write_domain); 527 569 else 528 570 err = i915_gem_object_set_to_cpu_domain(obj, write_domain); 529 - 530 - /* And bump the LRU for this access */ 531 - i915_gem_object_bump_inactive_ggtt(obj); 532 571 533 572 i915_gem_object_unlock(obj); 534 573
-1
drivers/gpu/drm/i915/gem/i915_gem_object.h
··· 486 486 u32 alignment, 487 487 const struct i915_ggtt_view *view, 488 488 unsigned int flags); 489 - void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma); 490 489 491 490 void i915_gem_object_make_unshrinkable(struct drm_i915_gem_object *obj); 492 491 void i915_gem_object_make_shrinkable(struct drm_i915_gem_object *obj);
+27 -22
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
··· 187 187 intel_engine_add_retire(b->irq_engine, tl); 188 188 } 189 189 190 - static bool __signal_request(struct i915_request *rq) 191 - { 192 - GEM_BUG_ON(test_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags)); 193 - 194 - if (!__dma_fence_signal(&rq->fence)) { 195 - i915_request_put(rq); 196 - return false; 197 - } 198 - 199 - return true; 200 - } 201 - 202 190 static struct llist_node * 203 191 slist_add(struct llist_node *node, struct llist_node *head) 204 192 { ··· 257 269 release = remove_signaling_context(b, ce); 258 270 spin_unlock(&ce->signal_lock); 259 271 260 - if (__signal_request(rq)) 272 + if (__dma_fence_signal(&rq->fence)) 261 273 /* We own signal_node now, xfer to local list */ 262 274 signal = slist_add(&rq->signal_node, signal); 275 + else 276 + i915_request_put(rq); 263 277 264 278 if (release) { 265 279 add_retire(b, ce->timeline); ··· 348 358 kfree(b); 349 359 } 350 360 361 + static void irq_signal_request(struct i915_request *rq, 362 + struct intel_breadcrumbs *b) 363 + { 364 + if (!__dma_fence_signal(&rq->fence)) 365 + return; 366 + 367 + i915_request_get(rq); 368 + if (llist_add(&rq->signal_node, &b->signaled_requests)) 369 + irq_work_queue(&b->irq_work); 370 + } 371 + 351 372 static void insert_breadcrumb(struct i915_request *rq) 352 373 { 353 374 struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs; ··· 368 367 if (test_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags)) 369 368 return; 370 369 371 - i915_request_get(rq); 372 - 373 370 /* 374 371 * If the request is already completed, we can transfer it 375 372 * straight onto a signaled list, and queue the irq worker for 376 373 * its signal completion. 377 374 */ 378 375 if (__i915_request_is_complete(rq)) { 379 - if (__signal_request(rq) && 380 - llist_add(&rq->signal_node, &b->signaled_requests)) 381 - irq_work_queue(&b->irq_work); 376 + irq_signal_request(rq, b); 382 377 return; 383 378 } 384 379 ··· 405 408 break; 406 409 } 407 410 } 411 + 412 + i915_request_get(rq); 408 413 list_add_rcu(&rq->signal_link, pos); 409 414 GEM_BUG_ON(!check_signal_order(ce, rq)); 410 415 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags)); ··· 447 448 448 449 void i915_request_cancel_breadcrumb(struct i915_request *rq) 449 450 { 451 + struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs; 450 452 struct intel_context *ce = rq->context; 451 453 bool release; 452 454 453 - if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags)) 454 - return; 455 - 456 455 spin_lock(&ce->signal_lock); 456 + if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags)) { 457 + spin_unlock(&ce->signal_lock); 458 + return; 459 + } 460 + 457 461 list_del_rcu(&rq->signal_link); 458 - release = remove_signaling_context(rq->engine->breadcrumbs, ce); 462 + release = remove_signaling_context(b, ce); 459 463 spin_unlock(&ce->signal_lock); 460 464 if (release) 461 465 intel_context_put(ce); 466 + 467 + if (__i915_request_is_complete(rq)) 468 + irq_signal_request(rq, b); 462 469 463 470 i915_request_put(rq); 464 471 }
+29 -6
drivers/gpu/drm/nouveau/nouveau_bo.c
··· 547 547 { 548 548 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 549 549 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm; 550 - int i; 550 + int i, j; 551 551 552 552 if (!ttm_dma) 553 553 return; ··· 556 556 if (nvbo->force_coherent) 557 557 return; 558 558 559 - for (i = 0; i < ttm_dma->num_pages; i++) 559 + for (i = 0; i < ttm_dma->num_pages; ++i) { 560 + struct page *p = ttm_dma->pages[i]; 561 + size_t num_pages = 1; 562 + 563 + for (j = i + 1; j < ttm_dma->num_pages; ++j) { 564 + if (++p != ttm_dma->pages[j]) 565 + break; 566 + 567 + ++num_pages; 568 + } 560 569 dma_sync_single_for_device(drm->dev->dev, 561 570 ttm_dma->dma_address[i], 562 - PAGE_SIZE, DMA_TO_DEVICE); 571 + num_pages * PAGE_SIZE, DMA_TO_DEVICE); 572 + i += num_pages; 573 + } 563 574 } 564 575 565 576 void ··· 578 567 { 579 568 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 580 569 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm; 581 - int i; 570 + int i, j; 582 571 583 572 if (!ttm_dma) 584 573 return; ··· 587 576 if (nvbo->force_coherent) 588 577 return; 589 578 590 - for (i = 0; i < ttm_dma->num_pages; i++) 579 + for (i = 0; i < ttm_dma->num_pages; ++i) { 580 + struct page *p = ttm_dma->pages[i]; 581 + size_t num_pages = 1; 582 + 583 + for (j = i + 1; j < ttm_dma->num_pages; ++j) { 584 + if (++p != ttm_dma->pages[j]) 585 + break; 586 + 587 + ++num_pages; 588 + } 589 + 591 590 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], 592 - PAGE_SIZE, DMA_FROM_DEVICE); 591 + num_pages * PAGE_SIZE, DMA_FROM_DEVICE); 592 + i += num_pages; 593 + } 593 594 } 594 595 595 596 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
+1 -1
drivers/gpu/drm/ttm/ttm_pool.c
··· 84 84 * put_page() on a TTM allocated page is illegal. 85 85 */ 86 86 if (order) 87 - gfp_flags |= __GFP_NOMEMALLOC | __GFP_NORETRY | 87 + gfp_flags |= __GFP_NOMEMALLOC | __GFP_NORETRY | __GFP_NOWARN | 88 88 __GFP_KSWAPD_RECLAIM; 89 89 90 90 if (!pool->use_dma_alloc) {
+1
include/drm/drm_dp_mst_helper.h
··· 783 783 784 784 struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); 785 785 786 + int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count); 786 787 787 788 int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc); 788 789