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drm/i915: Remove i915_reg.h from intel_psr.c

Move some chicken registers to display header to make
intel_psr.c free from including i915_reg.h.

v3: Update commit header

v2: Use display header instead of gmd common include (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-16-uma.shankar@intel.com

Uma Shankar 8ed75212 5344a8bb

+26 -29
+26
drivers/gpu/drm/i915/display/intel_display_regs.h
··· 357 357 #define OGAMC1 _MMIO(0x30020) 358 358 #define OGAMC0 _MMIO(0x30024) 359 359 360 + #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 361 + #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) 362 + #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 363 + #define _LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 364 + #define _LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 365 + #define _LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 366 + #define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \ 367 + _LATENCY_REPORTING_REMOVED_PIPE_A, \ 368 + _LATENCY_REPORTING_REMOVED_PIPE_B, \ 369 + _LATENCY_REPORTING_REMOVED_PIPE_C, \ 370 + _LATENCY_REPORTING_REMOVED_PIPE_D) 371 + #define ICL_DELAY_PMRSP REG_BIT(22) 372 + #define DISABLE_FLR_SRC REG_BIT(15) 373 + #define MASK_WAKEMEM REG_BIT(13) 374 + #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 375 + 376 + #define CHICKEN_PAR1_1 _MMIO(0x42080) 377 + #define IGNORE_KVMR_PIPE_A REG_BIT(23) 378 + #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 379 + #define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16) 380 + #define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15) 381 + #define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */ 382 + #define FORCE_ARB_IDLE_PLANES REG_BIT(14) 383 + #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3) 384 + #define IGNORE_PSR2_HW_TRACKING REG_BIT(1) 385 + 360 386 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 361 387 #define BXT_GMBUS_GATING_DIS (1 << 14) 362 388 #define DG2_DPFC_GATING_DIS REG_BIT(31)
-1
drivers/gpu/drm/i915/display/intel_psr.c
··· 29 29 #include <drm/drm_print.h> 30 30 #include <drm/drm_vblank.h> 31 31 32 - #include "i915_reg.h" 33 32 #include "intel_alpm.h" 34 33 #include "intel_atomic.h" 35 34 #include "intel_crtc.h"
-28
drivers/gpu/drm/i915/i915_reg.h
··· 805 805 #define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5) 806 806 #define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2) 807 807 808 - #define CHICKEN_PAR1_1 _MMIO(0x42080) 809 - #define IGNORE_KVMR_PIPE_A REG_BIT(23) 810 - #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 811 - #define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16) 812 - #define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15) 813 - #define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */ 814 - #define FORCE_ARB_IDLE_PLANES REG_BIT(14) 815 - #define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3) 816 - #define IGNORE_PSR2_HW_TRACKING REG_BIT(1) 817 - 818 808 #define CHICKEN_PAR2_1 _MMIO(0x42090) 819 809 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) 820 - 821 - 822 - #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 823 - #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) 824 - #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 825 - #define _LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 826 - #define _LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 827 - #define _LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 828 - #define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \ 829 - _LATENCY_REPORTING_REMOVED_PIPE_A, \ 830 - _LATENCY_REPORTING_REMOVED_PIPE_B, \ 831 - _LATENCY_REPORTING_REMOVED_PIPE_C, \ 832 - _LATENCY_REPORTING_REMOVED_PIPE_D) 833 - #define ICL_DELAY_PMRSP REG_BIT(22) 834 - #define DISABLE_FLR_SRC REG_BIT(15) 835 - #define MASK_WAKEMEM REG_BIT(13) 836 - #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 837 - 838 810 839 811 #define VLV_PMWGICZ _MMIO(0x1300a4) 840 812