Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
agp/intel-gtt: Add intel_gmch_gtt_read_entry()
i915 wants to read out the PTE(s) populated by the BIOS/GOP
to verify that the framebuffer is in the correct location.
Introduce intel_gmch_gtt_read_entry() that reads out the
PTE and decodes it to a somewhat abstract form. For now
we just return the dma_addr, present bit, and local memory
bit. I didn't bother with the snoop bit/etc.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250313140838.29742-4-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
+57
+55
drivers/char/agp/intel-gtt.c
+55
drivers/char/agp/intel-gtt.c
···
53
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* of the mmio register file, that's done in the generic code. */
54
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void (*cleanup)(void);
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void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
56
+
dma_addr_t (*read_entry)(unsigned int entry, bool *is_present, bool *is_local);
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/* Flags is a more or less chipset specific opaque value.
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* For chipsets that need to support old ums (non-gem) code, this
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* needs to be identical to the various supported agp memory types! */
···
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}
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writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
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+
}
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+
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+
static dma_addr_t i810_read_entry(unsigned int entry,
340
+
bool *is_present, bool *is_local)
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+
{
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u32 val;
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+
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+
val = readl(intel_private.gtt + entry);
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+
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*is_present = val & I810_PTE_VALID;
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+
*is_local = val & I810_PTE_LOCAL;
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+
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return val & ~0xfff;
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}
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static resource_size_t intel_gtt_stolen_size(void)
···
755
741
writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
756
742
}
757
743
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+
static dma_addr_t i830_read_entry(unsigned int entry,
745
+
bool *is_present, bool *is_local)
746
+
{
747
+
u32 val;
748
+
749
+
val = readl(intel_private.gtt + entry);
750
+
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+
*is_present = val & I810_PTE_VALID;
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*is_local = false;
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+
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return val & ~0xfff;
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+
}
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+
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bool intel_gmch_enable_gtt(void)
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{
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u8 __iomem *reg;
···
904
877
intel_private.driver->chipset_flush();
905
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}
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EXPORT_SYMBOL(intel_gmch_gtt_insert_sg_entries);
880
+
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+
dma_addr_t intel_gmch_gtt_read_entry(unsigned int pg,
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bool *is_present, bool *is_local)
883
+
{
884
+
return intel_private.driver->read_entry(pg, is_present, is_local);
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+
}
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EXPORT_SYMBOL(intel_gmch_gtt_read_entry);
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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static void intel_gmch_gtt_insert_pages(unsigned int first_entry,
···
1160
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writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
1161
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}
1162
1128
1129
+
static dma_addr_t i965_read_entry(unsigned int entry,
1130
+
bool *is_present, bool *is_local)
1131
+
{
1132
+
u64 val;
1133
+
1134
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val = readl(intel_private.gtt + entry);
1135
+
1136
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*is_present = val & I810_PTE_VALID;
1137
+
*is_local = false;
1138
+
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return ((val & 0xf0) << 28) | (val & ~0xfff);
1140
+
}
1141
+
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static int i9xx_setup(void)
1164
1143
{
1165
1144
phys_addr_t reg_addr;
···
1234
1187
.cleanup = i810_cleanup,
1235
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.check_flags = i830_check_flags,
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.write_entry = i810_write_entry,
1190
+
.read_entry = i810_read_entry,
1237
1191
};
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static const struct intel_gtt_driver i8xx_gtt_driver = {
1239
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.gen = 2,
···
1242
1194
.setup = i830_setup,
1243
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.cleanup = i830_cleanup,
1244
1196
.write_entry = i830_write_entry,
1197
+
.read_entry = i830_read_entry,
1245
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.dma_mask_size = 32,
1246
1199
.check_flags = i830_check_flags,
1247
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.chipset_flush = i830_chipset_flush,
···
1254
1205
.cleanup = i9xx_cleanup,
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/* i945 is the last gpu to need phys mem (for overlay and cursors). */
1256
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.write_entry = i830_write_entry,
1208
+
.read_entry = i830_read_entry,
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.dma_mask_size = 32,
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.check_flags = i830_check_flags,
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.chipset_flush = i9xx_chipset_flush,
···
1265
1215
.setup = i9xx_setup,
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1216
.cleanup = i9xx_cleanup,
1267
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.write_entry = i965_write_entry,
1218
+
.read_entry = i965_read_entry,
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.dma_mask_size = 36,
1269
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.check_flags = i830_check_flags,
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.chipset_flush = i9xx_chipset_flush,
···
1276
1225
.setup = i9xx_setup,
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.cleanup = i9xx_cleanup,
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.write_entry = i965_write_entry,
1228
+
.read_entry = i965_read_entry,
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.dma_mask_size = 36,
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.check_flags = i830_check_flags,
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.chipset_flush = i9xx_chipset_flush,
···
1287
1235
.setup = i9xx_setup,
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.cleanup = i9xx_cleanup,
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.write_entry = i965_write_entry,
1238
+
.read_entry = i965_read_entry,
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.dma_mask_size = 36,
1291
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.check_flags = i830_check_flags,
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.chipset_flush = i9xx_chipset_flush,
···
1297
1244
.setup = i9xx_setup,
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.cleanup = i9xx_cleanup,
1299
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.write_entry = i965_write_entry,
1247
+
.read_entry = i965_read_entry,
1300
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.dma_mask_size = 36,
1301
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.check_flags = i830_check_flags,
1302
1250
.chipset_flush = i9xx_chipset_flush,
···
1308
1254
.setup = i9xx_setup,
1309
1255
.cleanup = i9xx_cleanup,
1310
1256
.write_entry = i965_write_entry,
1257
+
.read_entry = i965_read_entry,
1311
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.dma_mask_size = 36,
1312
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.check_flags = i830_check_flags,
1313
1260
.chipset_flush = i9xx_chipset_flush,
+2
include/drm/intel/intel-gtt.h
+2
include/drm/intel/intel-gtt.h
···
28
28
unsigned int pg_start,
29
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unsigned int flags);
30
30
void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
31
+
dma_addr_t intel_gmch_gtt_read_entry(unsigned int pg,
32
+
bool *is_present, bool *is_local);
31
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/* Special gtt memory types */
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#define AGP_DCACHE_MEMORY 1