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drm/msm/dpu: move scaling limitations out of the hw_catalog

Max upscale / downscale factors are constant between platforms. In
preparation to adding support for virtual planes and allocating SSPP
blocks on demand move max scaling factors out of the HW catalog and
handle them in the dpu_plane directly. If any of the scaling blocks gets
different limitations, this will have to be handled separately, after
the plane refactoring.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/621481/
Link: https://lore.kernel.org/r/20241025-dpu-virtual-wide-v6-4-0310fd519765@linaro.org

+13 -23
-16
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 147 147 #define MAX_HORZ_DECIMATION 4 148 148 #define MAX_VERT_DECIMATION 4 149 149 150 - #define MAX_UPSCALE_RATIO 20 151 - #define MAX_DOWNSCALE_RATIO 4 152 - #define SSPP_UNITY_SCALE 1 153 - 154 150 #define STRCAT(X, Y) (X Y) 155 151 156 152 static const uint32_t plane_formats[] = { ··· 304 308 /* SSPP common configuration */ 305 309 #define _VIG_SBLK(scaler_ver) \ 306 310 { \ 307 - .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 308 - .maxupscale = MAX_UPSCALE_RATIO, \ 309 311 .scaler_blk = {.name = "scaler", \ 310 312 .version = scaler_ver, \ 311 313 .base = 0xa00, .len = 0xa0,}, \ ··· 316 322 317 323 #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \ 318 324 { \ 319 - .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 320 - .maxupscale = MAX_UPSCALE_RATIO, \ 321 325 .scaler_blk = {.name = "scaler", \ 322 326 .version = scaler_ver, \ 323 327 .base = 0xa00, .len = 0xa0,}, \ ··· 328 336 329 337 #define _VIG_SBLK_NOSCALE() \ 330 338 { \ 331 - .maxdwnscale = SSPP_UNITY_SCALE, \ 332 - .maxupscale = SSPP_UNITY_SCALE, \ 333 339 .format_list = plane_formats, \ 334 340 .num_formats = ARRAY_SIZE(plane_formats), \ 335 341 } ··· 335 345 /* qseed2 is not supported, so disabled scaling */ 336 346 #define _VIG_SBLK_QSEED2() \ 337 347 { \ 338 - .maxdwnscale = SSPP_UNITY_SCALE, \ 339 - .maxupscale = SSPP_UNITY_SCALE, \ 340 348 .scaler_blk = {.name = "scaler", \ 341 349 /* no version for qseed2 */ \ 342 350 .base = 0x200, .len = 0xa0,}, \ ··· 347 359 348 360 #define _RGB_SBLK() \ 349 361 { \ 350 - .maxdwnscale = SSPP_UNITY_SCALE, \ 351 - .maxupscale = SSPP_UNITY_SCALE, \ 352 362 .scaler_blk = {.name = "scaler", \ 353 363 .base = 0x200, .len = 0x28,}, \ 354 364 .format_list = plane_formats, \ ··· 355 369 356 370 #define _DMA_SBLK() \ 357 371 { \ 358 - .maxdwnscale = SSPP_UNITY_SCALE, \ 359 - .maxupscale = SSPP_UNITY_SCALE, \ 360 372 .format_list = plane_formats, \ 361 373 .num_formats = ARRAY_SIZE(plane_formats), \ 362 374 }
-4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
··· 364 364 /** 365 365 * struct dpu_sspp_sub_blks : SSPP sub-blocks 366 366 * common: Pointer to common configurations shared by sub blocks 367 - * @maxdwnscale: max downscale ratio supported(without DECIMATION) 368 - * @maxupscale: maxupscale ratio supported 369 367 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 370 368 * @qseed_ver: qseed version 371 369 * @scaler_blk: ··· 373 375 * @dpu_rotation_cfg: inline rotation configuration 374 376 */ 375 377 struct dpu_sspp_sub_blks { 376 - u32 maxdwnscale; 377 - u32 maxupscale; 378 378 u32 max_per_pipe_bw; 379 379 u32 qseed_ver; 380 380 struct dpu_scaler_blk scaler_blk;
+13 -3
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
··· 777 777 return 0; 778 778 } 779 779 780 + #define MAX_UPSCALE_RATIO 20 781 + #define MAX_DOWNSCALE_RATIO 4 782 + 780 783 static int dpu_plane_atomic_check(struct drm_plane *plane, 781 784 struct drm_atomic_state *state) 782 785 { 783 786 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 784 787 plane); 785 - int i, ret = 0, min_scale; 788 + int i, ret = 0, min_scale, max_scale; 786 789 struct dpu_plane *pdpu = to_dpu_plane(plane); 787 790 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 788 791 u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; ··· 816 813 pipe_hw_caps = pipe->sspp->cap; 817 814 sblk = pipe->sspp->cap->sblk; 818 815 819 - min_scale = FRAC_16_16(1, sblk->maxupscale); 816 + if (sblk->scaler_blk.len) { 817 + min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); 818 + max_scale = MAX_DOWNSCALE_RATIO << 16; 819 + } else { 820 + min_scale = DRM_PLANE_NO_SCALING; 821 + max_scale = DRM_PLANE_NO_SCALING; 822 + } 823 + 820 824 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 821 825 min_scale, 822 - sblk->maxdwnscale << 16, 826 + max_scale, 823 827 true, true); 824 828 if (ret) { 825 829 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);