Merge tag 'mmc-v5.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC fixes from Ulf Hansson
"MMC core:
- Clear flags before allowing to retune

MMC host:
- sdhci: Clear unused bounce buffer at DMA mmap error path
- sdhci: Fix warning message when accessing RPMB in HS400 mode
- sdhci-of-arasan: Use clock-frequency property to update clk_xin
- mtk-sd: Fixup compatible string for MT8195"

* tag 'mmc-v5.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
mmc: sdhci: Fix warning message when accessing RPMB in HS400 mode
dt-bindings: mmc: change compatiable string for MT8195 mmc host IP
mmc: sdhci: Clear unused bounce buffer at DMA mmap error path
phy: intel: Fix for warnings due to EMMC clock 175Mhz change in FIP
mmc: sdhci-of-arasan: Use clock-frequency property to update clk_xin
mmc: core: clear flags before allowing to retune

Linus Torvalds 5 years ago 8f3f2ccf b8052599

+31 -6

6 changed files

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Documentation

devicetree

bindings

mmc

mtk-sd.yaml

drivers

mmc

core

core.c

host

sdhci-of-arasan.c

sdhci.c

sdhci.h

phy

intel

phy-intel-keembay-emmc.c

Documentation/devicetree/bindings/mmc/mtk-sd.yaml

··· 31 31 - const: mediatek,mt2701-mmc 32 32 - items: 33 33 - const: mediatek,mt8192-mmc 34 + - const: mediatek,mt8183-mmc 35 + - items: 34 36 - const: mediatek,mt8195-mmc 35 37 - const: mediatek,mt8183-mmc 36 38

+5 -2

drivers/mmc/core/core.c

··· 937 937 938 938 err = host->ops->execute_tuning(host, opcode); 939 939 940 - if (err) 940 + if (err) { 941 941 pr_err("%s: tuning execution failed: %d\n", 942 942 mmc_hostname(host), err); 943 - else 943 + } else { 944 + host->retune_now = 0; 945 + host->need_retune = 0; 944 946 mmc_retune_enable(host); 947 + } 945 948 946 949 return err; 947 950 }

+12 -2

drivers/mmc/host/sdhci-of-arasan.c

··· 1542 1542 } 1543 1543 } 1544 1544 1545 + sdhci_get_of_property(pdev); 1546 + 1545 1547 sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb"); 1546 1548 if (IS_ERR(sdhci_arasan->clk_ahb)) { 1547 1549 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb), ··· 1563 1561 goto err_pltfm_free; 1564 1562 } 1565 1563 1564 + /* If clock-frequency property is set, use the provided value */ 1565 + if (pltfm_host->clock && 1566 + pltfm_host->clock != clk_get_rate(clk_xin)) { 1567 + ret = clk_set_rate(clk_xin, pltfm_host->clock); 1568 + if (ret) { 1569 + dev_err(&pdev->dev, "Failed to set SD clock rate\n"); 1570 + goto clk_dis_ahb; 1571 + } 1572 + } 1573 + 1566 1574 ret = clk_prepare_enable(clk_xin); 1567 1575 if (ret) { 1568 1576 dev_err(dev, "Unable to enable SD clock.\n"); 1569 1577 goto clk_dis_ahb; 1570 1578 } 1571 - 1572 - sdhci_get_of_property(pdev); 1573 1579 1574 1580 if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) 1575 1581 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;

+9 -1

drivers/mmc/host/sdhci.c

··· 1812 1812 u16 preset = 0; 1813 1813 1814 1814 switch (host->timing) { 1815 + case MMC_TIMING_MMC_HS: 1816 + case MMC_TIMING_SD_HS: 1817 + preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED); 1818 + break; 1815 1819 case MMC_TIMING_UHS_SDR12: 1816 1820 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1817 1821 break; ··· 4076 4072 bounce_size, 4077 4073 DMA_BIDIRECTIONAL); 4078 4074 ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr); 4079 - if (ret) 4075 + if (ret) { 4076 + devm_kfree(mmc_dev(mmc), host->bounce_buffer); 4077 + host->bounce_buffer = NULL; 4080 4078 /* Again fall back to max_segs == 1 */ 4081 4079 return; 4080 + } 4081 + 4082 4082 host->bounce_buffer_size = bounce_size; 4083 4083 4084 4084 /* Lie about this since we're bouncing */

drivers/mmc/host/sdhci.h

··· 255 255 256 256 /* 60-FB reserved */ 257 257 258 + #define SDHCI_PRESET_FOR_HIGH_SPEED 0x64 258 259 #define SDHCI_PRESET_FOR_SDR12 0x66 259 260 #define SDHCI_PRESET_FOR_SDR25 0x68 260 261 #define SDHCI_PRESET_FOR_SDR50 0x6A

+2 -1

drivers/phy/intel/phy-intel-keembay-emmc.c

··· 95 95 else 96 96 freqsel = 0x0; 97 97 98 - if (mhz < 50 || mhz > 200) 98 + /* Check for EMMC clock rate*/ 99 + if (mhz > 175) 99 100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); 100 101 101 102 /*

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