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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull "ARM: SoC fixes" from Olof Johansson:
* at91, ux500, imx, omap and bcmring:
- at91 fixes for =m driver build issues, irqdomain fixes and config
dependency fixes
- ux500 kconfig dependency fixes and a smp wakeup bugfix
- imx idle bugfix and build fix due to irq domain changes
- omap uart pinmux fixes, softreset regression revert and misc fixes
- bcmring build error regression fix

* ux500 and imx had some small defconfig updates in this branch

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (27 commits)
ARM: bcmring: fix UART declarations
ARM: imx: Fix imx5 idle logic bug
ARM: imx27-dt: Fix build due to removal of irq_domain_add_simple()
ARM: imx_v4_v5_defconfig: Add support for CONFIG_REGULATOR_FIXED_VOLTAGE
ARM: OMAP1: DMTIMER: fix broken timer clock source selection
ARM: OMAP: serial: Fix the ocp smart idlemode handling bug
ARM: OMAP2+: UART: Fix incorrect population of default uart pads
ARM: OMAP: sram: fix BUG in dpll code for !PM case
dmaengine: Kconfig: fix Atmel at_hdmac entry
USB: gadget/at91_udc: add gpio_to_irq() function to vbus interrupt
USB: ohci-at91: change annotations for probe/remove functions
leds-atmel-pwm.c: Make pwmled_probe() __devinit
ARM: at91: fix at91sam9261ek Ethernet dm9000 irq
ARM: at91: fix rm9200ek flash size
ARM: at91: remove empty at91_init_serial function
ARM: at91: fix typo in at91_pmc_base assembly declaration
ARM: at91: Export at91_matrix_base
ARM: at91: Export at91_pmc_base
ARM: at91: Export at91_ramc_base
ARM: at91: Export at91_st_base
...

+80 -161
+1
arch/arm/configs/imx_v4_v5_defconfig
··· 112 112 CONFIG_IMX2_WDT=y 113 113 CONFIG_MFD_MC13XXX=y 114 114 CONFIG_REGULATOR=y 115 + CONFIG_REGULATOR_FIXED_VOLTAGE=y 115 116 CONFIG_REGULATOR_MC13783=y 116 117 CONFIG_REGULATOR_MC13892=y 117 118 CONFIG_FB=y
+4 -5
arch/arm/configs/u8500_defconfig
··· 8 8 # CONFIG_LBDAF is not set 9 9 # CONFIG_BLK_DEV_BSG is not set 10 10 CONFIG_ARCH_U8500=y 11 - CONFIG_UX500_SOC_DB5500=y 12 - CONFIG_UX500_SOC_DB8500=y 13 11 CONFIG_MACH_HREFV60=y 14 12 CONFIG_MACH_SNOWBALL=y 15 13 CONFIG_MACH_U5500=y ··· 37 39 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 38 40 CONFIG_BLK_DEV_RAM=y 39 41 CONFIG_BLK_DEV_RAM_SIZE=65536 40 - CONFIG_MISC_DEVICES=y 41 42 CONFIG_AB8500_PWM=y 42 43 CONFIG_SENSORS_BH1780=y 43 44 CONFIG_NETDEVICES=y ··· 62 65 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 63 66 CONFIG_HW_RANDOM=y 64 67 CONFIG_HW_RANDOM_NOMADIK=y 65 - CONFIG_I2C=y 66 - CONFIG_I2C_NOMADIK=y 67 68 CONFIG_SPI=y 68 69 CONFIG_SPI_PL022=y 69 70 CONFIG_GPIO_STMPE=y 70 71 CONFIG_GPIO_TC3589X=y 72 + CONFIG_POWER_SUPPLY=y 73 + CONFIG_AB8500_BM=y 74 + CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y 71 75 CONFIG_MFD_STMPE=y 72 76 CONFIG_MFD_TC3589X=y 73 77 CONFIG_AB5500_CORE=y 74 78 CONFIG_AB8500_CORE=y 79 + CONFIG_REGULATOR=y 75 80 CONFIG_REGULATOR_AB8500=y 76 81 # CONFIG_HID_SUPPORT is not set 77 82 CONFIG_USB_GADGET=y
-1
arch/arm/mach-at91/at91rm9200_devices.c
··· 1173 1173 printk(KERN_INFO "AT91: No default serial console defined.\n"); 1174 1174 } 1175 1175 #else 1176 - void __init __deprecated at91_init_serial(struct at91_uart_config *config) {} 1177 1176 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} 1178 1177 void __init at91_set_serial_console(unsigned portnr) {} 1179 1178 void __init at91_add_device_serial(void) {}
+2
arch/arm/mach-at91/at91rm9200_time.c
··· 23 23 #include <linux/interrupt.h> 24 24 #include <linux/irq.h> 25 25 #include <linux/clockchips.h> 26 + #include <linux/export.h> 26 27 27 28 #include <asm/mach/time.h> 28 29 ··· 177 176 }; 178 177 179 178 void __iomem *at91_st_base; 179 + EXPORT_SYMBOL_GPL(at91_st_base); 180 180 181 181 void __init at91rm9200_ioremap_st(u32 addr) 182 182 {
+1 -1
arch/arm/mach-at91/board-rm9200ek.c
··· 117 117 }; 118 118 119 119 #define EK_FLASH_BASE AT91_CHIPSELECT_0 120 - #define EK_FLASH_SIZE SZ_2M 120 + #define EK_FLASH_SIZE SZ_8M 121 121 122 122 static struct physmap_flash_data ek_flash_data = { 123 123 .width = 2,
+3 -2
arch/arm/mach-at91/board-sam9261ek.c
··· 85 85 .flags = IORESOURCE_MEM 86 86 }, 87 87 [2] = { 88 - .start = AT91_PIN_PC11, 89 - .end = AT91_PIN_PC11, 90 88 .flags = IORESOURCE_IRQ 91 89 | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE, 92 90 } ··· 128 130 129 131 static void __init ek_add_device_dm9000(void) 130 132 { 133 + struct resource *r = &dm9000_resource[2]; 134 + 131 135 /* Configure chip-select 2 (DM9000) */ 132 136 sam9_smc_configure(0, 2, &dm9000_smc_config); 133 137 ··· 139 139 /* Configure Interrupt pin as input, no pull-up */ 140 140 at91_set_gpio_input(AT91_PIN_PC11, 0); 141 141 142 + r->start = r->end = gpio_to_irq(AT91_PIN_PC11); 142 143 platform_device_register(&dm9000_device); 143 144 } 144 145 #else
+1
arch/arm/mach-at91/clock.c
··· 35 35 #include "generic.h" 36 36 37 37 void __iomem *at91_pmc_base; 38 + EXPORT_SYMBOL_GPL(at91_pmc_base); 38 39 39 40 /* 40 41 * There's a lot more which can be done with clocks, including cpufreq
+1 -1
arch/arm/mach-at91/include/mach/at91_pmc.h
··· 25 25 #define at91_pmc_write(field, value) \ 26 26 __raw_writel(value, at91_pmc_base + field) 27 27 #else 28 - .extern at91_aic_base 28 + .extern at91_pmc_base 29 29 #endif 30 30 31 31 #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
+2
arch/arm/mach-at91/setup.c
··· 54 54 } 55 55 56 56 void __iomem *at91_ramc_base[2]; 57 + EXPORT_SYMBOL_GPL(at91_ramc_base); 57 58 58 59 void __init at91_ioremap_ramc(int id, u32 addr, u32 size) 59 60 { ··· 293 292 } 294 293 295 294 void __iomem *at91_matrix_base; 295 + EXPORT_SYMBOL_GPL(at91_matrix_base); 296 296 297 297 void __init at91_ioremap_matrix(u32 base_addr) 298 298 {
+2 -2
arch/arm/mach-bcmring/core.c
··· 52 52 #include <mach/csp/chipcHw_inline.h> 53 53 #include <mach/csp/tmrHw_reg.h> 54 54 55 - static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL); 56 - static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL); 55 + static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL); 56 + static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL); 57 57 58 58 static struct clk pll1_clk = { 59 59 .name = "PLL1",
+4 -2
arch/arm/mach-imx/imx27-dt.c
··· 35 35 static int __init imx27_avic_add_irq_domain(struct device_node *np, 36 36 struct device_node *interrupt_parent) 37 37 { 38 - irq_domain_add_simple(np, 0); 38 + irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL); 39 39 return 0; 40 40 } 41 41 ··· 44 44 { 45 45 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; 46 46 47 - irq_domain_add_simple(np, gpio_irq_base); 47 + gpio_irq_base -= 32; 48 + irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, 49 + NULL); 48 50 49 51 return 0; 50 52 }
+1 -1
arch/arm/mach-imx/mm-imx5.c
··· 35 35 } 36 36 clk_enable(gpc_dvfs_clk); 37 37 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); 38 - if (tzic_enable_wake() != 0) 38 + if (!tzic_enable_wake()) 39 39 cpu_do_idle(); 40 40 clk_disable(gpc_dvfs_clk); 41 41 }
+1
arch/arm/mach-omap1/mux.c
··· 27 27 #include <linux/io.h> 28 28 #include <linux/spinlock.h> 29 29 30 + #include <mach/hardware.h> 30 31 31 32 #include <plat/mux.h> 32 33
+2 -2
arch/arm/mach-omap1/timer.c
··· 47 47 int n = (pdev->id - 1) << 1; 48 48 u32 l; 49 49 50 - l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); 50 + l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); 51 51 l |= source << n; 52 - __raw_writel(l, MOD_CONF_CTRL_1); 52 + omap_writel(l, MOD_CONF_CTRL_1); 53 53 54 54 return 0; 55 55 }
+15 -2
arch/arm/mach-omap2/omap_hwmod.c
··· 1422 1422 goto dis_opt_clks; 1423 1423 _write_sysconfig(v, oh); 1424 1424 1425 + if (oh->class->sysc->srst_udelay) 1426 + udelay(oh->class->sysc->srst_udelay); 1427 + 1425 1428 if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) 1426 1429 omap_test_timeout((omap_hwmod_read(oh, 1427 1430 oh->class->sysc->syss_offs) ··· 1906 1903 */ 1907 1904 int omap_hwmod_softreset(struct omap_hwmod *oh) 1908 1905 { 1909 - if (!oh) 1906 + u32 v; 1907 + int ret; 1908 + 1909 + if (!oh || !(oh->_sysc_cache)) 1910 1910 return -EINVAL; 1911 1911 1912 - return _ocp_softreset(oh); 1912 + v = oh->_sysc_cache; 1913 + ret = _set_softreset(oh, &v); 1914 + if (ret) 1915 + goto error; 1916 + _write_sysconfig(v, oh); 1917 + 1918 + error: 1919 + return ret; 1913 1920 } 1914 1921 1915 1922 /**
-1
arch/arm/mach-omap2/omap_hwmod_2420_data.c
··· 1000 1000 .flags = OMAP_FIREWALL_L4, 1001 1001 } 1002 1002 }, 1003 - .flags = OCPIF_SWSUP_IDLE, 1004 1003 .user = OCP_USER_MPU | OCP_USER_SDMA, 1005 1004 }; 1006 1005
-1
arch/arm/mach-omap2/omap_hwmod_2430_data.c
··· 1049 1049 .slave = &omap2430_dss_venc_hwmod, 1050 1050 .clk = "dss_ick", 1051 1051 .addr = omap2_dss_venc_addrs, 1052 - .flags = OCPIF_SWSUP_IDLE, 1053 1052 .user = OCP_USER_MPU | OCP_USER_SDMA, 1054 1053 }; 1055 1054
-1
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
··· 1676 1676 .flags = OMAP_FIREWALL_L4, 1677 1677 } 1678 1678 }, 1679 - .flags = OCPIF_SWSUP_IDLE, 1680 1679 .user = OCP_USER_MPU | OCP_USER_SDMA, 1681 1680 }; 1682 1681
+9
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
··· 2594 2594 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { 2595 2595 .rev_offs = 0x0000, 2596 2596 .sysc_offs = 0x0010, 2597 + /* 2598 + * ISS needs 100 OCP clk cycles delay after a softreset before 2599 + * accessing sysconfig again. 2600 + * The lowest frequency at the moment for L3 bus is 100 MHz, so 2601 + * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). 2602 + * 2603 + * TODO: Indicate errata when available. 2604 + */ 2605 + .srst_udelay = 2, 2597 2606 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | 2598 2607 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2599 2608 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+7 -117
arch/arm/mach-omap2/serial.c
··· 108 108 static void omap_uart_set_smartidle(struct platform_device *pdev) 109 109 { 110 110 struct omap_device *od = to_omap_device(pdev); 111 + u8 idlemode; 111 112 112 - omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART); 113 + if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP) 114 + idlemode = HWMOD_IDLEMODE_SMART_WKUP; 115 + else 116 + idlemode = HWMOD_IDLEMODE_SMART; 117 + 118 + omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode); 113 119 } 114 120 115 121 #else ··· 126 120 #endif /* CONFIG_PM */ 127 121 128 122 #ifdef CONFIG_OMAP_MUX 129 - static struct omap_device_pad default_uart1_pads[] __initdata = { 130 - { 131 - .name = "uart1_cts.uart1_cts", 132 - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, 133 - }, 134 - { 135 - .name = "uart1_rts.uart1_rts", 136 - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, 137 - }, 138 - { 139 - .name = "uart1_tx.uart1_tx", 140 - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, 141 - }, 142 - { 143 - .name = "uart1_rx.uart1_rx", 144 - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, 145 - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, 146 - .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, 147 - }, 148 - }; 149 - 150 - static struct omap_device_pad default_uart2_pads[] __initdata = { 151 - { 152 - .name = "uart2_cts.uart2_cts", 153 - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, 154 - }, 155 - { 156 - .name = "uart2_rts.uart2_rts", 157 - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, 158 - }, 159 - { 160 - .name = "uart2_tx.uart2_tx", 161 - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, 162 - }, 163 - { 164 - .name = "uart2_rx.uart2_rx", 165 - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, 166 - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, 167 - .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, 168 - }, 169 - }; 170 - 171 - static struct omap_device_pad default_uart3_pads[] __initdata = { 172 - { 173 - .name = "uart3_cts_rctx.uart3_cts_rctx", 174 - .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, 175 - }, 176 - { 177 - .name = "uart3_rts_sd.uart3_rts_sd", 178 - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, 179 - }, 180 - { 181 - .name = "uart3_tx_irtx.uart3_tx_irtx", 182 - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, 183 - }, 184 - { 185 - .name = "uart3_rx_irrx.uart3_rx_irrx", 186 - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, 187 - .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0, 188 - .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0, 189 - }, 190 - }; 191 - 192 - static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = { 193 - { 194 - .name = "gpmc_wait2.uart4_tx", 195 - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, 196 - }, 197 - { 198 - .name = "gpmc_wait3.uart4_rx", 199 - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, 200 - .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2, 201 - .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2, 202 - }, 203 - }; 204 - 205 - static struct omap_device_pad default_omap4_uart4_pads[] __initdata = { 206 - { 207 - .name = "uart4_tx.uart4_tx", 208 - .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, 209 - }, 210 - { 211 - .name = "uart4_rx.uart4_rx", 212 - .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, 213 - .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0, 214 - .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0, 215 - }, 216 - }; 217 - 218 123 static void omap_serial_fill_default_pads(struct omap_board_data *bdata) 219 124 { 220 - switch (bdata->id) { 221 - case 0: 222 - bdata->pads = default_uart1_pads; 223 - bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads); 224 - break; 225 - case 1: 226 - bdata->pads = default_uart2_pads; 227 - bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads); 228 - break; 229 - case 2: 230 - bdata->pads = default_uart3_pads; 231 - bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads); 232 - break; 233 - case 3: 234 - if (cpu_is_omap44xx()) { 235 - bdata->pads = default_omap4_uart4_pads; 236 - bdata->pads_cnt = 237 - ARRAY_SIZE(default_omap4_uart4_pads); 238 - } else if (cpu_is_omap3630()) { 239 - bdata->pads = default_omap36xx_uart4_pads; 240 - bdata->pads_cnt = 241 - ARRAY_SIZE(default_omap36xx_uart4_pads); 242 - } 243 - break; 244 - default: 245 - break; 246 - } 247 125 } 248 126 #else 249 127 static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
+1
arch/arm/mach-ux500/Kconfig
··· 17 17 config UX500_SOC_DB8500 18 18 bool 19 19 select MFD_DB8500_PRCMU 20 + select REGULATOR 20 21 select REGULATOR_DB8500_PRCMU 21 22 select CPU_FREQ_TABLE if CPU_FREQ 22 23
+1 -1
arch/arm/mach-ux500/platsmp.c
··· 99 99 */ 100 100 write_pen_release(cpu_logical_map(cpu)); 101 101 102 - gic_raise_softirq(cpumask_of(cpu), 1); 102 + smp_send_reschedule(cpu); 103 103 104 104 timeout = jiffies + (1 * HZ); 105 105 while (time_before(jiffies, timeout)) {
+3 -1
arch/arm/plat-omap/include/plat/omap_hwmod.h
··· 305 305 * @rev_offs: IP block revision register offset (from module base addr) 306 306 * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) 307 307 * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) 308 + * @srst_udelay: Delay needed after doing a softreset in usecs 308 309 * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} 309 310 * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported 310 311 * @clockact: the default value of the module CLOCKACTIVITY bits ··· 331 330 u16 sysc_offs; 332 331 u16 syss_offs; 333 332 u16 sysc_flags; 333 + struct omap_hwmod_sysc_fields *sysc_fields; 334 + u8 srst_udelay; 334 335 u8 idlemodes; 335 336 u8 clockact; 336 - struct omap_hwmod_sysc_fields *sysc_fields; 337 337 }; 338 338 339 339 /**
+6 -6
arch/arm/plat-omap/sram.c
··· 348 348 sdrc_actim_ctrl_b_1, sdrc_mr_1); 349 349 } 350 350 351 - #ifdef CONFIG_PM 352 351 void omap3_sram_restore_context(void) 353 352 { 354 353 omap_sram_ceil = omap_sram_base + omap_sram_size; ··· 357 358 omap3_sram_configure_core_dpll_sz); 358 359 omap_push_sram_idle(); 359 360 } 360 - #endif /* CONFIG_PM */ 361 - 362 - #endif /* CONFIG_ARCH_OMAP3 */ 363 361 364 362 static inline int omap34xx_sram_init(void) 365 363 { 366 - #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 367 364 omap3_sram_restore_context(); 368 - #endif 369 365 return 0; 370 366 } 367 + #else 368 + static inline int omap34xx_sram_init(void) 369 + { 370 + return 0; 371 + } 372 + #endif /* CONFIG_ARCH_OMAP3 */ 371 373 372 374 static inline int am33xx_sram_init(void) 373 375 {
+2 -3
drivers/dma/Kconfig
··· 91 91 92 92 config AT_HDMAC 93 93 tristate "Atmel AHB DMA support" 94 - depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 94 + depends on ARCH_AT91 95 95 select DMA_ENGINE 96 96 help 97 - Support the Atmel AHB DMA controller. This can be integrated in 98 - chips such as the Atmel AT91SAM9RL. 97 + Support the Atmel AHB DMA controller. 99 98 100 99 config FSL_DMA 101 100 tristate "Freescale Elo and Elo Plus DMA support"
+1 -1
drivers/leds/leds-atmel-pwm.c
··· 35 35 * NOTE: we reuse the platform_data structure of GPIO leds, 36 36 * but repurpose its "gpio" number as a PWM channel number. 37 37 */ 38 - static int __init pwmled_probe(struct platform_device *pdev) 38 + static int __devinit pwmled_probe(struct platform_device *pdev) 39 39 { 40 40 const struct gpio_led_platform_data *pdata; 41 41 struct pwmled *leds;
+4 -4
drivers/usb/gadget/at91_udc.c
··· 1863 1863 mod_timer(&udc->vbus_timer, 1864 1864 jiffies + VBUS_POLL_TIMEOUT); 1865 1865 } else { 1866 - if (request_irq(udc->board.vbus_pin, at91_vbus_irq, 1867 - 0, driver_name, udc)) { 1866 + if (request_irq(gpio_to_irq(udc->board.vbus_pin), 1867 + at91_vbus_irq, 0, driver_name, udc)) { 1868 1868 DBG("request vbus irq %d failed\n", 1869 1869 udc->board.vbus_pin); 1870 1870 retval = -EBUSY; ··· 1886 1886 return 0; 1887 1887 fail4: 1888 1888 if (gpio_is_valid(udc->board.vbus_pin) && !udc->board.vbus_polled) 1889 - free_irq(udc->board.vbus_pin, udc); 1889 + free_irq(gpio_to_irq(udc->board.vbus_pin), udc); 1890 1890 fail3: 1891 1891 if (gpio_is_valid(udc->board.vbus_pin)) 1892 1892 gpio_free(udc->board.vbus_pin); ··· 1924 1924 device_init_wakeup(&pdev->dev, 0); 1925 1925 remove_debug_file(udc); 1926 1926 if (gpio_is_valid(udc->board.vbus_pin)) { 1927 - free_irq(udc->board.vbus_pin, udc); 1927 + free_irq(gpio_to_irq(udc->board.vbus_pin), udc); 1928 1928 gpio_free(udc->board.vbus_pin); 1929 1929 } 1930 1930 free_irq(udc->udp_irq, udc);
+6 -6
drivers/usb/host/ohci-at91.c
··· 94 94 95 95 /*-------------------------------------------------------------------------*/ 96 96 97 - static void usb_hcd_at91_remove (struct usb_hcd *, struct platform_device *); 97 + static void __devexit usb_hcd_at91_remove (struct usb_hcd *, struct platform_device *); 98 98 99 99 /* configure so an HC device and id are always provided */ 100 100 /* always called with process context; sleeping is OK */ ··· 108 108 * then invokes the start() method for the HCD associated with it 109 109 * through the hotplug entry's driver_data. 110 110 */ 111 - static int usb_hcd_at91_probe(const struct hc_driver *driver, 111 + static int __devinit usb_hcd_at91_probe(const struct hc_driver *driver, 112 112 struct platform_device *pdev) 113 113 { 114 114 int retval; ··· 203 203 * context, "rmmod" or something similar. 204 204 * 205 205 */ 206 - static void usb_hcd_at91_remove(struct usb_hcd *hcd, 206 + static void __devexit usb_hcd_at91_remove(struct usb_hcd *hcd, 207 207 struct platform_device *pdev) 208 208 { 209 209 usb_remove_hcd(hcd); ··· 545 545 546 546 /*-------------------------------------------------------------------------*/ 547 547 548 - static int ohci_hcd_at91_drv_probe(struct platform_device *pdev) 548 + static int __devinit ohci_hcd_at91_drv_probe(struct platform_device *pdev) 549 549 { 550 550 struct at91_usbh_data *pdata; 551 551 int i; ··· 620 620 return usb_hcd_at91_probe(&ohci_at91_hc_driver, pdev); 621 621 } 622 622 623 - static int ohci_hcd_at91_drv_remove(struct platform_device *pdev) 623 + static int __devexit ohci_hcd_at91_drv_remove(struct platform_device *pdev) 624 624 { 625 625 struct at91_usbh_data *pdata = pdev->dev.platform_data; 626 626 int i; ··· 696 696 697 697 static struct platform_driver ohci_hcd_at91_driver = { 698 698 .probe = ohci_hcd_at91_drv_probe, 699 - .remove = ohci_hcd_at91_drv_remove, 699 + .remove = __devexit_p(ohci_hcd_at91_drv_remove), 700 700 .shutdown = usb_hcd_platform_shutdown, 701 701 .suspend = ohci_hcd_at91_drv_suspend, 702 702 .resume = ohci_hcd_at91_drv_resume,