tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
"A few patches have come up since the merge window. The largest one is
a rewrite of the PXA lubbock/mainstone IRQ handling. This was already
broken in 2011 by a change to the GPIO code and only noticed now.

The other changes contained here are:

MAINTAINERS file updates:

- Ray Jui and Scott Branden are now co-maintainers for some of the
mach-bcm chips, while Christian Daudt and Marc Carino have stepped
down.

- Andrew Victor is no longer maintaining at91. Instead, Alexandre
Belloni now becomes an official maintainer, after having done a
bulk of the work for a while.

- Baruch Siach, who added the mach-digicolor platform in 4.1 is now
listed as maintainer

- The git URL for mach-socfpga has changed

Bug fixes:

- Three bug fixes for new rockchip rk3288 code

- A regression fix to make SD card support work on certain ux500
boards

- multiple smaller dts fixes for imx, omap, mvebu, and shmobile

- a regression fiix for omap3 power consumption

- a fix for regression in the ARM CCI bus driver

Configuration changes:

- more imx platforms are now enabled in multi_v7_defconfig"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits)
MAINTAINERS: add Conexant Digicolor machines entry
MAINTAINERS: socfpga: update the git repo for SoCFPGA
ARM: multi_v7_defconfig: Select more FSL SoCs
MAINTAINERS: replace an AT91 maintainer
drivers: CCI: fix used_mask init in validate_group()
bus: omap_l3_noc: Fix master id address decoding for OMAP5
bus: omap_l3_noc: Fix offset for DRA7 CLK1_HOST_CLK1_2 instance
ARM: dts: dra7: Fix efuse register size for ABB
ARM: dts: am57xx-beagle-x15: Switch GPIO fan number
ARM: dts: am57xx-beagle-x15: Switch UART mux pins
ARM: dts: am437x-sk: reduce col-scan-delay-us
ARM: dts: am437x-sk: fix for new newhaven display module revision
ARM: dts: am57xx-beagle-x15: Fix RTC aliases
ARM: dts: am57xx-beagle-x15: Fix IRQ type for mcp7941x
ARM: dts: omap3: Add #iommu-cells to isp and iva iommu
ARM: omap2plus_defconfig: Enable EXTCON_USB_GPIO
ARM: dts: OMAP3-N900: Add microphone bias voltages
ARM: OMAP2+: Fix omap off idle power consumption creeping up
MAINTAINERS: Update brcmstb entry
MAINTAINERS: Remove Christian Daudt for mach-bcm
...

Linus Torvalds 8f59ae06 51dfcb07

+480 -234
+7
CREDITS
··· 3709 3709 D: Co-author of German book ``Linux-Kernel-Programmierung'' 3710 3710 D: Co-founder of Berlin Linux User Group 3711 3711 3712 + N: Andrew Victor 3713 + E: linux@maxim.org.za 3714 + W: http://maxim.org.za/at91_26.html 3715 + D: First maintainer of Atmel ARM-based SoC, aka AT91 3716 + D: Introduced support for at91rm9200, the first chip of AT91 family 3717 + S: South Africa 3718 + 3712 3719 N: Riku Voipio 3713 3720 E: riku.voipio@iki.fi 3714 3721 D: Author of PCA9532 LED and Fintek f75375s hwmon driver
+1
Documentation/devicetree/bindings/arm/omap/l3-noc.txt
··· 6 6 Required properties: 7 7 - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family 8 8 Should be "ti,omap4-l3-noc" for OMAP4 family 9 + Should be "ti,omap5-l3-noc" for OMAP5 family 9 10 Should be "ti,dra7-l3-noc" for DRA7 family 10 11 Should be "ti,am4372-l3-noc" for AM43 family 11 12 - reg: Contains L3 register address range for each noc domain.
+1 -1
Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
··· 38 38 80 81 68 69 39 39 70 71 72 73 40 40 74 75 76 77>; 41 - interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", 41 + interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", 42 42 "saif0", "saif1", "i2c0", "i2c1", 43 43 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", 44 44 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
+12 -6
MAINTAINERS
··· 892 892 F: arch/arm/mach-alpine/ 893 893 894 894 ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES 895 - M: Andrew Victor <linux@maxim.org.za> 896 895 M: Nicolas Ferre <nicolas.ferre@atmel.com> 896 + M: Alexandre Belloni <alexandre.belloni@free-electrons.com> 897 897 M: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> 898 898 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 899 - W: http://maxim.org.za/at91_26.html 900 899 W: http://www.linux4sam.org 901 900 S: Supported 902 901 F: arch/arm/mach-at91/ ··· 988 989 F: drivers/clocksource/timer-prima2.c 989 990 F: drivers/clocksource/timer-atlas7.c 990 991 N: [^a-z]sirf 992 + 993 + ARM/CONEXANT DIGICOLOR MACHINE SUPPORT 994 + M: Baruch Siach <baruch@tkos.co.il> 995 + L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 996 + S: Maintained 997 + N: digicolor 991 998 992 999 ARM/EBSA110 MACHINE SUPPORT 993 1000 M: Russell King <linux@arm.linux.org.uk> ··· 1444 1439 M: Dinh Nguyen <dinguyen@opensource.altera.com> 1445 1440 S: Maintained 1446 1441 F: arch/arm/mach-socfpga/ 1442 + F: arch/arm/boot/dts/socfpga* 1443 + F: arch/arm/configs/socfpga_defconfig 1447 1444 W: http://www.rocketboards.org 1448 - T: git://git.rocketboards.org/linux-socfpga.git 1449 - T: git://git.rocketboards.org/linux-socfpga-next.git 1445 + T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git 1450 1446 1451 1447 ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT 1452 1448 M: Dinh Nguyen <dinguyen@opensource.altera.com> ··· 2122 2116 F: drivers/net/ethernet/broadcom/bnx2x/ 2123 2117 2124 2118 BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE 2125 - M: Christian Daudt <bcm@fixthebug.org> 2126 2119 M: Florian Fainelli <f.fainelli@gmail.com> 2120 + M: Ray Jui <rjui@broadcom.com> 2121 + M: Scott Branden <sbranden@broadcom.com> 2127 2122 L: bcm-kernel-feedback-list@broadcom.com 2128 2123 T: git git://github.com/broadcom/mach-bcm 2129 2124 S: Maintained ··· 2175 2168 F: drivers/usb/gadget/udc/bcm63xx_udc.* 2176 2169 2177 2170 BROADCOM BCM7XXX ARM ARCHITECTURE 2178 - M: Marc Carino <marc.ceeeee@gmail.com> 2179 2171 M: Brian Norris <computersforpeace@gmail.com> 2180 2172 M: Gregory Fong <gregory.0xf0@gmail.com> 2181 2173 M: Florian Fainelli <f.fainelli@gmail.com>
+2 -2
arch/arm/boot/dts/am437x-sk-evm.dts
··· 49 49 pinctrl-0 = <&matrix_keypad_pins>; 50 50 51 51 debounce-delay-ms = <5>; 52 - col-scan-delay-us = <1500>; 52 + col-scan-delay-us = <5>; 53 53 54 54 row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ 55 55 &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ ··· 473 473 interrupt-parent = <&gpio0>; 474 474 interrupts = <31 0>; 475 475 476 - wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 476 + reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; 477 477 478 478 touchscreen-size-x = <480>; 479 479 touchscreen-size-y = <272>;
+6 -5
arch/arm/boot/dts/am57xx-beagle-x15.dts
··· 18 18 aliases { 19 19 rtc0 = &mcp_rtc; 20 20 rtc1 = &tps659038_rtc; 21 + rtc2 = &rtc; 21 22 }; 22 23 23 24 memory { ··· 84 83 gpio_fan: gpio_fan { 85 84 /* Based on 5v 500mA AFB02505HHB */ 86 85 compatible = "gpio-fan"; 87 - gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>; 86 + gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; 88 87 gpio-fan,speed-map = <0 0>, 89 88 <13000 1>; 90 89 #cooling-cells = <2>; ··· 131 130 132 131 uart3_pins_default: uart3_pins_default { 133 132 pinctrl-single,pins = < 134 - 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */ 135 - 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */ 133 + 0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */ 134 + 0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */ 136 135 >; 137 136 }; 138 137 ··· 456 455 mcp_rtc: rtc@6f { 457 456 compatible = "microchip,mcp7941x"; 458 457 reg = <0x6f>; 459 - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */ 458 + interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */ 460 459 461 460 pinctrl-names = "default"; 462 461 pinctrl-0 = <&mcp79410_pins_default>; ··· 479 478 &uart3 { 480 479 status = "okay"; 481 480 interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 482 - <&dra7_pmx_core 0x248>; 481 + <&dra7_pmx_core 0x3f8>; 483 482 484 483 pinctrl-names = "default"; 485 484 pinctrl-0 = <&uart3_pins_default>;
+4
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
··· 105 105 }; 106 106 107 107 internal-regs { 108 + rtc@10300 { 109 + /* No crystal connected to the internal RTC */ 110 + status = "disabled"; 111 + }; 108 112 serial@12000 { 109 113 status = "okay"; 110 114 };
+5 -5
arch/arm/boot/dts/dra7.dtsi
··· 911 911 ti,clock-cycles = <16>; 912 912 913 913 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 914 - <0x4ae06014 0x4>, <0x4a003b20 0x8>, 914 + <0x4ae06014 0x4>, <0x4a003b20 0xc>, 915 915 <0x4ae0c158 0x4>; 916 916 reg-names = "setup-address", "control-address", 917 917 "int-address", "efuse-address", ··· 944 944 ti,clock-cycles = <16>; 945 945 946 946 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 947 - <0x4ae06010 0x4>, <0x4a0025cc 0x8>, 947 + <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 948 948 <0x4a002470 0x4>; 949 949 reg-names = "setup-address", "control-address", 950 950 "int-address", "efuse-address", ··· 977 977 ti,clock-cycles = <16>; 978 978 979 979 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 980 - <0x4ae06010 0x4>, <0x4a0025e0 0x8>, 980 + <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 981 981 <0x4a00246c 0x4>; 982 982 reg-names = "setup-address", "control-address", 983 983 "int-address", "efuse-address", ··· 1010 1010 ti,clock-cycles = <16>; 1011 1011 1012 1012 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 1013 - <0x4ae06010 0x4>, <0x4a003b08 0x8>, 1013 + <0x4ae06010 0x4>, <0x4a003b08 0xc>, 1014 1014 <0x4ae0c154 0x4>; 1015 1015 reg-names = "setup-address", "control-address", 1016 1016 "int-address", "efuse-address", ··· 1203 1203 status = "disabled"; 1204 1204 }; 1205 1205 1206 - rtc@48838000 { 1206 + rtc: rtc@48838000 { 1207 1207 compatible = "ti,am3352-rtc"; 1208 1208 reg = <0x48838000 0x100>; 1209 1209 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+3 -1
arch/arm/boot/dts/imx23-olinuxino.dts
··· 12 12 */ 13 13 14 14 /dts-v1/; 15 + #include <dt-bindings/gpio/gpio.h> 15 16 #include "imx23.dtsi" 16 17 17 18 / { ··· 94 93 95 94 ahb@80080000 { 96 95 usb0: usb@80080000 { 96 + dr_mode = "host"; 97 97 vbus-supply = <&reg_usb0_vbus>; 98 98 status = "okay"; 99 99 }; ··· 124 122 125 123 user { 126 124 label = "green"; 127 - gpios = <&gpio2 1 1>; 125 + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 128 126 }; 129 127 }; 130 128 };
+1
arch/arm/boot/dts/imx25.dtsi
··· 428 428 429 429 pwm4: pwm@53fc8000 { 430 430 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm"; 431 + #pwm-cells = <2>; 431 432 reg = <0x53fc8000 0x4000>; 432 433 clocks = <&clks 108>, <&clks 52>; 433 434 clock-names = "ipg", "per";
+1 -1
arch/arm/boot/dts/imx28.dtsi
··· 913 913 80 81 68 69 914 914 70 71 72 73 915 915 74 75 76 77>; 916 - interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", 916 + interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", 917 917 "saif0", "saif1", "i2c0", "i2c1", 918 918 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", 919 919 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
+2
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
··· 31 31 regulator-min-microvolt = <5000000>; 32 32 regulator-max-microvolt = <5000000>; 33 33 gpio = <&gpio4 15 0>; 34 + enable-active-high; 34 35 }; 35 36 36 37 reg_usb_h1_vbus: regulator@1 { ··· 41 40 regulator-min-microvolt = <5000000>; 42 41 regulator-max-microvolt = <5000000>; 43 42 gpio = <&gpio1 0 0>; 43 + enable-active-high; 44 44 }; 45 45 }; 46 46
-1
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
··· 185 185 &i2c3 { 186 186 pinctrl-names = "default"; 187 187 pinctrl-0 = <&pinctrl_i2c3>; 188 - pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 189 188 status = "okay"; 190 189 191 190 max7310_a: gpio@30 {
+4
arch/arm/boot/dts/omap3-n900.dts
··· 498 498 DRVDD-supply = <&vmmc2>; 499 499 IOVDD-supply = <&vio>; 500 500 DVDD-supply = <&vio>; 501 + 502 + ai3x-micbias-vg = <1>; 501 503 }; 502 504 503 505 tlv320aic3x_aux: tlv320aic3x@19 { ··· 511 509 DRVDD-supply = <&vmmc2>; 512 510 IOVDD-supply = <&vio>; 513 511 DVDD-supply = <&vio>; 512 + 513 + ai3x-micbias-vg = <2>; 514 514 }; 515 515 516 516 tsl2563: tsl2563@29 {
+2
arch/arm/boot/dts/omap3.dtsi
··· 456 456 }; 457 457 458 458 mmu_isp: mmu@480bd400 { 459 + #iommu-cells = <0>; 459 460 compatible = "ti,omap2-iommu"; 460 461 reg = <0x480bd400 0x80>; 461 462 interrupts = <24>; ··· 465 464 }; 466 465 467 466 mmu_iva: mmu@5d000000 { 467 + #iommu-cells = <0>; 468 468 compatible = "ti,omap2-iommu"; 469 469 reg = <0x5d000000 0x80>; 470 470 interrupts = <28>;
+1 -1
arch/arm/boot/dts/omap5.dtsi
··· 128 128 * hierarchy. 129 129 */ 130 130 ocp { 131 - compatible = "ti,omap4-l3-noc", "simple-bus"; 131 + compatible = "ti,omap5-l3-noc", "simple-bus"; 132 132 #address-cells = <1>; 133 133 #size-cells = <1>; 134 134 ranges;
+1 -1
arch/arm/boot/dts/r8a7791-koelsch.dts
··· 545 545 compatible = "adi,adv7511w"; 546 546 reg = <0x39>; 547 547 interrupt-parent = <&gpio3>; 548 - interrupts = <29 IRQ_TYPE_EDGE_FALLING>; 548 + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 549 549 550 550 adi,input-depth = <8>; 551 551 adi,input-colorspace = "rgb";
-17
arch/arm/boot/dts/ste-dbx5x0.dtsi
··· 1017 1017 status = "disabled"; 1018 1018 }; 1019 1019 1020 - vmmci: regulator-gpio { 1021 - compatible = "regulator-gpio"; 1022 - 1023 - regulator-min-microvolt = <1800000>; 1024 - regulator-max-microvolt = <2900000>; 1025 - regulator-name = "mmci-reg"; 1026 - regulator-type = "voltage"; 1027 - 1028 - startup-delay-us = <100>; 1029 - enable-active-high; 1030 - 1031 - states = <1800000 0x1 1032 - 2900000 0x0>; 1033 - 1034 - status = "disabled"; 1035 - }; 1036 - 1037 1020 mcde@a0350000 { 1038 1021 compatible = "stericsson,mcde"; 1039 1022 reg = <0xa0350000 0x1000>, /* MCDE */
+15
arch/arm/boot/dts/ste-href.dtsi
··· 111 111 pinctrl-1 = <&i2c3_sleep_mode>; 112 112 }; 113 113 114 + vmmci: regulator-gpio { 115 + compatible = "regulator-gpio"; 116 + 117 + regulator-min-microvolt = <1800000>; 118 + regulator-max-microvolt = <2900000>; 119 + regulator-name = "mmci-reg"; 120 + regulator-type = "voltage"; 121 + 122 + startup-delay-us = <100>; 123 + enable-active-high; 124 + 125 + states = <1800000 0x1 126 + 2900000 0x0>; 127 + }; 128 + 114 129 // External Micro SD slot 115 130 sdi0_per1@80126000 { 116 131 arm,primecell-periphid = <0x10480180>;
+13
arch/arm/boot/dts/ste-snowball.dts
··· 146 146 }; 147 147 148 148 vmmci: regulator-gpio { 149 + compatible = "regulator-gpio"; 150 + 149 151 gpios = <&gpio7 4 0x4>; 150 152 enable-gpio = <&gpio6 25 0x4>; 153 + 154 + regulator-min-microvolt = <1800000>; 155 + regulator-max-microvolt = <2900000>; 156 + regulator-name = "mmci-reg"; 157 + regulator-type = "voltage"; 158 + 159 + startup-delay-us = <100>; 160 + enable-active-high; 161 + 162 + states = <1800000 0x1 163 + 2900000 0x0>; 151 164 }; 152 165 153 166 // External Micro SD slot
+3
arch/arm/configs/multi_v7_defconfig
··· 39 39 CONFIG_ARCH_KEYSTONE=y 40 40 CONFIG_ARCH_MESON=y 41 41 CONFIG_ARCH_MXC=y 42 + CONFIG_SOC_IMX50=y 42 43 CONFIG_SOC_IMX51=y 43 44 CONFIG_SOC_IMX53=y 44 45 CONFIG_SOC_IMX6Q=y 45 46 CONFIG_SOC_IMX6SL=y 47 + CONFIG_SOC_IMX6SX=y 46 48 CONFIG_SOC_VF610=y 49 + CONFIG_SOC_LS1021A=y 47 50 CONFIG_ARCH_OMAP3=y 48 51 CONFIG_ARCH_OMAP4=y 49 52 CONFIG_SOC_OMAP5=y
+1 -1
arch/arm/configs/omap2plus_defconfig
··· 393 393 CONFIG_DMA_OMAP=y 394 394 # CONFIG_IOMMU_SUPPORT is not set 395 395 CONFIG_EXTCON=m 396 - CONFIG_EXTCON_GPIO=m 396 + CONFIG_EXTCON_USB_GPIO=m 397 397 CONFIG_EXTCON_PALMAS=m 398 398 CONFIG_TI_EMIF=m 399 399 CONFIG_PWM=y
+1 -1
arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
··· 1 1 /* 2 - * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> 2 + * Copyright (C) 2010 Pengutronix, Wolfram Sang <kernel@pengutronix.de> 3 3 * 4 4 * This program is free software; you can redistribute it and/or modify it under 5 5 * the terms of the GNU General Public License version 2 as published by the
+1
arch/arm/mach-omap2/prm-regbits-34xx.h
··· 112 112 #define OMAP3430_VC_CMD_ONLP_SHIFT 16 113 113 #define OMAP3430_VC_CMD_RET_SHIFT 8 114 114 #define OMAP3430_VC_CMD_OFF_SHIFT 0 115 + #define OMAP3430_SREN_MASK (1 << 4) 115 116 #define OMAP3430_HSEN_MASK (1 << 3) 116 117 #define OMAP3430_MCODE_MASK (0x7 << 0) 117 118 #define OMAP3430_VALID_MASK (1 << 24)
+1
arch/arm/mach-omap2/prm-regbits-44xx.h
··· 35 35 #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 36 36 #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) 37 37 #define OMAP4430_HSMCODE_MASK (0x7 << 0) 38 + #define OMAP4430_SRMODEEN_MASK (1 << 4) 38 39 #define OMAP4430_HSMODEEN_MASK (1 << 3) 39 40 #define OMAP4430_HSSCLL_SHIFT 24 40 41 #define OMAP4430_ICEPICK_RST_SHIFT 9
+10 -2
arch/arm/mach-omap2/vc.c
··· 316 316 * idle. And we can also scale voltages to zero for off-idle. 317 317 * Note that no actual voltage scaling during off-idle will 318 318 * happen unless the board specific twl4030 PMIC scripts are 319 - * loaded. 319 + * loaded. See also omap_vc_i2c_init for comments regarding 320 + * erratum i531. 320 321 */ 321 322 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); 322 323 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { ··· 705 704 return; 706 705 } 707 706 707 + /* 708 + * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around 709 + * erratum i531 "Extra Power Consumed When Repeated Start Operation 710 + * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)". 711 + * Otherwise I2C4 eventually leads into about 23mW extra power being 712 + * consumed even during off idle using VMODE. 713 + */ 708 714 i2c_high_speed = voltdm->pmic->i2c_high_speed; 709 715 if (i2c_high_speed) 710 - voltdm->rmw(vc->common->i2c_cfg_hsen_mask, 716 + voltdm->rmw(vc->common->i2c_cfg_clear_mask, 711 717 vc->common->i2c_cfg_hsen_mask, 712 718 vc->common->i2c_cfg_reg); 713 719
+2
arch/arm/mach-omap2/vc.h
··· 34 34 * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register 35 35 * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register 36 36 * @i2c_cfg_reg: I2C configuration register offset 37 + * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register 37 38 * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register 38 39 * @i2c_mcode_mask: MCODE field mask for I2C config register 39 40 * ··· 53 52 u8 cmd_ret_shift; 54 53 u8 cmd_off_shift; 55 54 u8 i2c_cfg_reg; 55 + u8 i2c_cfg_clear_mask; 56 56 u8 i2c_cfg_hsen_mask; 57 57 u8 i2c_mcode_mask; 58 58 };
+1
arch/arm/mach-omap2/vc3xxx_data.c
··· 40 40 .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT, 41 41 .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT, 42 42 .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT, 43 + .i2c_cfg_clear_mask = OMAP3430_SREN_MASK | OMAP3430_HSEN_MASK, 43 44 .i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK, 44 45 .i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET, 45 46 .i2c_mcode_mask = OMAP3430_MCODE_MASK,
+1
arch/arm/mach-omap2/vc44xx_data.c
··· 42 42 .cmd_ret_shift = OMAP4430_RET_SHIFT, 43 43 .cmd_off_shift = OMAP4430_OFF_SHIFT, 44 44 .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET, 45 + .i2c_cfg_clear_mask = OMAP4430_SRMODEEN_MASK | OMAP4430_HSMODEEN_MASK, 45 46 .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK, 46 47 .i2c_mcode_mask = OMAP4430_HSMCODE_MASK, 47 48 };
+9
arch/arm/mach-pxa/Kconfig
··· 691 691 config PXA310_ULPI 692 692 bool 693 693 694 + config PXA_SYSTEMS_CPLDS 695 + tristate "Motherboard cplds" 696 + default ARCH_LUBBOCK || MACH_MAINSTONE 697 + help 698 + This driver supports the Lubbock and Mainstone multifunction chip 699 + found on the pxa25x development platform system (Lubbock) and pxa27x 700 + development platform system (Mainstone). This IO board supports the 701 + interrupts handling, ethernet controller, flash chips, etc ... 702 + 694 703 endif
+1
arch/arm/mach-pxa/Makefile
··· 90 90 obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o 91 91 obj-$(CONFIG_MACH_ZIPIT2) += z2.o 92 92 93 + obj-$(CONFIG_PXA_SYSTEMS_CPLDS) += pxa_cplds_irqs.o 93 94 obj-$(CONFIG_TOSA_BT) += tosa-bt.o
+4 -3
arch/arm/mach-pxa/include/mach/lubbock.h
··· 37 37 #define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) 38 38 39 39 /* Board specific IRQs */ 40 - #define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x)) 40 + #define LUBBOCK_NR_IRQS IRQ_BOARD_START 41 + 42 + #define LUBBOCK_IRQ(x) (LUBBOCK_NR_IRQS + (x)) 41 43 #define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) 42 44 #define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) 43 45 #define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ ··· 49 47 #define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ 50 48 #define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) 51 49 52 - #define LUBBOCK_SA1111_IRQ_BASE (IRQ_BOARD_START + 16) 53 - #define LUBBOCK_NR_IRQS (IRQ_BOARD_START + 16 + 55) 50 + #define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32) 54 51 55 52 #ifndef __ASSEMBLY__ 56 53 extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
+3 -3
arch/arm/mach-pxa/include/mach/mainstone.h
··· 120 120 #define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ 121 121 122 122 /* board specific IRQs */ 123 - #define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) 123 + #define MAINSTONE_NR_IRQS IRQ_BOARD_START 124 + 125 + #define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x)) 124 126 #define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) 125 127 #define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) 126 128 #define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) ··· 137 135 #define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) 138 136 #define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) 139 137 #define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) 140 - 141 - #define MAINSTONE_NR_IRQS (IRQ_BOARD_START + 16) 142 138 143 139 #endif
+29 -79
arch/arm/mach-pxa/lubbock.c
··· 12 12 * published by the Free Software Foundation. 13 13 */ 14 14 #include <linux/gpio.h> 15 + #include <linux/gpio/machine.h> 15 16 #include <linux/module.h> 16 17 #include <linux/kernel.h> 17 18 #include <linux/init.h> ··· 123 122 local_irq_restore(flags); 124 123 } 125 124 EXPORT_SYMBOL(lubbock_set_misc_wr); 126 - 127 - static unsigned long lubbock_irq_enabled; 128 - 129 - static void lubbock_mask_irq(struct irq_data *d) 130 - { 131 - int lubbock_irq = (d->irq - LUBBOCK_IRQ(0)); 132 - LUB_IRQ_MASK_EN = (lubbock_irq_enabled &= ~(1 << lubbock_irq)); 133 - } 134 - 135 - static void lubbock_unmask_irq(struct irq_data *d) 136 - { 137 - int lubbock_irq = (d->irq - LUBBOCK_IRQ(0)); 138 - /* the irq can be acknowledged only if deasserted, so it's done here */ 139 - LUB_IRQ_SET_CLR &= ~(1 << lubbock_irq); 140 - LUB_IRQ_MASK_EN = (lubbock_irq_enabled |= (1 << lubbock_irq)); 141 - } 142 - 143 - static struct irq_chip lubbock_irq_chip = { 144 - .name = "FPGA", 145 - .irq_ack = lubbock_mask_irq, 146 - .irq_mask = lubbock_mask_irq, 147 - .irq_unmask = lubbock_unmask_irq, 148 - }; 149 - 150 - static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc) 151 - { 152 - unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled; 153 - do { 154 - /* clear our parent irq */ 155 - desc->irq_data.chip->irq_ack(&desc->irq_data); 156 - if (likely(pending)) { 157 - irq = LUBBOCK_IRQ(0) + __ffs(pending); 158 - generic_handle_irq(irq); 159 - } 160 - pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled; 161 - } while (pending); 162 - } 163 - 164 - static void __init lubbock_init_irq(void) 165 - { 166 - int irq; 167 - 168 - pxa25x_init_irq(); 169 - 170 - /* setup extra lubbock irqs */ 171 - for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { 172 - irq_set_chip_and_handler(irq, &lubbock_irq_chip, 173 - handle_level_irq); 174 - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 175 - } 176 - 177 - irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lubbock_irq_handler); 178 - irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING); 179 - } 180 - 181 - #ifdef CONFIG_PM 182 - 183 - static void lubbock_irq_resume(void) 184 - { 185 - LUB_IRQ_MASK_EN = lubbock_irq_enabled; 186 - } 187 - 188 - static struct syscore_ops lubbock_irq_syscore_ops = { 189 - .resume = lubbock_irq_resume, 190 - }; 191 - 192 - static int __init lubbock_irq_device_init(void) 193 - { 194 - if (machine_is_lubbock()) { 195 - register_syscore_ops(&lubbock_irq_syscore_ops); 196 - return 0; 197 - } 198 - return -ENODEV; 199 - } 200 - 201 - device_initcall(lubbock_irq_device_init); 202 - 203 - #endif 204 125 205 126 static int lubbock_udc_is_connected(void) 206 127 { ··· 306 383 }, 307 384 }; 308 385 386 + static struct resource lubbock_cplds_resources[] = { 387 + [0] = { 388 + .start = LUBBOCK_FPGA_PHYS + 0xc0, 389 + .end = LUBBOCK_FPGA_PHYS + 0xe0 - 1, 390 + .flags = IORESOURCE_MEM, 391 + }, 392 + [1] = { 393 + .start = PXA_GPIO_TO_IRQ(0), 394 + .end = PXA_GPIO_TO_IRQ(0), 395 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, 396 + }, 397 + [2] = { 398 + .start = LUBBOCK_IRQ(0), 399 + .end = LUBBOCK_IRQ(6), 400 + .flags = IORESOURCE_IRQ, 401 + }, 402 + }; 403 + 404 + static struct platform_device lubbock_cplds_device = { 405 + .name = "pxa_cplds_irqs", 406 + .id = -1, 407 + .resource = &lubbock_cplds_resources[0], 408 + .num_resources = 3, 409 + }; 410 + 411 + 309 412 static struct platform_device *devices[] __initdata = { 310 413 &sa1111_device, 311 414 &smc91x_device, 312 415 &lubbock_flash_device[0], 313 416 &lubbock_flash_device[1], 417 + &lubbock_cplds_device, 314 418 }; 315 419 316 420 static struct pxafb_mode_info sharp_lm8v31_mode = { ··· 598 648 /* Maintainer: MontaVista Software Inc. */ 599 649 .map_io = lubbock_map_io, 600 650 .nr_irqs = LUBBOCK_NR_IRQS, 601 - .init_irq = lubbock_init_irq, 651 + .init_irq = pxa25x_init_irq, 602 652 .handle_irq = pxa25x_handle_irq, 603 653 .init_time = pxa_timer_init, 604 654 .init_machine = lubbock_init,
+28 -87
arch/arm/mach-pxa/mainstone.c
··· 13 13 * published by the Free Software Foundation. 14 14 */ 15 15 #include <linux/gpio.h> 16 + #include <linux/gpio/machine.h> 16 17 #include <linux/init.h> 17 18 #include <linux/platform_device.h> 18 19 #include <linux/syscore_ops.h> ··· 122 121 /* GPIO */ 123 122 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, 124 123 }; 125 - 126 - static unsigned long mainstone_irq_enabled; 127 - 128 - static void mainstone_mask_irq(struct irq_data *d) 129 - { 130 - int mainstone_irq = (d->irq - MAINSTONE_IRQ(0)); 131 - MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq)); 132 - } 133 - 134 - static void mainstone_unmask_irq(struct irq_data *d) 135 - { 136 - int mainstone_irq = (d->irq - MAINSTONE_IRQ(0)); 137 - /* the irq can be acknowledged only if deasserted, so it's done here */ 138 - MST_INTSETCLR &= ~(1 << mainstone_irq); 139 - MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq)); 140 - } 141 - 142 - static struct irq_chip mainstone_irq_chip = { 143 - .name = "FPGA", 144 - .irq_ack = mainstone_mask_irq, 145 - .irq_mask = mainstone_mask_irq, 146 - .irq_unmask = mainstone_unmask_irq, 147 - }; 148 - 149 - static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc) 150 - { 151 - unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled; 152 - do { 153 - /* clear useless edge notification */ 154 - desc->irq_data.chip->irq_ack(&desc->irq_data); 155 - if (likely(pending)) { 156 - irq = MAINSTONE_IRQ(0) + __ffs(pending); 157 - generic_handle_irq(irq); 158 - } 159 - pending = MST_INTSETCLR & mainstone_irq_enabled; 160 - } while (pending); 161 - } 162 - 163 - static void __init mainstone_init_irq(void) 164 - { 165 - int irq; 166 - 167 - pxa27x_init_irq(); 168 - 169 - /* setup extra Mainstone irqs */ 170 - for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { 171 - irq_set_chip_and_handler(irq, &mainstone_irq_chip, 172 - handle_level_irq); 173 - if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) 174 - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); 175 - else 176 - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 177 - } 178 - set_irq_flags(MAINSTONE_IRQ(8), 0); 179 - set_irq_flags(MAINSTONE_IRQ(12), 0); 180 - 181 - MST_INTMSKENA = 0; 182 - MST_INTSETCLR = 0; 183 - 184 - irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), mainstone_irq_handler); 185 - irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING); 186 - } 187 - 188 - #ifdef CONFIG_PM 189 - 190 - static void mainstone_irq_resume(void) 191 - { 192 - MST_INTMSKENA = mainstone_irq_enabled; 193 - } 194 - 195 - static struct syscore_ops mainstone_irq_syscore_ops = { 196 - .resume = mainstone_irq_resume, 197 - }; 198 - 199 - static int __init mainstone_irq_device_init(void) 200 - { 201 - if (machine_is_mainstone()) 202 - register_syscore_ops(&mainstone_irq_syscore_ops); 203 - 204 - return 0; 205 - } 206 - 207 - device_initcall(mainstone_irq_device_init); 208 - 209 - #endif 210 - 211 124 212 125 static struct resource smc91x_resources[] = { 213 126 [0] = { ··· 402 487 }, 403 488 }; 404 489 490 + static struct resource mst_cplds_resources[] = { 491 + [0] = { 492 + .start = MST_FPGA_PHYS + 0xc0, 493 + .end = MST_FPGA_PHYS + 0xe0 - 1, 494 + .flags = IORESOURCE_MEM, 495 + }, 496 + [1] = { 497 + .start = PXA_GPIO_TO_IRQ(0), 498 + .end = PXA_GPIO_TO_IRQ(0), 499 + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, 500 + }, 501 + [2] = { 502 + .start = MAINSTONE_IRQ(0), 503 + .end = MAINSTONE_IRQ(15), 504 + .flags = IORESOURCE_IRQ, 505 + }, 506 + }; 507 + 508 + static struct platform_device mst_cplds_device = { 509 + .name = "pxa_cplds_irqs", 510 + .id = -1, 511 + .resource = &mst_cplds_resources[0], 512 + .num_resources = 3, 513 + }; 514 + 405 515 static struct platform_device *platform_devices[] __initdata = { 406 516 &smc91x_device, 407 517 &mst_flash_device[0], 408 518 &mst_flash_device[1], 409 519 &mst_gpio_keys_device, 520 + &mst_cplds_device, 410 521 }; 411 522 412 523 static struct pxaohci_platform_data mainstone_ohci_platform_data = { ··· 659 718 .atag_offset = 0x100, /* BLOB boot parameter setting */ 660 719 .map_io = mainstone_map_io, 661 720 .nr_irqs = MAINSTONE_NR_IRQS, 662 - .init_irq = mainstone_init_irq, 721 + .init_irq = pxa27x_init_irq, 663 722 .handle_irq = pxa27x_handle_irq, 664 723 .init_time = pxa_timer_init, 665 724 .init_machine = mainstone_init,
+200
arch/arm/mach-pxa/pxa_cplds_irqs.c
··· 1 + /* 2 + * Intel Reference Systems cplds 3 + * 4 + * Copyright (C) 2014 Robert Jarzmik 5 + * 6 + * This program is free software; you can redistribute it and/or modify 7 + * it under the terms of the GNU General Public License as published by 8 + * the Free Software Foundation; either version 2 of the License, or 9 + * (at your option) any later version. 10 + * 11 + * Cplds motherboard driver, supporting lubbock and mainstone SoC board. 12 + */ 13 + 14 + #include <linux/bitops.h> 15 + #include <linux/gpio.h> 16 + #include <linux/gpio/consumer.h> 17 + #include <linux/interrupt.h> 18 + #include <linux/io.h> 19 + #include <linux/irq.h> 20 + #include <linux/irqdomain.h> 21 + #include <linux/mfd/core.h> 22 + #include <linux/module.h> 23 + #include <linux/of_platform.h> 24 + 25 + #define FPGA_IRQ_MASK_EN 0x0 26 + #define FPGA_IRQ_SET_CLR 0x10 27 + 28 + #define CPLDS_NB_IRQ 32 29 + 30 + struct cplds { 31 + void __iomem *base; 32 + int irq; 33 + unsigned int irq_mask; 34 + struct gpio_desc *gpio0; 35 + struct irq_domain *irqdomain; 36 + }; 37 + 38 + static irqreturn_t cplds_irq_handler(int in_irq, void *d) 39 + { 40 + struct cplds *fpga = d; 41 + unsigned long pending; 42 + unsigned int bit; 43 + 44 + pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask; 45 + for_each_set_bit(bit, &pending, CPLDS_NB_IRQ) 46 + generic_handle_irq(irq_find_mapping(fpga->irqdomain, bit)); 47 + 48 + return IRQ_HANDLED; 49 + } 50 + 51 + static void cplds_irq_mask_ack(struct irq_data *d) 52 + { 53 + struct cplds *fpga = irq_data_get_irq_chip_data(d); 54 + unsigned int cplds_irq = irqd_to_hwirq(d); 55 + unsigned int set, bit = BIT(cplds_irq); 56 + 57 + fpga->irq_mask &= ~bit; 58 + writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); 59 + set = readl(fpga->base + FPGA_IRQ_SET_CLR); 60 + writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR); 61 + } 62 + 63 + static void cplds_irq_unmask(struct irq_data *d) 64 + { 65 + struct cplds *fpga = irq_data_get_irq_chip_data(d); 66 + unsigned int cplds_irq = irqd_to_hwirq(d); 67 + unsigned int bit = BIT(cplds_irq); 68 + 69 + fpga->irq_mask |= bit; 70 + writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); 71 + } 72 + 73 + static struct irq_chip cplds_irq_chip = { 74 + .name = "pxa_cplds", 75 + .irq_mask_ack = cplds_irq_mask_ack, 76 + .irq_unmask = cplds_irq_unmask, 77 + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE, 78 + }; 79 + 80 + static int cplds_irq_domain_map(struct irq_domain *d, unsigned int irq, 81 + irq_hw_number_t hwirq) 82 + { 83 + struct cplds *fpga = d->host_data; 84 + 85 + irq_set_chip_and_handler(irq, &cplds_irq_chip, handle_level_irq); 86 + irq_set_chip_data(irq, fpga); 87 + 88 + return 0; 89 + } 90 + 91 + static const struct irq_domain_ops cplds_irq_domain_ops = { 92 + .xlate = irq_domain_xlate_twocell, 93 + .map = cplds_irq_domain_map, 94 + }; 95 + 96 + static int cplds_resume(struct platform_device *pdev) 97 + { 98 + struct cplds *fpga = platform_get_drvdata(pdev); 99 + 100 + writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); 101 + 102 + return 0; 103 + } 104 + 105 + static int cplds_probe(struct platform_device *pdev) 106 + { 107 + struct resource *res; 108 + struct cplds *fpga; 109 + int ret; 110 + unsigned int base_irq = 0; 111 + unsigned long irqflags = 0; 112 + 113 + fpga = devm_kzalloc(&pdev->dev, sizeof(*fpga), GFP_KERNEL); 114 + if (!fpga) 115 + return -ENOMEM; 116 + 117 + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 118 + if (res) { 119 + fpga->irq = (unsigned int)res->start; 120 + irqflags = res->flags; 121 + } 122 + if (!fpga->irq) 123 + return -ENODEV; 124 + 125 + base_irq = platform_get_irq(pdev, 1); 126 + if (base_irq < 0) 127 + base_irq = 0; 128 + 129 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 130 + fpga->base = devm_ioremap_resource(&pdev->dev, res); 131 + if (IS_ERR(fpga->base)) 132 + return PTR_ERR(fpga->base); 133 + 134 + platform_set_drvdata(pdev, fpga); 135 + 136 + writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); 137 + writel(0, fpga->base + FPGA_IRQ_SET_CLR); 138 + 139 + ret = devm_request_irq(&pdev->dev, fpga->irq, cplds_irq_handler, 140 + irqflags, dev_name(&pdev->dev), fpga); 141 + if (ret == -ENOSYS) 142 + return -EPROBE_DEFER; 143 + 144 + if (ret) { 145 + dev_err(&pdev->dev, "couldn't request main irq%d: %d\n", 146 + fpga->irq, ret); 147 + return ret; 148 + } 149 + 150 + irq_set_irq_wake(fpga->irq, 1); 151 + fpga->irqdomain = irq_domain_add_linear(pdev->dev.of_node, 152 + CPLDS_NB_IRQ, 153 + &cplds_irq_domain_ops, fpga); 154 + if (!fpga->irqdomain) 155 + return -ENODEV; 156 + 157 + if (base_irq) { 158 + ret = irq_create_strict_mappings(fpga->irqdomain, base_irq, 0, 159 + CPLDS_NB_IRQ); 160 + if (ret) { 161 + dev_err(&pdev->dev, "couldn't create the irq mapping %d..%d\n", 162 + base_irq, base_irq + CPLDS_NB_IRQ); 163 + return ret; 164 + } 165 + } 166 + 167 + return 0; 168 + } 169 + 170 + static int cplds_remove(struct platform_device *pdev) 171 + { 172 + struct cplds *fpga = platform_get_drvdata(pdev); 173 + 174 + irq_set_chip_and_handler(fpga->irq, NULL, NULL); 175 + 176 + return 0; 177 + } 178 + 179 + static const struct of_device_id cplds_id_table[] = { 180 + { .compatible = "intel,lubbock-cplds-irqs", }, 181 + { .compatible = "intel,mainstone-cplds-irqs", }, 182 + { } 183 + }; 184 + MODULE_DEVICE_TABLE(of, cplds_id_table); 185 + 186 + static struct platform_driver cplds_driver = { 187 + .driver = { 188 + .name = "pxa_cplds_irqs", 189 + .of_match_table = of_match_ptr(cplds_id_table), 190 + }, 191 + .probe = cplds_probe, 192 + .remove = cplds_remove, 193 + .resume = cplds_resume, 194 + }; 195 + 196 + module_platform_driver(cplds_driver); 197 + 198 + MODULE_DESCRIPTION("PXA Cplds interrupts driver"); 199 + MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>"); 200 + MODULE_LICENSE("GPL");
+33
arch/arm/mach-rockchip/pm.c
··· 44 44 static phys_addr_t rk3288_bootram_phy; 45 45 46 46 static struct regmap *pmu_regmap; 47 + static struct regmap *grf_regmap; 47 48 static struct regmap *sgrf_regmap; 48 49 49 50 static u32 rk3288_pmu_pwr_mode_con; 51 + static u32 rk3288_grf_soc_con0; 50 52 static u32 rk3288_sgrf_soc_con0; 51 53 52 54 static inline u32 rk3288_l2_config(void) ··· 72 70 { 73 71 u32 mode_set, mode_set1; 74 72 73 + regmap_read(grf_regmap, RK3288_GRF_SOC_CON0, &rk3288_grf_soc_con0); 74 + 75 75 regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); 76 76 77 77 regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON, 78 78 &rk3288_pmu_pwr_mode_con); 79 + 80 + /* 81 + * We need set this bit GRF_FORCE_JTAG here, for the debug module, 82 + * otherwise, it may become inaccessible after resume. 83 + * This creates a potential security issue, as the sdmmc pins may 84 + * accept jtag data for a short time during resume if no card is 85 + * inserted. 86 + * But this is of course also true for the regular boot, before we 87 + * turn of the jtag/sdmmc autodetect. 88 + */ 89 + regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, GRF_FORCE_JTAG | 90 + GRF_FORCE_JTAG_WRITE); 79 91 80 92 /* 81 93 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR ··· 98 82 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, 99 83 SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN 100 84 | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE); 85 + 86 + /* 87 + * The dapswjdp can not auto reset before resume, that cause it may 88 + * access some illegal address during resume. Let's disable it before 89 + * suspend, and the MASKROM will enable it back. 90 + */ 91 + regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE); 101 92 102 93 /* booting address of resuming system is from this register value */ 103 94 regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR, ··· 151 128 regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0, 152 129 rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE 153 130 | SGRF_FAST_BOOT_EN_WRITE); 131 + 132 + regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, rk3288_grf_soc_con0 | 133 + GRF_FORCE_JTAG_WRITE); 154 134 } 155 135 156 136 static int rockchip_lpmode_enter(unsigned long arg) ··· 209 183 "rockchip,rk3288-sgrf"); 210 184 if (IS_ERR(sgrf_regmap)) { 211 185 pr_err("%s: could not find sgrf regmap\n", __func__); 186 + return PTR_ERR(pmu_regmap); 187 + } 188 + 189 + grf_regmap = syscon_regmap_lookup_by_compatible( 190 + "rockchip,rk3288-grf"); 191 + if (IS_ERR(grf_regmap)) { 192 + pr_err("%s: could not find grf regmap\n", __func__); 212 193 return PTR_ERR(pmu_regmap); 213 194 } 214 195
+8
arch/arm/mach-rockchip/pm.h
··· 48 48 #define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44 49 49 #define RK3288_PMU_PWRMODE_CON1 0x90 50 50 51 + #define RK3288_GRF_SOC_CON0 0x244 52 + #define GRF_FORCE_JTAG BIT(12) 53 + #define GRF_FORCE_JTAG_WRITE BIT(28) 54 + 51 55 #define RK3288_SGRF_SOC_CON0 (0x0000) 52 56 #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120) 53 57 #define SGRF_PCLK_WDT_GATE BIT(6) 54 58 #define SGRF_PCLK_WDT_GATE_WRITE BIT(22) 55 59 #define SGRF_FAST_BOOT_EN BIT(8) 56 60 #define SGRF_FAST_BOOT_EN_WRITE BIT(24) 61 + 62 + #define RK3288_SGRF_CPU_CON0 (0x40) 63 + #define SGRF_DAPDEVICEEN BIT(0) 64 + #define SGRF_DAPDEVICEEN_WRITE BIT(16) 57 65 58 66 #define RK3288_CRU_MODE_CON 0x50 59 67 #define RK3288_CRU_SEL0_CON 0x60
+19
arch/arm/mach-rockchip/rockchip.c
··· 30 30 #include "pm.h" 31 31 32 32 #define RK3288_GRF_SOC_CON0 0x244 33 + #define RK3288_TIMER6_7_PHYS 0xff810000 33 34 34 35 static void __init rockchip_timer_init(void) 35 36 { 36 37 if (of_machine_is_compatible("rockchip,rk3288")) { 37 38 struct regmap *grf; 39 + void __iomem *reg_base; 40 + 41 + /* 42 + * Most/all uboot versions for rk3288 don't enable timer7 43 + * which is needed for the architected timer to work. 44 + * So make sure it is running during early boot. 45 + */ 46 + reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); 47 + if (reg_base) { 48 + writel(0, reg_base + 0x30); 49 + writel(0xffffffff, reg_base + 0x20); 50 + writel(0xffffffff, reg_base + 0x24); 51 + writel(1, reg_base + 0x30); 52 + dsb(); 53 + iounmap(reg_base); 54 + } else { 55 + pr_err("rockchip: could not map timer7 registers\n"); 56 + } 38 57 39 58 /* 40 59 * Disable auto jtag/sdmmc switching that causes issues
+1 -1
drivers/bus/arm-cci.c
··· 660 660 * Initialise the fake PMU. We only need to populate the 661 661 * used_mask for the purposes of validation. 662 662 */ 663 - .used_mask = CPU_BITS_NONE, 663 + .used_mask = { 0 }, 664 664 }; 665 665 666 666 if (!validate_event(event->pmu, &fake_pmu, leader))
+3 -2
drivers/bus/omap_l3_noc.c
··· 1 1 /* 2 2 * OMAP L3 Interconnect error handling driver 3 3 * 4 - * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/ 4 + * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/ 5 5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 6 * Sricharan <r.sricharan@ti.com> 7 7 * ··· 233 233 } 234 234 235 235 static const struct of_device_id l3_noc_match[] = { 236 - {.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data}, 236 + {.compatible = "ti,omap4-l3-noc", .data = &omap4_l3_data}, 237 + {.compatible = "ti,omap5-l3-noc", .data = &omap5_l3_data}, 237 238 {.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data}, 238 239 {.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data}, 239 240 {},
+40 -14
drivers/bus/omap_l3_noc.h
··· 1 1 /* 2 2 * OMAP L3 Interconnect error handling driver header 3 3 * 4 - * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/ 4 + * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/ 5 5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 6 * sricharan <r.sricharan@ti.com> 7 7 * ··· 175 175 }; 176 176 177 177 178 - static struct l3_target_data omap_l3_target_data_clk3[] = { 179 - {0x0100, "EMUSS",}, 180 - {0x0300, "DEBUG SOURCE",}, 181 - {0x0, "HOST CLK3",}, 178 + static struct l3_target_data omap4_l3_target_data_clk3[] = { 179 + {0x0100, "DEBUGSS",}, 182 180 }; 183 181 184 - static struct l3_flagmux_data omap_l3_flagmux_clk3 = { 182 + static struct l3_flagmux_data omap4_l3_flagmux_clk3 = { 185 183 .offset = 0x0200, 186 - .l3_targ = omap_l3_target_data_clk3, 187 - .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3), 184 + .l3_targ = omap4_l3_target_data_clk3, 185 + .num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3), 188 186 }; 189 187 190 188 static struct l3_masters_data omap_l3_masters[] = { ··· 213 215 { 0x32, "USBHOSTFS"} 214 216 }; 215 217 216 - static struct l3_flagmux_data *omap_l3_flagmux[] = { 218 + static struct l3_flagmux_data *omap4_l3_flagmux[] = { 217 219 &omap_l3_flagmux_clk1, 218 220 &omap_l3_flagmux_clk2, 219 - &omap_l3_flagmux_clk3, 221 + &omap4_l3_flagmux_clk3, 220 222 }; 221 223 222 - static const struct omap_l3 omap_l3_data = { 223 - .l3_flagmux = omap_l3_flagmux, 224 - .num_modules = ARRAY_SIZE(omap_l3_flagmux), 224 + static const struct omap_l3 omap4_l3_data = { 225 + .l3_flagmux = omap4_l3_flagmux, 226 + .num_modules = ARRAY_SIZE(omap4_l3_flagmux), 225 227 .l3_masters = omap_l3_masters, 226 228 .num_masters = ARRAY_SIZE(omap_l3_masters), 227 229 /* The 6 MSBs of register field used to distinguish initiator */ 228 230 .mst_addr_mask = 0xFC, 231 + }; 232 + 233 + /* OMAP5 data */ 234 + static struct l3_target_data omap5_l3_target_data_clk3[] = { 235 + {0x0100, "L3INSTR",}, 236 + {0x0300, "DEBUGSS",}, 237 + {0x0, "HOSTCLK3",}, 238 + }; 239 + 240 + static struct l3_flagmux_data omap5_l3_flagmux_clk3 = { 241 + .offset = 0x0200, 242 + .l3_targ = omap5_l3_target_data_clk3, 243 + .num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3), 244 + }; 245 + 246 + static struct l3_flagmux_data *omap5_l3_flagmux[] = { 247 + &omap_l3_flagmux_clk1, 248 + &omap_l3_flagmux_clk2, 249 + &omap5_l3_flagmux_clk3, 250 + }; 251 + 252 + static const struct omap_l3 omap5_l3_data = { 253 + .l3_flagmux = omap5_l3_flagmux, 254 + .num_modules = ARRAY_SIZE(omap5_l3_flagmux), 255 + .l3_masters = omap_l3_masters, 256 + .num_masters = ARRAY_SIZE(omap_l3_masters), 257 + /* The 6 MSBs of register field used to distinguish initiator */ 258 + .mst_addr_mask = 0x7E0, 229 259 }; 230 260 231 261 /* DRA7 data */ ··· 300 274 301 275 static struct l3_target_data dra_l3_target_data_clk2[] = { 302 276 {0x0, "HOST CLK1",}, 303 - {0x0, "HOST CLK2",}, 277 + {0x800000, "HOST CLK2",}, 304 278 {0xdead, L3_TARGET_NOT_SUPPORTED,}, 305 279 {0x3400, "SHA2_2",}, 306 280 {0x0900, "BB2D",},