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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: mediatek: Add MT8196 I2C clock support
Add support for the MT8196 I2C clock controller, which provides clock
gate control for I2C.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Laura Nao
and committed by
Stephen Boyd
8f61d9d3
c9b9a66b
+126
+7
drivers/clk/mediatek/Kconfig
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drivers/clk/mediatek/Kconfig
···
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help
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This driver supports MediaTek MT8196 basic clocks.
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config COMMON_CLK_MT8196_IMP_IIC_WRAP
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tristate "Clock driver for MediaTek MT8196 imp_iic_wrap"
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depends on COMMON_CLK_MT8196
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default COMMON_CLK_MT8196
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help
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This driver supports MediaTek MT8196 i2c clocks.
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config COMMON_CLK_MT8196_PEXTPSYS
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tristate "Clock driver for MediaTek MT8196 pextpsys"
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depends on COMMON_CLK_MT8196
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drivers/clk/mediatek/Makefile
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drivers/clk/mediatek/Makefile
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obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \
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clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
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clk-mt8196-peri_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
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obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
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obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
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drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
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drivers/clk/mediatek/clk-mt8196-imp_iic_wrap.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Guangjie Song <guangjie.song@mediatek.com>
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* Copyright (c) 2025 Collabora Ltd.
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* Laura Nao <laura.nao@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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+
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static const struct mtk_gate_regs imp_cg_regs = {
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.set_ofs = 0xe08,
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.clr_ofs = 0xe04,
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.sta_ofs = 0xe00,
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};
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#define GATE_IMP(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &imp_cg_regs, \
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.shift = _shift, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate impc_clks[] = {
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GATE_IMP(CLK_IMPC_I2C11, "impc_i2c11", "i2c_p", 0),
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GATE_IMP(CLK_IMPC_I2C12, "impc_i2c12", "i2c_p", 1),
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GATE_IMP(CLK_IMPC_I2C13, "impc_i2c13", "i2c_p", 2),
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GATE_IMP(CLK_IMPC_I2C14, "impc_i2c14", "i2c_p", 3),
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};
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static const struct mtk_clk_desc impc_mcd = {
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.clks = impc_clks,
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.num_clks = ARRAY_SIZE(impc_clks),
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};
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static const struct mtk_gate impe_clks[] = {
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GATE_IMP(CLK_IMPE_I2C5, "impe_i2c5", "i2c_east", 0),
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};
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static const struct mtk_clk_desc impe_mcd = {
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.clks = impe_clks,
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.num_clks = ARRAY_SIZE(impe_clks),
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};
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static const struct mtk_gate_regs impn_hwv_regs = {
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.set_ofs = 0x0000,
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.clr_ofs = 0x0004,
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.sta_ofs = 0x2c00,
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};
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#define GATE_HWV_IMPN(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &imp_cg_regs, \
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.hwv_regs = &impn_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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static const struct mtk_gate impn_clks[] = {
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GATE_IMP(CLK_IMPN_I2C1, "impn_i2c1", "i2c_north", 0),
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GATE_IMP(CLK_IMPN_I2C2, "impn_i2c2", "i2c_north", 1),
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GATE_IMP(CLK_IMPN_I2C4, "impn_i2c4", "i2c_north", 2),
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GATE_HWV_IMPN(CLK_IMPN_I2C7, "impn_i2c7", "i2c_north", 3),
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GATE_IMP(CLK_IMPN_I2C8, "impn_i2c8", "i2c_north", 4),
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GATE_IMP(CLK_IMPN_I2C9, "impn_i2c9", "i2c_north", 5),
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};
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static const struct mtk_clk_desc impn_mcd = {
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.clks = impn_clks,
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.num_clks = ARRAY_SIZE(impn_clks),
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};
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static const struct mtk_gate impw_clks[] = {
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GATE_IMP(CLK_IMPW_I2C0, "impw_i2c0", "i2c_west", 0),
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GATE_IMP(CLK_IMPW_I2C3, "impw_i2c3", "i2c_west", 1),
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GATE_IMP(CLK_IMPW_I2C6, "impw_i2c6", "i2c_west", 2),
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GATE_IMP(CLK_IMPW_I2C10, "impw_i2c10", "i2c_west", 3),
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};
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static const struct mtk_clk_desc impw_mcd = {
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.clks = impw_clks,
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.num_clks = ARRAY_SIZE(impw_clks),
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};
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static const struct of_device_id of_match_clk_mt8196_imp_iic_wrap[] = {
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{ .compatible = "mediatek,mt8196-imp-iic-wrap-c", .data = &impc_mcd },
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{ .compatible = "mediatek,mt8196-imp-iic-wrap-e", .data = &impe_mcd },
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{ .compatible = "mediatek,mt8196-imp-iic-wrap-n", .data = &impn_mcd },
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{ .compatible = "mediatek,mt8196-imp-iic-wrap-w", .data = &impw_mcd },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_imp_iic_wrap);
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static struct platform_driver clk_mt8196_imp_iic_wrap_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8196-imp_iic_wrap",
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.of_match_table = of_match_clk_mt8196_imp_iic_wrap,
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},
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};
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module_platform_driver(clk_mt8196_imp_iic_wrap_drv);
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MODULE_DESCRIPTION("MediaTek MT8196 I2C Wrapper clocks driver");
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MODULE_LICENSE("GPL");