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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
clk: qcom: gcc-msm8939: Add missing CSI2 related clocks
When adding in the indexes for this clock-controller we missed
GCC_CAMSS_CSI2_AHB_CLK, GCC_CAMSS_CSI2_CLK, GCC_CAMSS_CSI2PHY_CLK,
GCC_CAMSS_CSI2PIX_CLK and GCC_CAMSS_CSI2RDI_CLK.
Add them in now and rename ftbl_gcc_camss_csi0_1_clk
to account for csi2 also using it.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Link: https://lore.kernel.org/r/20231029061948.505883-2-vincent.knecht@mailoo.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Vincent Knecht
and committed by
Bjorn Andersson
8f799d30
3f373de6
+107
-3
+107
-3
drivers/clk/qcom/gcc-msm8939.c
+107
-3
drivers/clk/qcom/gcc-msm8939.c
···
696
696
},
697
697
};
698
698
699
-
static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
699
+
static const struct freq_tbl ftbl_gcc_camss_csi0_1_2_clk[] = {
700
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F(100000000, P_GPLL0, 8, 0, 0),
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701
F(200000000, P_GPLL0, 4, 0, 0),
702
702
{ }
···
706
706
.cmd_rcgr = 0x4e020,
707
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.hid_width = 5,
708
708
.parent_map = gcc_xo_gpll0_map,
709
-
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
709
+
.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
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.clkr.hw.init = &(struct clk_init_data){
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711
.name = "csi0_clk_src",
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.parent_data = gcc_xo_gpll0_parent_data,
···
719
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.cmd_rcgr = 0x4f020,
720
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.hid_width = 5,
721
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.parent_map = gcc_xo_gpll0_map,
722
-
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
722
+
.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "csi1_clk_src",
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+
.parent_data = gcc_xo_gpll0_parent_data,
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+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
727
+
.ops = &clk_rcg2_ops,
728
+
},
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+
};
730
+
731
+
static struct clk_rcg2 csi2_clk_src = {
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+
.cmd_rcgr = 0x3c020,
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+
.hid_width = 5,
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+
.parent_map = gcc_xo_gpll0_map,
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+
.freq_tbl = ftbl_gcc_camss_csi0_1_2_clk,
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+
.clkr.hw.init = &(struct clk_init_data){
737
+
.name = "csi2_clk_src",
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738
.parent_data = gcc_xo_gpll0_parent_data,
726
739
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_parent_data),
727
740
.ops = &clk_rcg2_ops,
···
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2385
},
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};
2400
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+
static struct clk_branch gcc_camss_csi2_ahb_clk = {
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+
.halt_reg = 0x3c040,
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+
.clkr = {
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+
.enable_reg = 0x3c040,
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+
.enable_mask = BIT(0),
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+
.hw.init = &(struct clk_init_data){
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+
.name = "gcc_camss_csi2_ahb_clk",
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+
.parent_hws = (const struct clk_hw*[]){
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+
&camss_ahb_clk_src.clkr.hw,
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+
},
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+
.num_parents = 1,
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+
.flags = CLK_SET_RATE_PARENT,
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+
.ops = &clk_branch2_ops,
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+
},
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+
},
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+
};
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+
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+
static struct clk_branch gcc_camss_csi2_clk = {
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+
.halt_reg = 0x3c03c,
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+
.clkr = {
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+
.enable_reg = 0x3c03c,
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+
.enable_mask = BIT(0),
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+
.hw.init = &(struct clk_init_data){
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+
.name = "gcc_camss_csi2_clk",
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+
.parent_hws = (const struct clk_hw*[]){
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+
&csi2_clk_src.clkr.hw,
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+
},
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+
.num_parents = 1,
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+
.flags = CLK_SET_RATE_PARENT,
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+
.ops = &clk_branch2_ops,
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+
},
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+
},
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+
};
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+
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+
static struct clk_branch gcc_camss_csi2phy_clk = {
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+
.halt_reg = 0x3c048,
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+
.clkr = {
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+
.enable_reg = 0x3c048,
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+
.enable_mask = BIT(0),
2427
+
.hw.init = &(struct clk_init_data){
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+
.name = "gcc_camss_csi2phy_clk",
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+
.parent_hws = (const struct clk_hw*[]){
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+
&csi2_clk_src.clkr.hw,
2431
+
},
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+
.num_parents = 1,
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+
.flags = CLK_SET_RATE_PARENT,
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+
.ops = &clk_branch2_ops,
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+
},
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+
},
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+
};
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+
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+
static struct clk_branch gcc_camss_csi2pix_clk = {
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+
.halt_reg = 0x3c058,
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+
.clkr = {
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+
.enable_reg = 0x3c058,
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+
.enable_mask = BIT(0),
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+
.hw.init = &(struct clk_init_data){
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+
.name = "gcc_camss_csi2pix_clk",
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+
.parent_hws = (const struct clk_hw*[]){
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+
&csi2_clk_src.clkr.hw,
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+
},
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+
.num_parents = 1,
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+
.flags = CLK_SET_RATE_PARENT,
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+
.ops = &clk_branch2_ops,
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+
},
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+
},
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+
};
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+
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+
static struct clk_branch gcc_camss_csi2rdi_clk = {
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+
.halt_reg = 0x3c050,
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+
.clkr = {
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+
.enable_reg = 0x3c050,
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+
.enable_mask = BIT(0),
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+
.hw.init = &(struct clk_init_data){
2462
+
.name = "gcc_camss_csi2rdi_clk",
2463
+
.parent_hws = (const struct clk_hw*[]){
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+
&csi2_clk_src.clkr.hw,
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+
},
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+
.num_parents = 1,
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+
.flags = CLK_SET_RATE_PARENT,
2468
+
.ops = &clk_branch2_ops,
2469
+
},
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+
},
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+
};
2472
+
2401
2473
static struct clk_branch gcc_camss_csi_vfe0_clk = {
2402
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.halt_reg = 0x58050,
2403
2475
.clkr = {
···
3780
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[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
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[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
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[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
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+
[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
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3686
[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
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[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
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[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
···
3850
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[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3851
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[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
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[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3754
+
[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
3755
+
[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
3756
+
[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
3757
+
[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
3758
+
[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
3853
3759
[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3854
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[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
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[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,