Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: phy-rockchip-samsung-hdptx: Add eDP mode support for RK3588
The PHY is based on a Samsung IP block that supports HDMI 2.1, and eDP
1.4b. RK3588 integrates the Analogix eDP 1.3 TX controller IP and the
HDMI/eDP TX Combo PHY to support eDP display.
Add basic support for RBR/HBR/HBR2 link rates, and the voltage swing and
pre-emphasis configurations of each link rate are set according to the
eDP 1.3 requirements.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250205105157.580060-5-damon.ding@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Damon Ding
and committed by
Vinod Koul
8f831f27
2dc8224e
+869
-10
+869
-10
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+869
-10
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
···
25
25
#define HDPTX_I_PLL_EN BIT(7)
26
26
#define HDPTX_I_BIAS_EN BIT(6)
27
27
#define HDPTX_I_BGR_EN BIT(5)
28
+
#define HDPTX_MODE_SEL BIT(0)
28
29
#define GRF_HDPTX_STATUS 0x80
29
30
#define HDPTX_O_PLL_LOCK_DONE BIT(3)
30
31
#define HDPTX_O_PHY_CLK_RDY BIT(2)
···
45
44
#define LANE_REG(n) HDTPX_REG(n, 0300, 062d)
46
45
47
46
/* CMN_REG(0008) */
47
+
#define OVRD_LCPLL_EN_MASK BIT(7)
48
48
#define LCPLL_EN_MASK BIT(6)
49
49
#define LCPLL_LCVCO_MODE_EN_MASK BIT(4)
50
50
/* CMN_REG(001e) */
···
63
61
/* CMN_REG(002f) */
64
62
#define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2)
65
63
#define LCPLL_SDC_NDIV_RSTN_MASK BIT(0)
64
+
/* CMN_REG(003c) */
65
+
#define ANA_LCPLL_RESERVED7_MASK BIT(7)
66
66
/* CMN_REG(003d) */
67
+
#define OVRD_ROPLL_EN_MASK BIT(7)
68
+
#define ROPLL_EN_MASK BIT(6)
67
69
#define ROPLL_LCVCO_EN_MASK BIT(4)
70
+
/* CMN_REG(0046) */
71
+
#define ROPLL_ANA_CPP_CTRL_COARSE_MASK GENMASK(7, 4)
72
+
#define ROPLL_ANA_CPP_CTRL_FINE_MASK GENMASK(3, 0)
73
+
/* CMN_REG(0047) */
74
+
#define ROPLL_ANA_LPF_C_SEL_COARSE_MASK GENMASK(5, 3)
75
+
#define ROPLL_ANA_LPF_C_SEL_FINE_MASK GENMASK(2, 0)
68
76
/* CMN_REG(004e) */
69
77
#define ROPLL_PI_EN_MASK BIT(5)
78
+
/* CMN_REG(0051) */
79
+
#define ROPLL_PMS_MDIV_MASK GENMASK(7, 0)
80
+
/* CMN_REG(0055) */
81
+
#define ROPLL_PMS_MDIV_AFC_MASK GENMASK(7, 0)
82
+
/* CMN_REG(0059) */
83
+
#define ANA_ROPLL_PMS_PDIV_MASK GENMASK(7, 4)
84
+
#define ANA_ROPLL_PMS_REFDIV_MASK GENMASK(3, 0)
85
+
/* CMN_REG(005a) */
86
+
#define ROPLL_PMS_SDIV_RBR_MASK GENMASK(7, 4)
87
+
#define ROPLL_PMS_SDIV_HBR_MASK GENMASK(3, 0)
88
+
/* CMN_REG(005b) */
89
+
#define ROPLL_PMS_SDIV_HBR2_MASK GENMASK(7, 4)
70
90
/* CMN_REG(005c) */
71
91
#define ROPLL_PMS_IQDIV_RSTN_MASK BIT(5)
72
92
/* CMN_REG(005e) */
73
93
#define ROPLL_SDM_EN_MASK BIT(6)
94
+
#define OVRD_ROPLL_SDM_RSTN_MASK BIT(5)
95
+
#define ROPLL_SDM_RSTN_MASK BIT(4)
74
96
#define ROPLL_SDC_FRAC_EN_RBR_MASK BIT(3)
75
97
#define ROPLL_SDC_FRAC_EN_HBR_MASK BIT(2)
76
98
#define ROPLL_SDC_FRAC_EN_HBR2_MASK BIT(1)
77
99
#define ROPLL_SDM_FRAC_EN_HBR3_MASK BIT(0)
100
+
/* CMN_REG(005f) */
101
+
#define OVRD_ROPLL_SDC_RSTN_MASK BIT(5)
102
+
#define ROPLL_SDC_RSTN_MASK BIT(4)
103
+
/* CMN_REG(0060) */
104
+
#define ROPLL_SDM_DENOMINATOR_MASK GENMASK(7, 0)
78
105
/* CMN_REG(0064) */
79
106
#define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3)
107
+
#define ROPLL_SDM_NUM_SIGN_HBR_MASK BIT(2)
108
+
#define ROPLL_SDM_NUM_SIGN_HBR2_MASK BIT(1)
109
+
/* CMN_REG(0065) */
110
+
#define ROPLL_SDM_NUM_MASK GENMASK(7, 0)
80
111
/* CMN_REG(0069) */
81
112
#define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0)
113
+
/* CMN_REG(006a) */
114
+
#define ROPLL_SDC_N_HBR_MASK GENMASK(5, 3)
115
+
#define ROPLL_SDC_N_HBR2_MASK GENMASK(2, 0)
116
+
/* CMN_REG(006b) */
117
+
#define ROPLL_SDC_N_HBR3_MASK GENMASK(3, 1)
118
+
/* CMN_REG(006c) */
119
+
#define ROPLL_SDC_NUM_MASK GENMASK(5, 0)
120
+
/* cmn_reg0070 */
121
+
#define ROPLL_SDC_DENO_MASK GENMASK(5, 0)
82
122
/* CMN_REG(0074) */
123
+
#define OVRD_ROPLL_SDC_NDIV_RSTN_MASK BIT(3)
83
124
#define ROPLL_SDC_NDIV_RSTN_MASK BIT(2)
125
+
#define OVRD_ROPLL_SSC_EN_MASK BIT(1)
84
126
#define ROPLL_SSC_EN_MASK BIT(0)
127
+
/* CMN_REG(0075) */
128
+
#define ANA_ROPLL_SSC_FM_DEVIATION_MASK GENMASK(5, 0)
129
+
/* CMN_REG(0076) */
130
+
#define ANA_ROPLL_SSC_FM_FREQ_MASK GENMASK(6, 2)
131
+
/* CMN_REG(0077) */
132
+
#define ANA_ROPLL_SSC_CLK_DIV_SEL_MASK GENMASK(6, 3)
85
133
/* CMN_REG(0081) */
86
134
#define OVRD_PLL_CD_CLK_EN_MASK BIT(8)
135
+
#define ANA_PLL_CD_TX_SER_RATE_SEL_MASK BIT(3)
136
+
#define ANA_PLL_CD_HSCLK_WEST_EN_MASK BIT(1)
87
137
#define ANA_PLL_CD_HSCLK_EAST_EN_MASK BIT(0)
138
+
/* CMN_REG(0082) */
139
+
#define ANA_PLL_CD_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
140
+
/* CMN_REG(0083) */
141
+
#define ANA_PLL_CD_VREG_ICTRL_MASK GENMASK(6, 5)
142
+
/* CMN_REG(0084) */
143
+
#define PLL_LCRO_CLK_SEL_MASK BIT(5)
144
+
/* CMN_REG(0085) */
145
+
#define ANA_PLL_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0)
88
146
/* CMN_REG(0086) */
89
147
#define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)
90
148
#define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)
···
154
92
#define ANA_PLL_TX_HS_CLK_EN_MASK BIT(2)
155
93
/* CMN_REG(0089) */
156
94
#define LCPLL_ALONE_MODE_MASK BIT(1)
95
+
/* CMN_REG(0095) */
96
+
#define DP_TX_LINK_BW_MASK GENMASK(1, 0)
157
97
/* CMN_REG(0097) */
158
98
#define DIG_CLK_SEL_MASK BIT(1)
159
99
#define LCPLL_REF BIT(1)
160
100
#define ROPLL_REF 0
161
101
/* CMN_REG(0099) */
102
+
#define SSC_EN_MASK GENMASK(7, 6)
162
103
#define CMN_ROPLL_ALONE_MODE_MASK BIT(2)
163
104
#define ROPLL_ALONE_MODE BIT(2)
164
105
/* CMN_REG(009a) */
···
183
118
/* SB_REG(0104) */
184
119
#define OVRD_SB_EN_MASK BIT(5)
185
120
#define SB_EN_MASK BIT(4)
121
+
#define OVRD_SB_AUX_EN_MASK BIT(1)
122
+
#define SB_AUX_EN_MASK BIT(0)
186
123
/* SB_REG(0105) */
187
124
#define OVRD_SB_EARC_CMDC_EN_MASK BIT(6)
188
125
#define SB_EARC_CMDC_EN_MASK BIT(5)
···
193
126
#define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4)
194
127
/* SB_REG(0109) */
195
128
#define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0)
129
+
/* SB_REG(010d) */
130
+
#define ANA_SB_DMRX_LPBK_DATA_MASK BIT(4)
196
131
/* SB_REG(010f) */
197
132
#define OVRD_SB_VREG_EN_MASK BIT(7)
198
133
#define SB_VREG_EN_MASK BIT(6)
···
202
133
#define SB_VREG_LPF_BYPASS_MASK BIT(4)
203
134
#define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
204
135
/* SB_REG(0110) */
136
+
#define ANA_SB_VREG_OUT_SEL_MASK BIT(1)
205
137
#define ANA_SB_VREG_REF_SEL_MASK BIT(0)
206
138
/* SB_REG(0113) */
207
139
#define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4)
···
217
147
#define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4)
218
148
/* SB_REG(0117) */
219
149
#define FAST_PULSE_TIME_MASK GENMASK(3, 0)
150
+
/* SB_REG(0118) */
151
+
#define SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK GENMASK(7, 0)
152
+
/* SB_REG(011a) */
153
+
#define SB_TG_CNT_RUN_NO_7_0_MASK GENMASK(7, 0)
220
154
/* SB_REG(011b) */
221
155
#define SB_EARC_SIG_DET_BYPASS_MASK BIT(4)
222
156
#define SB_AFC_TOL_MASK GENMASK(3, 0)
157
+
/* SB_REG(011c) */
158
+
#define SB_AFC_STB_NUM_MASK GENMASK(3, 0)
159
+
/* SB_REG(011d) */
160
+
#define SB_TG_OSC_CNT_MIN_MASK GENMASK(7, 0)
161
+
/* SB_REG(011e) */
162
+
#define SB_TG_OSC_CNT_MAX_MASK GENMASK(7, 0)
223
163
/* SB_REG(011f) */
224
164
#define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2)
225
165
#define SB_RCAL_RSTN_MASK BIT(1)
226
166
/* SB_REG(0120) */
167
+
#define SB_AUX_EN_IN_MASK BIT(7)
227
168
#define SB_EARC_EN_MASK BIT(1)
228
169
#define SB_EARC_AFC_EN_MASK BIT(2)
229
170
/* SB_REG(0123) */
···
246
165
#define HDMI_MODE BIT(2)
247
166
#define HDMI_TMDS_FRL_SEL BIT(1)
248
167
/* LNTOP_REG(0206) */
168
+
#define DATA_BUS_WIDTH_MASK GENMASK(2, 1)
249
169
#define DATA_BUS_WIDTH_SEL_MASK BIT(0)
250
170
#define DATA_BUS_36_40 BIT(0)
251
171
/* LNTOP_REG(0207) */
252
172
#define LANE_EN_MASK 0xf
253
173
#define ALL_LANE_EN 0xf
254
174
175
+
/* LANE_REG(0301) */
176
+
#define OVRD_LN_TX_DRV_EI_EN_MASK BIT(7)
177
+
#define LN_TX_DRV_EI_EN_MASK BIT(6)
178
+
/* LANE_REG(0303) */
179
+
#define OVRD_LN_TX_DRV_LVL_CTRL_MASK BIT(5)
180
+
#define LN_TX_DRV_LVL_CTRL_MASK GENMASK(4, 0)
181
+
/* LANE_REG(0304) */
182
+
#define OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK BIT(4)
183
+
#define LN_TX_DRV_POST_LVL_CTRL_MASK GENMASK(3, 0)
184
+
/* LANE_REG(0305) */
185
+
#define OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK BIT(6)
186
+
#define LN_TX_DRV_PRE_LVL_CTRL_MASK GENMASK(5, 2)
187
+
/* LANE_REG(0306) */
188
+
#define LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK GENMASK(7, 5)
189
+
#define LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK GENMASK(4, 2)
190
+
#define LN_ANA_TX_DRV_ACCDRV_EN_MASK BIT(0)
191
+
/* LANE_REG(0307) */
192
+
#define LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK BIT(6)
193
+
#define LN_ANA_TX_DRV_ACCDRV_CTRL_MASK GENMASK(5, 3)
194
+
/* LANE_REG(030a) */
195
+
#define LN_ANA_TX_JEQ_EN_MASK BIT(4)
196
+
#define LN_TX_JEQ_EVEN_CTRL_RBR_MASK GENMASK(3, 0)
197
+
/* LANE_REG(030b) */
198
+
#define LN_TX_JEQ_EVEN_CTRL_HBR_MASK GENMASK(7, 4)
199
+
#define LN_TX_JEQ_EVEN_CTRL_HBR2_MASK GENMASK(3, 0)
200
+
/* LANE_REG(030c) */
201
+
#define LN_TX_JEQ_ODD_CTRL_RBR_MASK GENMASK(3, 0)
202
+
/* LANE_REG(030d) */
203
+
#define LN_TX_JEQ_ODD_CTRL_HBR_MASK GENMASK(7, 4)
204
+
#define LN_TX_JEQ_ODD_CTRL_HBR2_MASK GENMASK(3, 0)
205
+
/* LANE_REG(0310) */
206
+
#define LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0)
207
+
/* LANE_REG(0311) */
208
+
#define LN_TX_SER_40BIT_EN_RBR_MASK BIT(3)
209
+
#define LN_TX_SER_40BIT_EN_HBR_MASK BIT(2)
210
+
#define LN_TX_SER_40BIT_EN_HBR2_MASK BIT(1)
255
211
/* LANE_REG(0312) */
256
212
#define LN0_TX_SER_RATE_SEL_RBR_MASK BIT(5)
257
213
#define LN0_TX_SER_RATE_SEL_HBR_MASK BIT(4)
258
214
#define LN0_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
259
215
#define LN0_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
216
+
/* LANE_REG(0316) */
217
+
#define LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
218
+
/* LANE_REG(031B) */
219
+
#define LN_ANA_TX_RESERVED_MASK GENMASK(7, 0)
220
+
/* LANE_REG(031e) */
221
+
#define LN_POLARITY_INV_MASK BIT(2)
222
+
#define LN_LANE_MODE_MASK BIT(1)
223
+
260
224
/* LANE_REG(0412) */
261
225
#define LN1_TX_SER_RATE_SEL_RBR_MASK BIT(5)
262
226
#define LN1_TX_SER_RATE_SEL_HBR_MASK BIT(4)
263
227
#define LN1_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
264
228
#define LN1_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
229
+
265
230
/* LANE_REG(0512) */
266
231
#define LN2_TX_SER_RATE_SEL_RBR_MASK BIT(5)
267
232
#define LN2_TX_SER_RATE_SEL_HBR_MASK BIT(4)
268
233
#define LN2_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
269
234
#define LN2_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
235
+
270
236
/* LANE_REG(0612) */
271
237
#define LN3_TX_SER_RATE_SEL_RBR_MASK BIT(5)
272
238
#define LN3_TX_SER_RATE_SEL_HBR_MASK BIT(4)
···
321
193
#define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
322
194
323
195
#define HDMI20_MAX_RATE 600000000
196
+
197
+
enum dp_link_rate {
198
+
DP_BW_RBR,
199
+
DP_BW_HBR,
200
+
DP_BW_HBR2,
201
+
};
324
202
325
203
struct lcpll_config {
326
204
u32 bit_rate;
···
389
255
u8 cd_tx_ser_rate_sel;
390
256
};
391
257
258
+
struct tx_drv_ctrl {
259
+
u8 tx_drv_lvl_ctrl;
260
+
u8 tx_drv_post_lvl_ctrl;
261
+
u8 ana_tx_drv_idrv_idn_ctrl;
262
+
u8 ana_tx_drv_idrv_iup_ctrl;
263
+
u8 ana_tx_drv_accdrv_en;
264
+
u8 ana_tx_drv_accdrv_ctrl;
265
+
u8 tx_drv_pre_lvl_ctrl;
266
+
u8 ana_tx_jeq_en;
267
+
u8 tx_jeq_even_ctrl;
268
+
u8 tx_jeq_odd_ctrl;
269
+
};
270
+
392
271
enum rk_hdptx_reset {
393
272
RST_APB = 0,
394
273
RST_INIT,
···
437
290
unsigned long rate;
438
291
439
292
atomic_t usage_count;
293
+
294
+
/* used for dp mode */
295
+
unsigned int link_rate;
296
+
unsigned int lanes;
440
297
};
441
298
442
299
static const struct ropll_config ropll_tmds_cfg[] = {
···
717
566
REG_SEQ0(LANE_REG(0406), 0x1c),
718
567
REG_SEQ0(LANE_REG(0506), 0x1c),
719
568
REG_SEQ0(LANE_REG(0606), 0x1c),
569
+
};
570
+
571
+
static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = {
572
+
/* voltage swing 0, pre-emphasis 0->3 */
573
+
{
574
+
{ 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
575
+
{ 0x4, 0x3, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
576
+
{ 0x7, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
577
+
{ 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
578
+
},
579
+
580
+
/* voltage swing 1, pre-emphasis 0->2 */
581
+
{
582
+
{ 0x4, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
583
+
{ 0x9, 0x5, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
584
+
{ 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
585
+
},
586
+
587
+
/* voltage swing 2, pre-emphasis 0->1 */
588
+
{
589
+
{ 0x8, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
590
+
{ 0xc, 0x5, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
591
+
},
592
+
593
+
/* voltage swing 3, pre-emphasis 0 */
594
+
{
595
+
{ 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
596
+
}
597
+
};
598
+
599
+
static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = {
600
+
/* voltage swing 0, pre-emphasis 0->3 */
601
+
{
602
+
{ 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
603
+
{ 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
604
+
{ 0x9, 0x8, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
605
+
{ 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
606
+
},
607
+
608
+
/* voltage swing 1, pre-emphasis 0->2 */
609
+
{
610
+
{ 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
611
+
{ 0xa, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
612
+
{ 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
613
+
},
614
+
615
+
/* voltage swing 2, pre-emphasis 0->1 */
616
+
{
617
+
{ 0x9, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
618
+
{ 0xd, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
619
+
},
620
+
621
+
/* voltage swing 3, pre-emphasis 0 */
622
+
{
623
+
{ 0xc, 0x1, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
624
+
}
625
+
};
626
+
627
+
static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = {
628
+
/* voltage swing 0, pre-emphasis 0->3 */
629
+
{
630
+
{ 0x2, 0x1, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
631
+
{ 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
632
+
{ 0x9, 0x8, 0x4, 0x6, 0x1, 0x4, 0x0, 0x1, 0x7, 0x7 },
633
+
{ 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
634
+
},
635
+
636
+
/* voltage swing 1, pre-emphasis 0->2 */
637
+
{
638
+
{ 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
639
+
{ 0xb, 0x7, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
640
+
{ 0xd, 0x9, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
641
+
},
642
+
643
+
/* voltage swing 2, pre-emphasis 0->1 */
644
+
{
645
+
{ 0x8, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
646
+
{ 0xc, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
647
+
},
648
+
649
+
/* voltage swing 3, pre-emphasis 0 */
650
+
{
651
+
{ 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
652
+
}
720
653
};
721
654
722
655
static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg)
···
1089
854
return rk_hdptx_post_enable_lane(hdptx);
1090
855
}
1091
856
857
+
static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx)
858
+
{
859
+
reset_control_assert(hdptx->rsts[RST_LANE].rstc);
860
+
reset_control_assert(hdptx->rsts[RST_CMN].rstc);
861
+
reset_control_assert(hdptx->rsts[RST_INIT].rstc);
862
+
863
+
reset_control_assert(hdptx->rsts[RST_APB].rstc);
864
+
udelay(10);
865
+
reset_control_deassert(hdptx->rsts[RST_APB].rstc);
866
+
867
+
regmap_update_bits(hdptx->regmap, LANE_REG(0301),
868
+
OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
869
+
FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
870
+
FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
871
+
regmap_update_bits(hdptx->regmap, LANE_REG(0401),
872
+
OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
873
+
FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
874
+
FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
875
+
regmap_update_bits(hdptx->regmap, LANE_REG(0501),
876
+
OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
877
+
FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
878
+
FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
879
+
regmap_update_bits(hdptx->regmap, LANE_REG(0601),
880
+
OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
881
+
FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
882
+
FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
883
+
884
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
885
+
HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0));
886
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
887
+
HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x0));
888
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
889
+
HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0));
890
+
}
891
+
1092
892
static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
1093
893
unsigned int rate)
1094
894
{
895
+
enum phy_mode mode = phy_get_mode(hdptx->phy);
1095
896
u32 status;
1096
897
int ret;
1097
898
···
1141
870
if (status & HDPTX_O_PLL_LOCK_DONE)
1142
871
dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n");
1143
872
1144
-
if (rate) {
1145
-
ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
1146
-
if (ret)
1147
-
goto dec_usage;
873
+
if (mode == PHY_MODE_DP) {
874
+
rk_hdptx_dp_reset(hdptx);
875
+
} else {
876
+
if (rate) {
877
+
ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
878
+
if (ret)
879
+
goto dec_usage;
880
+
}
1148
881
}
1149
882
1150
883
return 0;
···
1160
885
1161
886
static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force)
1162
887
{
888
+
enum phy_mode mode = phy_get_mode(hdptx->phy);
1163
889
u32 status;
1164
890
int ret;
1165
891
···
1174
898
} else {
1175
899
ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
1176
900
if (!ret) {
1177
-
if (status & HDPTX_O_PLL_LOCK_DONE)
1178
-
rk_hdptx_phy_disable(hdptx);
901
+
if (status & HDPTX_O_PLL_LOCK_DONE) {
902
+
if (mode == PHY_MODE_DP)
903
+
rk_hdptx_dp_reset(hdptx);
904
+
else
905
+
rk_hdptx_phy_disable(hdptx);
906
+
}
1179
907
return 0;
1180
908
} else if (force) {
1181
909
return 0;
···
1190
910
return ret;
1191
911
}
1192
912
913
+
static void rk_hdptx_dp_pll_init(struct rk_hdptx_phy *hdptx)
914
+
{
915
+
regmap_update_bits(hdptx->regmap, CMN_REG(003c), ANA_LCPLL_RESERVED7_MASK,
916
+
FIELD_PREP(ANA_LCPLL_RESERVED7_MASK, 0x1));
917
+
918
+
regmap_update_bits(hdptx->regmap, CMN_REG(0046),
919
+
ROPLL_ANA_CPP_CTRL_COARSE_MASK | ROPLL_ANA_CPP_CTRL_FINE_MASK,
920
+
FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE_MASK, 0xe) |
921
+
FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE_MASK, 0xe));
922
+
regmap_update_bits(hdptx->regmap, CMN_REG(0047),
923
+
ROPLL_ANA_LPF_C_SEL_COARSE_MASK |
924
+
ROPLL_ANA_LPF_C_SEL_FINE_MASK,
925
+
FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE_MASK, 0x4) |
926
+
FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE_MASK, 0x4));
927
+
928
+
regmap_write(hdptx->regmap, CMN_REG(0051), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x87));
929
+
regmap_write(hdptx->regmap, CMN_REG(0052), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71));
930
+
regmap_write(hdptx->regmap, CMN_REG(0053), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71));
931
+
932
+
regmap_write(hdptx->regmap, CMN_REG(0055),
933
+
FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x87));
934
+
regmap_write(hdptx->regmap, CMN_REG(0056),
935
+
FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71));
936
+
regmap_write(hdptx->regmap, CMN_REG(0057),
937
+
FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71));
938
+
939
+
regmap_write(hdptx->regmap, CMN_REG(0059),
940
+
FIELD_PREP(ANA_ROPLL_PMS_PDIV_MASK, 0x1) |
941
+
FIELD_PREP(ANA_ROPLL_PMS_REFDIV_MASK, 0x1));
942
+
regmap_write(hdptx->regmap, CMN_REG(005a),
943
+
FIELD_PREP(ROPLL_PMS_SDIV_RBR_MASK, 0x3) |
944
+
FIELD_PREP(ROPLL_PMS_SDIV_HBR_MASK, 0x1));
945
+
regmap_update_bits(hdptx->regmap, CMN_REG(005b), ROPLL_PMS_SDIV_HBR2_MASK,
946
+
FIELD_PREP(ROPLL_PMS_SDIV_HBR2_MASK, 0x0));
947
+
948
+
regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK,
949
+
FIELD_PREP(ROPLL_SDM_EN_MASK, 0x1));
950
+
regmap_update_bits(hdptx->regmap, CMN_REG(005e),
951
+
OVRD_ROPLL_SDM_RSTN_MASK | ROPLL_SDM_RSTN_MASK,
952
+
FIELD_PREP(OVRD_ROPLL_SDM_RSTN_MASK, 0x1) |
953
+
FIELD_PREP(ROPLL_SDM_RSTN_MASK, 0x1));
954
+
regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_RBR_MASK,
955
+
FIELD_PREP(ROPLL_SDC_FRAC_EN_RBR_MASK, 0x1));
956
+
regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR_MASK,
957
+
FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR_MASK, 0x1));
958
+
regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR2_MASK,
959
+
FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR2_MASK, 0x1));
960
+
961
+
regmap_update_bits(hdptx->regmap, CMN_REG(005f),
962
+
OVRD_ROPLL_SDC_RSTN_MASK | ROPLL_SDC_RSTN_MASK,
963
+
FIELD_PREP(OVRD_ROPLL_SDC_RSTN_MASK, 0x1) |
964
+
FIELD_PREP(ROPLL_SDC_RSTN_MASK, 0x1));
965
+
regmap_write(hdptx->regmap, CMN_REG(0060),
966
+
FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x21));
967
+
regmap_write(hdptx->regmap, CMN_REG(0061),
968
+
FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27));
969
+
regmap_write(hdptx->regmap, CMN_REG(0062),
970
+
FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27));
971
+
972
+
regmap_update_bits(hdptx->regmap, CMN_REG(0064),
973
+
ROPLL_SDM_NUM_SIGN_RBR_MASK |
974
+
ROPLL_SDM_NUM_SIGN_HBR_MASK |
975
+
ROPLL_SDM_NUM_SIGN_HBR2_MASK,
976
+
FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, 0x0) |
977
+
FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR_MASK, 0x1) |
978
+
FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR2_MASK, 0x1));
979
+
regmap_write(hdptx->regmap, CMN_REG(0065),
980
+
FIELD_PREP(ROPLL_SDM_NUM_MASK, 0x0));
981
+
regmap_write(hdptx->regmap, CMN_REG(0066),
982
+
FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd));
983
+
regmap_write(hdptx->regmap, CMN_REG(0067),
984
+
FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd));
985
+
986
+
regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK,
987
+
FIELD_PREP(ROPLL_SDC_N_RBR_MASK, 0x2));
988
+
989
+
regmap_update_bits(hdptx->regmap, CMN_REG(006a),
990
+
ROPLL_SDC_N_HBR_MASK | ROPLL_SDC_N_HBR2_MASK,
991
+
FIELD_PREP(ROPLL_SDC_N_HBR_MASK, 0x1) |
992
+
FIELD_PREP(ROPLL_SDC_N_HBR2_MASK, 0x1));
993
+
994
+
regmap_write(hdptx->regmap, CMN_REG(006c),
995
+
FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x3));
996
+
regmap_write(hdptx->regmap, CMN_REG(006d),
997
+
FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7));
998
+
regmap_write(hdptx->regmap, CMN_REG(006e),
999
+
FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7));
1000
+
1001
+
regmap_write(hdptx->regmap, CMN_REG(0070),
1002
+
FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x8));
1003
+
regmap_write(hdptx->regmap, CMN_REG(0071),
1004
+
FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18));
1005
+
regmap_write(hdptx->regmap, CMN_REG(0072),
1006
+
FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18));
1007
+
1008
+
regmap_update_bits(hdptx->regmap, CMN_REG(0074),
1009
+
OVRD_ROPLL_SDC_NDIV_RSTN_MASK | ROPLL_SDC_NDIV_RSTN_MASK,
1010
+
FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN_MASK, 0x1) |
1011
+
FIELD_PREP(ROPLL_SDC_NDIV_RSTN_MASK, 0x1));
1012
+
1013
+
regmap_update_bits(hdptx->regmap, CMN_REG(0077), ANA_ROPLL_SSC_CLK_DIV_SEL_MASK,
1014
+
FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL_MASK, 0x1));
1015
+
1016
+
regmap_update_bits(hdptx->regmap, CMN_REG(0081), ANA_PLL_CD_TX_SER_RATE_SEL_MASK,
1017
+
FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL_MASK, 0x0));
1018
+
regmap_update_bits(hdptx->regmap, CMN_REG(0081),
1019
+
ANA_PLL_CD_HSCLK_EAST_EN_MASK | ANA_PLL_CD_HSCLK_WEST_EN_MASK,
1020
+
FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN_MASK, 0x1) |
1021
+
FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN_MASK, 0x0));
1022
+
1023
+
regmap_update_bits(hdptx->regmap, CMN_REG(0082), ANA_PLL_CD_VREG_GAIN_CTRL_MASK,
1024
+
FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL_MASK, 0x4));
1025
+
regmap_update_bits(hdptx->regmap, CMN_REG(0083), ANA_PLL_CD_VREG_ICTRL_MASK,
1026
+
FIELD_PREP(ANA_PLL_CD_VREG_ICTRL_MASK, 0x1));
1027
+
regmap_update_bits(hdptx->regmap, CMN_REG(0084), PLL_LCRO_CLK_SEL_MASK,
1028
+
FIELD_PREP(PLL_LCRO_CLK_SEL_MASK, 0x1));
1029
+
regmap_update_bits(hdptx->regmap, CMN_REG(0085), ANA_PLL_SYNC_LOSS_DET_MODE_MASK,
1030
+
FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE_MASK, 0x3));
1031
+
1032
+
regmap_update_bits(hdptx->regmap, CMN_REG(0087), ANA_PLL_TX_HS_CLK_EN_MASK,
1033
+
FIELD_PREP(ANA_PLL_TX_HS_CLK_EN_MASK, 0x1));
1034
+
1035
+
regmap_update_bits(hdptx->regmap, CMN_REG(0097), DIG_CLK_SEL_MASK,
1036
+
FIELD_PREP(DIG_CLK_SEL_MASK, 0x1));
1037
+
1038
+
regmap_update_bits(hdptx->regmap, CMN_REG(0099), CMN_ROPLL_ALONE_MODE_MASK,
1039
+
FIELD_PREP(CMN_ROPLL_ALONE_MODE_MASK, 0x1));
1040
+
regmap_update_bits(hdptx->regmap, CMN_REG(009a), HS_SPEED_SEL_MASK,
1041
+
FIELD_PREP(HS_SPEED_SEL_MASK, 0x1));
1042
+
regmap_update_bits(hdptx->regmap, CMN_REG(009b), LS_SPEED_SEL_MASK,
1043
+
FIELD_PREP(LS_SPEED_SEL_MASK, 0x1));
1044
+
}
1045
+
1046
+
static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy *hdptx)
1047
+
{
1048
+
u32 status;
1049
+
int ret;
1050
+
1051
+
regmap_update_bits(hdptx->regmap, SB_REG(0102), ANA_SB_RXTERM_OFFSP_MASK,
1052
+
FIELD_PREP(ANA_SB_RXTERM_OFFSP_MASK, 0x3));
1053
+
regmap_update_bits(hdptx->regmap, SB_REG(0103), ANA_SB_RXTERM_OFFSN_MASK,
1054
+
FIELD_PREP(ANA_SB_RXTERM_OFFSN_MASK, 0x3));
1055
+
regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK,
1056
+
FIELD_PREP(SB_AUX_EN_MASK, 0x1));
1057
+
regmap_update_bits(hdptx->regmap, SB_REG(0105), ANA_SB_TX_HLVL_PROG_MASK,
1058
+
FIELD_PREP(ANA_SB_TX_HLVL_PROG_MASK, 0x7));
1059
+
regmap_update_bits(hdptx->regmap, SB_REG(0106), ANA_SB_TX_LLVL_PROG_MASK,
1060
+
FIELD_PREP(ANA_SB_TX_LLVL_PROG_MASK, 0x7));
1061
+
1062
+
regmap_update_bits(hdptx->regmap, SB_REG(010d), ANA_SB_DMRX_LPBK_DATA_MASK,
1063
+
FIELD_PREP(ANA_SB_DMRX_LPBK_DATA_MASK, 0x1));
1064
+
1065
+
regmap_update_bits(hdptx->regmap, SB_REG(010f), ANA_SB_VREG_GAIN_CTRL_MASK,
1066
+
FIELD_PREP(ANA_SB_VREG_GAIN_CTRL_MASK, 0x0));
1067
+
regmap_update_bits(hdptx->regmap, SB_REG(0110),
1068
+
ANA_SB_VREG_OUT_SEL_MASK | ANA_SB_VREG_REF_SEL_MASK,
1069
+
FIELD_PREP(ANA_SB_VREG_OUT_SEL_MASK, 0x1) |
1070
+
FIELD_PREP(ANA_SB_VREG_REF_SEL_MASK, 0x1));
1071
+
1072
+
regmap_update_bits(hdptx->regmap, SB_REG(0113),
1073
+
SB_RX_RCAL_OPT_CODE_MASK | SB_RX_RTERM_CTRL_MASK,
1074
+
FIELD_PREP(SB_RX_RCAL_OPT_CODE_MASK, 0x1) |
1075
+
FIELD_PREP(SB_RX_RTERM_CTRL_MASK, 0x3));
1076
+
regmap_update_bits(hdptx->regmap, SB_REG(0114),
1077
+
SB_TG_SB_EN_DELAY_TIME_MASK | SB_TG_RXTERM_EN_DELAY_TIME_MASK,
1078
+
FIELD_PREP(SB_TG_SB_EN_DELAY_TIME_MASK, 0x2) |
1079
+
FIELD_PREP(SB_TG_RXTERM_EN_DELAY_TIME_MASK, 0x2));
1080
+
regmap_update_bits(hdptx->regmap, SB_REG(0115),
1081
+
SB_READY_DELAY_TIME_MASK | SB_TG_OSC_EN_DELAY_TIME_MASK,
1082
+
FIELD_PREP(SB_READY_DELAY_TIME_MASK, 0x2) |
1083
+
FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME_MASK, 0x2));
1084
+
regmap_update_bits(hdptx->regmap, SB_REG(0116),
1085
+
AFC_RSTN_DELAY_TIME_MASK,
1086
+
FIELD_PREP(AFC_RSTN_DELAY_TIME_MASK, 0x2));
1087
+
regmap_update_bits(hdptx->regmap, SB_REG(0117),
1088
+
FAST_PULSE_TIME_MASK,
1089
+
FIELD_PREP(FAST_PULSE_TIME_MASK, 0x4));
1090
+
regmap_update_bits(hdptx->regmap, SB_REG(0118),
1091
+
SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK,
1092
+
FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK, 0xa));
1093
+
1094
+
regmap_update_bits(hdptx->regmap, SB_REG(011a), SB_TG_CNT_RUN_NO_7_0_MASK,
1095
+
FIELD_PREP(SB_TG_CNT_RUN_NO_7_0_MASK, 0x3));
1096
+
regmap_update_bits(hdptx->regmap, SB_REG(011b),
1097
+
SB_EARC_SIG_DET_BYPASS_MASK | SB_AFC_TOL_MASK,
1098
+
FIELD_PREP(SB_EARC_SIG_DET_BYPASS_MASK, 0x1) |
1099
+
FIELD_PREP(SB_AFC_TOL_MASK, 0x3));
1100
+
regmap_update_bits(hdptx->regmap, SB_REG(011c), SB_AFC_STB_NUM_MASK,
1101
+
FIELD_PREP(SB_AFC_STB_NUM_MASK, 0x4));
1102
+
regmap_update_bits(hdptx->regmap, SB_REG(011d), SB_TG_OSC_CNT_MIN_MASK,
1103
+
FIELD_PREP(SB_TG_OSC_CNT_MIN_MASK, 0x67));
1104
+
regmap_update_bits(hdptx->regmap, SB_REG(011e), SB_TG_OSC_CNT_MAX_MASK,
1105
+
FIELD_PREP(SB_TG_OSC_CNT_MAX_MASK, 0x6a));
1106
+
regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_PWM_AFC_CTRL_MASK,
1107
+
FIELD_PREP(SB_PWM_AFC_CTRL_MASK, 0x5));
1108
+
regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_RCAL_RSTN_MASK,
1109
+
FIELD_PREP(SB_RCAL_RSTN_MASK, 0x1));
1110
+
regmap_update_bits(hdptx->regmap, SB_REG(0120), SB_AUX_EN_IN_MASK,
1111
+
FIELD_PREP(SB_AUX_EN_IN_MASK, 0x1));
1112
+
1113
+
regmap_update_bits(hdptx->regmap, SB_REG(0102), OVRD_SB_RXTERM_EN_MASK,
1114
+
FIELD_PREP(OVRD_SB_RXTERM_EN_MASK, 0x1));
1115
+
regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK,
1116
+
FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1));
1117
+
regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_EN_MASK,
1118
+
FIELD_PREP(OVRD_SB_EN_MASK, 0x1));
1119
+
regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_AUX_EN_MASK,
1120
+
FIELD_PREP(OVRD_SB_AUX_EN_MASK, 0x1));
1121
+
1122
+
regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_EN_MASK,
1123
+
FIELD_PREP(OVRD_SB_VREG_EN_MASK, 0x1));
1124
+
1125
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1126
+
HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x1));
1127
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1128
+
HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x1));
1129
+
usleep_range(20, 25);
1130
+
1131
+
reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
1132
+
usleep_range(20, 25);
1133
+
reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
1134
+
usleep_range(20, 25);
1135
+
1136
+
regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK,
1137
+
FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1));
1138
+
usleep_range(100, 110);
1139
+
regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_EN_MASK,
1140
+
FIELD_PREP(SB_EN_MASK, 0x1));
1141
+
usleep_range(100, 110);
1142
+
regmap_update_bits(hdptx->regmap, SB_REG(0102), SB_RXTERM_EN_MASK,
1143
+
FIELD_PREP(SB_RXTERM_EN_MASK, 0x1));
1144
+
usleep_range(20, 25);
1145
+
regmap_update_bits(hdptx->regmap, SB_REG(010f), SB_VREG_EN_MASK,
1146
+
FIELD_PREP(SB_VREG_EN_MASK, 0x1));
1147
+
usleep_range(20, 25);
1148
+
regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK,
1149
+
FIELD_PREP(SB_AUX_EN_MASK, 0x1));
1150
+
usleep_range(100, 110);
1151
+
1152
+
ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS,
1153
+
status, FIELD_GET(HDPTX_O_SB_RDY, status),
1154
+
50, 1000);
1155
+
if (ret) {
1156
+
dev_err(hdptx->dev, "Failed to get phy sb ready: %d\n", ret);
1157
+
return ret;
1158
+
}
1159
+
1160
+
return 0;
1161
+
}
1162
+
1193
1163
static int rk_hdptx_phy_power_on(struct phy *phy)
1194
1164
{
1195
1165
struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
1196
1166
int bus_width = phy_get_bus_width(hdptx->phy);
1197
-
int ret;
1167
+
enum phy_mode mode = phy_get_mode(phy);
1168
+
int ret, lane;
1198
1169
1199
1170
/*
1200
1171
* FIXME: Temporary workaround to pass pixel_clk_rate
···
1461
930
if (ret)
1462
931
return ret;
1463
932
1464
-
ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
1465
-
if (ret)
1466
-
rk_hdptx_phy_consumer_put(hdptx, true);
933
+
if (mode == PHY_MODE_DP) {
934
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
935
+
HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x1));
936
+
937
+
for (lane = 0; lane < 4; lane++) {
938
+
regmap_update_bits(hdptx->regmap, LANE_REG(031e) + 0x400 * lane,
939
+
LN_POLARITY_INV_MASK | LN_LANE_MODE_MASK,
940
+
FIELD_PREP(LN_POLARITY_INV_MASK, 0) |
941
+
FIELD_PREP(LN_LANE_MODE_MASK, 1));
942
+
}
943
+
944
+
regmap_update_bits(hdptx->regmap, LNTOP_REG(0200), PROTOCOL_SEL_MASK,
945
+
FIELD_PREP(PROTOCOL_SEL_MASK, 0x0));
946
+
regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_MASK,
947
+
FIELD_PREP(DATA_BUS_WIDTH_MASK, 0x1));
948
+
regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_SEL_MASK,
949
+
FIELD_PREP(DATA_BUS_WIDTH_SEL_MASK, 0x0));
950
+
951
+
rk_hdptx_dp_pll_init(hdptx);
952
+
953
+
ret = rk_hdptx_dp_aux_init(hdptx);
954
+
if (ret)
955
+
rk_hdptx_phy_consumer_put(hdptx, true);
956
+
} else {
957
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
958
+
HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
959
+
960
+
ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
961
+
if (ret)
962
+
rk_hdptx_phy_consumer_put(hdptx, true);
963
+
}
1467
964
1468
965
return ret;
1469
966
}
···
1503
944
return rk_hdptx_phy_consumer_put(hdptx, false);
1504
945
}
1505
946
947
+
static int rk_hdptx_phy_verify_config(struct rk_hdptx_phy *hdptx,
948
+
struct phy_configure_opts_dp *dp)
949
+
{
950
+
int i;
951
+
952
+
if (dp->set_rate) {
953
+
switch (dp->link_rate) {
954
+
case 1620:
955
+
case 2700:
956
+
case 5400:
957
+
break;
958
+
default:
959
+
return -EINVAL;
960
+
}
961
+
}
962
+
963
+
if (dp->set_lanes) {
964
+
switch (dp->lanes) {
965
+
case 1:
966
+
case 2:
967
+
case 4:
968
+
break;
969
+
default:
970
+
return -EINVAL;
971
+
}
972
+
}
973
+
974
+
if (dp->set_voltages) {
975
+
for (i = 0; i < hdptx->lanes; i++) {
976
+
if (dp->voltage[i] > 3 || dp->pre[i] > 3)
977
+
return -EINVAL;
978
+
979
+
if (dp->voltage[i] + dp->pre[i] > 3)
980
+
return -EINVAL;
981
+
}
982
+
}
983
+
984
+
return 0;
985
+
}
986
+
987
+
static int rk_hdptx_phy_set_rate(struct rk_hdptx_phy *hdptx,
988
+
struct phy_configure_opts_dp *dp)
989
+
{
990
+
u32 bw, status;
991
+
int ret;
992
+
993
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
994
+
HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0));
995
+
996
+
switch (dp->link_rate) {
997
+
case 1620:
998
+
bw = DP_BW_RBR;
999
+
break;
1000
+
case 2700:
1001
+
bw = DP_BW_HBR;
1002
+
break;
1003
+
case 5400:
1004
+
bw = DP_BW_HBR2;
1005
+
break;
1006
+
default:
1007
+
return -EINVAL;
1008
+
}
1009
+
hdptx->link_rate = dp->link_rate;
1010
+
1011
+
regmap_update_bits(hdptx->regmap, CMN_REG(0008), OVRD_LCPLL_EN_MASK | LCPLL_EN_MASK,
1012
+
FIELD_PREP(OVRD_LCPLL_EN_MASK, 0x1) |
1013
+
FIELD_PREP(LCPLL_EN_MASK, 0x0));
1014
+
1015
+
regmap_update_bits(hdptx->regmap, CMN_REG(003d), OVRD_ROPLL_EN_MASK | ROPLL_EN_MASK,
1016
+
FIELD_PREP(OVRD_ROPLL_EN_MASK, 0x1) |
1017
+
FIELD_PREP(ROPLL_EN_MASK, 0x1));
1018
+
1019
+
if (dp->ssc) {
1020
+
regmap_update_bits(hdptx->regmap, CMN_REG(0074),
1021
+
OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK,
1022
+
FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) |
1023
+
FIELD_PREP(ROPLL_SSC_EN_MASK, 0x1));
1024
+
regmap_write(hdptx->regmap, CMN_REG(0075),
1025
+
FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0xc));
1026
+
regmap_update_bits(hdptx->regmap, CMN_REG(0076),
1027
+
ANA_ROPLL_SSC_FM_FREQ_MASK,
1028
+
FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0x1f));
1029
+
1030
+
regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK,
1031
+
FIELD_PREP(SSC_EN_MASK, 0x2));
1032
+
} else {
1033
+
regmap_update_bits(hdptx->regmap, CMN_REG(0074),
1034
+
OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK,
1035
+
FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) |
1036
+
FIELD_PREP(ROPLL_SSC_EN_MASK, 0x0));
1037
+
regmap_write(hdptx->regmap, CMN_REG(0075),
1038
+
FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0x20));
1039
+
regmap_update_bits(hdptx->regmap, CMN_REG(0076),
1040
+
ANA_ROPLL_SSC_FM_FREQ_MASK,
1041
+
FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0xc));
1042
+
1043
+
regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK,
1044
+
FIELD_PREP(SSC_EN_MASK, 0x0));
1045
+
}
1046
+
1047
+
regmap_update_bits(hdptx->regmap, CMN_REG(0095), DP_TX_LINK_BW_MASK,
1048
+
FIELD_PREP(DP_TX_LINK_BW_MASK, bw));
1049
+
1050
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1051
+
HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x1));
1052
+
1053
+
ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS,
1054
+
status, FIELD_GET(HDPTX_O_PLL_LOCK_DONE, status),
1055
+
50, 1000);
1056
+
if (ret) {
1057
+
dev_err(hdptx->dev, "Failed to get phy pll lock: %d\n", ret);
1058
+
return ret;
1059
+
}
1060
+
1061
+
return 0;
1062
+
}
1063
+
1064
+
static int rk_hdptx_phy_set_lanes(struct rk_hdptx_phy *hdptx,
1065
+
struct phy_configure_opts_dp *dp)
1066
+
{
1067
+
hdptx->lanes = dp->lanes;
1068
+
1069
+
regmap_update_bits(hdptx->regmap, LNTOP_REG(0207), LANE_EN_MASK,
1070
+
FIELD_PREP(LANE_EN_MASK, GENMASK(hdptx->lanes - 1, 0)));
1071
+
1072
+
return 0;
1073
+
}
1074
+
1075
+
static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
1076
+
struct phy_configure_opts_dp *dp,
1077
+
u8 lane)
1078
+
{
1079
+
const struct tx_drv_ctrl *ctrl;
1080
+
u32 offset = lane * 0x400;
1081
+
1082
+
switch (hdptx->link_rate) {
1083
+
case 1620:
1084
+
ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]];
1085
+
regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
1086
+
LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
1087
+
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
1088
+
ctrl->tx_jeq_even_ctrl));
1089
+
regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset,
1090
+
LN_TX_JEQ_ODD_CTRL_RBR_MASK,
1091
+
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK,
1092
+
ctrl->tx_jeq_odd_ctrl));
1093
+
regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
1094
+
LN_TX_SER_40BIT_EN_RBR_MASK,
1095
+
FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1));
1096
+
break;
1097
+
case 2700:
1098
+
ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];
1099
+
regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
1100
+
LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
1101
+
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
1102
+
ctrl->tx_jeq_even_ctrl));
1103
+
regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
1104
+
LN_TX_JEQ_ODD_CTRL_HBR_MASK,
1105
+
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK,
1106
+
ctrl->tx_jeq_odd_ctrl));
1107
+
regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
1108
+
LN_TX_SER_40BIT_EN_HBR_MASK,
1109
+
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1));
1110
+
break;
1111
+
case 5400:
1112
+
default:
1113
+
ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]];
1114
+
regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
1115
+
LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
1116
+
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
1117
+
ctrl->tx_jeq_even_ctrl));
1118
+
regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
1119
+
LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
1120
+
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
1121
+
ctrl->tx_jeq_odd_ctrl));
1122
+
regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
1123
+
LN_TX_SER_40BIT_EN_HBR2_MASK,
1124
+
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1));
1125
+
break;
1126
+
}
1127
+
1128
+
regmap_update_bits(hdptx->regmap, LANE_REG(0303) + offset,
1129
+
OVRD_LN_TX_DRV_LVL_CTRL_MASK | LN_TX_DRV_LVL_CTRL_MASK,
1130
+
FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL_MASK, 0x1) |
1131
+
FIELD_PREP(LN_TX_DRV_LVL_CTRL_MASK,
1132
+
ctrl->tx_drv_lvl_ctrl));
1133
+
regmap_update_bits(hdptx->regmap, LANE_REG(0304) + offset,
1134
+
OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK |
1135
+
LN_TX_DRV_POST_LVL_CTRL_MASK,
1136
+
FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK, 0x1) |
1137
+
FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK,
1138
+
ctrl->tx_drv_post_lvl_ctrl));
1139
+
regmap_update_bits(hdptx->regmap, LANE_REG(0305) + offset,
1140
+
OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK |
1141
+
LN_TX_DRV_PRE_LVL_CTRL_MASK,
1142
+
FIELD_PREP(OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK, 0x1) |
1143
+
FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK,
1144
+
ctrl->tx_drv_pre_lvl_ctrl));
1145
+
regmap_update_bits(hdptx->regmap, LANE_REG(0306) + offset,
1146
+
LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK |
1147
+
LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK |
1148
+
LN_ANA_TX_DRV_ACCDRV_EN_MASK,
1149
+
FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK,
1150
+
ctrl->ana_tx_drv_idrv_idn_ctrl) |
1151
+
FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK,
1152
+
ctrl->ana_tx_drv_idrv_iup_ctrl) |
1153
+
FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN_MASK,
1154
+
ctrl->ana_tx_drv_accdrv_en));
1155
+
regmap_update_bits(hdptx->regmap, LANE_REG(0307) + offset,
1156
+
LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK |
1157
+
LN_ANA_TX_DRV_ACCDRV_CTRL_MASK,
1158
+
FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK, 0x1) |
1159
+
FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL_MASK,
1160
+
ctrl->ana_tx_drv_accdrv_ctrl));
1161
+
1162
+
regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
1163
+
LN_ANA_TX_JEQ_EN_MASK,
1164
+
FIELD_PREP(LN_ANA_TX_JEQ_EN_MASK, ctrl->ana_tx_jeq_en));
1165
+
1166
+
regmap_update_bits(hdptx->regmap, LANE_REG(0310) + offset,
1167
+
LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK,
1168
+
FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK, 0x3));
1169
+
1170
+
regmap_update_bits(hdptx->regmap, LANE_REG(0316) + offset,
1171
+
LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK,
1172
+
FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK, 0x2));
1173
+
1174
+
regmap_update_bits(hdptx->regmap, LANE_REG(031b) + offset,
1175
+
LN_ANA_TX_RESERVED_MASK,
1176
+
FIELD_PREP(LN_ANA_TX_RESERVED_MASK, 0x1));
1177
+
}
1178
+
1179
+
static int rk_hdptx_phy_set_voltages(struct rk_hdptx_phy *hdptx,
1180
+
struct phy_configure_opts_dp *dp)
1181
+
{
1182
+
u8 lane;
1183
+
u32 status;
1184
+
int ret;
1185
+
1186
+
for (lane = 0; lane < hdptx->lanes; lane++)
1187
+
rk_hdptx_phy_set_voltage(hdptx, dp, lane);
1188
+
1189
+
reset_control_deassert(hdptx->rsts[RST_LANE].rstc);
1190
+
1191
+
ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS,
1192
+
status, FIELD_GET(HDPTX_O_PHY_RDY, status),
1193
+
50, 5000);
1194
+
if (ret) {
1195
+
dev_err(hdptx->dev, "Failed to get phy ready: %d\n", ret);
1196
+
return ret;
1197
+
}
1198
+
1199
+
return 0;
1200
+
}
1201
+
1202
+
static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opts)
1203
+
{
1204
+
struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
1205
+
enum phy_mode mode = phy_get_mode(phy);
1206
+
int ret;
1207
+
1208
+
if (mode != PHY_MODE_DP)
1209
+
return 0;
1210
+
1211
+
ret = rk_hdptx_phy_verify_config(hdptx, &opts->dp);
1212
+
if (ret) {
1213
+
dev_err(hdptx->dev, "invalid params for phy configure\n");
1214
+
return ret;
1215
+
}
1216
+
1217
+
if (opts->dp.set_rate) {
1218
+
ret = rk_hdptx_phy_set_rate(hdptx, &opts->dp);
1219
+
if (ret) {
1220
+
dev_err(hdptx->dev, "failed to set rate: %d\n", ret);
1221
+
return ret;
1222
+
}
1223
+
}
1224
+
1225
+
if (opts->dp.set_lanes) {
1226
+
ret = rk_hdptx_phy_set_lanes(hdptx, &opts->dp);
1227
+
if (ret) {
1228
+
dev_err(hdptx->dev, "failed to set lanes: %d\n", ret);
1229
+
return ret;
1230
+
}
1231
+
}
1232
+
1233
+
if (opts->dp.set_voltages) {
1234
+
ret = rk_hdptx_phy_set_voltages(hdptx, &opts->dp);
1235
+
if (ret) {
1236
+
dev_err(hdptx->dev, "failed to set voltages: %d\n",
1237
+
ret);
1238
+
return ret;
1239
+
}
1240
+
}
1241
+
1242
+
return 0;
1243
+
}
1244
+
1506
1245
static const struct phy_ops rk_hdptx_phy_ops = {
1507
1246
.power_on = rk_hdptx_phy_power_on,
1508
1247
.power_off = rk_hdptx_phy_power_off,
1248
+
.configure = rk_hdptx_phy_configure,
1509
1249
.owner = THIS_MODULE,
1510
1250
};
1511
1251
···
2046
1188
2047
1189
MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
2048
1190
MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>");
1191
+
MODULE_AUTHOR("Damon Ding <damon.ding@rock-chips.com>");
2049
1192
MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver");
2050
1193
MODULE_LICENSE("GPL");