Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu/gfx: decouple the number of kgqs from the hw
The driver currently sets up one kgq per pipe. As such
adev->gfx.me.num_queue_per_pipe is hardcoded to 1 everywhere.
This is fine for kernel queues, but when we enable user queues
we need to know that actual number of queues per pipe. Decouple
the kgq setup from the actual hardware count. For dev core
dumps and user queues, we want to know the actual number
of queues per pipe.
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+13
-9
+7
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+7
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
···
77
77
static int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
78
78
int me, int pipe, int queue)
79
79
{
80
+
int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
80
81
int bit = 0;
81
82
82
83
bit += me * adev->gfx.me.num_pipe_per_me
83
-
* adev->gfx.me.num_queue_per_pipe;
84
-
bit += pipe * adev->gfx.me.num_queue_per_pipe;
84
+
* num_queue_per_pipe;
85
+
bit += pipe * num_queue_per_pipe;
85
86
bit += queue;
86
87
87
88
return bit;
···
239
238
{
240
239
int i, queue, pipe;
241
240
bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
242
-
int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
243
-
adev->gfx.me.num_queue_per_pipe;
241
+
int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
242
+
int max_queues_per_me = adev->gfx.me.num_pipe_per_me * num_queue_per_pipe;
244
243
245
244
if (multipipe_policy) {
246
245
/* policy: amdgpu owns the first queue per pipe at this stage
···
248
247
for (i = 0; i < max_queues_per_me; i++) {
249
248
pipe = i % adev->gfx.me.num_pipe_per_me;
250
249
queue = (i / adev->gfx.me.num_pipe_per_me) %
251
-
adev->gfx.me.num_queue_per_pipe;
250
+
num_queue_per_pipe;
252
251
253
-
set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
252
+
set_bit(pipe * num_queue_per_pipe + queue,
254
253
adev->gfx.me.queue_bitmap);
255
254
}
256
255
} else {
+2
-1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+2
-1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
···
4752
4752
int i, j, k, r, ring_id = 0;
4753
4753
int xcc_id = 0;
4754
4754
struct amdgpu_device *adev = ip_block->adev;
4755
+
int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
4755
4756
4756
4757
INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
4757
4758
···
4917
4916
4918
4917
/* set up the gfx ring */
4919
4918
for (i = 0; i < adev->gfx.me.num_me; i++) {
4920
-
for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4919
+
for (j = 0; j < num_queue_per_pipe; j++) {
4921
4920
for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4922
4921
if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4923
4922
continue;
+2
-1
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+2
-1
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
···
1571
1571
int i, j, k, r, ring_id = 0;
1572
1572
int xcc_id = 0;
1573
1573
struct amdgpu_device *adev = ip_block->adev;
1574
+
int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
1574
1575
1575
1576
INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
1576
1577
···
1704
1703
1705
1704
/* set up the gfx ring */
1706
1705
for (i = 0; i < adev->gfx.me.num_me; i++) {
1707
-
for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1706
+
for (j = 0; j < num_queue_per_pipe; j++) {
1708
1707
for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1709
1708
if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1710
1709
continue;
+2
-1
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+2
-1
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
···
1346
1346
unsigned num_compute_rings;
1347
1347
int xcc_id = 0;
1348
1348
struct amdgpu_device *adev = ip_block->adev;
1349
+
int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
1349
1350
1350
1351
INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
1351
1352
···
1436
1435
1437
1436
/* set up the gfx ring */
1438
1437
for (i = 0; i < adev->gfx.me.num_me; i++) {
1439
-
for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1438
+
for (j = 0; j < num_queue_per_pipe; j++) {
1440
1439
for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1441
1440
if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1442
1441
continue;