Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2025-04-11-1' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Weekly fixes, as expected it has a bit more in it than probably usual
for rc2. amdgpu/xe/i915 lead the way with fixes all over for a bunch
of other drivers. Nothing major stands out from what I can see.
tests:
- Clean up struct drm_display_mode in various places
i915:
- Fix scanline offset for LNL+ and BMG+
- Fix GVT unterminated-string-initialization build warning
- Fix DP rate limit when sink doesn't support TPS4
- Handle GDDR + ECC memory type detection
- Fix VRR parameter change check
- Fix fence not released on early probe errors
- Disable render power gating during live selftests
xe:
- Add another BMG PCI ID
- Fix UAFs on migration paths
- Fix shift-out-of-bounds access on TLB invalidation
- Ensure ccs_mode is correctly set on gt reset
- Extend some HW workarounds to Xe3
- Fix PM runtime get/put on sysfs files
- Fix u64 division on 32b
- Fix flickering due to missing L3 invalidations
- Fix missing error code return
amdgpu:
- MES FW version caching fixes
- Only use GTT as a fallback if we already have a backing store
- dma_buf fix
- IP discovery fix
- Replay and PSR with VRR fix
- DC FP fixes
- eDP fixes
- KIQ TLB invalidate fix
- Enable dmem groups support
- Allow pinning VRAM dma bufs if imports can do P2P
- Workload profile fixes
- Prevent possible division by 0 in fan handling
amdkfd:
- Queue reset fixes
imagination:
- Fix overflow
- Fix use-after-free
ivpu:
- Fix suspend/resume
nouveau:
- Do not deref dangling pointer
rockchip:
- Set DP/HDMI registers correctly
udmabuf:
- Fix overflow
virtgpu:
- Set reservation lock on dma-buf import
- Fix error handling in prepare_fb"
* tag 'drm-fixes-2025-04-11-1' of https://gitlab.freedesktop.org/drm/kernel: (58 commits)
drm/rockchip: dw_hdmi_qp: Fix io init for dw_hdmi_qp_rockchip_resume
drm/rockchip: vop2: Fix interface enable/mux setting of DP1 on rk3588
drm/amdgpu/mes12: optimize MES pipe FW version fetching
drm/amd/pm/smu11: Prevent division by zero
drm/amdgpu: cancel gfx idle work in device suspend for s0ix
drm/amd/display: pause the workload setting in dm
drm/amdgpu/pm/swsmu: implement pause workload profile
drm/amdgpu/pm: add workload profile pause helper
drm/i915/huc: Fix fence not released on early probe errors
drm/i915/vrr: Add vrr.vsync_{start, end} in vrr_params_changed
drm/tests: probe-helper: Fix drm_display_mode memory leak
drm/tests: modes: Fix drm_display_mode memory leak
drm/tests: modes: Fix drm_display_mode memory leak
drm/tests: cmdline: Fix drm_display_mode memory leak
drm/tests: modeset: Fix drm_display_mode memory leak
drm/tests: modeset: Fix drm_display_mode memory leak
drm/tests: helpers: Create kunit helper to destroy a drm_display_mode
drm/xe: Restore EIO errno return when GuC PC start fails
drm/xe: Invalidate L3 read-only cachelines for geometry streams too
drm/xe: avoid plain 64-bit division
...
+543
-197
+2
-2
drivers/accel/ivpu/ivpu_debugfs.c
+2
-2
drivers/accel/ivpu/ivpu_debugfs.c
···
332
332
return -EINVAL;
333
333
334
334
ret = ivpu_rpm_get(vdev);
335
-
if (ret)
335
+
if (ret < 0)
336
336
return ret;
337
337
338
338
ivpu_pm_trigger_recovery(vdev, "debugfs");
···
383
383
return -EINVAL;
384
384
385
385
ret = ivpu_rpm_get(vdev);
386
-
if (ret)
386
+
if (ret < 0)
387
387
return ret;
388
388
389
389
if (active_percent)
+2
-1
drivers/accel/ivpu/ivpu_ipc.c
+2
-1
drivers/accel/ivpu/ivpu_ipc.c
···
302
302
struct ivpu_ipc_consumer cons;
303
303
int ret;
304
304
305
-
drm_WARN_ON(&vdev->drm, pm_runtime_status_suspended(vdev->drm.dev));
305
+
drm_WARN_ON(&vdev->drm, pm_runtime_status_suspended(vdev->drm.dev) &&
306
+
pm_runtime_enabled(vdev->drm.dev));
306
307
307
308
ivpu_ipc_consumer_add(vdev, &cons, channel, NULL);
308
309
+24
drivers/accel/ivpu/ivpu_ms.c
+24
drivers/accel/ivpu/ivpu_ms.c
···
4
4
*/
5
5
6
6
#include <drm/drm_file.h>
7
+
#include <linux/pm_runtime.h>
7
8
8
9
#include "ivpu_drv.h"
9
10
#include "ivpu_gem.h"
···
44
43
if (!args->metric_group_mask || !args->read_period_samples ||
45
44
args->sampling_period_ns < MS_MIN_SAMPLE_PERIOD_NS)
46
45
return -EINVAL;
46
+
47
+
ret = ivpu_rpm_get(vdev);
48
+
if (ret < 0)
49
+
return ret;
47
50
48
51
mutex_lock(&file_priv->ms_lock);
49
52
···
101
96
kfree(ms);
102
97
unlock:
103
98
mutex_unlock(&file_priv->ms_lock);
99
+
100
+
ivpu_rpm_put(vdev);
104
101
return ret;
105
102
}
106
103
···
167
160
if (!args->metric_group_mask)
168
161
return -EINVAL;
169
162
163
+
ret = ivpu_rpm_get(vdev);
164
+
if (ret < 0)
165
+
return ret;
166
+
170
167
mutex_lock(&file_priv->ms_lock);
171
168
172
169
ms = get_instance_by_mask(file_priv, args->metric_group_mask);
···
198
187
unlock:
199
188
mutex_unlock(&file_priv->ms_lock);
200
189
190
+
ivpu_rpm_put(vdev);
201
191
return ret;
202
192
}
203
193
···
216
204
{
217
205
struct ivpu_file_priv *file_priv = file->driver_priv;
218
206
struct drm_ivpu_metric_streamer_stop *args = data;
207
+
struct ivpu_device *vdev = file_priv->vdev;
219
208
struct ivpu_ms_instance *ms;
209
+
int ret;
220
210
221
211
if (!args->metric_group_mask)
222
212
return -EINVAL;
213
+
214
+
ret = ivpu_rpm_get(vdev);
215
+
if (ret < 0)
216
+
return ret;
223
217
224
218
mutex_lock(&file_priv->ms_lock);
225
219
···
235
217
236
218
mutex_unlock(&file_priv->ms_lock);
237
219
220
+
ivpu_rpm_put(vdev);
238
221
return ms ? 0 : -EINVAL;
239
222
}
240
223
···
300
281
void ivpu_ms_cleanup(struct ivpu_file_priv *file_priv)
301
282
{
302
283
struct ivpu_ms_instance *ms, *tmp;
284
+
struct ivpu_device *vdev = file_priv->vdev;
285
+
286
+
pm_runtime_get_sync(vdev->drm.dev);
303
287
304
288
mutex_lock(&file_priv->ms_lock);
305
289
···
315
293
free_instance(file_priv, ms);
316
294
317
295
mutex_unlock(&file_priv->ms_lock);
296
+
297
+
pm_runtime_put_autosuspend(vdev->drm.dev);
318
298
}
319
299
320
300
void ivpu_ms_cleanup_all(struct ivpu_device *vdev)
+1
-1
drivers/dma-buf/udmabuf.c
+1
-1
drivers/dma-buf/udmabuf.c
-1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
-1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
···
353
353
AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
354
354
AMDGPU_CP_KIQ_IRQ_LAST
355
355
};
356
-
#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
357
356
#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
358
357
#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
359
358
#define MAX_KIQ_REG_TRY 1000
+7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
3643
3643
adev, adev->ip_blocks[i].version->type))
3644
3644
continue;
3645
3645
3646
+
/* Since we skip suspend for S0i3, we need to cancel the delayed
3647
+
* idle work here as the suspend callback never gets called.
3648
+
*/
3649
+
if (adev->in_s0ix &&
3650
+
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX &&
3651
+
amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 0, 0))
3652
+
cancel_delayed_work_sync(&adev->gfx.idle_work);
3646
3653
/* skip suspend of gfx/mes and psp for S0ix
3647
3654
* gfx is in gfxoff state, so on resume it will exit gfxoff just
3648
3655
* like at runtime. PSP is also part of the always on hardware
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
···
120
120
MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin");
121
121
MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin");
122
122
MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin");
123
+
MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin");
124
+
MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin");
123
125
124
126
#define mmIP_DISCOVERY_VERSION 0x16A00
125
127
#define mmRCC_CONFIG_MEMSIZE 0xde3
+19
-8
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+19
-8
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
···
75
75
*/
76
76
static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
77
77
{
78
-
struct drm_gem_object *obj = attach->dmabuf->priv;
79
-
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
78
+
struct dma_buf *dmabuf = attach->dmabuf;
79
+
struct amdgpu_bo *bo = gem_to_amdgpu_bo(dmabuf->priv);
80
+
u32 domains = bo->preferred_domains;
80
81
81
-
/* pin buffer into GTT */
82
-
return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
82
+
dma_resv_assert_held(dmabuf->resv);
83
+
84
+
/*
85
+
* Try pinning into VRAM to allow P2P with RDMA NICs without ODP
86
+
* support if all attachments can do P2P. If any attachment can't do
87
+
* P2P just pin into GTT instead.
88
+
*/
89
+
list_for_each_entry(attach, &dmabuf->attachments, node)
90
+
if (!attach->peer2peer)
91
+
domains &= ~AMDGPU_GEM_DOMAIN_VRAM;
92
+
93
+
if (domains & AMDGPU_GEM_DOMAIN_VRAM)
94
+
bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
95
+
96
+
return amdgpu_bo_pin(bo, domains);
83
97
}
84
98
85
99
/**
···
148
134
r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
149
135
if (r)
150
136
return ERR_PTR(r);
151
-
152
-
} else if (bo->tbo.resource->mem_type != TTM_PL_TT) {
153
-
return ERR_PTR(-EBUSY);
154
137
}
155
138
156
139
switch (bo->tbo.resource->mem_type) {
···
195
184
struct sg_table *sgt,
196
185
enum dma_data_direction dir)
197
186
{
198
-
if (sgt->sgl->page_link) {
187
+
if (sg_page(sgt->sgl)) {
199
188
dma_unmap_sgtable(attach->dev, sgt, dir, 0);
200
189
sg_free_table(sgt);
201
190
kfree(sgt);
+14
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+14
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
···
699
699
uint32_t flush_type, bool all_hub,
700
700
uint32_t inst)
701
701
{
702
-
u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT :
703
-
adev->usec_timeout;
704
702
struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;
705
703
struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
706
704
unsigned int ndw;
707
-
int r;
705
+
int r, cnt = 0;
708
706
uint32_t seq;
709
707
710
708
/*
···
759
761
760
762
amdgpu_ring_commit(ring);
761
763
spin_unlock(&adev->gfx.kiq[inst].ring_lock);
762
-
if (amdgpu_fence_wait_polling(ring, seq, usec_timeout) < 1) {
764
+
765
+
r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
766
+
767
+
might_sleep();
768
+
while (r < 1 && cnt++ < MAX_KIQ_REG_TRY &&
769
+
!amdgpu_reset_pending(adev->reset_domain)) {
770
+
msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
771
+
r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
772
+
}
773
+
774
+
if (cnt > MAX_KIQ_REG_TRY) {
763
775
dev_err(adev->dev, "timeout waiting for kiq fence\n");
764
776
r = -ETIME;
765
-
}
777
+
} else
778
+
r = 0;
766
779
}
767
780
768
781
error_unlock_reset:
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
···
163
163
* When GTT is just an alternative to VRAM make sure that we
164
164
* only use it as fallback and still try to fill up VRAM first.
165
165
*/
166
-
if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
167
-
!(adev->flags & AMD_IS_APU))
166
+
if (abo->tbo.resource && !(adev->flags & AMD_IS_APU) &&
167
+
domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)
168
168
places[c].flags |= TTM_PL_FLAG_FALLBACK;
169
169
c++;
170
170
}
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
···
24
24
25
25
#include <linux/dma-mapping.h>
26
26
#include <drm/ttm/ttm_range_manager.h>
27
+
#include <drm/drm_drv.h>
27
28
28
29
#include "amdgpu.h"
29
30
#include "amdgpu_vm.h"
···
908
907
struct ttm_resource_manager *man = &mgr->manager;
909
908
int err;
910
909
910
+
man->cg = drmm_cgroup_register_region(adev_to_drm(adev), "vram", adev->gmc.real_vram_size);
911
+
if (IS_ERR(man->cg))
912
+
return PTR_ERR(man->cg);
911
913
ttm_resource_manager_init(man, &adev->mman.bdev,
912
914
adev->gmc.real_vram_size);
913
915
+4
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+4
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+12
-9
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+12
-9
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
···
1392
1392
mes_v12_0_queue_init_register(ring);
1393
1393
}
1394
1394
1395
-
/* get MES scheduler/KIQ versions */
1396
-
mutex_lock(&adev->srbm_mutex);
1397
-
soc21_grbm_select(adev, 3, pipe, 0, 0);
1395
+
if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) ||
1396
+
((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) {
1397
+
/* get MES scheduler/KIQ versions */
1398
+
mutex_lock(&adev->srbm_mutex);
1399
+
soc21_grbm_select(adev, 3, pipe, 0, 0);
1398
1400
1399
-
if (pipe == AMDGPU_MES_SCHED_PIPE)
1400
-
adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1401
-
else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1402
-
adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1401
+
if (pipe == AMDGPU_MES_SCHED_PIPE)
1402
+
adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1403
+
else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1404
+
adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1403
1405
1404
-
soc21_grbm_select(adev, 0, 0, 0, 0);
1405
-
mutex_unlock(&adev->srbm_mutex);
1406
+
soc21_grbm_select(adev, 0, 0, 0, 0);
1407
+
mutex_unlock(&adev->srbm_mutex);
1408
+
}
1406
1409
1407
1410
return 0;
1408
1411
}
+5
-4
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+5
-4
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
···
1983
1983
if (kfd_dbg_has_ttmps_always_setup(dev->gpu))
1984
1984
dev->node_props.debug_prop |= HSA_DBG_DISPATCH_INFO_ALWAYS_VALID;
1985
1985
1986
-
if (dev->gpu->adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)
1987
-
dev->node_props.capability2 |= HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;
1988
-
1989
1986
if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0)) {
1990
1987
if (KFD_GC_VERSION(dev->gpu) == IP_VERSION(9, 4, 3) ||
1991
1988
KFD_GC_VERSION(dev->gpu) == IP_VERSION(9, 4, 4))
···
1998
2001
dev->node_props.capability |=
1999
2002
HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;
2000
2003
2001
-
dev->node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED;
2004
+
if (!amdgpu_sriov_vf(dev->gpu->adev))
2005
+
dev->node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED;
2006
+
2007
+
if (dev->gpu->adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)
2008
+
dev->node_props.capability2 |= HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;
2002
2009
} else {
2003
2010
dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |
2004
2011
HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
+21
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+21
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
1726
1726
.callback = edp0_on_dp1_callback,
1727
1727
.matches = {
1728
1728
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1729
+
DMI_MATCH(DMI_PRODUCT_NAME, "HP EliteBook 645 14 inch G11 Notebook PC"),
1730
+
},
1731
+
},
1732
+
{
1733
+
.callback = edp0_on_dp1_callback,
1734
+
.matches = {
1735
+
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1729
1736
DMI_MATCH(DMI_PRODUCT_NAME, "HP EliteBook 665 16 inch G11 Notebook PC"),
1737
+
},
1738
+
},
1739
+
{
1740
+
.callback = edp0_on_dp1_callback,
1741
+
.matches = {
1742
+
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1743
+
DMI_MATCH(DMI_PRODUCT_NAME, "HP ProBook 445 14 inch G11 Notebook PC"),
1744
+
},
1745
+
},
1746
+
{
1747
+
.callback = edp0_on_dp1_callback,
1748
+
.matches = {
1749
+
DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1750
+
DMI_MATCH(DMI_PRODUCT_NAME, "HP ProBook 465 16 inch G11 Notebook PC"),
1730
1751
},
1731
1752
},
1732
1753
{}
+14
-3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+14
-3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
···
113
113
*
114
114
* Panel Replay and PSR SU
115
115
* - Enable when:
116
+
* - VRR is disabled
116
117
* - vblank counter is disabled
117
118
* - entry is allowed: usermode demonstrates an adequate number of fast
118
119
* commits)
···
132
131
bool is_sr_active = (link->replay_settings.replay_allow_active ||
133
132
link->psr_settings.psr_allow_active);
134
133
bool is_crc_window_active = false;
134
+
bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(vblank_work->acrtc);
135
135
136
136
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
137
137
is_crc_window_active =
138
138
amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base);
139
139
#endif
140
140
141
-
if (link->replay_settings.replay_feature_enabled &&
141
+
if (link->replay_settings.replay_feature_enabled && !vrr_active &&
142
142
allow_sr_entry && !is_sr_active && !is_crc_window_active) {
143
143
amdgpu_dm_replay_enable(vblank_work->stream, true);
144
144
} else if (vblank_enabled) {
145
145
if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
146
146
amdgpu_dm_psr_disable(vblank_work->stream, false);
147
-
} else if (link->psr_settings.psr_feature_enabled &&
147
+
} else if (link->psr_settings.psr_feature_enabled && !vrr_active &&
148
148
allow_sr_entry && !is_sr_active && !is_crc_window_active) {
149
149
150
150
struct amdgpu_dm_connector *aconn =
···
246
244
struct vblank_control_work *vblank_work =
247
245
container_of(work, struct vblank_control_work, work);
248
246
struct amdgpu_display_manager *dm = vblank_work->dm;
247
+
struct amdgpu_device *adev = drm_to_adev(dm->ddev);
248
+
int r;
249
249
250
250
mutex_lock(&dm->dc_lock);
251
251
···
275
271
vblank_work->acrtc->dm_irq_params.allow_sr_entry);
276
272
}
277
273
278
-
if (dm->active_vblank_irq_count == 0)
274
+
if (dm->active_vblank_irq_count == 0) {
275
+
r = amdgpu_dpm_pause_power_profile(adev, true);
276
+
if (r)
277
+
dev_warn(adev->dev, "failed to set default power profile mode\n");
279
278
dc_allow_idle_optimizations(dm->dc, true);
279
+
r = amdgpu_dpm_pause_power_profile(adev, false);
280
+
if (r)
281
+
dev_warn(adev->dev, "failed to restore the power profile mode\n");
282
+
}
280
283
281
284
mutex_unlock(&dm->dc_lock);
282
285
+15
-2
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
+15
-2
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
···
86
86
/* Store configuration options */
87
87
(*dml_ctx)->config = *config;
88
88
89
+
DC_FP_START();
90
+
89
91
/*Initialize SOCBB and DCNIP params */
90
92
dml21_initialize_soc_bb_params(&(*dml_ctx)->v21.dml_init, config, in_dc);
91
93
dml21_initialize_ip_params(&(*dml_ctx)->v21.dml_init, config, in_dc);
···
98
96
99
97
/*Initialize DML21 instance */
100
98
dml2_initialize_instance(&(*dml_ctx)->v21.dml_init);
99
+
100
+
DC_FP_END();
101
101
}
102
102
103
103
bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)
···
287
283
{
288
284
bool out = false;
289
285
286
+
DC_FP_START();
287
+
290
288
/* Use dml_validate_only for fast_validate path */
291
-
if (fast_validate) {
289
+
if (fast_validate)
292
290
out = dml21_check_mode_support(in_dc, context, dml_ctx);
293
-
} else
291
+
else
294
292
out = dml21_mode_check_and_programming(in_dc, context, dml_ctx);
293
+
294
+
DC_FP_END();
295
+
295
296
return out;
296
297
}
297
298
···
435
426
436
427
dst_dml_ctx->v21.mode_programming.programming = dst_dml2_programming;
437
428
429
+
DC_FP_START();
430
+
438
431
/* need to initialize copied instance for internal references to be correct */
439
432
dml2_initialize_instance(&dst_dml_ctx->v21.dml_init);
433
+
434
+
DC_FP_END();
440
435
}
441
436
442
437
bool dml21_create_copy(struct dml2_context **dst_dml_ctx,
+9
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+9
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
···
732
732
return out;
733
733
}
734
734
735
+
DC_FP_START();
736
+
735
737
/* Use dml_validate_only for fast_validate path */
736
738
if (fast_validate)
737
739
out = dml2_validate_only(context);
738
740
else
739
741
out = dml2_validate_and_build_resource(in_dc, context);
742
+
743
+
DC_FP_END();
744
+
740
745
return out;
741
746
}
742
747
···
784
779
break;
785
780
}
786
781
782
+
DC_FP_START();
783
+
787
784
initialize_dml2_ip_params(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.ip);
788
785
789
786
initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc);
790
787
791
788
initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states);
789
+
790
+
DC_FP_END();
792
791
}
793
792
794
793
bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)
+1
drivers/gpu/drm/amd/include/kgd_pp_interface.h
+1
drivers/gpu/drm/amd/include/kgd_pp_interface.h
···
429
429
int (*set_pp_table)(void *handle, const char *buf, size_t size);
430
430
void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
431
431
int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
432
+
int (*pause_power_profile)(void *handle, bool pause);
432
433
/* export to amdgpu */
433
434
struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
434
435
int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
+19
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+19
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
···
349
349
return ret;
350
350
}
351
351
352
+
int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev,
353
+
bool pause)
354
+
{
355
+
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
356
+
int ret = 0;
357
+
358
+
if (amdgpu_sriov_vf(adev))
359
+
return 0;
360
+
361
+
if (pp_funcs && pp_funcs->pause_power_profile) {
362
+
mutex_lock(&adev->pm.mutex);
363
+
ret = pp_funcs->pause_power_profile(
364
+
adev->powerplay.pp_handle, pause);
365
+
mutex_unlock(&adev->pm.mutex);
366
+
}
367
+
368
+
return ret;
369
+
}
370
+
352
371
int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
353
372
uint32_t pstate)
354
373
{
+2
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+2
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
···
410
410
int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
411
411
enum PP_SMC_POWER_PROFILE type,
412
412
bool en);
413
+
int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev,
414
+
bool pause);
413
415
414
416
int amdgpu_dpm_baco_reset(struct amdgpu_device *adev);
415
417
+35
-1
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+35
-1
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
···
2398
2398
smu_power_profile_mode_get(smu, type);
2399
2399
else
2400
2400
smu_power_profile_mode_put(smu, type);
2401
-
ret = smu_bump_power_profile_mode(smu, NULL, 0);
2401
+
/* don't switch the active workload when paused */
2402
+
if (smu->pause_workload)
2403
+
ret = 0;
2404
+
else
2405
+
ret = smu_bump_power_profile_mode(smu, NULL, 0);
2402
2406
if (ret) {
2403
2407
if (enable)
2404
2408
smu_power_profile_mode_put(smu, type);
···
2410
2406
smu_power_profile_mode_get(smu, type);
2411
2407
return ret;
2412
2408
}
2409
+
}
2410
+
2411
+
return 0;
2412
+
}
2413
+
2414
+
static int smu_pause_power_profile(void *handle,
2415
+
bool pause)
2416
+
{
2417
+
struct smu_context *smu = handle;
2418
+
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2419
+
u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
2420
+
int ret;
2421
+
2422
+
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2423
+
return -EOPNOTSUPP;
2424
+
2425
+
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2426
+
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2427
+
smu->pause_workload = pause;
2428
+
2429
+
/* force to bootup default profile */
2430
+
if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode)
2431
+
ret = smu->ppt_funcs->set_power_profile_mode(smu,
2432
+
workload_mask,
2433
+
NULL,
2434
+
0);
2435
+
else
2436
+
ret = smu_bump_power_profile_mode(smu, NULL, 0);
2437
+
return ret;
2413
2438
}
2414
2439
2415
2440
return 0;
···
3766
3733
.get_pp_table = smu_sys_get_pp_table,
3767
3734
.set_pp_table = smu_sys_set_pp_table,
3768
3735
.switch_power_profile = smu_switch_power_profile,
3736
+
.pause_power_profile = smu_pause_power_profile,
3769
3737
/* export to amdgpu */
3770
3738
.dispatch_tasks = smu_handle_dpm_task,
3771
3739
.load_firmware = smu_load_microcode,
+1
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+1
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+1
-1
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+1
-1
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+13
-1
drivers/gpu/drm/i915/display/intel_bw.c
+13
-1
drivers/gpu/drm/i915/display/intel_bw.c
···
244
244
qi->deinterleave = 4;
245
245
break;
246
246
case INTEL_DRAM_GDDR:
247
+
case INTEL_DRAM_GDDR_ECC:
247
248
qi->channel_width = 32;
248
249
break;
249
250
default:
···
395
394
396
395
static const struct intel_sa_info xe2_hpd_sa_info = {
397
396
.derating = 30,
397
+
.deprogbwlimit = 53,
398
+
/* Other values not used by simplified algorithm */
399
+
};
400
+
401
+
static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
402
+
.derating = 45,
398
403
.deprogbwlimit = 53,
399
404
/* Other values not used by simplified algorithm */
400
405
};
···
747
740
748
741
void intel_bw_init_hw(struct drm_i915_private *dev_priv)
749
742
{
743
+
const struct dram_info *dram_info = &dev_priv->dram_info;
744
+
750
745
if (!HAS_DISPLAY(dev_priv))
751
746
return;
752
747
753
-
if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))
748
+
if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv) &&
749
+
dram_info->type == INTEL_DRAM_GDDR_ECC)
750
+
xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_ecc_sa_info);
751
+
else if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))
754
752
xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info);
755
753
else if (DISPLAY_VER(dev_priv) >= 14)
756
754
tgl_get_bw_info(dev_priv, &mtl_sa_info);
+3
-1
drivers/gpu/drm/i915/display/intel_display.c
+3
-1
drivers/gpu/drm/i915/display/intel_display.c
···
968
968
old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
969
969
old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
970
970
old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
971
-
old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
971
+
old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full ||
972
+
old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start ||
973
+
old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end;
972
974
}
973
975
974
976
static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+43
-8
drivers/gpu/drm/i915/display/intel_dp.c
+43
-8
drivers/gpu/drm/i915/display/intel_dp.c
···
172
172
173
173
static int max_dprx_rate(struct intel_dp *intel_dp)
174
174
{
175
-
if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
176
-
return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
175
+
struct intel_display *display = to_intel_display(intel_dp);
176
+
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
177
+
int max_rate;
177
178
178
-
return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
179
+
if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
180
+
max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
181
+
else
182
+
max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
183
+
184
+
/*
185
+
* Some broken eDP sinks illegally declare support for
186
+
* HBR3 without TPS4, and are unable to produce a stable
187
+
* output. Reject HBR3 when TPS4 is not available.
188
+
*/
189
+
if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
190
+
drm_dbg_kms(display->drm,
191
+
"[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",
192
+
encoder->base.base.id, encoder->base.name);
193
+
max_rate = 540000;
194
+
}
195
+
196
+
return max_rate;
179
197
}
180
198
181
199
static int max_dprx_lane_count(struct intel_dp *intel_dp)
···
4188
4170
static void
4189
4171
intel_edp_set_sink_rates(struct intel_dp *intel_dp)
4190
4172
{
4173
+
struct intel_display *display = to_intel_display(intel_dp);
4174
+
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4175
+
4191
4176
intel_dp->num_sink_rates = 0;
4192
4177
4193
4178
if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
···
4201
4180
sink_rates, sizeof(sink_rates));
4202
4181
4203
4182
for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4204
-
int val = le16_to_cpu(sink_rates[i]);
4205
-
4206
-
if (val == 0)
4207
-
break;
4183
+
int rate;
4208
4184
4209
4185
/* Value read multiplied by 200kHz gives the per-lane
4210
4186
* link rate in kHz. The source rates are, however,
···
4209
4191
* back to symbols is
4210
4192
* (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4211
4193
*/
4212
-
intel_dp->sink_rates[i] = (val * 200) / 10;
4194
+
rate = le16_to_cpu(sink_rates[i]) * 200 / 10;
4195
+
4196
+
if (rate == 0)
4197
+
break;
4198
+
4199
+
/*
4200
+
* Some broken eDP sinks illegally declare support for
4201
+
* HBR3 without TPS4, and are unable to produce a stable
4202
+
* output. Reject HBR3 when TPS4 is not available.
4203
+
*/
4204
+
if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
4205
+
drm_dbg_kms(display->drm,
4206
+
"[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",
4207
+
encoder->base.base.id, encoder->base.name);
4208
+
break;
4209
+
}
4210
+
4211
+
intel_dp->sink_rates[i] = rate;
4213
4212
}
4214
4213
intel_dp->num_sink_rates = i;
4215
4214
}
+3
-1
drivers/gpu/drm/i915/display/intel_vblank.c
+3
-1
drivers/gpu/drm/i915/display/intel_vblank.c
···
222
222
* However if queried just before the start of vblank we'll get an
223
223
* answer that's slightly in the future.
224
224
*/
225
-
if (DISPLAY_VER(display) == 2)
225
+
if (DISPLAY_VER(display) >= 20 || display->platform.battlemage)
226
+
return 1;
227
+
else if (DISPLAY_VER(display) == 2)
226
228
return -1;
227
229
else if (HAS_DDI(display) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
228
230
return 2;
+4
-15
drivers/gpu/drm/i915/gt/intel_rc6.c
+4
-15
drivers/gpu/drm/i915/gt/intel_rc6.c
···
117
117
GEN6_RC_CTL_RC6_ENABLE |
118
118
GEN6_RC_CTL_EI_MODE(1);
119
119
120
-
/*
121
-
* BSpec 52698 - Render powergating must be off.
122
-
* FIXME BSpec is outdated, disabling powergating for MTL is just
123
-
* temporary wa and should be removed after fixing real cause
124
-
* of forcewake timeouts.
125
-
*/
126
-
if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
127
-
pg_enable =
128
-
GEN9_MEDIA_PG_ENABLE |
129
-
GEN11_MEDIA_SAMPLER_PG_ENABLE;
130
-
else
131
-
pg_enable =
132
-
GEN9_RENDER_PG_ENABLE |
133
-
GEN9_MEDIA_PG_ENABLE |
134
-
GEN11_MEDIA_SAMPLER_PG_ENABLE;
120
+
pg_enable =
121
+
GEN9_RENDER_PG_ENABLE |
122
+
GEN9_MEDIA_PG_ENABLE |
123
+
GEN11_MEDIA_SAMPLER_PG_ENABLE;
135
124
136
125
if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) {
137
126
for (i = 0; i < I915_MAX_VCS; i++)
+5
-6
drivers/gpu/drm/i915/gt/uc/intel_huc.c
+5
-6
drivers/gpu/drm/i915/gt/uc/intel_huc.c
···
317
317
}
318
318
}
319
319
320
+
void intel_huc_fini_late(struct intel_huc *huc)
321
+
{
322
+
delayed_huc_load_fini(huc);
323
+
}
324
+
320
325
#define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy")
321
326
static int check_huc_loading_mode(struct intel_huc *huc)
322
327
{
···
419
414
420
415
void intel_huc_fini(struct intel_huc *huc)
421
416
{
422
-
/*
423
-
* the fence is initialized in init_early, so we need to clean it up
424
-
* even if HuC loading is off.
425
-
*/
426
-
delayed_huc_load_fini(huc);
427
-
428
417
if (huc->heci_pkt)
429
418
i915_vma_unpin_and_release(&huc->heci_pkt, 0);
430
419
+1
drivers/gpu/drm/i915/gt/uc/intel_huc.h
+1
drivers/gpu/drm/i915/gt/uc/intel_huc.h
···
55
55
56
56
int intel_huc_sanitize(struct intel_huc *huc);
57
57
void intel_huc_init_early(struct intel_huc *huc);
58
+
void intel_huc_fini_late(struct intel_huc *huc);
58
59
int intel_huc_init(struct intel_huc *huc);
59
60
void intel_huc_fini(struct intel_huc *huc);
60
61
int intel_huc_auth(struct intel_huc *huc, enum intel_huc_authentication_type type);
+1
drivers/gpu/drm/i915/gt/uc/intel_uc.c
+1
drivers/gpu/drm/i915/gt/uc/intel_uc.c
+4
-3
drivers/gpu/drm/i915/gvt/opregion.c
+4
-3
drivers/gpu/drm/i915/gvt/opregion.c
···
222
222
u8 *buf;
223
223
struct opregion_header *header;
224
224
struct vbt v;
225
-
const char opregion_signature[16] = OPREGION_SIGNATURE;
226
225
227
226
gvt_dbg_core("init vgpu%d opregion\n", vgpu->id);
228
227
vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_KERNEL |
···
235
236
/* emulated opregion with VBT mailbox only */
236
237
buf = (u8 *)vgpu_opregion(vgpu)->va;
237
238
header = (struct opregion_header *)buf;
238
-
memcpy(header->signature, opregion_signature,
239
-
sizeof(opregion_signature));
239
+
240
+
static_assert(sizeof(header->signature) == sizeof(OPREGION_SIGNATURE) - 1);
241
+
memcpy(header->signature, OPREGION_SIGNATURE, sizeof(header->signature));
242
+
240
243
header->size = 0x8;
241
244
header->opregion_ver = 0x02000000;
242
245
header->mboxes = MBOX_VBT;
+1
drivers/gpu/drm/i915/i915_drv.h
+1
drivers/gpu/drm/i915/i915_drv.h
+18
drivers/gpu/drm/i915/selftests/i915_selftest.c
+18
drivers/gpu/drm/i915/selftests/i915_selftest.c
···
23
23
24
24
#include <linux/random.h>
25
25
26
+
#include "gt/intel_gt.h"
26
27
#include "gt/intel_gt_pm.h"
28
+
#include "gt/intel_gt_regs.h"
27
29
#include "gt/uc/intel_gsc_fw.h"
28
30
29
31
#include "i915_driver.h"
···
255
253
int i915_live_selftests(struct pci_dev *pdev)
256
254
{
257
255
struct drm_i915_private *i915 = pdev_to_i915(pdev);
256
+
struct intel_uncore *uncore = &i915->uncore;
258
257
int err;
258
+
u32 pg_enable;
259
+
intel_wakeref_t wakeref;
259
260
260
261
if (!i915_selftest.live)
261
262
return 0;
263
+
264
+
/*
265
+
* FIXME Disable render powergating, this is temporary wa and should be removed
266
+
* after fixing real cause of forcewake timeouts.
267
+
*/
268
+
with_intel_runtime_pm(uncore->rpm, wakeref) {
269
+
if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 00), IP_VER(12, 74))) {
270
+
pg_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
271
+
if (pg_enable & GEN9_RENDER_PG_ENABLE)
272
+
intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
273
+
pg_enable & ~GEN9_RENDER_PG_ENABLE);
274
+
}
275
+
}
262
276
263
277
__wait_gsc_proxy_completed(i915);
264
278
__wait_gsc_huc_load_completed(i915);
+4
drivers/gpu/drm/i915/soc/intel_dram.c
+4
drivers/gpu/drm/i915/soc/intel_dram.c
+20
-7
drivers/gpu/drm/imagination/pvr_fw.c
+20
-7
drivers/gpu/drm/imagination/pvr_fw.c
···
732
732
fw_mem->core_data, fw_mem->core_code_alloc_size);
733
733
734
734
if (err)
735
-
goto err_free_fw_core_data_obj;
735
+
goto err_free_kdata;
736
736
737
737
memcpy(fw_code_ptr, fw_mem->code, fw_mem->code_alloc_size);
738
738
memcpy(fw_data_ptr, fw_mem->data, fw_mem->data_alloc_size);
···
742
742
memcpy(fw_core_data_ptr, fw_mem->core_data, fw_mem->core_data_alloc_size);
743
743
744
744
/* We're finished with the firmware section memory on the CPU, unmap. */
745
-
if (fw_core_data_ptr)
745
+
if (fw_core_data_ptr) {
746
746
pvr_fw_object_vunmap(fw_mem->core_data_obj);
747
-
if (fw_core_code_ptr)
747
+
fw_core_data_ptr = NULL;
748
+
}
749
+
if (fw_core_code_ptr) {
748
750
pvr_fw_object_vunmap(fw_mem->core_code_obj);
751
+
fw_core_code_ptr = NULL;
752
+
}
749
753
pvr_fw_object_vunmap(fw_mem->data_obj);
750
754
fw_data_ptr = NULL;
751
755
pvr_fw_object_vunmap(fw_mem->code_obj);
···
757
753
758
754
err = pvr_fw_create_fwif_connection_ctl(pvr_dev);
759
755
if (err)
760
-
goto err_free_fw_core_data_obj;
756
+
goto err_free_kdata;
761
757
762
758
return 0;
763
759
···
767
763
kfree(fw_mem->data);
768
764
kfree(fw_mem->code);
769
765
770
-
err_free_fw_core_data_obj:
771
766
if (fw_core_data_ptr)
772
-
pvr_fw_object_unmap_and_destroy(fw_mem->core_data_obj);
767
+
pvr_fw_object_vunmap(fw_mem->core_data_obj);
768
+
if (fw_mem->core_data_obj)
769
+
pvr_fw_object_destroy(fw_mem->core_data_obj);
773
770
774
771
err_free_fw_core_code_obj:
775
772
if (fw_core_code_ptr)
776
-
pvr_fw_object_unmap_and_destroy(fw_mem->core_code_obj);
773
+
pvr_fw_object_vunmap(fw_mem->core_code_obj);
774
+
if (fw_mem->core_code_obj)
775
+
pvr_fw_object_destroy(fw_mem->core_code_obj);
777
776
778
777
err_free_fw_data_obj:
779
778
if (fw_data_ptr)
···
843
836
struct pvr_fw_mem *fw_mem = &pvr_dev->fw_dev.mem;
844
837
845
838
pvr_fw_fini_fwif_connection_ctl(pvr_dev);
839
+
840
+
kfree(fw_mem->core_data);
841
+
kfree(fw_mem->core_code);
842
+
kfree(fw_mem->data);
843
+
kfree(fw_mem->code);
844
+
846
845
if (fw_mem->core_code_obj)
847
846
pvr_fw_object_destroy(fw_mem->core_code_obj);
848
847
if (fw_mem->core_data_obj)
+7
drivers/gpu/drm/imagination/pvr_job.c
+7
drivers/gpu/drm/imagination/pvr_job.c
···
671
671
geom_job->paired_job = frag_job;
672
672
frag_job->paired_job = geom_job;
673
673
674
+
/* The geometry job pvr_job structure is used when the fragment
675
+
* job is being prepared by the GPU scheduler. Have the fragment
676
+
* job hold a reference on the geometry job to prevent it being
677
+
* freed until the fragment job has finished with it.
678
+
*/
679
+
pvr_job_get(geom_job);
680
+
674
681
/* Skip the fragment job we just paired to the geometry job. */
675
682
i++;
676
683
}
+4
drivers/gpu/drm/imagination/pvr_queue.c
+4
drivers/gpu/drm/imagination/pvr_queue.c
···
866
866
struct pvr_job *job = container_of(sched_job, struct pvr_job, base);
867
867
868
868
drm_sched_job_cleanup(sched_job);
869
+
870
+
if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job)
871
+
pvr_job_put(job->paired_job);
872
+
869
873
job->paired_job = NULL;
870
874
pvr_job_put(job);
871
875
}
+3
drivers/gpu/drm/nouveau/nouveau_bo.c
+3
drivers/gpu/drm/nouveau/nouveau_bo.c
···
144
144
nouveau_bo_del_io_reserve_lru(bo);
145
145
nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
146
146
147
+
if (bo->base.import_attach)
148
+
drm_prime_gem_destroy(&bo->base, bo->sg);
149
+
147
150
/*
148
151
* If nouveau_bo_new() allocated this buffer, the GEM object was never
149
152
* initialized, so don't attempt to release it.
-3
drivers/gpu/drm/nouveau/nouveau_gem.c
-3
drivers/gpu/drm/nouveau/nouveau_gem.c
+3
-20
drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
+3
-20
drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
···
94
94
struct gpio_desc *enable_gpio;
95
95
struct delayed_work hpd_work;
96
96
int port_id;
97
+
const struct rockchip_hdmi_qp_ctrl_ops *ctrl_ops;
97
98
};
98
99
99
100
struct rockchip_hdmi_qp_ctrl_ops {
···
462
461
return -ENODEV;
463
462
}
464
463
464
+
hdmi->ctrl_ops = cfg->ctrl_ops;
465
465
hdmi->dev = &pdev->dev;
466
466
hdmi->port_id = -ENODEV;
467
467
···
602
600
static int __maybe_unused dw_hdmi_qp_rockchip_resume(struct device *dev)
603
601
{
604
602
struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev);
605
-
u32 val;
606
603
607
-
val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) |
608
-
HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) |
609
-
HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) |
610
-
HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK);
611
-
regmap_write(hdmi->vo_regmap,
612
-
hdmi->port_id ? RK3588_GRF_VO1_CON6 : RK3588_GRF_VO1_CON3,
613
-
val);
614
-
615
-
val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK,
616
-
RK3588_SET_HPD_PATH_MASK);
617
-
regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val);
618
-
619
-
if (hdmi->port_id)
620
-
val = HIWORD_UPDATE(RK3588_HDMI1_GRANT_SEL,
621
-
RK3588_HDMI1_GRANT_SEL);
622
-
else
623
-
val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL,
624
-
RK3588_HDMI0_GRANT_SEL);
625
-
regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val);
604
+
hdmi->ctrl_ops->io_init(hdmi);
626
605
627
606
dw_hdmi_qp_resume(dev, hdmi->hdmi);
628
607
+3
-3
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
+3
-3
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
···
1754
1754
dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP0_PIN_POL, polflags);
1755
1755
break;
1756
1756
case ROCKCHIP_VOP2_EP_DP1:
1757
-
die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX;
1758
-
die |= RK3588_SYS_DSP_INFACE_EN_MIPI1 |
1759
-
FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id);
1757
+
die &= ~RK3588_SYS_DSP_INFACE_EN_DP1_MUX;
1758
+
die |= RK3588_SYS_DSP_INFACE_EN_DP1 |
1759
+
FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_DP1_MUX, vp->id);
1760
1760
dip &= ~RK3588_DSP_IF_POL__DP1_PIN_POL;
1761
1761
dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP1_PIN_POL, polflags);
1762
1762
break;
-2
drivers/gpu/drm/sti/Makefile
-2
drivers/gpu/drm/sti/Makefile
+8
-1
drivers/gpu/drm/tests/drm_client_modeset_test.c
+8
-1
drivers/gpu/drm/tests/drm_client_modeset_test.c
···
95
95
expected_mode = drm_mode_find_dmt(priv->drm, 1920, 1080, 60, false);
96
96
KUNIT_ASSERT_NOT_NULL(test, expected_mode);
97
97
98
+
ret = drm_kunit_add_mode_destroy_action(test, expected_mode);
99
+
KUNIT_ASSERT_EQ(test, ret, 0);
100
+
98
101
KUNIT_ASSERT_TRUE(test,
99
102
drm_mode_parse_command_line_for_connector(cmdline,
100
103
connector,
···
132
129
struct drm_device *drm = priv->drm;
133
130
struct drm_connector *connector = &priv->connector;
134
131
struct drm_cmdline_mode *cmdline_mode = &connector->cmdline_mode;
135
-
const struct drm_display_mode *expected_mode, *mode;
132
+
const struct drm_display_mode *mode;
133
+
struct drm_display_mode *expected_mode;
136
134
const char *cmdline = params->cmdline;
137
135
int ret;
138
136
···
152
148
153
149
expected_mode = params->func(drm);
154
150
KUNIT_ASSERT_NOT_NULL(test, expected_mode);
151
+
152
+
ret = drm_kunit_add_mode_destroy_action(test, expected_mode);
153
+
KUNIT_ASSERT_EQ(test, ret, 0);
155
154
156
155
KUNIT_EXPECT_TRUE(test, drm_mode_equal(expected_mode, mode));
157
156
}
+9
-1
drivers/gpu/drm/tests/drm_cmdline_parser_test.c
+9
-1
drivers/gpu/drm/tests/drm_cmdline_parser_test.c
···
7
7
#include <kunit/test.h>
8
8
9
9
#include <drm/drm_connector.h>
10
+
#include <drm/drm_kunit_helpers.h>
10
11
#include <drm/drm_modes.h>
11
12
12
13
static const struct drm_connector no_connector = {};
···
956
955
static void drm_test_cmdline_tv_options(struct kunit *test)
957
956
{
958
957
const struct drm_cmdline_tv_option_test *params = test->param_value;
959
-
const struct drm_display_mode *expected_mode = params->mode_fn(NULL);
958
+
struct drm_display_mode *expected_mode;
960
959
struct drm_cmdline_mode mode = { };
960
+
int ret;
961
+
962
+
expected_mode = params->mode_fn(NULL);
963
+
KUNIT_ASSERT_NOT_NULL(test, expected_mode);
964
+
965
+
ret = drm_kunit_add_mode_destroy_action(test, expected_mode);
966
+
KUNIT_ASSERT_EQ(test, ret, 0);
961
967
962
968
KUNIT_EXPECT_TRUE(test, drm_mode_parse_command_line_for_connector(params->cmdline,
963
969
&no_connector, &mode));
+22
drivers/gpu/drm/tests/drm_kunit_helpers.c
+22
drivers/gpu/drm/tests/drm_kunit_helpers.c
···
279
279
}
280
280
281
281
/**
282
+
* drm_kunit_add_mode_destroy_action() - Add a drm_destroy_mode kunit action
283
+
* @test: The test context object
284
+
* @mode: The drm_display_mode to destroy eventually
285
+
*
286
+
* Registers a kunit action that will destroy the drm_display_mode at
287
+
* the end of the test.
288
+
*
289
+
* If an error occurs, the drm_display_mode will be destroyed.
290
+
*
291
+
* Returns:
292
+
* 0 on success, an error code otherwise.
293
+
*/
294
+
int drm_kunit_add_mode_destroy_action(struct kunit *test,
295
+
struct drm_display_mode *mode)
296
+
{
297
+
return kunit_add_action_or_reset(test,
298
+
kunit_action_drm_mode_destroy,
299
+
mode);
300
+
}
301
+
EXPORT_SYMBOL_GPL(drm_kunit_add_mode_destroy_action);
302
+
303
+
/**
282
304
* drm_kunit_display_mode_from_cea_vic() - return a mode for CEA VIC for a KUnit test
283
305
* @test: The test context object
284
306
* @dev: DRM device
+26
drivers/gpu/drm/tests/drm_modes_test.c
+26
drivers/gpu/drm/tests/drm_modes_test.c
···
40
40
{
41
41
struct drm_test_modes_priv *priv = test->priv;
42
42
struct drm_display_mode *mode;
43
+
int ret;
43
44
44
45
mode = drm_analog_tv_mode(priv->drm,
45
46
DRM_MODE_TV_MODE_NTSC,
46
47
13500 * HZ_PER_KHZ, 720, 480,
47
48
true);
48
49
KUNIT_ASSERT_NOT_NULL(test, mode);
50
+
51
+
ret = drm_kunit_add_mode_destroy_action(test, mode);
52
+
KUNIT_ASSERT_EQ(test, ret, 0);
49
53
50
54
KUNIT_EXPECT_EQ(test, drm_mode_vrefresh(mode), 60);
51
55
KUNIT_EXPECT_EQ(test, mode->hdisplay, 720);
···
74
70
{
75
71
struct drm_test_modes_priv *priv = test->priv;
76
72
struct drm_display_mode *expected, *mode;
73
+
int ret;
77
74
78
75
expected = drm_analog_tv_mode(priv->drm,
79
76
DRM_MODE_TV_MODE_NTSC,
···
82
77
true);
83
78
KUNIT_ASSERT_NOT_NULL(test, expected);
84
79
80
+
ret = drm_kunit_add_mode_destroy_action(test, expected);
81
+
KUNIT_ASSERT_EQ(test, ret, 0);
82
+
85
83
mode = drm_mode_analog_ntsc_480i(priv->drm);
86
84
KUNIT_ASSERT_NOT_NULL(test, mode);
85
+
86
+
ret = drm_kunit_add_mode_destroy_action(test, mode);
87
+
KUNIT_ASSERT_EQ(test, ret, 0);
87
88
88
89
KUNIT_EXPECT_TRUE(test, drm_mode_equal(expected, mode));
89
90
}
···
98
87
{
99
88
struct drm_test_modes_priv *priv = test->priv;
100
89
struct drm_display_mode *mode;
90
+
int ret;
101
91
102
92
mode = drm_analog_tv_mode(priv->drm,
103
93
DRM_MODE_TV_MODE_PAL,
104
94
13500 * HZ_PER_KHZ, 720, 576,
105
95
true);
106
96
KUNIT_ASSERT_NOT_NULL(test, mode);
97
+
98
+
ret = drm_kunit_add_mode_destroy_action(test, mode);
99
+
KUNIT_ASSERT_EQ(test, ret, 0);
107
100
108
101
KUNIT_EXPECT_EQ(test, drm_mode_vrefresh(mode), 50);
109
102
KUNIT_EXPECT_EQ(test, mode->hdisplay, 720);
···
132
117
{
133
118
struct drm_test_modes_priv *priv = test->priv;
134
119
struct drm_display_mode *expected, *mode;
120
+
int ret;
135
121
136
122
expected = drm_analog_tv_mode(priv->drm,
137
123
DRM_MODE_TV_MODE_PAL,
···
140
124
true);
141
125
KUNIT_ASSERT_NOT_NULL(test, expected);
142
126
127
+
ret = drm_kunit_add_mode_destroy_action(test, expected);
128
+
KUNIT_ASSERT_EQ(test, ret, 0);
129
+
143
130
mode = drm_mode_analog_pal_576i(priv->drm);
144
131
KUNIT_ASSERT_NOT_NULL(test, mode);
132
+
133
+
ret = drm_kunit_add_mode_destroy_action(test, mode);
134
+
KUNIT_ASSERT_EQ(test, ret, 0);
145
135
146
136
KUNIT_EXPECT_TRUE(test, drm_mode_equal(expected, mode));
147
137
}
···
156
134
{
157
135
struct drm_test_modes_priv *priv = test->priv;
158
136
struct drm_display_mode *mode;
137
+
int ret;
159
138
160
139
mode = drm_analog_tv_mode(priv->drm,
161
140
DRM_MODE_TV_MODE_MONOCHROME,
162
141
13500 * HZ_PER_KHZ, 720, 576,
163
142
true);
164
143
KUNIT_ASSERT_NOT_NULL(test, mode);
144
+
145
+
ret = drm_kunit_add_mode_destroy_action(test, mode);
146
+
KUNIT_ASSERT_EQ(test, ret, 0);
165
147
166
148
KUNIT_EXPECT_EQ(test, drm_mode_vrefresh(mode), 50);
167
149
KUNIT_EXPECT_EQ(test, mode->hdisplay, 720);
+7
-1
drivers/gpu/drm/tests/drm_probe_helper_test.c
+7
-1
drivers/gpu/drm/tests/drm_probe_helper_test.c
···
98
98
struct drm_connector *connector = &priv->connector;
99
99
struct drm_cmdline_mode *cmdline = &connector->cmdline_mode;
100
100
struct drm_display_mode *mode;
101
-
const struct drm_display_mode *expected;
101
+
struct drm_display_mode *expected;
102
102
size_t len;
103
103
int ret;
104
104
···
134
134
135
135
KUNIT_EXPECT_TRUE(test, drm_mode_equal(mode, expected));
136
136
KUNIT_EXPECT_TRUE(test, mode->type & DRM_MODE_TYPE_PREFERRED);
137
+
138
+
ret = drm_kunit_add_mode_destroy_action(test, expected);
139
+
KUNIT_ASSERT_EQ(test, ret, 0);
137
140
}
138
141
139
142
if (params->num_expected_modes >= 2) {
···
148
145
149
146
KUNIT_EXPECT_TRUE(test, drm_mode_equal(mode, expected));
150
147
KUNIT_EXPECT_FALSE(test, mode->type & DRM_MODE_TYPE_PREFERRED);
148
+
149
+
ret = drm_kunit_add_mode_destroy_action(test, expected);
150
+
KUNIT_ASSERT_EQ(test, ret, 0);
151
151
}
152
152
153
153
mutex_unlock(&priv->drm->mode_config.mutex);
+6
-5
drivers/gpu/drm/virtio/virtgpu_gem.c
+6
-5
drivers/gpu/drm/virtio/virtgpu_gem.c
···
115
115
if (!vgdev->has_context_init)
116
116
virtio_gpu_create_context(obj->dev, file);
117
117
118
-
objs = virtio_gpu_array_alloc(1);
119
-
if (!objs)
120
-
return -ENOMEM;
121
-
virtio_gpu_array_add_obj(objs, obj);
118
+
if (vfpriv->context_created) {
119
+
objs = virtio_gpu_array_alloc(1);
120
+
if (!objs)
121
+
return -ENOMEM;
122
+
virtio_gpu_array_add_obj(objs, obj);
122
123
123
-
if (vfpriv->ctx_id)
124
124
virtio_gpu_cmd_context_attach_resource(vgdev, vfpriv->ctx_id, objs);
125
+
}
125
126
126
127
out_notify:
127
128
virtio_gpu_notify(vgdev);
+14
-6
drivers/gpu/drm/virtio/virtgpu_plane.c
+14
-6
drivers/gpu/drm/virtio/virtgpu_plane.c
···
366
366
return 0;
367
367
368
368
obj = new_state->fb->obj[0];
369
-
if (obj->import_attach) {
370
-
ret = virtio_gpu_prepare_imported_obj(plane, new_state, obj);
371
-
if (ret)
372
-
return ret;
373
-
}
374
-
375
369
if (bo->dumb || obj->import_attach) {
376
370
vgplane_st->fence = virtio_gpu_fence_alloc(vgdev,
377
371
vgdev->fence_drv.context,
···
374
380
return -ENOMEM;
375
381
}
376
382
383
+
if (obj->import_attach) {
384
+
ret = virtio_gpu_prepare_imported_obj(plane, new_state, obj);
385
+
if (ret)
386
+
goto err_fence;
387
+
}
388
+
377
389
return 0;
390
+
391
+
err_fence:
392
+
if (vgplane_st->fence) {
393
+
dma_fence_put(&vgplane_st->fence->f);
394
+
vgplane_st->fence = NULL;
395
+
}
396
+
397
+
return ret;
378
398
}
379
399
380
400
static void virtio_gpu_cleanup_imported_obj(struct drm_gem_object *obj)
+1
drivers/gpu/drm/virtio/virtgpu_prime.c
+1
drivers/gpu/drm/virtio/virtgpu_prime.c
+1
drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
+1
drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
···
41
41
42
42
#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
43
43
44
+
#define PIPE_CONTROL0_L3_READ_ONLY_CACHE_INVALIDATE BIT(10) /* gen12 */
44
45
#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */
45
46
46
47
#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29)
+1
drivers/gpu/drm/xe/xe_device_types.h
+1
drivers/gpu/drm/xe/xe_device_types.h
+10
-2
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
+10
-2
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
···
322
322
return 0;
323
323
}
324
324
325
+
/*
326
+
* Ensure that roundup_pow_of_two(length) doesn't overflow.
327
+
* Note that roundup_pow_of_two() operates on unsigned long,
328
+
* not on u64.
329
+
*/
330
+
#define MAX_RANGE_TLB_INVALIDATION_LENGTH (rounddown_pow_of_two(ULONG_MAX))
331
+
325
332
/**
326
333
* xe_gt_tlb_invalidation_range - Issue a TLB invalidation on this GT for an
327
334
* address range
···
353
346
struct xe_device *xe = gt_to_xe(gt);
354
347
#define MAX_TLB_INVALIDATION_LEN 7
355
348
u32 action[MAX_TLB_INVALIDATION_LEN];
349
+
u64 length = end - start;
356
350
int len = 0;
357
351
358
352
xe_gt_assert(gt, fence);
···
366
358
367
359
action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
368
360
action[len++] = 0; /* seqno, replaced in send_tlb_invalidation */
369
-
if (!xe->info.has_range_tlb_invalidation) {
361
+
if (!xe->info.has_range_tlb_invalidation ||
362
+
length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
370
363
action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
371
364
} else {
372
365
u64 orig_start = start;
373
-
u64 length = end - start;
374
366
u64 align;
375
367
376
368
if (length < SZ_4K)
+1
drivers/gpu/drm/xe/xe_guc_pc.c
+1
drivers/gpu/drm/xe/xe_guc_pc.c
+6
-6
drivers/gpu/drm/xe/xe_hw_engine.c
+6
-6
drivers/gpu/drm/xe/xe_hw_engine.c
···
389
389
blit_cctl_val,
390
390
XE_RTP_ACTION_FLAG(ENGINE_BASE)))
391
391
},
392
-
/* Use Fixed slice CCS mode */
393
-
{ XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"),
394
-
XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)),
395
-
XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
396
-
RCU_MODE_FIXED_SLICE_CCS_MODE))
397
-
},
398
392
/* Disable WMTP if HW doesn't support it */
399
393
{ XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
400
394
XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
···
454
460
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
455
461
XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,
456
462
XE_RTP_ACTION_FLAG(ENGINE_BASE)))
463
+
},
464
+
/* Use Fixed slice CCS mode */
465
+
{ XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"),
466
+
XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)),
467
+
XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
468
+
RCU_MODE_FIXED_SLICE_CCS_MODE))
457
469
},
458
470
};
459
471
+52
-56
drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.c
+52
-56
drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.c
···
32
32
return timeout >= min && timeout <= max;
33
33
}
34
34
35
-
static void kobj_xe_hw_engine_release(struct kobject *kobj)
35
+
static void xe_hw_engine_sysfs_kobj_release(struct kobject *kobj)
36
36
{
37
37
kfree(kobj);
38
38
}
39
39
40
+
static ssize_t xe_hw_engine_class_sysfs_attr_show(struct kobject *kobj,
41
+
struct attribute *attr,
42
+
char *buf)
43
+
{
44
+
struct xe_device *xe = kobj_to_xe(kobj);
45
+
struct kobj_attribute *kattr;
46
+
ssize_t ret = -EIO;
47
+
48
+
kattr = container_of(attr, struct kobj_attribute, attr);
49
+
if (kattr->show) {
50
+
xe_pm_runtime_get(xe);
51
+
ret = kattr->show(kobj, kattr, buf);
52
+
xe_pm_runtime_put(xe);
53
+
}
54
+
55
+
return ret;
56
+
}
57
+
58
+
static ssize_t xe_hw_engine_class_sysfs_attr_store(struct kobject *kobj,
59
+
struct attribute *attr,
60
+
const char *buf,
61
+
size_t count)
62
+
{
63
+
struct xe_device *xe = kobj_to_xe(kobj);
64
+
struct kobj_attribute *kattr;
65
+
ssize_t ret = -EIO;
66
+
67
+
kattr = container_of(attr, struct kobj_attribute, attr);
68
+
if (kattr->store) {
69
+
xe_pm_runtime_get(xe);
70
+
ret = kattr->store(kobj, kattr, buf, count);
71
+
xe_pm_runtime_put(xe);
72
+
}
73
+
74
+
return ret;
75
+
}
76
+
77
+
static const struct sysfs_ops xe_hw_engine_class_sysfs_ops = {
78
+
.show = xe_hw_engine_class_sysfs_attr_show,
79
+
.store = xe_hw_engine_class_sysfs_attr_store,
80
+
};
81
+
40
82
static const struct kobj_type kobj_xe_hw_engine_type = {
41
-
.release = kobj_xe_hw_engine_release,
42
-
.sysfs_ops = &kobj_sysfs_ops
83
+
.release = xe_hw_engine_sysfs_kobj_release,
84
+
.sysfs_ops = &xe_hw_engine_class_sysfs_ops,
85
+
};
86
+
87
+
static const struct kobj_type kobj_xe_hw_engine_type_def = {
88
+
.release = xe_hw_engine_sysfs_kobj_release,
89
+
.sysfs_ops = &kobj_sysfs_ops,
43
90
};
44
91
45
92
static ssize_t job_timeout_max_store(struct kobject *kobj,
···
590
543
if (!kobj)
591
544
return -ENOMEM;
592
545
593
-
kobject_init(kobj, &kobj_xe_hw_engine_type);
546
+
kobject_init(kobj, &kobj_xe_hw_engine_type_def);
594
547
err = kobject_add(kobj, parent, "%s", ".defaults");
595
548
if (err)
596
549
goto err_object;
···
606
559
return err;
607
560
}
608
561
609
-
static void xe_hw_engine_sysfs_kobj_release(struct kobject *kobj)
610
-
{
611
-
kfree(kobj);
612
-
}
613
-
614
-
static ssize_t xe_hw_engine_class_sysfs_attr_show(struct kobject *kobj,
615
-
struct attribute *attr,
616
-
char *buf)
617
-
{
618
-
struct xe_device *xe = kobj_to_xe(kobj);
619
-
struct kobj_attribute *kattr;
620
-
ssize_t ret = -EIO;
621
-
622
-
kattr = container_of(attr, struct kobj_attribute, attr);
623
-
if (kattr->show) {
624
-
xe_pm_runtime_get(xe);
625
-
ret = kattr->show(kobj, kattr, buf);
626
-
xe_pm_runtime_put(xe);
627
-
}
628
-
629
-
return ret;
630
-
}
631
-
632
-
static ssize_t xe_hw_engine_class_sysfs_attr_store(struct kobject *kobj,
633
-
struct attribute *attr,
634
-
const char *buf,
635
-
size_t count)
636
-
{
637
-
struct xe_device *xe = kobj_to_xe(kobj);
638
-
struct kobj_attribute *kattr;
639
-
ssize_t ret = -EIO;
640
-
641
-
kattr = container_of(attr, struct kobj_attribute, attr);
642
-
if (kattr->store) {
643
-
xe_pm_runtime_get(xe);
644
-
ret = kattr->store(kobj, kattr, buf, count);
645
-
xe_pm_runtime_put(xe);
646
-
}
647
-
648
-
return ret;
649
-
}
650
-
651
-
static const struct sysfs_ops xe_hw_engine_class_sysfs_ops = {
652
-
.show = xe_hw_engine_class_sysfs_attr_show,
653
-
.store = xe_hw_engine_class_sysfs_attr_store,
654
-
};
655
-
656
-
static const struct kobj_type xe_hw_engine_sysfs_kobj_type = {
657
-
.release = xe_hw_engine_sysfs_kobj_release,
658
-
.sysfs_ops = &xe_hw_engine_class_sysfs_ops,
659
-
};
660
562
661
563
static void hw_engine_class_sysfs_fini(void *arg)
662
564
{
···
636
640
if (!kobj)
637
641
return -ENOMEM;
638
642
639
-
kobject_init(kobj, &xe_hw_engine_sysfs_kobj_type);
643
+
kobject_init(kobj, &kobj_xe_hw_engine_type);
640
644
641
645
err = kobject_add(kobj, gt->sysfs, "engines");
642
646
if (err)
+3
-3
drivers/gpu/drm/xe/xe_migrate.c
+3
-3
drivers/gpu/drm/xe/xe_migrate.c
···
1177
1177
err_sync:
1178
1178
/* Sync partial copies if any. FIXME: job_mutex? */
1179
1179
if (fence) {
1180
-
dma_fence_wait(m->fence, false);
1180
+
dma_fence_wait(fence, false);
1181
1181
dma_fence_put(fence);
1182
1182
}
1183
1183
···
1547
1547
static u32 pte_update_cmd_size(u64 size)
1548
1548
{
1549
1549
u32 num_dword;
1550
-
u64 entries = DIV_ROUND_UP(size, XE_PAGE_SIZE);
1550
+
u64 entries = DIV_U64_ROUND_UP(size, XE_PAGE_SIZE);
1551
1551
1552
1552
XE_WARN_ON(size > MAX_PREEMPTDISABLE_TRANSFER);
1553
1553
/*
···
1558
1558
* 2 dword for the page table's physical location
1559
1559
* 2*n dword for value of pte to fill (each pte entry is 2 dwords)
1560
1560
*/
1561
-
num_dword = (1 + 2) * DIV_ROUND_UP(entries, 0x1ff);
1561
+
num_dword = (1 + 2) * DIV_U64_ROUND_UP(entries, 0x1ff);
1562
1562
num_dword += entries * 2;
1563
1563
1564
1564
return num_dword;
+9
-4
drivers/gpu/drm/xe/xe_ring_ops.c
+9
-4
drivers/gpu/drm/xe/xe_ring_ops.c
···
137
137
static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw,
138
138
int i)
139
139
{
140
-
u32 flags = PIPE_CONTROL_CS_STALL |
140
+
u32 flags0 = 0;
141
+
u32 flags1 = PIPE_CONTROL_CS_STALL |
141
142
PIPE_CONTROL_COMMAND_CACHE_INVALIDATE |
142
143
PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
143
144
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
···
149
148
PIPE_CONTROL_STORE_DATA_INDEX;
150
149
151
150
if (invalidate_tlb)
152
-
flags |= PIPE_CONTROL_TLB_INVALIDATE;
151
+
flags1 |= PIPE_CONTROL_TLB_INVALIDATE;
153
152
154
-
flags &= ~mask_flags;
153
+
flags1 &= ~mask_flags;
155
154
156
-
return emit_pipe_control(dw, i, 0, flags, LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR, 0);
155
+
if (flags1 & PIPE_CONTROL_VF_CACHE_INVALIDATE)
156
+
flags0 |= PIPE_CONTROL0_L3_READ_ONLY_CACHE_INVALIDATE;
157
+
158
+
return emit_pipe_control(dw, i, flags0, flags1,
159
+
LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR, 0);
157
160
}
158
161
159
162
static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
+5
-2
drivers/gpu/drm/xe/xe_svm.c
+5
-2
drivers/gpu/drm/xe/xe_svm.c
···
696
696
list_for_each_entry(block, blocks, link)
697
697
block->private = vr;
698
698
699
+
xe_bo_get(bo);
699
700
err = drm_gpusvm_migrate_to_devmem(&vm->svm.gpusvm, &range->base,
700
701
&bo->devmem_allocation, ctx);
701
-
xe_bo_unlock(bo);
702
702
if (err)
703
-
xe_bo_put(bo); /* Creation ref */
703
+
xe_svm_devmem_release(&bo->devmem_allocation);
704
+
705
+
xe_bo_unlock(bo);
706
+
xe_bo_put(bo);
704
707
705
708
unlock:
706
709
mmap_read_unlock(mm);
+2
drivers/gpu/drm/xe/xe_wa_oob.rules
+2
drivers/gpu/drm/xe/xe_wa_oob.rules
···
32
32
GRAPHICS_VERSION(3001)
33
33
14022293748 GRAPHICS_VERSION(2001)
34
34
GRAPHICS_VERSION(2004)
35
+
GRAPHICS_VERSION_RANGE(3000, 3001)
35
36
22019794406 GRAPHICS_VERSION(2001)
36
37
GRAPHICS_VERSION(2004)
38
+
GRAPHICS_VERSION_RANGE(3000, 3001)
37
39
22019338487 MEDIA_VERSION(2000)
38
40
GRAPHICS_VERSION(2001)
39
41
MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_not_sriov_vf)
+3
include/drm/drm_kunit_helpers.h
+3
include/drm/drm_kunit_helpers.h
···
118
118
const struct drm_crtc_funcs *funcs,
119
119
const struct drm_crtc_helper_funcs *helper_funcs);
120
120
121
+
int drm_kunit_add_mode_destroy_action(struct kunit *test,
122
+
struct drm_display_mode *mode);
123
+
121
124
struct drm_display_mode *
122
125
drm_kunit_display_mode_from_cea_vic(struct kunit *test, struct drm_device *dev,
123
126
u8 video_code);
+1
include/drm/intel/pciids.h
+1
include/drm/intel/pciids.h