Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'iommu-fixes-v5.4-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel:
- Fixes for page-table issues on Mali GPUs
- Missing free in an error path for ARM-SMMU
- PASID decoding in the AMD IOMMU Event log code
- Another update for the locking fixes in the AMD IOMMU driver
- Reduce the calls to platform_get_irq() in the IPMMU-VMSA and Rockchip
IOMMUs to get rid of the warning message added to this function
recently
* tag 'iommu-fixes-v5.4-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/amd: Check PM_LEVEL_SIZE() condition in locked section
iommu/amd: Fix incorrect PASID decoding from event log
iommu/ipmmu-vmsa: Only call platform_get_irq() when interrupt is mandatory
iommu/rockchip: Don't use platform_get_irq to implicitly count irqs
iommu/io-pgtable-arm: Support all Mali configurations
iommu/io-pgtable-arm: Correct Mali attributes
iommu/arm-smmu: Free context bitmap in the err path of arm_smmu_init_domain_context
+70
-27
+7
-5
drivers/iommu/amd_iommu.c
+7
-5
drivers/iommu/amd_iommu.c
···
583
583
retry:
584
584
type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
585
585
devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
586
-
pasid = PPR_PASID(*(u64 *)&event[0]);
586
+
pasid = (event[0] & EVENT_DOMID_MASK_HI) |
587
+
(event[1] & EVENT_DOMID_MASK_LO);
587
588
flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
588
589
address = (u64)(((u64)event[3]) << 32) | event[2];
589
590
···
617
616
address, flags);
618
617
break;
619
618
case EVENT_TYPE_PAGE_TAB_ERR:
620
-
dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
619
+
dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
621
620
PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
622
621
pasid, address, flags);
623
622
break;
···
1464
1463
* to 64 bits.
1465
1464
*/
1466
1465
static bool increase_address_space(struct protection_domain *domain,
1466
+
unsigned long address,
1467
1467
gfp_t gfp)
1468
1468
{
1469
1469
unsigned long flags;
···
1473
1471
1474
1472
spin_lock_irqsave(&domain->lock, flags);
1475
1473
1476
-
if (WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
1477
-
/* address space already 64 bit large */
1474
+
if (address <= PM_LEVEL_SIZE(domain->mode) ||
1475
+
WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
1478
1476
goto out;
1479
1477
1480
1478
pte = (void *)get_zeroed_page(gfp);
···
1507
1505
BUG_ON(!is_power_of_2(page_size));
1508
1506
1509
1507
while (address > PM_LEVEL_SIZE(domain->mode))
1510
-
*updated = increase_address_space(domain, gfp) || *updated;
1508
+
*updated = increase_address_space(domain, address, gfp) || *updated;
1511
1509
1512
1510
level = domain->mode - 1;
1513
1511
pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
+2
-2
drivers/iommu/amd_iommu_types.h
+2
-2
drivers/iommu/amd_iommu_types.h
···
130
130
#define EVENT_TYPE_INV_PPR_REQ 0x9
131
131
#define EVENT_DEVID_MASK 0xffff
132
132
#define EVENT_DEVID_SHIFT 0
133
-
#define EVENT_DOMID_MASK 0xffff
134
-
#define EVENT_DOMID_SHIFT 0
133
+
#define EVENT_DOMID_MASK_LO 0xffff
134
+
#define EVENT_DOMID_MASK_HI 0xf0000
135
135
#define EVENT_FLAGS_MASK 0xfff
136
136
#define EVENT_FLAGS_SHIFT 0x10
137
137
+1
drivers/iommu/arm-smmu.c
+1
drivers/iommu/arm-smmu.c
+45
-13
drivers/iommu/io-pgtable-arm.c
+45
-13
drivers/iommu/io-pgtable-arm.c
···
166
166
#define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2)
167
167
#define ARM_MALI_LPAE_TTBR_SHARE_OUTER BIT(4)
168
168
169
+
#define ARM_MALI_LPAE_MEMATTR_IMP_DEF 0x88ULL
170
+
#define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL
171
+
169
172
/* IOPTE accessors */
170
173
#define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
171
174
···
1018
1015
static struct io_pgtable *
1019
1016
arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
1020
1017
{
1021
-
struct io_pgtable *iop;
1018
+
struct arm_lpae_io_pgtable *data;
1022
1019
1023
-
if (cfg->ias != 48 || cfg->oas > 40)
1020
+
/* No quirks for Mali (hopefully) */
1021
+
if (cfg->quirks)
1022
+
return NULL;
1023
+
1024
+
if (cfg->ias > 48 || cfg->oas > 40)
1024
1025
return NULL;
1025
1026
1026
1027
cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
1027
-
iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
1028
-
if (iop) {
1029
-
u64 mair, ttbr;
1030
1028
1031
-
/* Copy values as union fields overlap */
1032
-
mair = cfg->arm_lpae_s1_cfg.mair[0];
1033
-
ttbr = cfg->arm_lpae_s1_cfg.ttbr[0];
1029
+
data = arm_lpae_alloc_pgtable(cfg);
1030
+
if (!data)
1031
+
return NULL;
1034
1032
1035
-
cfg->arm_mali_lpae_cfg.memattr = mair;
1036
-
cfg->arm_mali_lpae_cfg.transtab = ttbr |
1037
-
ARM_MALI_LPAE_TTBR_READ_INNER |
1038
-
ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
1033
+
/* Mali seems to need a full 4-level table regardless of IAS */
1034
+
if (data->levels < ARM_LPAE_MAX_LEVELS) {
1035
+
data->levels = ARM_LPAE_MAX_LEVELS;
1036
+
data->pgd_size = sizeof(arm_lpae_iopte);
1039
1037
}
1038
+
/*
1039
+
* MEMATTR: Mali has no actual notion of a non-cacheable type, so the
1040
+
* best we can do is mimic the out-of-tree driver and hope that the
1041
+
* "implementation-defined caching policy" is good enough. Similarly,
1042
+
* we'll use it for the sake of a valid attribute for our 'device'
1043
+
* index, although callers should never request that in practice.
1044
+
*/
1045
+
cfg->arm_mali_lpae_cfg.memattr =
1046
+
(ARM_MALI_LPAE_MEMATTR_IMP_DEF
1047
+
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
1048
+
(ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC
1049
+
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
1050
+
(ARM_MALI_LPAE_MEMATTR_IMP_DEF
1051
+
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
1040
1052
1041
-
return iop;
1053
+
data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
1054
+
if (!data->pgd)
1055
+
goto out_free_data;
1056
+
1057
+
/* Ensure the empty pgd is visible before TRANSTAB can be written */
1058
+
wmb();
1059
+
1060
+
cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
1061
+
ARM_MALI_LPAE_TTBR_READ_INNER |
1062
+
ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
1063
+
return &data->iop;
1064
+
1065
+
out_free_data:
1066
+
kfree(data);
1067
+
return NULL;
1042
1068
}
1043
1069
1044
1070
struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
+1
-2
drivers/iommu/ipmmu-vmsa.c
+1
-2
drivers/iommu/ipmmu-vmsa.c
···
1086
1086
1087
1087
mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts);
1088
1088
1089
-
irq = platform_get_irq(pdev, 0);
1090
-
1091
1089
/*
1092
1090
* Determine if this IPMMU instance is a root device by checking for
1093
1091
* the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property.
···
1104
1106
1105
1107
/* Root devices have mandatory IRQs */
1106
1108
if (ipmmu_is_root(mmu)) {
1109
+
irq = platform_get_irq(pdev, 0);
1107
1110
if (irq < 0) {
1108
1111
dev_err(&pdev->dev, "no IRQ found\n");
1109
1112
return irq;
+14
-5
drivers/iommu/rockchip-iommu.c
+14
-5
drivers/iommu/rockchip-iommu.c
···
100
100
struct device *dev;
101
101
void __iomem **bases;
102
102
int num_mmu;
103
+
int num_irq;
103
104
struct clk_bulk_data *clocks;
104
105
int num_clocks;
105
106
bool reset_disabled;
···
1137
1136
struct rk_iommu *iommu;
1138
1137
struct resource *res;
1139
1138
int num_res = pdev->num_resources;
1140
-
int err, i, irq;
1139
+
int err, i;
1141
1140
1142
1141
iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
1143
1142
if (!iommu)
···
1163
1162
}
1164
1163
if (iommu->num_mmu == 0)
1165
1164
return PTR_ERR(iommu->bases[0]);
1165
+
1166
+
iommu->num_irq = platform_irq_count(pdev);
1167
+
if (iommu->num_irq < 0)
1168
+
return iommu->num_irq;
1166
1169
1167
1170
iommu->reset_disabled = device_property_read_bool(dev,
1168
1171
"rockchip,disable-mmu-reset");
···
1224
1219
1225
1220
pm_runtime_enable(dev);
1226
1221
1227
-
i = 0;
1228
-
while ((irq = platform_get_irq(pdev, i++)) != -ENXIO) {
1222
+
for (i = 0; i < iommu->num_irq; i++) {
1223
+
int irq = platform_get_irq(pdev, i);
1224
+
1229
1225
if (irq < 0)
1230
1226
return irq;
1231
1227
···
1251
1245
static void rk_iommu_shutdown(struct platform_device *pdev)
1252
1246
{
1253
1247
struct rk_iommu *iommu = platform_get_drvdata(pdev);
1254
-
int i = 0, irq;
1248
+
int i;
1255
1249
1256
-
while ((irq = platform_get_irq(pdev, i++)) != -ENXIO)
1250
+
for (i = 0; i < iommu->num_irq; i++) {
1251
+
int irq = platform_get_irq(pdev, i);
1252
+
1257
1253
devm_free_irq(iommu->dev, irq, iommu);
1254
+
}
1258
1255
1259
1256
pm_runtime_force_suspend(&pdev->dev);
1260
1257
}