Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: qcom: Add Hawi pinctrl driver
Add pinctrl driver for TLMM block found in the Hawi SoC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
authored by
Mukesh Ojha
and committed by
Linus Walleij
90700e10
ec25710c
+1621
+10
drivers/pinctrl/qcom/Kconfig.msm
+10
drivers/pinctrl/qcom/Kconfig.msm
···
35
35
Say Y here to compile statically, or M here to compile it as a module.
36
36
If unsure, say N.
37
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38
+
config PINCTRL_HAWI
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tristate "Qualcomm Technologies Inc Hawi pin controller driver"
40
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depends on ARM64 || COMPILE_TEST
41
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help
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This is the pinctrl, pinmux, pinconf and gpiolib driver for the
43
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Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
44
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block found on the Qualcomm Technologies Inc Hawi platform.
45
+
Say Y here to compile statically, or M here to compile it as a module.
46
+
If unsure, say N.
47
+
38
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config PINCTRL_IPQ4019
39
49
tristate "Qualcomm IPQ4019 pin controller driver"
40
50
depends on ARM || COMPILE_TEST
+1
drivers/pinctrl/qcom/Makefile
+1
drivers/pinctrl/qcom/Makefile
···
5
5
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
6
6
obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o
7
7
obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o
8
+
obj-$(CONFIG_PINCTRL_HAWI) += pinctrl-hawi.o
8
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obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
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obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
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obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
+1610
drivers/pinctrl/qcom/pinctrl-hawi.c
+1610
drivers/pinctrl/qcom/pinctrl-hawi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/module.h>
7
+
#include <linux/of.h>
8
+
#include <linux/platform_device.h>
9
+
10
+
#include "pinctrl-msm.h"
11
+
12
+
#define REG_SIZE 0x1000
13
+
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
14
+
{ \
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.grp = PINCTRL_PINGROUP("gpio" #id, \
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gpio##id##_pins, \
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+
ARRAY_SIZE(gpio##id##_pins)), \
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+
.funcs = (int[]){ \
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msm_mux_gpio, /* gpio mode */ \
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msm_mux_##f1, \
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msm_mux_##f2, \
22
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msm_mux_##f3, \
23
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msm_mux_##f4, \
24
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msm_mux_##f5, \
25
+
msm_mux_##f6, \
26
+
msm_mux_##f7, \
27
+
msm_mux_##f8, \
28
+
msm_mux_##f9, \
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+
msm_mux_##f10, \
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msm_mux_##f11 /* egpio mode */ \
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+
}, \
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+
.nfuncs = 12, \
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.ctl_reg = REG_SIZE * id, \
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+
.io_reg = 0x4 + REG_SIZE * id, \
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+
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
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.intr_status_reg = 0xc + REG_SIZE * id, \
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.mux_bit = 2, \
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.pull_bit = 0, \
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.drv_bit = 6, \
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.egpio_enable = 12, \
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.egpio_present = 11, \
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.oe_bit = 9, \
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.in_bit = 0, \
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.out_bit = 1, \
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.intr_enable_bit = 0, \
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.intr_status_bit = 0, \
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.intr_wakeup_present_bit = 6, \
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.intr_wakeup_enable_bit = 7, \
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.intr_target_bit = 8, \
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.intr_target_kpss_val = 3, \
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.intr_raw_status_bit = 4, \
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.intr_polarity_bit = 1, \
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.intr_detection_bit = 2, \
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.intr_detection_width = 2, \
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}
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+
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#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
58
+
{ \
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+
.grp = PINCTRL_PINGROUP(#pg_name, \
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+
pg_name##_pins, \
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+
ARRAY_SIZE(pg_name##_pins)), \
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+
.ctl_reg = ctl, \
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+
.io_reg = 0, \
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+
.intr_cfg_reg = 0, \
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+
.intr_status_reg = 0, \
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+
.intr_target_reg = 0, \
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.mux_bit = -1, \
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+
.pull_bit = pull, \
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.drv_bit = drv, \
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+
.oe_bit = -1, \
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.in_bit = -1, \
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+
.out_bit = -1, \
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.intr_enable_bit = -1, \
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.intr_status_bit = -1, \
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+
.intr_target_bit = -1, \
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+
.intr_raw_status_bit = -1, \
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.intr_polarity_bit = -1, \
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+
.intr_detection_bit = -1, \
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.intr_detection_width = -1, \
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+
}
81
+
82
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#define UFS_RESET(pg_name, ctl, io) \
83
+
{ \
84
+
.grp = PINCTRL_PINGROUP(#pg_name, \
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+
pg_name##_pins, \
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+
ARRAY_SIZE(pg_name##_pins)), \
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.ctl_reg = ctl, \
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+
.io_reg = io, \
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+
.intr_cfg_reg = 0, \
90
+
.intr_status_reg = 0, \
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+
.intr_target_reg = 0, \
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.mux_bit = -1, \
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+
.pull_bit = 3, \
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.drv_bit = 0, \
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+
.oe_bit = -1, \
96
+
.in_bit = -1, \
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+
.out_bit = 0, \
98
+
.intr_enable_bit = -1, \
99
+
.intr_status_bit = -1, \
100
+
.intr_target_bit = -1, \
101
+
.intr_raw_status_bit = -1, \
102
+
.intr_polarity_bit = -1, \
103
+
.intr_detection_bit = -1, \
104
+
.intr_detection_width = -1, \
105
+
}
106
+
107
+
static const struct pinctrl_pin_desc hawi_pins[] = {
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+
PINCTRL_PIN(0, "GPIO_0"),
109
+
PINCTRL_PIN(1, "GPIO_1"),
110
+
PINCTRL_PIN(2, "GPIO_2"),
111
+
PINCTRL_PIN(3, "GPIO_3"),
112
+
PINCTRL_PIN(4, "GPIO_4"),
113
+
PINCTRL_PIN(5, "GPIO_5"),
114
+
PINCTRL_PIN(6, "GPIO_6"),
115
+
PINCTRL_PIN(7, "GPIO_7"),
116
+
PINCTRL_PIN(8, "GPIO_8"),
117
+
PINCTRL_PIN(9, "GPIO_9"),
118
+
PINCTRL_PIN(10, "GPIO_10"),
119
+
PINCTRL_PIN(11, "GPIO_11"),
120
+
PINCTRL_PIN(12, "GPIO_12"),
121
+
PINCTRL_PIN(13, "GPIO_13"),
122
+
PINCTRL_PIN(14, "GPIO_14"),
123
+
PINCTRL_PIN(15, "GPIO_15"),
124
+
PINCTRL_PIN(16, "GPIO_16"),
125
+
PINCTRL_PIN(17, "GPIO_17"),
126
+
PINCTRL_PIN(18, "GPIO_18"),
127
+
PINCTRL_PIN(19, "GPIO_19"),
128
+
PINCTRL_PIN(20, "GPIO_20"),
129
+
PINCTRL_PIN(21, "GPIO_21"),
130
+
PINCTRL_PIN(22, "GPIO_22"),
131
+
PINCTRL_PIN(23, "GPIO_23"),
132
+
PINCTRL_PIN(24, "GPIO_24"),
133
+
PINCTRL_PIN(25, "GPIO_25"),
134
+
PINCTRL_PIN(26, "GPIO_26"),
135
+
PINCTRL_PIN(27, "GPIO_27"),
136
+
PINCTRL_PIN(28, "GPIO_28"),
137
+
PINCTRL_PIN(29, "GPIO_29"),
138
+
PINCTRL_PIN(30, "GPIO_30"),
139
+
PINCTRL_PIN(31, "GPIO_31"),
140
+
PINCTRL_PIN(32, "GPIO_32"),
141
+
PINCTRL_PIN(33, "GPIO_33"),
142
+
PINCTRL_PIN(34, "GPIO_34"),
143
+
PINCTRL_PIN(35, "GPIO_35"),
144
+
PINCTRL_PIN(36, "GPIO_36"),
145
+
PINCTRL_PIN(37, "GPIO_37"),
146
+
PINCTRL_PIN(38, "GPIO_38"),
147
+
PINCTRL_PIN(39, "GPIO_39"),
148
+
PINCTRL_PIN(40, "GPIO_40"),
149
+
PINCTRL_PIN(41, "GPIO_41"),
150
+
PINCTRL_PIN(42, "GPIO_42"),
151
+
PINCTRL_PIN(43, "GPIO_43"),
152
+
PINCTRL_PIN(44, "GPIO_44"),
153
+
PINCTRL_PIN(45, "GPIO_45"),
154
+
PINCTRL_PIN(46, "GPIO_46"),
155
+
PINCTRL_PIN(47, "GPIO_47"),
156
+
PINCTRL_PIN(48, "GPIO_48"),
157
+
PINCTRL_PIN(49, "GPIO_49"),
158
+
PINCTRL_PIN(50, "GPIO_50"),
159
+
PINCTRL_PIN(51, "GPIO_51"),
160
+
PINCTRL_PIN(52, "GPIO_52"),
161
+
PINCTRL_PIN(53, "GPIO_53"),
162
+
PINCTRL_PIN(54, "GPIO_54"),
163
+
PINCTRL_PIN(55, "GPIO_55"),
164
+
PINCTRL_PIN(56, "GPIO_56"),
165
+
PINCTRL_PIN(57, "GPIO_57"),
166
+
PINCTRL_PIN(58, "GPIO_58"),
167
+
PINCTRL_PIN(59, "GPIO_59"),
168
+
PINCTRL_PIN(60, "GPIO_60"),
169
+
PINCTRL_PIN(61, "GPIO_61"),
170
+
PINCTRL_PIN(62, "GPIO_62"),
171
+
PINCTRL_PIN(63, "GPIO_63"),
172
+
PINCTRL_PIN(64, "GPIO_64"),
173
+
PINCTRL_PIN(65, "GPIO_65"),
174
+
PINCTRL_PIN(66, "GPIO_66"),
175
+
PINCTRL_PIN(67, "GPIO_67"),
176
+
PINCTRL_PIN(68, "GPIO_68"),
177
+
PINCTRL_PIN(69, "GPIO_69"),
178
+
PINCTRL_PIN(70, "GPIO_70"),
179
+
PINCTRL_PIN(71, "GPIO_71"),
180
+
PINCTRL_PIN(72, "GPIO_72"),
181
+
PINCTRL_PIN(73, "GPIO_73"),
182
+
PINCTRL_PIN(74, "GPIO_74"),
183
+
PINCTRL_PIN(75, "GPIO_75"),
184
+
PINCTRL_PIN(76, "GPIO_76"),
185
+
PINCTRL_PIN(77, "GPIO_77"),
186
+
PINCTRL_PIN(78, "GPIO_78"),
187
+
PINCTRL_PIN(79, "GPIO_79"),
188
+
PINCTRL_PIN(80, "GPIO_80"),
189
+
PINCTRL_PIN(81, "GPIO_81"),
190
+
PINCTRL_PIN(82, "GPIO_82"),
191
+
PINCTRL_PIN(83, "GPIO_83"),
192
+
PINCTRL_PIN(84, "GPIO_84"),
193
+
PINCTRL_PIN(85, "GPIO_85"),
194
+
PINCTRL_PIN(86, "GPIO_86"),
195
+
PINCTRL_PIN(87, "GPIO_87"),
196
+
PINCTRL_PIN(88, "GPIO_88"),
197
+
PINCTRL_PIN(89, "GPIO_89"),
198
+
PINCTRL_PIN(90, "GPIO_90"),
199
+
PINCTRL_PIN(91, "GPIO_91"),
200
+
PINCTRL_PIN(92, "GPIO_92"),
201
+
PINCTRL_PIN(93, "GPIO_93"),
202
+
PINCTRL_PIN(94, "GPIO_94"),
203
+
PINCTRL_PIN(95, "GPIO_95"),
204
+
PINCTRL_PIN(96, "GPIO_96"),
205
+
PINCTRL_PIN(97, "GPIO_97"),
206
+
PINCTRL_PIN(98, "GPIO_98"),
207
+
PINCTRL_PIN(99, "GPIO_99"),
208
+
PINCTRL_PIN(100, "GPIO_100"),
209
+
PINCTRL_PIN(101, "GPIO_101"),
210
+
PINCTRL_PIN(102, "GPIO_102"),
211
+
PINCTRL_PIN(103, "GPIO_103"),
212
+
PINCTRL_PIN(104, "GPIO_104"),
213
+
PINCTRL_PIN(105, "GPIO_105"),
214
+
PINCTRL_PIN(106, "GPIO_106"),
215
+
PINCTRL_PIN(107, "GPIO_107"),
216
+
PINCTRL_PIN(108, "GPIO_108"),
217
+
PINCTRL_PIN(109, "GPIO_109"),
218
+
PINCTRL_PIN(110, "GPIO_110"),
219
+
PINCTRL_PIN(111, "GPIO_111"),
220
+
PINCTRL_PIN(112, "GPIO_112"),
221
+
PINCTRL_PIN(113, "GPIO_113"),
222
+
PINCTRL_PIN(114, "GPIO_114"),
223
+
PINCTRL_PIN(115, "GPIO_115"),
224
+
PINCTRL_PIN(116, "GPIO_116"),
225
+
PINCTRL_PIN(117, "GPIO_117"),
226
+
PINCTRL_PIN(118, "GPIO_118"),
227
+
PINCTRL_PIN(119, "GPIO_119"),
228
+
PINCTRL_PIN(120, "GPIO_120"),
229
+
PINCTRL_PIN(121, "GPIO_121"),
230
+
PINCTRL_PIN(122, "GPIO_122"),
231
+
PINCTRL_PIN(123, "GPIO_123"),
232
+
PINCTRL_PIN(124, "GPIO_124"),
233
+
PINCTRL_PIN(125, "GPIO_125"),
234
+
PINCTRL_PIN(126, "GPIO_126"),
235
+
PINCTRL_PIN(127, "GPIO_127"),
236
+
PINCTRL_PIN(128, "GPIO_128"),
237
+
PINCTRL_PIN(129, "GPIO_129"),
238
+
PINCTRL_PIN(130, "GPIO_130"),
239
+
PINCTRL_PIN(131, "GPIO_131"),
240
+
PINCTRL_PIN(132, "GPIO_132"),
241
+
PINCTRL_PIN(133, "GPIO_133"),
242
+
PINCTRL_PIN(134, "GPIO_134"),
243
+
PINCTRL_PIN(135, "GPIO_135"),
244
+
PINCTRL_PIN(136, "GPIO_136"),
245
+
PINCTRL_PIN(137, "GPIO_137"),
246
+
PINCTRL_PIN(138, "GPIO_138"),
247
+
PINCTRL_PIN(139, "GPIO_139"),
248
+
PINCTRL_PIN(140, "GPIO_140"),
249
+
PINCTRL_PIN(141, "GPIO_141"),
250
+
PINCTRL_PIN(142, "GPIO_142"),
251
+
PINCTRL_PIN(143, "GPIO_143"),
252
+
PINCTRL_PIN(144, "GPIO_144"),
253
+
PINCTRL_PIN(145, "GPIO_145"),
254
+
PINCTRL_PIN(146, "GPIO_146"),
255
+
PINCTRL_PIN(147, "GPIO_147"),
256
+
PINCTRL_PIN(148, "GPIO_148"),
257
+
PINCTRL_PIN(149, "GPIO_149"),
258
+
PINCTRL_PIN(150, "GPIO_150"),
259
+
PINCTRL_PIN(151, "GPIO_151"),
260
+
PINCTRL_PIN(152, "GPIO_152"),
261
+
PINCTRL_PIN(153, "GPIO_153"),
262
+
PINCTRL_PIN(154, "GPIO_154"),
263
+
PINCTRL_PIN(155, "GPIO_155"),
264
+
PINCTRL_PIN(156, "GPIO_156"),
265
+
PINCTRL_PIN(157, "GPIO_157"),
266
+
PINCTRL_PIN(158, "GPIO_158"),
267
+
PINCTRL_PIN(159, "GPIO_159"),
268
+
PINCTRL_PIN(160, "GPIO_160"),
269
+
PINCTRL_PIN(161, "GPIO_161"),
270
+
PINCTRL_PIN(162, "GPIO_162"),
271
+
PINCTRL_PIN(163, "GPIO_163"),
272
+
PINCTRL_PIN(164, "GPIO_164"),
273
+
PINCTRL_PIN(165, "GPIO_165"),
274
+
PINCTRL_PIN(166, "GPIO_166"),
275
+
PINCTRL_PIN(167, "GPIO_167"),
276
+
PINCTRL_PIN(168, "GPIO_168"),
277
+
PINCTRL_PIN(169, "GPIO_169"),
278
+
PINCTRL_PIN(170, "GPIO_170"),
279
+
PINCTRL_PIN(171, "GPIO_171"),
280
+
PINCTRL_PIN(172, "GPIO_172"),
281
+
PINCTRL_PIN(173, "GPIO_173"),
282
+
PINCTRL_PIN(174, "GPIO_174"),
283
+
PINCTRL_PIN(175, "GPIO_175"),
284
+
PINCTRL_PIN(176, "GPIO_176"),
285
+
PINCTRL_PIN(177, "GPIO_177"),
286
+
PINCTRL_PIN(178, "GPIO_178"),
287
+
PINCTRL_PIN(179, "GPIO_179"),
288
+
PINCTRL_PIN(180, "GPIO_180"),
289
+
PINCTRL_PIN(181, "GPIO_181"),
290
+
PINCTRL_PIN(182, "GPIO_182"),
291
+
PINCTRL_PIN(183, "GPIO_183"),
292
+
PINCTRL_PIN(184, "GPIO_184"),
293
+
PINCTRL_PIN(185, "GPIO_185"),
294
+
PINCTRL_PIN(186, "GPIO_186"),
295
+
PINCTRL_PIN(187, "GPIO_187"),
296
+
PINCTRL_PIN(188, "GPIO_188"),
297
+
PINCTRL_PIN(189, "GPIO_189"),
298
+
PINCTRL_PIN(190, "GPIO_190"),
299
+
PINCTRL_PIN(191, "GPIO_191"),
300
+
PINCTRL_PIN(192, "GPIO_192"),
301
+
PINCTRL_PIN(193, "GPIO_193"),
302
+
PINCTRL_PIN(194, "GPIO_194"),
303
+
PINCTRL_PIN(195, "GPIO_195"),
304
+
PINCTRL_PIN(196, "GPIO_196"),
305
+
PINCTRL_PIN(197, "GPIO_197"),
306
+
PINCTRL_PIN(198, "GPIO_198"),
307
+
PINCTRL_PIN(199, "GPIO_199"),
308
+
PINCTRL_PIN(200, "GPIO_200"),
309
+
PINCTRL_PIN(201, "GPIO_201"),
310
+
PINCTRL_PIN(202, "GPIO_202"),
311
+
PINCTRL_PIN(203, "GPIO_203"),
312
+
PINCTRL_PIN(204, "GPIO_204"),
313
+
PINCTRL_PIN(205, "GPIO_205"),
314
+
PINCTRL_PIN(206, "GPIO_206"),
315
+
PINCTRL_PIN(207, "GPIO_207"),
316
+
PINCTRL_PIN(208, "GPIO_208"),
317
+
PINCTRL_PIN(209, "GPIO_209"),
318
+
PINCTRL_PIN(210, "GPIO_210"),
319
+
PINCTRL_PIN(211, "GPIO_211"),
320
+
PINCTRL_PIN(212, "GPIO_212"),
321
+
PINCTRL_PIN(213, "GPIO_213"),
322
+
PINCTRL_PIN(214, "GPIO_214"),
323
+
PINCTRL_PIN(215, "GPIO_215"),
324
+
PINCTRL_PIN(216, "GPIO_216"),
325
+
PINCTRL_PIN(217, "GPIO_217"),
326
+
PINCTRL_PIN(218, "GPIO_218"),
327
+
PINCTRL_PIN(219, "GPIO_219"),
328
+
PINCTRL_PIN(220, "GPIO_220"),
329
+
PINCTRL_PIN(221, "GPIO_221"),
330
+
PINCTRL_PIN(222, "GPIO_222"),
331
+
PINCTRL_PIN(223, "GPIO_223"),
332
+
PINCTRL_PIN(224, "GPIO_224"),
333
+
PINCTRL_PIN(225, "GPIO_225"),
334
+
PINCTRL_PIN(226, "UFS_RESET"),
335
+
PINCTRL_PIN(227, "SDC2_CLK"),
336
+
PINCTRL_PIN(228, "SDC2_CMD"),
337
+
PINCTRL_PIN(229, "SDC2_DATA"),
338
+
};
339
+
340
+
#define DECLARE_MSM_GPIO_PINS(pin) \
341
+
static const unsigned int gpio##pin##_pins[] = { pin }
342
+
DECLARE_MSM_GPIO_PINS(0);
343
+
DECLARE_MSM_GPIO_PINS(1);
344
+
DECLARE_MSM_GPIO_PINS(2);
345
+
DECLARE_MSM_GPIO_PINS(3);
346
+
DECLARE_MSM_GPIO_PINS(4);
347
+
DECLARE_MSM_GPIO_PINS(5);
348
+
DECLARE_MSM_GPIO_PINS(6);
349
+
DECLARE_MSM_GPIO_PINS(7);
350
+
DECLARE_MSM_GPIO_PINS(8);
351
+
DECLARE_MSM_GPIO_PINS(9);
352
+
DECLARE_MSM_GPIO_PINS(10);
353
+
DECLARE_MSM_GPIO_PINS(11);
354
+
DECLARE_MSM_GPIO_PINS(12);
355
+
DECLARE_MSM_GPIO_PINS(13);
356
+
DECLARE_MSM_GPIO_PINS(14);
357
+
DECLARE_MSM_GPIO_PINS(15);
358
+
DECLARE_MSM_GPIO_PINS(16);
359
+
DECLARE_MSM_GPIO_PINS(17);
360
+
DECLARE_MSM_GPIO_PINS(18);
361
+
DECLARE_MSM_GPIO_PINS(19);
362
+
DECLARE_MSM_GPIO_PINS(20);
363
+
DECLARE_MSM_GPIO_PINS(21);
364
+
DECLARE_MSM_GPIO_PINS(22);
365
+
DECLARE_MSM_GPIO_PINS(23);
366
+
DECLARE_MSM_GPIO_PINS(24);
367
+
DECLARE_MSM_GPIO_PINS(25);
368
+
DECLARE_MSM_GPIO_PINS(26);
369
+
DECLARE_MSM_GPIO_PINS(27);
370
+
DECLARE_MSM_GPIO_PINS(28);
371
+
DECLARE_MSM_GPIO_PINS(29);
372
+
DECLARE_MSM_GPIO_PINS(30);
373
+
DECLARE_MSM_GPIO_PINS(31);
374
+
DECLARE_MSM_GPIO_PINS(32);
375
+
DECLARE_MSM_GPIO_PINS(33);
376
+
DECLARE_MSM_GPIO_PINS(34);
377
+
DECLARE_MSM_GPIO_PINS(35);
378
+
DECLARE_MSM_GPIO_PINS(36);
379
+
DECLARE_MSM_GPIO_PINS(37);
380
+
DECLARE_MSM_GPIO_PINS(38);
381
+
DECLARE_MSM_GPIO_PINS(39);
382
+
DECLARE_MSM_GPIO_PINS(40);
383
+
DECLARE_MSM_GPIO_PINS(41);
384
+
DECLARE_MSM_GPIO_PINS(42);
385
+
DECLARE_MSM_GPIO_PINS(43);
386
+
DECLARE_MSM_GPIO_PINS(44);
387
+
DECLARE_MSM_GPIO_PINS(45);
388
+
DECLARE_MSM_GPIO_PINS(46);
389
+
DECLARE_MSM_GPIO_PINS(47);
390
+
DECLARE_MSM_GPIO_PINS(48);
391
+
DECLARE_MSM_GPIO_PINS(49);
392
+
DECLARE_MSM_GPIO_PINS(50);
393
+
DECLARE_MSM_GPIO_PINS(51);
394
+
DECLARE_MSM_GPIO_PINS(52);
395
+
DECLARE_MSM_GPIO_PINS(53);
396
+
DECLARE_MSM_GPIO_PINS(54);
397
+
DECLARE_MSM_GPIO_PINS(55);
398
+
DECLARE_MSM_GPIO_PINS(56);
399
+
DECLARE_MSM_GPIO_PINS(57);
400
+
DECLARE_MSM_GPIO_PINS(58);
401
+
DECLARE_MSM_GPIO_PINS(59);
402
+
DECLARE_MSM_GPIO_PINS(60);
403
+
DECLARE_MSM_GPIO_PINS(61);
404
+
DECLARE_MSM_GPIO_PINS(62);
405
+
DECLARE_MSM_GPIO_PINS(63);
406
+
DECLARE_MSM_GPIO_PINS(64);
407
+
DECLARE_MSM_GPIO_PINS(65);
408
+
DECLARE_MSM_GPIO_PINS(66);
409
+
DECLARE_MSM_GPIO_PINS(67);
410
+
DECLARE_MSM_GPIO_PINS(68);
411
+
DECLARE_MSM_GPIO_PINS(69);
412
+
DECLARE_MSM_GPIO_PINS(70);
413
+
DECLARE_MSM_GPIO_PINS(71);
414
+
DECLARE_MSM_GPIO_PINS(72);
415
+
DECLARE_MSM_GPIO_PINS(73);
416
+
DECLARE_MSM_GPIO_PINS(74);
417
+
DECLARE_MSM_GPIO_PINS(75);
418
+
DECLARE_MSM_GPIO_PINS(76);
419
+
DECLARE_MSM_GPIO_PINS(77);
420
+
DECLARE_MSM_GPIO_PINS(78);
421
+
DECLARE_MSM_GPIO_PINS(79);
422
+
DECLARE_MSM_GPIO_PINS(80);
423
+
DECLARE_MSM_GPIO_PINS(81);
424
+
DECLARE_MSM_GPIO_PINS(82);
425
+
DECLARE_MSM_GPIO_PINS(83);
426
+
DECLARE_MSM_GPIO_PINS(84);
427
+
DECLARE_MSM_GPIO_PINS(85);
428
+
DECLARE_MSM_GPIO_PINS(86);
429
+
DECLARE_MSM_GPIO_PINS(87);
430
+
DECLARE_MSM_GPIO_PINS(88);
431
+
DECLARE_MSM_GPIO_PINS(89);
432
+
DECLARE_MSM_GPIO_PINS(90);
433
+
DECLARE_MSM_GPIO_PINS(91);
434
+
DECLARE_MSM_GPIO_PINS(92);
435
+
DECLARE_MSM_GPIO_PINS(93);
436
+
DECLARE_MSM_GPIO_PINS(94);
437
+
DECLARE_MSM_GPIO_PINS(95);
438
+
DECLARE_MSM_GPIO_PINS(96);
439
+
DECLARE_MSM_GPIO_PINS(97);
440
+
DECLARE_MSM_GPIO_PINS(98);
441
+
DECLARE_MSM_GPIO_PINS(99);
442
+
DECLARE_MSM_GPIO_PINS(100);
443
+
DECLARE_MSM_GPIO_PINS(101);
444
+
DECLARE_MSM_GPIO_PINS(102);
445
+
DECLARE_MSM_GPIO_PINS(103);
446
+
DECLARE_MSM_GPIO_PINS(104);
447
+
DECLARE_MSM_GPIO_PINS(105);
448
+
DECLARE_MSM_GPIO_PINS(106);
449
+
DECLARE_MSM_GPIO_PINS(107);
450
+
DECLARE_MSM_GPIO_PINS(108);
451
+
DECLARE_MSM_GPIO_PINS(109);
452
+
DECLARE_MSM_GPIO_PINS(110);
453
+
DECLARE_MSM_GPIO_PINS(111);
454
+
DECLARE_MSM_GPIO_PINS(112);
455
+
DECLARE_MSM_GPIO_PINS(113);
456
+
DECLARE_MSM_GPIO_PINS(114);
457
+
DECLARE_MSM_GPIO_PINS(115);
458
+
DECLARE_MSM_GPIO_PINS(116);
459
+
DECLARE_MSM_GPIO_PINS(117);
460
+
DECLARE_MSM_GPIO_PINS(118);
461
+
DECLARE_MSM_GPIO_PINS(119);
462
+
DECLARE_MSM_GPIO_PINS(120);
463
+
DECLARE_MSM_GPIO_PINS(121);
464
+
DECLARE_MSM_GPIO_PINS(122);
465
+
DECLARE_MSM_GPIO_PINS(123);
466
+
DECLARE_MSM_GPIO_PINS(124);
467
+
DECLARE_MSM_GPIO_PINS(125);
468
+
DECLARE_MSM_GPIO_PINS(126);
469
+
DECLARE_MSM_GPIO_PINS(127);
470
+
DECLARE_MSM_GPIO_PINS(128);
471
+
DECLARE_MSM_GPIO_PINS(129);
472
+
DECLARE_MSM_GPIO_PINS(130);
473
+
DECLARE_MSM_GPIO_PINS(131);
474
+
DECLARE_MSM_GPIO_PINS(132);
475
+
DECLARE_MSM_GPIO_PINS(133);
476
+
DECLARE_MSM_GPIO_PINS(134);
477
+
DECLARE_MSM_GPIO_PINS(135);
478
+
DECLARE_MSM_GPIO_PINS(136);
479
+
DECLARE_MSM_GPIO_PINS(137);
480
+
DECLARE_MSM_GPIO_PINS(138);
481
+
DECLARE_MSM_GPIO_PINS(139);
482
+
DECLARE_MSM_GPIO_PINS(140);
483
+
DECLARE_MSM_GPIO_PINS(141);
484
+
DECLARE_MSM_GPIO_PINS(142);
485
+
DECLARE_MSM_GPIO_PINS(143);
486
+
DECLARE_MSM_GPIO_PINS(144);
487
+
DECLARE_MSM_GPIO_PINS(145);
488
+
DECLARE_MSM_GPIO_PINS(146);
489
+
DECLARE_MSM_GPIO_PINS(147);
490
+
DECLARE_MSM_GPIO_PINS(148);
491
+
DECLARE_MSM_GPIO_PINS(149);
492
+
DECLARE_MSM_GPIO_PINS(150);
493
+
DECLARE_MSM_GPIO_PINS(151);
494
+
DECLARE_MSM_GPIO_PINS(152);
495
+
DECLARE_MSM_GPIO_PINS(153);
496
+
DECLARE_MSM_GPIO_PINS(154);
497
+
DECLARE_MSM_GPIO_PINS(155);
498
+
DECLARE_MSM_GPIO_PINS(156);
499
+
DECLARE_MSM_GPIO_PINS(157);
500
+
DECLARE_MSM_GPIO_PINS(158);
501
+
DECLARE_MSM_GPIO_PINS(159);
502
+
DECLARE_MSM_GPIO_PINS(160);
503
+
DECLARE_MSM_GPIO_PINS(161);
504
+
DECLARE_MSM_GPIO_PINS(162);
505
+
DECLARE_MSM_GPIO_PINS(163);
506
+
DECLARE_MSM_GPIO_PINS(164);
507
+
DECLARE_MSM_GPIO_PINS(165);
508
+
DECLARE_MSM_GPIO_PINS(166);
509
+
DECLARE_MSM_GPIO_PINS(167);
510
+
DECLARE_MSM_GPIO_PINS(168);
511
+
DECLARE_MSM_GPIO_PINS(169);
512
+
DECLARE_MSM_GPIO_PINS(170);
513
+
DECLARE_MSM_GPIO_PINS(171);
514
+
DECLARE_MSM_GPIO_PINS(172);
515
+
DECLARE_MSM_GPIO_PINS(173);
516
+
DECLARE_MSM_GPIO_PINS(174);
517
+
DECLARE_MSM_GPIO_PINS(175);
518
+
DECLARE_MSM_GPIO_PINS(176);
519
+
DECLARE_MSM_GPIO_PINS(177);
520
+
DECLARE_MSM_GPIO_PINS(178);
521
+
DECLARE_MSM_GPIO_PINS(179);
522
+
DECLARE_MSM_GPIO_PINS(180);
523
+
DECLARE_MSM_GPIO_PINS(181);
524
+
DECLARE_MSM_GPIO_PINS(182);
525
+
DECLARE_MSM_GPIO_PINS(183);
526
+
DECLARE_MSM_GPIO_PINS(184);
527
+
DECLARE_MSM_GPIO_PINS(185);
528
+
DECLARE_MSM_GPIO_PINS(186);
529
+
DECLARE_MSM_GPIO_PINS(187);
530
+
DECLARE_MSM_GPIO_PINS(188);
531
+
DECLARE_MSM_GPIO_PINS(189);
532
+
DECLARE_MSM_GPIO_PINS(190);
533
+
DECLARE_MSM_GPIO_PINS(191);
534
+
DECLARE_MSM_GPIO_PINS(192);
535
+
DECLARE_MSM_GPIO_PINS(193);
536
+
DECLARE_MSM_GPIO_PINS(194);
537
+
DECLARE_MSM_GPIO_PINS(195);
538
+
DECLARE_MSM_GPIO_PINS(196);
539
+
DECLARE_MSM_GPIO_PINS(197);
540
+
DECLARE_MSM_GPIO_PINS(198);
541
+
DECLARE_MSM_GPIO_PINS(199);
542
+
DECLARE_MSM_GPIO_PINS(200);
543
+
DECLARE_MSM_GPIO_PINS(201);
544
+
DECLARE_MSM_GPIO_PINS(202);
545
+
DECLARE_MSM_GPIO_PINS(203);
546
+
DECLARE_MSM_GPIO_PINS(204);
547
+
DECLARE_MSM_GPIO_PINS(205);
548
+
DECLARE_MSM_GPIO_PINS(206);
549
+
DECLARE_MSM_GPIO_PINS(207);
550
+
DECLARE_MSM_GPIO_PINS(208);
551
+
DECLARE_MSM_GPIO_PINS(209);
552
+
DECLARE_MSM_GPIO_PINS(210);
553
+
DECLARE_MSM_GPIO_PINS(211);
554
+
DECLARE_MSM_GPIO_PINS(212);
555
+
DECLARE_MSM_GPIO_PINS(213);
556
+
DECLARE_MSM_GPIO_PINS(214);
557
+
DECLARE_MSM_GPIO_PINS(215);
558
+
DECLARE_MSM_GPIO_PINS(216);
559
+
DECLARE_MSM_GPIO_PINS(217);
560
+
DECLARE_MSM_GPIO_PINS(218);
561
+
DECLARE_MSM_GPIO_PINS(219);
562
+
DECLARE_MSM_GPIO_PINS(220);
563
+
DECLARE_MSM_GPIO_PINS(221);
564
+
DECLARE_MSM_GPIO_PINS(222);
565
+
DECLARE_MSM_GPIO_PINS(223);
566
+
DECLARE_MSM_GPIO_PINS(224);
567
+
DECLARE_MSM_GPIO_PINS(225);
568
+
569
+
static const unsigned int ufs_reset_pins[] = { 226 };
570
+
static const unsigned int sdc2_clk_pins[] = { 227 };
571
+
static const unsigned int sdc2_cmd_pins[] = { 228 };
572
+
static const unsigned int sdc2_data_pins[] = { 229 };
573
+
574
+
enum hawi_functions {
575
+
msm_mux_gpio,
576
+
msm_mux_aoss_cti,
577
+
msm_mux_atest_char,
578
+
msm_mux_atest_usb,
579
+
msm_mux_audio_ext_mclk,
580
+
msm_mux_audio_ref_clk,
581
+
msm_mux_cam_mclk,
582
+
msm_mux_cci_async_in,
583
+
msm_mux_cci_i2c0,
584
+
msm_mux_cci_i2c1,
585
+
msm_mux_cci_i2c2,
586
+
msm_mux_cci_i2c3,
587
+
msm_mux_cci_i2c4,
588
+
msm_mux_cci_i2c5,
589
+
msm_mux_cci_timer,
590
+
msm_mux_coex_espmi,
591
+
msm_mux_coex_uart1_rx,
592
+
msm_mux_coex_uart1_tx,
593
+
msm_mux_dbg_out_clk,
594
+
msm_mux_ddr_bist,
595
+
msm_mux_ddr_pxi,
596
+
msm_mux_dp_hot,
597
+
msm_mux_egpio,
598
+
msm_mux_gcc_gp,
599
+
msm_mux_gnss_adc,
600
+
msm_mux_host_rst,
601
+
msm_mux_i2chub0_se0,
602
+
msm_mux_i2chub0_se1,
603
+
msm_mux_i2chub0_se2,
604
+
msm_mux_i2chub0_se3,
605
+
msm_mux_i2chub0_se4,
606
+
msm_mux_i2s0,
607
+
msm_mux_i2s1,
608
+
msm_mux_ibi_i3c,
609
+
msm_mux_jitter_bist,
610
+
msm_mux_mdp_esync0,
611
+
msm_mux_mdp_esync1,
612
+
msm_mux_mdp_esync2,
613
+
msm_mux_mdp_vsync,
614
+
msm_mux_mdp_vsync_e,
615
+
msm_mux_mdp_vsync_p,
616
+
msm_mux_mdp_vsync0_out,
617
+
msm_mux_mdp_vsync1_out,
618
+
msm_mux_mdp_vsync2_out,
619
+
msm_mux_mdp_vsync3_out,
620
+
msm_mux_mdp_vsync5_out,
621
+
msm_mux_modem_pps_in,
622
+
msm_mux_modem_pps_out,
623
+
msm_mux_nav_gpio,
624
+
msm_mux_nav_gpio0,
625
+
msm_mux_nav_gpio3,
626
+
msm_mux_nav_rffe,
627
+
msm_mux_pcie0_clk_req_n,
628
+
msm_mux_pcie0_rst_n,
629
+
msm_mux_pcie1_clk_req_n,
630
+
msm_mux_phase_flag,
631
+
msm_mux_pll_bist_sync,
632
+
msm_mux_pll_clk_aux,
633
+
msm_mux_qdss_cti,
634
+
msm_mux_qlink,
635
+
msm_mux_qspi,
636
+
msm_mux_qspi_clk,
637
+
msm_mux_qspi_cs,
638
+
msm_mux_qup1_se0,
639
+
msm_mux_qup1_se1,
640
+
msm_mux_qup1_se2,
641
+
msm_mux_qup1_se3,
642
+
msm_mux_qup1_se4,
643
+
msm_mux_qup1_se5,
644
+
msm_mux_qup1_se6,
645
+
msm_mux_qup1_se7,
646
+
msm_mux_qup2_se0,
647
+
msm_mux_qup2_se1,
648
+
msm_mux_qup2_se2,
649
+
msm_mux_qup2_se3,
650
+
msm_mux_qup2_se4_01,
651
+
msm_mux_qup2_se4_23,
652
+
msm_mux_qup3_se0_01,
653
+
msm_mux_qup3_se0_23,
654
+
msm_mux_qup3_se1,
655
+
msm_mux_qup3_se2,
656
+
msm_mux_qup3_se3,
657
+
msm_mux_qup3_se4,
658
+
msm_mux_qup3_se5,
659
+
msm_mux_qup4_se0,
660
+
msm_mux_qup4_se1,
661
+
msm_mux_qup4_se2,
662
+
msm_mux_qup4_se3_01,
663
+
msm_mux_qup4_se3_23,
664
+
msm_mux_qup4_se3_l3,
665
+
msm_mux_qup4_se4_01,
666
+
msm_mux_qup4_se4_23,
667
+
msm_mux_qup4_se4_l3,
668
+
msm_mux_rng_rosc,
669
+
msm_mux_sd_write_protect,
670
+
msm_mux_sdc4_clk,
671
+
msm_mux_sdc4_cmd,
672
+
msm_mux_sdc4_data,
673
+
msm_mux_sys_throttle,
674
+
msm_mux_tb_trig_sdc,
675
+
msm_mux_tmess_rng,
676
+
msm_mux_tsense_clm,
677
+
msm_mux_tsense_pwm,
678
+
msm_mux_uim0,
679
+
msm_mux_uim1,
680
+
msm_mux_usb0_hs,
681
+
msm_mux_usb_phy,
682
+
msm_mux_vfr,
683
+
msm_mux_vsense_trigger_mirnat,
684
+
msm_mux_wcn_sw_ctrl,
685
+
msm_mux__,
686
+
};
687
+
688
+
static const char *const gpio_groups[] = {
689
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
690
+
"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
691
+
"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
692
+
"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
693
+
"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
694
+
"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
695
+
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
696
+
"gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
697
+
"gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
698
+
"gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59",
699
+
"gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
700
+
"gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
701
+
"gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
702
+
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
703
+
"gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89",
704
+
"gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
705
+
"gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
706
+
"gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
707
+
"gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
708
+
"gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
709
+
"gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
710
+
"gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131",
711
+
"gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
712
+
"gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
713
+
"gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
714
+
"gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155",
715
+
"gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
716
+
"gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167",
717
+
"gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173",
718
+
"gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179",
719
+
"gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185",
720
+
"gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191",
721
+
"gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197",
722
+
"gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203",
723
+
"gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209",
724
+
"gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215",
725
+
"gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221",
726
+
"gpio222", "gpio223", "gpio224", "gpio225",
727
+
};
728
+
729
+
static const char *const aoss_cti_groups[] = {
730
+
"gpio74", "gpio75", "gpio76", "gpio77",
731
+
};
732
+
733
+
static const char *const atest_char_groups[] = {
734
+
"gpio126", "gpio127", "gpio128", "gpio129", "gpio133",
735
+
};
736
+
737
+
static const char *const atest_usb_groups[] = {
738
+
"gpio70", "gpio71", "gpio72", "gpio73", "gpio129",
739
+
};
740
+
741
+
static const char *const audio_ext_mclk_groups[] = {
742
+
"gpio120", "gpio121",
743
+
};
744
+
745
+
static const char *const audio_ref_clk_groups[] = {
746
+
"gpio120",
747
+
};
748
+
749
+
static const char *const cam_mclk_groups[] = {
750
+
"gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94",
751
+
"gpio95", "gpio96",
752
+
};
753
+
754
+
static const char *const cci_async_in_groups[] = {
755
+
"gpio15", "gpio109", "gpio110",
756
+
};
757
+
758
+
static const char *const cci_i2c0_groups[] = {
759
+
"gpio109", "gpio110",
760
+
};
761
+
762
+
static const char *const cci_i2c1_groups[] = {
763
+
"gpio111", "gpio112",
764
+
};
765
+
766
+
static const char *const cci_i2c2_groups[] = {
767
+
"gpio113", "gpio114",
768
+
};
769
+
770
+
static const char *const cci_i2c3_groups[] = {
771
+
"gpio107", "gpio160",
772
+
};
773
+
774
+
static const char *const cci_i2c4_groups[] = {
775
+
"gpio108", "gpio149",
776
+
};
777
+
778
+
static const char *const cci_i2c5_groups[] = {
779
+
"gpio115", "gpio116",
780
+
};
781
+
782
+
static const char *const cci_timer_groups[] = {
783
+
"gpio105", "gpio106", "gpio107", "gpio159", "gpio160",
784
+
};
785
+
786
+
static const char *const coex_espmi_groups[] = {
787
+
"gpio144", "gpio145",
788
+
};
789
+
790
+
static const char *const coex_uart1_rx_groups[] = {
791
+
"gpio144",
792
+
};
793
+
794
+
static const char *const coex_uart1_tx_groups[] = {
795
+
"gpio145",
796
+
};
797
+
798
+
static const char *const dbg_out_clk_groups[] = {
799
+
"gpio82",
800
+
};
801
+
802
+
static const char *const ddr_bist_groups[] = {
803
+
"gpio40", "gpio41", "gpio44", "gpio45",
804
+
};
805
+
806
+
static const char *const ddr_pxi_groups[] = {
807
+
"gpio43", "gpio44", "gpio45", "gpio46",
808
+
"gpio52", "gpio53", "gpio54", "gpio55",
809
+
};
810
+
811
+
static const char *const dp_hot_groups[] = {
812
+
"gpio47",
813
+
};
814
+
815
+
static const char *const egpio_groups[] = {
816
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
817
+
"gpio6", "gpio7", "gpio28", "gpio29", "gpio30", "gpio31",
818
+
"gpio48", "gpio49", "gpio50", "gpio51", "gpio163", "gpio164",
819
+
"gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
820
+
"gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
821
+
"gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
822
+
"gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
823
+
"gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
824
+
"gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
825
+
"gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
826
+
"gpio207", "gpio208", "gpio209", "gpio212", "gpio213", "gpio214",
827
+
"gpio215", "gpio216", "gpio217", "gpio218",
828
+
};
829
+
830
+
static const char *const gcc_gp_groups[] = {
831
+
"gpio86", "gpio87", "gpio130", "gpio131", "gpio132", "gpio158",
832
+
};
833
+
834
+
static const char *const gnss_adc_groups[] = {
835
+
"gpio40", "gpio41", "gpio42", "gpio77",
836
+
};
837
+
838
+
static const char *const host_rst_groups[] = {
839
+
"gpio106",
840
+
};
841
+
842
+
static const char *const i2chub0_se0_groups[] = {
843
+
"gpio66", "gpio67",
844
+
};
845
+
846
+
static const char *const i2chub0_se1_groups[] = {
847
+
"gpio78", "gpio79",
848
+
};
849
+
850
+
static const char *const i2chub0_se2_groups[] = {
851
+
"gpio68", "gpio69",
852
+
};
853
+
854
+
static const char *const i2chub0_se3_groups[] = {
855
+
"gpio70", "gpio71",
856
+
};
857
+
858
+
static const char *const i2chub0_se4_groups[] = {
859
+
"gpio72", "gpio73",
860
+
};
861
+
862
+
static const char *const i2s0_groups[] = {
863
+
"gpio122", "gpio123", "gpio124", "gpio125",
864
+
};
865
+
866
+
static const char *const i2s1_groups[] = {
867
+
"gpio117", "gpio118", "gpio119", "gpio120",
868
+
};
869
+
870
+
static const char *const ibi_i3c_groups[] = {
871
+
"gpio0", "gpio1", "gpio4", "gpio5", "gpio8", "gpio9",
872
+
"gpio12", "gpio13", "gpio28", "gpio29", "gpio32", "gpio33",
873
+
"gpio36", "gpio37", "gpio48", "gpio49", "gpio60", "gpio61",
874
+
};
875
+
876
+
static const char *const jitter_bist_groups[] = {
877
+
"gpio73",
878
+
};
879
+
880
+
static const char *const mdp_esync0_groups[] = {
881
+
"gpio88", "gpio100",
882
+
};
883
+
884
+
static const char *const mdp_esync1_groups[] = {
885
+
"gpio86", "gpio100",
886
+
};
887
+
888
+
static const char *const mdp_esync2_groups[] = {
889
+
"gpio87", "gpio97",
890
+
};
891
+
892
+
static const char *const mdp_vsync_groups[] = {
893
+
"gpio86", "gpio87", "gpio88", "gpio97",
894
+
};
895
+
896
+
static const char *const mdp_vsync_e_groups[] = {
897
+
"gpio98",
898
+
};
899
+
900
+
static const char *const mdp_vsync_p_groups[] = {
901
+
"gpio98",
902
+
};
903
+
904
+
static const char *const mdp_vsync0_out_groups[] = {
905
+
"gpio86",
906
+
};
907
+
908
+
static const char *const mdp_vsync1_out_groups[] = {
909
+
"gpio86",
910
+
};
911
+
912
+
static const char *const mdp_vsync2_out_groups[] = {
913
+
"gpio87",
914
+
};
915
+
916
+
static const char *const mdp_vsync3_out_groups[] = {
917
+
"gpio87",
918
+
};
919
+
920
+
static const char *const mdp_vsync5_out_groups[] = {
921
+
"gpio87",
922
+
};
923
+
924
+
static const char *const modem_pps_in_groups[] = {
925
+
"gpio151",
926
+
};
927
+
928
+
static const char *const modem_pps_out_groups[] = {
929
+
"gpio151",
930
+
};
931
+
932
+
static const char *const nav_gpio_groups[] = {
933
+
"gpio146", "gpio147", "gpio148", "gpio151",
934
+
};
935
+
936
+
static const char *const nav_gpio0_groups[] = {
937
+
"gpio150",
938
+
};
939
+
940
+
static const char *const nav_gpio3_groups[] = {
941
+
"gpio150",
942
+
};
943
+
944
+
static const char *const nav_rffe_groups[] = {
945
+
"gpio134", "gpio135", "gpio138", "gpio139",
946
+
};
947
+
948
+
static const char *const pcie0_clk_req_n_groups[] = {
949
+
"gpio103",
950
+
};
951
+
952
+
static const char *const pcie0_rst_n_groups[] = {
953
+
"gpio102",
954
+
};
955
+
956
+
static const char *const pcie1_clk_req_n_groups[] = {
957
+
"gpio221",
958
+
};
959
+
960
+
static const char *const phase_flag_groups[] = {
961
+
"gpio117", "gpio118", "gpio119", "gpio123", "gpio124", "gpio125",
962
+
"gpio169", "gpio170", "gpio171", "gpio172", "gpio173", "gpio175",
963
+
"gpio176", "gpio179", "gpio180", "gpio181", "gpio184", "gpio185",
964
+
"gpio192", "gpio196", "gpio197", "gpio198", "gpio199", "gpio204",
965
+
"gpio206", "gpio207", "gpio208", "gpio210", "gpio211", "gpio214",
966
+
"gpio215", "gpio216",
967
+
};
968
+
969
+
static const char *const pll_bist_sync_groups[] = {
970
+
"gpio104",
971
+
};
972
+
973
+
static const char *const pll_clk_aux_groups[] = {
974
+
"gpio94",
975
+
};
976
+
977
+
static const char *const qdss_cti_groups[] = {
978
+
"gpio27", "gpio31", "gpio72", "gpio73", "gpio82", "gpio83",
979
+
"gpio152", "gpio158",
980
+
};
981
+
982
+
static const char *const qlink_groups[] = {
983
+
"gpio152", "gpio153", "gpio154",
984
+
};
985
+
986
+
static const char *const qspi_groups[] = {
987
+
"gpio80", "gpio81", "gpio82", "gpio147",
988
+
};
989
+
990
+
static const char *const qspi_clk_groups[] = {
991
+
"gpio83",
992
+
};
993
+
994
+
static const char *const qspi_cs_groups[] = {
995
+
"gpio146", "gpio148",
996
+
};
997
+
998
+
static const char *const qup1_se0_groups[] = {
999
+
"gpio80", "gpio81", "gpio82", "gpio83",
1000
+
};
1001
+
1002
+
static const char *const qup1_se1_groups[] = {
1003
+
"gpio74", "gpio75", "gpio76", "gpio77",
1004
+
};
1005
+
1006
+
static const char *const qup1_se2_groups[] = {
1007
+
"gpio40", "gpio41", "gpio42", "gpio43", "gpio130", "gpio131", "gpio132",
1008
+
};
1009
+
1010
+
static const char *const qup1_se3_groups[] = {
1011
+
"gpio44", "gpio45", "gpio46", "gpio47",
1012
+
};
1013
+
1014
+
static const char *const qup1_se4_groups[] = {
1015
+
"gpio36", "gpio37", "gpio38", "gpio39",
1016
+
};
1017
+
1018
+
static const char *const qup1_se5_groups[] = {
1019
+
"gpio52", "gpio53", "gpio54", "gpio55",
1020
+
};
1021
+
1022
+
static const char *const qup1_se6_groups[] = {
1023
+
"gpio56", "gpio57", "gpio58", "gpio59",
1024
+
};
1025
+
1026
+
static const char *const qup1_se7_groups[] = {
1027
+
"gpio60", "gpio61", "gpio62", "gpio63",
1028
+
};
1029
+
1030
+
static const char *const qup2_se0_groups[] = {
1031
+
"gpio0", "gpio1", "gpio2", "gpio3",
1032
+
};
1033
+
1034
+
static const char *const qup2_se1_groups[] = {
1035
+
"gpio4", "gpio5", "gpio6", "gpio7",
1036
+
};
1037
+
1038
+
static const char *const qup2_se2_groups[] = {
1039
+
"gpio117", "gpio118", "gpio119", "gpio120",
1040
+
};
1041
+
1042
+
static const char *const qup2_se3_groups[] = {
1043
+
"gpio97", "gpio122", "gpio123", "gpio124", "gpio125",
1044
+
};
1045
+
1046
+
static const char *const qup2_se4_01_groups[] = {
1047
+
"gpio208", "gpio209",
1048
+
};
1049
+
1050
+
static const char *const qup2_se4_23_groups[] = {
1051
+
"gpio208", "gpio209",
1052
+
};
1053
+
1054
+
static const char *const qup3_se0_01_groups[] = {
1055
+
"gpio64", "gpio65",
1056
+
};
1057
+
1058
+
static const char *const qup3_se0_23_groups[] = {
1059
+
"gpio64", "gpio65",
1060
+
};
1061
+
1062
+
static const char *const qup3_se1_groups[] = {
1063
+
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio15",
1064
+
};
1065
+
1066
+
static const char *const qup3_se2_groups[] = {
1067
+
"gpio12", "gpio13", "gpio14", "gpio15",
1068
+
};
1069
+
1070
+
static const char *const qup3_se3_groups[] = {
1071
+
"gpio16", "gpio17", "gpio18", "gpio19",
1072
+
};
1073
+
1074
+
static const char *const qup3_se4_groups[] = {
1075
+
"gpio20", "gpio21", "gpio22", "gpio23",
1076
+
};
1077
+
1078
+
static const char *const qup3_se5_groups[] = {
1079
+
"gpio24", "gpio25", "gpio26", "gpio27",
1080
+
};
1081
+
1082
+
static const char *const qup4_se0_groups[] = {
1083
+
"gpio48", "gpio49", "gpio50", "gpio51",
1084
+
};
1085
+
1086
+
static const char *const qup4_se1_groups[] = {
1087
+
"gpio28", "gpio29", "gpio30", "gpio31",
1088
+
};
1089
+
1090
+
static const char *const qup4_se2_groups[] = {
1091
+
"gpio32", "gpio33", "gpio34", "gpio35",
1092
+
};
1093
+
1094
+
static const char *const qup4_se3_01_groups[] = {
1095
+
"gpio84", "gpio121",
1096
+
};
1097
+
1098
+
static const char *const qup4_se3_23_groups[] = {
1099
+
"gpio84", "gpio121",
1100
+
};
1101
+
1102
+
static const char *const qup4_se3_l3_groups[] = {
1103
+
"gpio98",
1104
+
};
1105
+
1106
+
static const char *const qup4_se4_01_groups[] = {
1107
+
"gpio161", "gpio162",
1108
+
};
1109
+
1110
+
static const char *const qup4_se4_23_groups[] = {
1111
+
"gpio161", "gpio162",
1112
+
};
1113
+
1114
+
static const char *const qup4_se4_l3_groups[] = {
1115
+
"gpio88",
1116
+
};
1117
+
1118
+
static const char *const rng_rosc_groups[] = {
1119
+
"gpio64", "gpio65", "gpio66", "gpio84",
1120
+
};
1121
+
1122
+
static const char *const sd_write_protect_groups[] = {
1123
+
"gpio85",
1124
+
};
1125
+
1126
+
static const char *const sdc4_clk_groups[] = {
1127
+
"gpio83",
1128
+
};
1129
+
1130
+
static const char *const sdc4_cmd_groups[] = {
1131
+
"gpio148",
1132
+
};
1133
+
1134
+
static const char *const sdc4_data_groups[] = {
1135
+
"gpio80", "gpio81", "gpio82", "gpio147",
1136
+
};
1137
+
1138
+
static const char *const sys_throttle_groups[] = {
1139
+
"gpio99",
1140
+
};
1141
+
1142
+
static const char *const tb_trig_sdc_groups[] = {
1143
+
"gpio88", "gpio146",
1144
+
};
1145
+
1146
+
static const char *const tmess_rng_groups[] = {
1147
+
"gpio64", "gpio65", "gpio66", "gpio84",
1148
+
};
1149
+
1150
+
static const char *const tsense_clm_groups[] = {
1151
+
"gpio10", "gpio87", "gpio97", "gpio99", "gpio105", "gpio106",
1152
+
"gpio159",
1153
+
};
1154
+
1155
+
static const char *const tsense_pwm_groups[] = {
1156
+
"gpio10", "gpio87", "gpio97", "gpio99", "gpio223", "gpio224",
1157
+
"gpio225",
1158
+
};
1159
+
1160
+
static const char *const uim0_groups[] = {
1161
+
"gpio126", "gpio127", "gpio128", "gpio129",
1162
+
};
1163
+
1164
+
static const char *const uim1_groups[] = {
1165
+
"gpio36", "gpio37", "gpio39", "gpio54", "gpio55", "gpio56",
1166
+
"gpio70", "gpio71", "gpio72", "gpio130", "gpio131", "gpio132",
1167
+
"gpio133",
1168
+
};
1169
+
1170
+
static const char *const usb0_hs_groups[] = {
1171
+
"gpio79",
1172
+
};
1173
+
1174
+
static const char *const usb_phy_groups[] = {
1175
+
"gpio59", "gpio60",
1176
+
};
1177
+
1178
+
static const char *const vfr_groups[] = {
1179
+
"gpio146", "gpio151",
1180
+
};
1181
+
1182
+
static const char *const vsense_trigger_mirnat_groups[] = {
1183
+
"gpio59",
1184
+
};
1185
+
1186
+
static const char *const wcn_sw_ctrl_groups[] = {
1187
+
"gpio18", "gpio19", "gpio155", "gpio156",
1188
+
};
1189
+
1190
+
static const struct pinfunction hawi_functions[] = {
1191
+
MSM_GPIO_PIN_FUNCTION(gpio),
1192
+
MSM_PIN_FUNCTION(aoss_cti),
1193
+
MSM_PIN_FUNCTION(atest_char),
1194
+
MSM_PIN_FUNCTION(atest_usb),
1195
+
MSM_PIN_FUNCTION(audio_ext_mclk),
1196
+
MSM_PIN_FUNCTION(audio_ref_clk),
1197
+
MSM_PIN_FUNCTION(cam_mclk),
1198
+
MSM_PIN_FUNCTION(cci_async_in),
1199
+
MSM_PIN_FUNCTION(cci_i2c0),
1200
+
MSM_PIN_FUNCTION(cci_i2c1),
1201
+
MSM_PIN_FUNCTION(cci_i2c2),
1202
+
MSM_PIN_FUNCTION(cci_i2c3),
1203
+
MSM_PIN_FUNCTION(cci_i2c4),
1204
+
MSM_PIN_FUNCTION(cci_i2c5),
1205
+
MSM_PIN_FUNCTION(cci_timer),
1206
+
MSM_PIN_FUNCTION(coex_espmi),
1207
+
MSM_PIN_FUNCTION(coex_uart1_rx),
1208
+
MSM_PIN_FUNCTION(coex_uart1_tx),
1209
+
MSM_PIN_FUNCTION(dbg_out_clk),
1210
+
MSM_PIN_FUNCTION(ddr_bist),
1211
+
MSM_PIN_FUNCTION(ddr_pxi),
1212
+
MSM_PIN_FUNCTION(dp_hot),
1213
+
MSM_PIN_FUNCTION(egpio),
1214
+
MSM_PIN_FUNCTION(gcc_gp),
1215
+
MSM_PIN_FUNCTION(gnss_adc),
1216
+
MSM_PIN_FUNCTION(host_rst),
1217
+
MSM_PIN_FUNCTION(i2chub0_se0),
1218
+
MSM_PIN_FUNCTION(i2chub0_se1),
1219
+
MSM_PIN_FUNCTION(i2chub0_se2),
1220
+
MSM_PIN_FUNCTION(i2chub0_se3),
1221
+
MSM_PIN_FUNCTION(i2chub0_se4),
1222
+
MSM_PIN_FUNCTION(i2s0),
1223
+
MSM_PIN_FUNCTION(i2s1),
1224
+
MSM_PIN_FUNCTION(ibi_i3c),
1225
+
MSM_PIN_FUNCTION(jitter_bist),
1226
+
MSM_PIN_FUNCTION(mdp_esync0),
1227
+
MSM_PIN_FUNCTION(mdp_esync1),
1228
+
MSM_PIN_FUNCTION(mdp_esync2),
1229
+
MSM_PIN_FUNCTION(mdp_vsync),
1230
+
MSM_PIN_FUNCTION(mdp_vsync_e),
1231
+
MSM_PIN_FUNCTION(mdp_vsync_p),
1232
+
MSM_PIN_FUNCTION(mdp_vsync0_out),
1233
+
MSM_PIN_FUNCTION(mdp_vsync1_out),
1234
+
MSM_PIN_FUNCTION(mdp_vsync2_out),
1235
+
MSM_PIN_FUNCTION(mdp_vsync3_out),
1236
+
MSM_PIN_FUNCTION(mdp_vsync5_out),
1237
+
MSM_PIN_FUNCTION(modem_pps_in),
1238
+
MSM_PIN_FUNCTION(modem_pps_out),
1239
+
MSM_PIN_FUNCTION(nav_gpio),
1240
+
MSM_PIN_FUNCTION(nav_gpio0),
1241
+
MSM_PIN_FUNCTION(nav_gpio3),
1242
+
MSM_PIN_FUNCTION(nav_rffe),
1243
+
MSM_PIN_FUNCTION(pcie0_clk_req_n),
1244
+
MSM_PIN_FUNCTION(pcie0_rst_n),
1245
+
MSM_PIN_FUNCTION(pcie1_clk_req_n),
1246
+
MSM_PIN_FUNCTION(phase_flag),
1247
+
MSM_PIN_FUNCTION(pll_bist_sync),
1248
+
MSM_PIN_FUNCTION(pll_clk_aux),
1249
+
MSM_PIN_FUNCTION(qdss_cti),
1250
+
MSM_PIN_FUNCTION(qlink),
1251
+
MSM_PIN_FUNCTION(qspi),
1252
+
MSM_PIN_FUNCTION(qspi_clk),
1253
+
MSM_PIN_FUNCTION(qspi_cs),
1254
+
MSM_PIN_FUNCTION(qup1_se0),
1255
+
MSM_PIN_FUNCTION(qup1_se1),
1256
+
MSM_PIN_FUNCTION(qup1_se2),
1257
+
MSM_PIN_FUNCTION(qup1_se3),
1258
+
MSM_PIN_FUNCTION(qup1_se4),
1259
+
MSM_PIN_FUNCTION(qup1_se5),
1260
+
MSM_PIN_FUNCTION(qup1_se6),
1261
+
MSM_PIN_FUNCTION(qup1_se7),
1262
+
MSM_PIN_FUNCTION(qup2_se0),
1263
+
MSM_PIN_FUNCTION(qup2_se1),
1264
+
MSM_PIN_FUNCTION(qup2_se2),
1265
+
MSM_PIN_FUNCTION(qup2_se3),
1266
+
MSM_PIN_FUNCTION(qup2_se4_01),
1267
+
MSM_PIN_FUNCTION(qup2_se4_23),
1268
+
MSM_PIN_FUNCTION(qup3_se0_01),
1269
+
MSM_PIN_FUNCTION(qup3_se0_23),
1270
+
MSM_PIN_FUNCTION(qup3_se1),
1271
+
MSM_PIN_FUNCTION(qup3_se2),
1272
+
MSM_PIN_FUNCTION(qup3_se3),
1273
+
MSM_PIN_FUNCTION(qup3_se4),
1274
+
MSM_PIN_FUNCTION(qup3_se5),
1275
+
MSM_PIN_FUNCTION(qup4_se0),
1276
+
MSM_PIN_FUNCTION(qup4_se1),
1277
+
MSM_PIN_FUNCTION(qup4_se2),
1278
+
MSM_PIN_FUNCTION(qup4_se3_01),
1279
+
MSM_PIN_FUNCTION(qup4_se3_23),
1280
+
MSM_PIN_FUNCTION(qup4_se3_l3),
1281
+
MSM_PIN_FUNCTION(qup4_se4_01),
1282
+
MSM_PIN_FUNCTION(qup4_se4_23),
1283
+
MSM_PIN_FUNCTION(qup4_se4_l3),
1284
+
MSM_PIN_FUNCTION(rng_rosc),
1285
+
MSM_PIN_FUNCTION(sd_write_protect),
1286
+
MSM_PIN_FUNCTION(sdc4_clk),
1287
+
MSM_PIN_FUNCTION(sdc4_cmd),
1288
+
MSM_PIN_FUNCTION(sdc4_data),
1289
+
MSM_PIN_FUNCTION(sys_throttle),
1290
+
MSM_PIN_FUNCTION(tb_trig_sdc),
1291
+
MSM_PIN_FUNCTION(tmess_rng),
1292
+
MSM_PIN_FUNCTION(tsense_clm),
1293
+
MSM_PIN_FUNCTION(tsense_pwm),
1294
+
MSM_PIN_FUNCTION(uim0),
1295
+
MSM_PIN_FUNCTION(uim1),
1296
+
MSM_PIN_FUNCTION(usb0_hs),
1297
+
MSM_PIN_FUNCTION(usb_phy),
1298
+
MSM_PIN_FUNCTION(vfr),
1299
+
MSM_PIN_FUNCTION(vsense_trigger_mirnat),
1300
+
MSM_PIN_FUNCTION(wcn_sw_ctrl),
1301
+
};
1302
+
1303
+
/*
1304
+
* Every pin is maintained as a single group, and missing or non-existing pin
1305
+
* would be maintained as dummy group to synchronize pin group index with
1306
+
* pin descriptor registered with pinctrl core.
1307
+
* Clients would not be able to request these dummy pin groups.
1308
+
*/
1309
+
static const struct msm_pingroup hawi_groups[] = {
1310
+
[0] = PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1311
+
[1] = PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1312
+
[2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio),
1313
+
[3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio),
1314
+
[4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1315
+
[5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1316
+
[6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio),
1317
+
[7] = PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio),
1318
+
[8] = PINGROUP(8, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
1319
+
[9] = PINGROUP(9, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
1320
+
[10] = PINGROUP(10, qup3_se1, _, tsense_clm, tsense_pwm, _, _, _, _, _, _, _),
1321
+
[11] = PINGROUP(11, qup3_se1, _, _, _, _, _, _, _, _, _, _),
1322
+
[12] = PINGROUP(12, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _),
1323
+
[13] = PINGROUP(13, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _),
1324
+
[14] = PINGROUP(14, qup3_se2, _, _, _, _, _, _, _, _, _, _),
1325
+
[15] = PINGROUP(15, qup3_se2, cci_async_in, qup3_se1, _, _, _, _, _, _, _, _),
1326
+
[16] = PINGROUP(16, qup3_se3, _, _, _, _, _, _, _, _, _, _),
1327
+
[17] = PINGROUP(17, qup3_se3, _, _, _, _, _, _, _, _, _, _),
1328
+
[18] = PINGROUP(18, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _),
1329
+
[19] = PINGROUP(19, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _),
1330
+
[20] = PINGROUP(20, qup3_se4, _, _, _, _, _, _, _, _, _, _),
1331
+
[21] = PINGROUP(21, qup3_se4, _, _, _, _, _, _, _, _, _, _),
1332
+
[22] = PINGROUP(22, qup3_se4, _, _, _, _, _, _, _, _, _, _),
1333
+
[23] = PINGROUP(23, qup3_se4, _, _, _, _, _, _, _, _, _, _),
1334
+
[24] = PINGROUP(24, qup3_se5, _, _, _, _, _, _, _, _, _, _),
1335
+
[25] = PINGROUP(25, qup3_se5, _, _, _, _, _, _, _, _, _, _),
1336
+
[26] = PINGROUP(26, qup3_se5, _, _, _, _, _, _, _, _, _, _),
1337
+
[27] = PINGROUP(27, qup3_se5, qdss_cti, _, _, _, _, _, _, _, _, _),
1338
+
[28] = PINGROUP(28, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1339
+
[29] = PINGROUP(29, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1340
+
[30] = PINGROUP(30, qup4_se1, _, _, _, _, _, _, _, _, _, egpio),
1341
+
[31] = PINGROUP(31, qup4_se1, qdss_cti, _, _, _, _, _, _, _, _, egpio),
1342
+
[32] = PINGROUP(32, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _),
1343
+
[33] = PINGROUP(33, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _),
1344
+
[34] = PINGROUP(34, qup4_se2, _, _, _, _, _, _, _, _, _, _),
1345
+
[35] = PINGROUP(35, qup4_se2, _, _, _, _, _, _, _, _, _, _),
1346
+
[36] = PINGROUP(36, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _),
1347
+
[37] = PINGROUP(37, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _),
1348
+
[38] = PINGROUP(38, qup1_se4, _, _, _, _, _, _, _, _, _, _),
1349
+
[39] = PINGROUP(39, qup1_se4, uim1, _, _, _, _, _, _, _, _, _),
1350
+
[40] = PINGROUP(40, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _),
1351
+
[41] = PINGROUP(41, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _),
1352
+
[42] = PINGROUP(42, qup1_se2, gnss_adc, _, _, _, _, _, _, _, _, _),
1353
+
[43] = PINGROUP(43, qup1_se2, _, ddr_pxi, _, _, _, _, _, _, _, _),
1354
+
[44] = PINGROUP(44, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _),
1355
+
[45] = PINGROUP(45, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _),
1356
+
[46] = PINGROUP(46, qup1_se3, ddr_pxi, _, _, _, _, _, _, _, _, _),
1357
+
[47] = PINGROUP(47, qup1_se3, dp_hot, _, _, _, _, _, _, _, _, _),
1358
+
[48] = PINGROUP(48, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1359
+
[49] = PINGROUP(49, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1360
+
[50] = PINGROUP(50, qup4_se0, _, _, _, _, _, _, _, _, _, egpio),
1361
+
[51] = PINGROUP(51, qup4_se0, _, _, _, _, _, _, _, _, _, egpio),
1362
+
[52] = PINGROUP(52, qup1_se5, ddr_pxi, _, _, _, _, _, _, _, _, _),
1363
+
[53] = PINGROUP(53, qup1_se5, _, ddr_pxi, _, _, _, _, _, _, _, _),
1364
+
[54] = PINGROUP(54, qup1_se5, uim1, ddr_pxi, _, _, _, _, _, _, _, _),
1365
+
[55] = PINGROUP(55, qup1_se5, uim1, ddr_pxi, _, _, _, _, _, _, _, _),
1366
+
[56] = PINGROUP(56, qup1_se6, uim1, _, _, _, _, _, _, _, _, _),
1367
+
[57] = PINGROUP(57, qup1_se6, _, _, _, _, _, _, _, _, _, _),
1368
+
[58] = PINGROUP(58, qup1_se6, _, _, _, _, _, _, _, _, _, _),
1369
+
[59] = PINGROUP(59, qup1_se6, usb_phy, vsense_trigger_mirnat, _, _, _, _, _, _, _, _),
1370
+
[60] = PINGROUP(60, qup1_se7, usb_phy, ibi_i3c, _, _, _, _, _, _, _, _),
1371
+
[61] = PINGROUP(61, qup1_se7, ibi_i3c, _, _, _, _, _, _, _, _, _),
1372
+
[62] = PINGROUP(62, qup1_se7, _, _, _, _, _, _, _, _, _, _),
1373
+
[63] = PINGROUP(63, qup1_se7, _, _, _, _, _, _, _, _, _, _),
1374
+
[64] = PINGROUP(64, qup3_se0_01, qup3_se0_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
1375
+
[65] = PINGROUP(65, qup3_se0_01, qup3_se0_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
1376
+
[66] = PINGROUP(66, i2chub0_se0, rng_rosc, tmess_rng, _, _, _, _, _, _, _, _),
1377
+
[67] = PINGROUP(67, i2chub0_se0, _, _, _, _, _, _, _, _, _, _),
1378
+
[68] = PINGROUP(68, i2chub0_se2, _, _, _, _, _, _, _, _, _, _),
1379
+
[69] = PINGROUP(69, i2chub0_se2, _, _, _, _, _, _, _, _, _, _),
1380
+
[70] = PINGROUP(70, i2chub0_se3, uim1, _, atest_usb, _, _, _, _, _, _, _),
1381
+
[71] = PINGROUP(71, i2chub0_se3, uim1, _, atest_usb, _, _, _, _, _, _, _),
1382
+
[72] = PINGROUP(72, i2chub0_se4, uim1, qdss_cti, _, atest_usb, _, _, _, _, _, _),
1383
+
[73] = PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, atest_usb, _, _, _, _, _, _, _),
1384
+
[74] = PINGROUP(74, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
1385
+
[75] = PINGROUP(75, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
1386
+
[76] = PINGROUP(76, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
1387
+
[77] = PINGROUP(77, qup1_se1, aoss_cti, gnss_adc, _, _, _, _, _, _, _, _),
1388
+
[78] = PINGROUP(78, i2chub0_se1, _, _, _, _, _, _, _, _, _, _),
1389
+
[79] = PINGROUP(79, i2chub0_se1, usb0_hs, _, _, _, _, _, _, _, _, _),
1390
+
[80] = PINGROUP(80, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _),
1391
+
[81] = PINGROUP(81, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _),
1392
+
[82] = PINGROUP(82, qup1_se0, sdc4_data, qdss_cti, qspi, dbg_out_clk, _, _, _, _, _, _),
1393
+
[83] = PINGROUP(83, qup1_se0, sdc4_clk, qdss_cti, qspi_clk, _, _, _, _, _, _, _),
1394
+
[84] = PINGROUP(84, qup4_se3_01, qup4_se3_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
1395
+
[85] = PINGROUP(85, sd_write_protect, _, _, _, _, _, _, _, _, _, _),
1396
+
[86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_esync1, gcc_gp,
1397
+
_, _, _, _, _, _),
1398
+
[87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
1399
+
mdp_esync2, gcc_gp, _, tsense_clm, tsense_pwm, _, _),
1400
+
[88] = PINGROUP(88, mdp_esync0, mdp_vsync, qup4_se4_l3, tb_trig_sdc, _, _, _, _, _, _, _),
1401
+
[89] = PINGROUP(89, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1402
+
[90] = PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1403
+
[91] = PINGROUP(91, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1404
+
[92] = PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1405
+
[93] = PINGROUP(93, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1406
+
[94] = PINGROUP(94, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _),
1407
+
[95] = PINGROUP(95, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1408
+
[96] = PINGROUP(96, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1409
+
[97] = PINGROUP(97, mdp_esync2, qup2_se3, mdp_vsync, tsense_clm, tsense_pwm, _, _,
1410
+
_, _, _, _),
1411
+
[98] = PINGROUP(98, mdp_vsync_e, qup4_se3_l3, mdp_vsync_p, _, _, _, _, _, _, _, _),
1412
+
[99] = PINGROUP(99, sys_throttle, tsense_clm, tsense_pwm, _, _, _, _, _, _, _, _),
1413
+
[100] = PINGROUP(100, mdp_esync1, mdp_esync0, _, _, _, _, _, _, _, _, _),
1414
+
[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),
1415
+
[102] = PINGROUP(102, pcie0_rst_n, _, _, _, _, _, _, _, _, _, _),
1416
+
[103] = PINGROUP(103, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1417
+
[104] = PINGROUP(104, pll_bist_sync, _, _, _, _, _, _, _, _, _, _),
1418
+
[105] = PINGROUP(105, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _),
1419
+
[106] = PINGROUP(106, host_rst, cci_timer, tsense_clm, _, _, _, _, _, _, _, _),
1420
+
[107] = PINGROUP(107, cci_i2c3, cci_timer, _, _, _, _, _, _, _, _, _),
1421
+
[108] = PINGROUP(108, cci_i2c4, _, _, _, _, _, _, _, _, _, _),
1422
+
[109] = PINGROUP(109, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _),
1423
+
[110] = PINGROUP(110, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _),
1424
+
[111] = PINGROUP(111, cci_i2c1, _, _, _, _, _, _, _, _, _, _),
1425
+
[112] = PINGROUP(112, cci_i2c1, _, _, _, _, _, _, _, _, _, _),
1426
+
[113] = PINGROUP(113, cci_i2c2, _, _, _, _, _, _, _, _, _, _),
1427
+
[114] = PINGROUP(114, cci_i2c2, _, _, _, _, _, _, _, _, _, _),
1428
+
[115] = PINGROUP(115, cci_i2c5, _, _, _, _, _, _, _, _, _, _),
1429
+
[116] = PINGROUP(116, cci_i2c5, _, _, _, _, _, _, _, _, _, _),
1430
+
[117] = PINGROUP(117, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
1431
+
[118] = PINGROUP(118, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
1432
+
[119] = PINGROUP(119, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
1433
+
[120] = PINGROUP(120, i2s1, qup2_se2, audio_ext_mclk, audio_ref_clk, _, _,
1434
+
_, _, _, _, _),
1435
+
[121] = PINGROUP(121, audio_ext_mclk, qup4_se3_01, qup4_se3_23, _, _, _, _, _, _, _, _),
1436
+
[122] = PINGROUP(122, i2s0, qup2_se3, _, _, _, _, _, _, _, _, _),
1437
+
[123] = PINGROUP(123, i2s0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _),
1438
+
[124] = PINGROUP(124, i2s0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _),
1439
+
[125] = PINGROUP(125, i2s0, qup2_se3, phase_flag, _, _, _, _, _, _, _, _),
1440
+
[126] = PINGROUP(126, uim0, atest_char, _, _, _, _, _, _, _, _, _),
1441
+
[127] = PINGROUP(127, uim0, atest_char, _, _, _, _, _, _, _, _, _),
1442
+
[128] = PINGROUP(128, uim0, atest_char, _, _, _, _, _, _, _, _, _),
1443
+
[129] = PINGROUP(129, uim0, atest_usb, atest_char, _, _, _, _, _, _, _, _),
1444
+
[130] = PINGROUP(130, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
1445
+
[131] = PINGROUP(131, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
1446
+
[132] = PINGROUP(132, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
1447
+
[133] = PINGROUP(133, uim1, atest_char, _, _, _, _, _, _, _, _, _),
1448
+
[134] = PINGROUP(134, _, _, nav_rffe, _, _, _, _, _, _, _, _),
1449
+
[135] = PINGROUP(135, _, _, nav_rffe, _, _, _, _, _, _, _, _),
1450
+
[136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _),
1451
+
[137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _),
1452
+
[138] = PINGROUP(138, _, _, nav_rffe, _, _, _, _, _, _, _, _),
1453
+
[139] = PINGROUP(139, _, _, nav_rffe, _, _, _, _, _, _, _, _),
1454
+
[140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _),
1455
+
[141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _),
1456
+
[142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _),
1457
+
[143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _),
1458
+
[144] = PINGROUP(144, coex_uart1_rx, coex_espmi, _, _, _, _, _, _, _, _, _),
1459
+
[145] = PINGROUP(145, coex_uart1_tx, coex_espmi, _, _, _, _, _, _, _, _, _),
1460
+
[146] = PINGROUP(146, _, vfr, nav_gpio, tb_trig_sdc, qspi_cs, _, _, _, _, _, _),
1461
+
[147] = PINGROUP(147, _, nav_gpio, sdc4_data, qspi, _, _, _, _, _, _, _),
1462
+
[148] = PINGROUP(148, nav_gpio, _, sdc4_cmd, qspi_cs, _, _, _, _, _, _, _),
1463
+
[149] = PINGROUP(149, cci_i2c4, _, _, _, _, _, _, _, _, _, _),
1464
+
[150] = PINGROUP(150, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _),
1465
+
[151] = PINGROUP(151, nav_gpio, vfr, modem_pps_in, modem_pps_out, _, _, _, _, _, _, _),
1466
+
[152] = PINGROUP(152, qlink, qdss_cti, _, _, _, _, _, _, _, _, _),
1467
+
[153] = PINGROUP(153, qlink, _, _, _, _, _, _, _, _, _, _),
1468
+
[154] = PINGROUP(154, qlink, _, _, _, _, _, _, _, _, _, _),
1469
+
[155] = PINGROUP(155, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),
1470
+
[156] = PINGROUP(156, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),
1471
+
[157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _),
1472
+
[158] = PINGROUP(158, qdss_cti, gcc_gp, _, _, _, _, _, _, _, _, _),
1473
+
[159] = PINGROUP(159, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _),
1474
+
[160] = PINGROUP(160, cci_timer, cci_i2c3, _, _, _, _, _, _, _, _, _),
1475
+
[161] = PINGROUP(161, qup4_se4_01, qup4_se4_23, _, _, _, _, _, _, _, _, _),
1476
+
[162] = PINGROUP(162, qup4_se4_01, qup4_se4_23, _, _, _, _, _, _, _, _, _),
1477
+
[163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, egpio),
1478
+
[164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, egpio),
1479
+
[165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio),
1480
+
[166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio),
1481
+
[167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio),
1482
+
[168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio),
1483
+
[169] = PINGROUP(169, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1484
+
[170] = PINGROUP(170, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1485
+
[171] = PINGROUP(171, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1486
+
[172] = PINGROUP(172, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1487
+
[173] = PINGROUP(173, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1488
+
[174] = PINGROUP(174, _, _, _, _, _, _, _, _, _, _, egpio),
1489
+
[175] = PINGROUP(175, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1490
+
[176] = PINGROUP(176, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1491
+
[177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio),
1492
+
[178] = PINGROUP(178, _, _, _, _, _, _, _, _, _, _, egpio),
1493
+
[179] = PINGROUP(179, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1494
+
[180] = PINGROUP(180, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1495
+
[181] = PINGROUP(181, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1496
+
[182] = PINGROUP(182, _, _, _, _, _, _, _, _, _, _, egpio),
1497
+
[183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, egpio),
1498
+
[184] = PINGROUP(184, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1499
+
[185] = PINGROUP(185, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1500
+
[186] = PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio),
1501
+
[187] = PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio),
1502
+
[188] = PINGROUP(188, _, _, _, _, _, _, _, _, _, _, egpio),
1503
+
[189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, _, egpio),
1504
+
[190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio),
1505
+
[191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio),
1506
+
[192] = PINGROUP(192, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1507
+
[193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio),
1508
+
[194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio),
1509
+
[195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio),
1510
+
[196] = PINGROUP(196, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1511
+
[197] = PINGROUP(197, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1512
+
[198] = PINGROUP(198, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1513
+
[199] = PINGROUP(199, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1514
+
[200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio),
1515
+
[201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio),
1516
+
[202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio),
1517
+
[203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio),
1518
+
[204] = PINGROUP(204, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1519
+
[205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio),
1520
+
[206] = PINGROUP(206, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1521
+
[207] = PINGROUP(207, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1522
+
[208] = PINGROUP(208, qup2_se4_01, qup2_se4_23, phase_flag, _, _, _, _, _, _, _, egpio),
1523
+
[209] = PINGROUP(209, qup2_se4_01, qup2_se4_23, _, _, _, _, _, _, _, _, egpio),
1524
+
[210] = PINGROUP(210, phase_flag, _, _, _, _, _, _, _, _, _, _),
1525
+
[211] = PINGROUP(211, phase_flag, _, _, _, _, _, _, _, _, _, _),
1526
+
[212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio),
1527
+
[213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio),
1528
+
[214] = PINGROUP(214, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1529
+
[215] = PINGROUP(215, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1530
+
[216] = PINGROUP(216, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1531
+
[217] = PINGROUP(217, _, _, _, _, _, _, _, _, _, _, egpio),
1532
+
[218] = PINGROUP(218, _, _, _, _, _, _, _, _, _, _, egpio),
1533
+
[219] = PINGROUP(219, _, _, _, _, _, _, _, _, _, _, _),
1534
+
[220] = PINGROUP(220, _, _, _, _, _, _, _, _, _, _, _),
1535
+
[221] = PINGROUP(221, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1536
+
[222] = PINGROUP(222, _, _, _, _, _, _, _, _, _, _, _),
1537
+
[223] = PINGROUP(223, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
1538
+
[224] = PINGROUP(224, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
1539
+
[225] = PINGROUP(225, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
1540
+
[226] = UFS_RESET(ufs_reset, 0xf1004, 0xf2000),
1541
+
[227] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe6000, 14, 6),
1542
+
[228] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe6000, 11, 3),
1543
+
[229] = SDC_QDSD_PINGROUP(sdc2_data, 0xe6000, 9, 0),
1544
+
};
1545
+
1546
+
static const struct msm_gpio_wakeirq_map hawi_pdc_map[] = {
1547
+
{ 0, 105 }, { 3, 113 }, { 4, 106 }, { 7, 107 }, { 8, 108 }, { 11, 109 },
1548
+
{ 12, 115 }, { 15, 131 }, { 16, 116 }, { 17, 141 }, { 18, 143 }, { 19, 112 },
1549
+
{ 23, 117 }, { 24, 118 }, { 27, 119 }, { 28, 125 }, { 31, 126 }, { 32, 127 },
1550
+
{ 35, 101 }, { 36, 128 }, { 39, 129 }, { 43, 130 }, { 47, 154 }, { 48, 135 },
1551
+
{ 51, 114 }, { 55, 104 }, { 57, 136 }, { 58, 137 }, { 59, 138 }, { 60, 139 },
1552
+
{ 61, 145 }, { 63, 124 }, { 64, 110 }, { 65, 123 }, { 67, 132 }, { 68, 146 },
1553
+
{ 69, 147 }, { 75, 151 }, { 77, 148 }, { 78, 149 }, { 79, 155 }, { 80, 156 },
1554
+
{ 81, 157 }, { 82, 158 }, { 84, 134 }, { 85, 159 }, { 86, 160 }, { 87, 161 },
1555
+
{ 88, 162 }, { 95, 163 }, { 96, 164 }, { 97, 133 }, { 98, 150 }, { 99, 111 },
1556
+
{ 101, 165 }, { 102, 166 }, { 103, 167 }, { 104, 168 }, { 120, 169 }, { 123, 170 },
1557
+
{ 125, 171 }, { 129, 153 }, { 133, 100 }, { 144, 172 }, { 146, 173 }, { 151, 174 },
1558
+
{ 152, 175 }, { 155, 122 }, { 158, 120 }, { 162, 142 }, { 164, 176 }, { 165, 177 },
1559
+
{ 167, 178 }, { 168, 179 }, { 174, 180 }, { 177, 181 }, { 179, 182 }, { 183, 183 },
1560
+
{ 184, 184 }, { 185, 185 }, { 186, 152 }, { 188, 144 }, { 202, 102 }, { 203, 103 },
1561
+
{ 205, 140 }, { 209, 186 }, { 213, 121 }, { 216, 187 }, { 221, 188 }, { 222, 189 },
1562
+
{ 223, 190 }, { 224, 191 }, { 225, 192 },
1563
+
};
1564
+
1565
+
static const struct msm_pinctrl_soc_data hawi_tlmm = {
1566
+
.pins = hawi_pins,
1567
+
.npins = ARRAY_SIZE(hawi_pins),
1568
+
.functions = hawi_functions,
1569
+
.nfunctions = ARRAY_SIZE(hawi_functions),
1570
+
.groups = hawi_groups,
1571
+
.ngroups = ARRAY_SIZE(hawi_groups),
1572
+
.ngpios = 227,
1573
+
.wakeirq_map = hawi_pdc_map,
1574
+
.nwakeirq_map = ARRAY_SIZE(hawi_pdc_map),
1575
+
.egpio_func = 11,
1576
+
};
1577
+
1578
+
static int hawi_tlmm_probe(struct platform_device *pdev)
1579
+
{
1580
+
return msm_pinctrl_probe(pdev, &hawi_tlmm);
1581
+
}
1582
+
1583
+
static const struct of_device_id hawi_tlmm_of_match[] = {
1584
+
{ .compatible = "qcom,hawi-tlmm", },
1585
+
{},
1586
+
};
1587
+
1588
+
static struct platform_driver hawi_tlmm_driver = {
1589
+
.driver = {
1590
+
.name = "hawi-tlmm",
1591
+
.of_match_table = hawi_tlmm_of_match,
1592
+
},
1593
+
.probe = hawi_tlmm_probe,
1594
+
};
1595
+
1596
+
static int __init hawi_tlmm_init(void)
1597
+
{
1598
+
return platform_driver_register(&hawi_tlmm_driver);
1599
+
}
1600
+
arch_initcall(hawi_tlmm_init);
1601
+
1602
+
static void __exit hawi_tlmm_exit(void)
1603
+
{
1604
+
platform_driver_unregister(&hawi_tlmm_driver);
1605
+
}
1606
+
module_exit(hawi_tlmm_exit);
1607
+
1608
+
MODULE_DESCRIPTION("QTI Hawi TLMM driver");
1609
+
MODULE_LICENSE("GPL");
1610
+
MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match);